/*1MCU tables for STM32F72*/34#if defined(STM32F7)56#define STM32_UNKNOWN 07#define STM32F74x_75x 0x4498#define STM32F76x_77x 0x451910typedef enum mcu_rev_e {11MCU_REV_STM32F7_REV_A = 0x1000,12MCU_REV_STM32F7_REV_Z = 0x1001,13} mcu_rev_e;1415// The default CPU ID of STM32_UNKNOWN is 0 and is in offset 016// Before a rev is known it is set to ?17// There for new silicon will result in STM32F4..,?18mcu_des_t mcu_descriptions[] = {19{ STM32_UNKNOWN, "STM32F??????" },20{ STM32F74x_75x, "STM32F7[4|5]x" },21{ STM32F76x_77x, "STM32F7[6|7]x" },22};2324const mcu_rev_t silicon_revs[] = {25{MCU_REV_STM32F7_REV_A, 'A'}, /* Revision A */26{MCU_REV_STM32F7_REV_Z, 'Z'}, /* Revision Z */27};2829#endif // STM32F7303132