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Path: blob/master/Tools/Linux_HAL_Essentials/devicetree/pxf/BB-PXF-01-00A0.dts
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/* * Copyright (C) 2013 Pantelis Antoniou <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ /dts-v1/; /plugin/; / { compatible = "ti,beaglebone", "ti,beaglebone-black"; /* identification */ part-number = "BB-PXF-01"; version = "00A0"; /* state the resources this cape uses */ exclusive-use = /* the pin header uses */ /* PRU RCInput */ "P8.11", /* pru0: pr1_pru0_pru_r30_15 */ "P8.15", /* pru0: pr1_pru0_pru_r31_15, PPM-sum, SBUS, DSM */ /* PRU RCOutput */ "P8.27", /* pru1: pr1_pru1_pru_r30_8, CH_2 */ "P8.28", /* pru1: pr1_pru1_pru_r30_10, CH_1 */ "P8.29", /* pru1: pr1_pru1_pru_r30_9, CH_4 */ "P8.30", /* pru1: pr1_pru1_pru_r30_11, CH_3 */ "P8.39", /* pru1: pr1_pru1_pru_r30_6, CH_6 */ "P8.40", /* pru1: pr1_pru1_pru_r30_7, CH_5 */ "P8.41", /* pru1: pr1_pru1_pru_r30_4, CH_8 */ "P8.42", /* pru1: pr1_pru1_pru_r30_5, CH_7 */ "P8.43", /* pru1: pr1_pru1_pru_r30_2, CH_10 */ "P8.44", /* pru1: pr1_pru1_pru_r30_3, CH_9 */ "P8.45", /* pru1: pr1_pru1_pru_r30_0, CH_12 */ "P8.46", /* pru1: pr1_pru1_pru_r30_1, CH_11 */ /* SPI0 */ "P9.22", /* SPI0_SCLK */ "P9.21", /* SPI0_MOSI */ "P9.18", /* SPI0_MISO */ "P9.17", /* LSM9DSO_AM CS */ "P8.9", /* LSM9DSO_G CS */ /* SPI1 */ "P9.31", /* SPI1_SCLK */ "P9.29", /* SPI1_MOSI */ "P9.30", /* SPI1_MISO */ "P9.42", /* MS5611 CS */ "P9.28", /* MPU6000 CS */ "P9.23", /* MPU9250 CS */ "P8.12", /* FRAM CS */ /* Buzzer PWM */ "P8.36", /* pwm: ehrpwm1A */ /* the hardware IP uses */ "pru0", "pru1", "spi0", "spi1", "ehrpwm1A"; fragment@0 { target = <&am33xx_pinmux>; __overlay__ { pru_gpio_pins: pinmux_pru_gpio_pins { pinctrl-single,pins = < 0x1a4 0x0f /* P9 27 GPIO3_19: mcasp0_fsr.gpio3[19] | MODE7 | OUTPUT */ >; }; pru_pru_pins: pinmux_pru_pru_pins { pinctrl-single,pins = < 0x034 0x26 /* gpmc_ad13.pr1_pru0_pru_r30_15, MODE6 | OUTPUT | PRU */ 0x03c 0x2e /* gpmc_ad15.pr1_pru0_pru_r31_15, MODE6 | INPUT | PRU, PPM-sum, SBUS, DSM */ 0x0e0 0x25 /* lcd_vsync.pr1_pru1_pru_r30_8, MODE5 | OUTPUT | PRU, CH_2 */ 0x0e8 0x25 /* lcd_pclk.pr1_pru1_pru_r30_10, MODE5 | OUTPUT | PRU, CH_1 */ 0x0e4 0x25 /* lcd_hsync.pr1_pru1_pru_r30_9, MODE5 | OUTPUT | PRU, CH_4 */ 0x0ec 0x25 /* lcd_ac_bias_en.pr1_pru1_pru_r30_11, MODE5 | OUTPUT | PRU, CH_3 */ 0x0b8 0x25 /* lcd_data6.pr1_pru1_pru_r30_6, MODE5 | OUTPUT | PRU, CH_6 */ 0x0bc 0x25 /* lcd_data7.pr1_pru1_pru_r30_7, MODE5 | OUTPUT | PRU, CH_5 */ 0x0b0 0x25 /* lcd_data4.pr1_pru1_pru_r30_4, MODE5 | OUTPUT | PRU, CH_8 */ 0x0b4 0x25 /* lcd_data5.pr1_pru1_pru_r30_5, MODE5 | OUTPUT | PRU, CH_7 */ 0x0a8 0x25 /* lcd_data2.pr1_pru1_pru_r30_2, MODE5 | OUTPUT | PRU, CH_10 */ 0x0ac 0x25 /* lcd_data3.pr1_pru1_pru_r30_3, MODE5 | OUTPUT | PRU, CH_9 */ 0x0a0 0x25 /* lcd_data0.pr1_pru1_pru_r30_0, MODE5 | OUTPUT | PRU, CH_12 */ 0x0a4 0x25 /* lcd_data1.pr1_pru1_pru_r30_1, MODE5 | OUTPUT | PRU, CH_11 */ >; }; spi0_pins_s0: spi0_pins_s0 { pinctrl-single,pins = < 0x150 0x30 /* spi0_sclk, SPI0_SCLK P9_22 */ 0x154 0x10 /* spi0_d0, SPI0_MOSI P9_21 */ 0x158 0x30 /* spi0_d1, SPI0_MISO P9_18 */ /* setup a dummy CS for the SPI driver to use, then setup pin modes for the two real CS lines to set them pull-up */ 0x054 0x07 /* led pin, dummy CS */ 0x15C 0x37 /* LSM9DSO_AM CS P9_17 */ 0x09C 0x37 /* LSM9DSO_G CS P8_9 */ >; }; spi1_pins_s0: spi1_pins_s0 { pinctrl-single,pins = < 0x190 0x33 /* mcasp0_aclkx.spi1_sclk, SPI1_SCLK P9_31 */ 0x194 0x13 /* mcasp0_fsx.spi1_d0, SPI1_MOSI P9_29 */ 0x198 0x33 /* mcasp0_axr0.spi1_d1, SPI1_MISO P9_30 */ /* setup a dummy CS for the SPI driver to use, then setup pin modes for the four real CS lines to set them pull-up */ 0x058 0x07 /* dummy CS */ 0x164 0x37 /* P9_42 MS5611 CS */ 0x19C 0x37 /* P9_28 MPU6000 CS */ 0x044 0x37 /* P9_23 MPU9250 CS */ 0x030 0x37 /* P8_12 FRAM CS */ >; }; pwm_P8_36: pinmux_pwm_P8_36_pins { pinctrl-single,pins = < 0x0C8 0x02 /* P8_36 (ZCZ ball U3) | MODE 2 */ >; }; }; }; fragment@2 { target = <&spi0>; __overlay__ { #address-cells = <1>; #size-cells = <0>; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins_s0>; ti,pindir-d0-out-d1-in = <1>; spidev@0 { spi-max-frequency = <24000000>; reg = <0>; compatible = "linux,spidev"; }; }; }; fragment@3{ target = <&spi1>; __overlay__ { #address-cells = <1>; #size-cells = <0>; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi1_pins_s0>; ti,pindir-d0-out-d1-in = <1>; spidev@1 { spi-max-frequency = <24000000>; reg = <0>; compatible = "linux,spidev"; }; }; }; fragment@4 { target = <&epwmss1>; __overlay__ { status = "okay"; }; }; fragment@5 { target = <&ehrpwm1>; __overlay__ { status = "okay"; }; }; fragment@6 { target = <&ocp>; __overlay__ { pwm_test_P8_36 { compatible = "pwm_test"; pwms = <&ehrpwm1 0 500000 1>; pwm-names = "PWM_P8_36"; pinctrl-names = "default"; pinctrl-0 = <&pwm_P8_36>; enabled = <1>; duty = <0>; status = "okay"; }; }; }; fragment@7 { target = <&ocp>; __overlay__ { /* avoid stupid warning */ #address-cells = <1>; #size-cells = <1>; prurproc { compatible = "ti,pru-rproc"; pinctrl-names = "default"; pinctrl-0 = <&pru_pru_pins>; reg = <0x4a300000 0x080000>; status = "okay"; ti,hwmods = "pruss"; ti,deassert-hard-reset = "pruss", "pruss"; interrupt-parent = <&intc>; /* interrupts on the host */ interrupts = <20 21 22 23 24 25 26 27>; /* events these interrupts map to (host interrupt) */ events = <2 3 4 5 6 7 8 9>; /* PRU interrupt controller offset */ pintc = <0x20000>; /* 12K Shared Data RAM global, size, local */ pdram = <0x10000 0x03000 0x10000>; /* * SYSEVENT ids * * - PRU/ARM communication * PRU0_PRU1 17 * PRU1_PRU0 18 * PRU0_ARM 19 * PRU1_ARM 20 * ARM_PRU0 21 * ARM_PRU1 22 * * Full SYSEVENT list * * parity_err_intr_pend 0 * pru0_r31_status_cnt16 1 * pru1_r31_status_cnt16 2 * uart_urxevt_intr_req 4 * uart_utxevt_intr_req 5 * uart_uint_intr_req 6 * iep_tim_cap_cmp_pend 7 * ecap_intr_req 15 * pru_mst_intr[0-15]_intr_req 16-31 * nirq 32 (UART1) * mcasp_x_intr_pend 33 (MCASP1) * mcasp_r_intr_pend 34 (MCASP1) * ecap_intr_intr_pend 35 (ECAP1) * ecap_intr_intr_pend 36 (ECAP2) * epwm_intr_intr_pend 37 (eHRPWM2) * dcan_uerr 38 (DCAN0) * dcan_int1 39 (DCAN0) * dcan_intr 40 (DCAN0) * POINTRPEND 41 (I2C0) * ecap_intr_intr_pend 42 (ECAP0) * epwm_intr_intr_pend 43 (eHRPWM0) * SINTERRUPTN 44 (McSPI0) * eqep_intr_intr_pend 45 (eQEP0) * epwm_intr_intr_pend 46 (eHRPWM1) * c0_misc_pend 47 3PGSW (GEMAC) * c0_tx_pend 48 3PGSW (GEMAC) * c0_rx_pend 49 3PGSW (GEMAC) * c0_rx_thresh_pend 50 3PGSW (GEMAC) * nirq 51 (UART0) * nirq 52 (UART2) * gen_intr_pend 53 (ADC_TSC) * mcasp_r_intr_pend 54 (McASP0) * mcasp_x_intr_pend 55 (McASP1) * pwm_trip_zone 56 (eHRPWM0/eHRPWM1/eHRP WM2) * POINTRPEND1 57 (GPIO0) * Emulation Suspend Signal 58 (Debugss) * initiator_sinterrupt_q_n2 59 (Mbox0 - mail_u2_irq (mailbox interrupt for pru1)) * initiator_sinterrupt_q_n1 60 (Mbox0 - mail_u1_irq (mailbox interrupt for pru0)) * tptc_erint_pend_po 61 (TPTC0 (EDMA)) * tpcc_errint_pend_po 62 (TPCC (EDMA)) * tpcc_int_pend_po1 63 (TPCC (EDMA)) * * HOST interrupt ids * * PRU0 0 * PRU1 1 * EVTOUT0-7 2-9 */ /* sysevent map to intc channel */ sysevent-to-channel-map = <17 1>, /* PRU0_PRU1 -> CH1 */ <18 0>, /* PRU1_PRU0 -> CH0 */ <19 2>, /* PRU0_ARM -> CH2 */ <20 3>, /* PRU1_ARM -> CH3 */ <21 0>, /* ARM_PRU0 -> CH0 */ <22 1>, /* ARM_PRU1 -> CH1 */ <24 4>, /* VRING Host->PRU0 -> CH4 */ <25 5>, /* VRING PRU0->Host -> CH5 */ <26 6>, /* VRING Host->PRU1 -> CH6 */ <27 7>; /* VRING PRU1->Host -> CH7 */ /* channel to host interrupt map */ channel-to-host-interrupt-map = <0 0>, /* CH0 -> PRU0 */ <1 1>, /* CH1 -> PRU1 */ <2 2>, /* CH2 -> EVTOUT0 */ <3 3>, /* CH3 -> EVTOUT1 */ <4 0>, /* CH4 -> PRU0 */ <5 6>, /* CH5 -> EVTOUT4 */ <6 1>, /* CH6 -> PRU1 */ <7 7>; /* CH7 -> EVTOUT5 */ /* indices are ARM=0, PRU0=1, PRU1=2 */ target-to-sysevent-map = <0xffffffff 21 22>, /* ARM: DONTCARE, ARM_PRU0, ARM_PRU1 */ < 19 0xffffffff 17>, /* PRU0: PRU0_ARM, DONTCARE, PRU0_PRU1 */ < 20 18 0xffffffff>; /* PRU1: PRU1_ARM, PRU1_PRU0, DONTCARE */ /* both the PRUs have 200MHz frequency so period is 5ns */ clock-freq = <200000000>; /* the linux pwms we support */ pru-pwm-channels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 21>; /* first PRU controls the PWMs */ pru-pwm-controller = <0>; /* the IDs of the downcalls the firmware expects for PWMs */ /* CONFIG=0, ENABLE=1, DISABLE=2 */ pru-pwm-dc-ids = <0 1 2>; /* definition for the first PRU */ pru0 { pru-index = <0>; /* offset, size, local */ iram = <0x34000 0x02000 0x00000>; /* code ram (8K) */ /* offset, size, local, other */ dram = <0x00000 0x02000 0x00000 0x10000>; /* data ram (8K) */ pctrl = <0x22000>; pdbg = <0x22400>; firmware-elf; firmware = "testpru0"; /* sysevents signaling ring activity (host, pru)*/ vring-sysev = <24 25>; resource_table { resource-table; version = <1>; pru0_rproc_serial: pru0_vdev_rproc_serial { vdev-rproc-serial; /* notification IDs are totally bogus */ /* rproc will idr_alloc anyway */ notifyid = <8>; /* <- bogus */ /* da align num notifyid */ vring-0 = <0 16 8 0>; vring-1 = <0 16 8 0>; }; }; }; /* definition for the second PRU */ pru1 { pru-index = <1>; /* offset, size, local */ iram = <0x38000 0x02000 0x00000>; /* code ram (8K) */ /* offset, size, local, other */ dram = <0x02000 0x02000 0x00000 0x10000>; /* data ram (8K) */ pctrl = <0x24000>; pdbg = <0x24400>; firmware-elf; firmware = "pwmpru1"; /* NOTE: no resource table, no vrings for this one */ }; }; }; }; };