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CTCaer
GitHub Repository: CTCaer/hekate
 Path: blob/master/bdk/soc/pmc.h
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/*

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 * Copyright (c) 2018 naehrwert

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 * Copyright (c) 2018 st4rk

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 * Copyright (c) 2018-2026 CTCaer

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 *

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 * This program is free software; you can redistribute it and/or modify it

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 * under the terms and conditions of the GNU General Public License,

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 * version 2, as published by the Free Software Foundation.

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 *

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 * This program is distributed in the hope it will be useful, but WITHOUT

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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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 * more details.

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 *

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 * You should have received a copy of the GNU General Public License

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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

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 */

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#ifndef _PMC_H_

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#define _PMC_H_

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#include <utils/types.h>

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#include <soc/pmc_t210.h>

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typedef enum _pmc_sec_lock_t

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{

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	PMC_SEC_LOCK_MISC           = BIT(0),

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	PMC_SEC_LOCK_LP0_PARAMS     = BIT(1),

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	PMC_SEC_LOCK_RST_VECTOR     = BIT(2),

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	PMC_SEC_LOCK_CARVEOUTS      = BIT(3),

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	PMC_SEC_LOCK_TZ_CMAC_W      = BIT(4),

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	PMC_SEC_LOCK_TZ_CMAC_R      = BIT(5),

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	PMC_SEC_LOCK_TZ_KEK_W       = BIT(6),

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	PMC_SEC_LOCK_TZ_KEK_R       = BIT(7),

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	PMC_SEC_LOCK_SE_SRK         = BIT(8),

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	PMC_SEC_LOCK_SE2_SRK_B01    = BIT(9),

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	PMC_SEC_LOCK_MISC_B01       = BIT(10),

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	PMC_SEC_LOCK_CARVEOUTS_L4T  = BIT(11),

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	PMC_SEC_LOCK_LP0_PARAMS_B01 = BIT(12),

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} pmc_sec_lock_t;

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typedef enum _pmc_power_rail_t

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{

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	POWER_RAIL_CRAIL = 0,

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	POWER_RAIL_VE    = 2,

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	POWER_RAIL_PCIE  = 3,

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	POWER_RAIL_NVENC = 6,

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	POWER_RAIL_SATA  = 8,

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	POWER_RAIL_CE1   = 9,

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	POWER_RAIL_CE2   = 10,

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	POWER_RAIL_CE3   = 11,

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	POWER_RAIL_CELP  = 12,

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	POWER_RAIL_CE0   = 14,

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	POWER_RAIL_C0NC  = 15,

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	POWER_RAIL_C1NC  = 16,

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	POWER_RAIL_SOR   = 17,

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	POWER_RAIL_DIS   = 18,

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	POWER_RAIL_DISB  = 19,

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	POWER_RAIL_XUSBA = 20,

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	POWER_RAIL_XUSBB = 21,

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	POWER_RAIL_XUSBC = 22,

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	POWER_RAIL_VIC   = 23,

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	POWER_RAIL_IRAM  = 24,

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	POWER_RAIL_NVDEC = 25,

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	POWER_RAIL_NVJPG = 26,

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	POWER_RAIL_AUD   = 27,

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	POWER_RAIL_DFD   = 28,

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	POWER_RAIL_VE2   = 29

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} pmc_power_rail_t;

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void pmc_scratch_lock(pmc_sec_lock_t lock_mask);

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int  pmc_domain_pwrgate_set(pmc_power_rail_t part, u32 enable);

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#endif

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