Path: blob/master/modules/hekate_libsys_minerva/mtc_mc_emc_regs.h
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/*1* Minerva Training Cell2* DRAM Training for Tegra X1 SoC. Supports LPDDR4.3*4* Copyright (c) 2018-2025 CTCaer <[email protected]>5*6* This program is free software; you can redistribute it and/or modify it7* under the terms and conditions of the GNU General Public License,8* version 2, as published by the Free Software Foundation.9*10* This program is distributed in the hope it will be useful, but WITHOUT11* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or12* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for13* more details.14*15* You should have received a copy of the GNU General Public License16* along with this program. If not, see <http://www.gnu.org/licenses/>.17*/1819#ifndef _MTC_MC_EMC_REGS_H_20#define _MTC_MC_EMC_REGS_H_2122/* APB misc registers */23#define APB_MISC_GP_HIDREV 0x80424#define HIDREV_MAJOR_T210 0x125#define HIDREV_MAJOR_T210B01 0x226#define HIDREV_CHIPID_T210 0x212728/* Fuse registers */29#define FUSE_SKU_INFO 0x11030#define SKU_ODIN 0x833132/* Clock controller registers */33#define CLK_RST_CONTROLLER_PLLM_BASE 0x9034#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C35#define PLLM_ENABLE (1 << 30)36#define PLLM_LOCK (1 << 27)37#define PLLM_EN_LCKDET (1 << 4)3839#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C40#define EMC_2X_CLK_SRC_SHIFT 294142#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x28043#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x28444#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR 0x28845#define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E846#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x66447#define EMC_DLL_PLLM_VCOB (1 << 10)48#define EMC_DLL_SWITCH_OUT (1 << 11)4950#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE 0x7245152/* Memory controller registers */53#define MC_EMEM_ADR_CFG 0x5454#define MC_EMEM_ARB_CFG 0x9055#define MC_EMEM_ARB_OUTSTANDING_REQ 0x9456#define MC_EMEM_ARB_TIMING_RCD 0x9857#define MC_EMEM_ARB_TIMING_RP 0x9C58#define MC_EMEM_ARB_TIMING_RC 0xA059#define MC_EMEM_ARB_TIMING_RAS 0xA460#define MC_EMEM_ARB_TIMING_FAW 0xA861#define MC_EMEM_ARB_TIMING_RRD 0xAC62#define MC_EMEM_ARB_TIMING_RAP2PRE 0xB063#define MC_EMEM_ARB_TIMING_WAP2PRE 0xB464#define MC_EMEM_ARB_TIMING_R2R 0xB865#define MC_EMEM_ARB_TIMING_W2W 0xBC66#define MC_EMEM_ARB_TIMING_R2W 0xC067#define MC_EMEM_ARB_TIMING_W2R 0xC468#define MC_EMEM_ARB_MISC2 0xC869#define MC_EMEM_ARB_DA_TURNS 0xD070#define MC_EMEM_ARB_DA_COVERS 0xD471#define MC_EMEM_ARB_MISC0 0xD872#define MC_EMEM_ARB_MISC1 0xDC73#define MC_EMEM_ARB_RING1_THROTTLE 0xE07475#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2E476#define MC_LATENCY_ALLOWANCE_HC_0 0x31077#define MC_LATENCY_ALLOWANCE_HC_1 0x31478#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x32079#define MC_LATENCY_ALLOWANCE_NVENC_0 0x32880#define MC_LATENCY_ALLOWANCE_PPCS_0 0x34481#define MC_LATENCY_ALLOWANCE_PPCS_1 0x34882#define MC_LATENCY_ALLOWANCE_ISP2_0 0x37083#define MC_LATENCY_ALLOWANCE_ISP2_1 0x37484#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37C85#define MC_LATENCY_ALLOWANCE_XUSB_1 0x38086#define MC_LATENCY_ALLOWANCE_TSEC_0 0x39087#define MC_LATENCY_ALLOWANCE_VIC_0 0x39488#define MC_LATENCY_ALLOWANCE_VI2_0 0x39889#define MC_LATENCY_ALLOWANCE_GPU_0 0x3AC90#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3B891#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3BC92#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3C093#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3C494#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3D895#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3E89697#define MC_MLL_MPCORER_PTSA_RATE 0x44C98#define MC_FTOP_PTSA_RATE 0x50C99100#define MC_EMEM_ARB_TIMING_RFCPB 0x6C0101#define MC_EMEM_ARB_TIMING_CCDMW 0x6C4102#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6F0103#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6F4104105#define MC_PTSA_GRANT_DECREMENT 0x960106107#define MC_EMEM_ARB_DHYST_CTRL 0xBCC108#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xBD0109#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xBD4110#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xBD8111#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xBDC112#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xBE0113#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xBE4114#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xBE8115#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xBEC116117/* External Memory controller registers */118#define EMC_INTSTATUS 0x0119#define CLKCHANGE_COMPLETE_INT (1 << 4)120121#define EMC_DBG 0x8122#define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)123#define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)124#define EMC_DBG_CFG_SWAP_ACTIVE_ONLY (0 << 26u)125#define EMC_DBG_CFG_SWAP_SWAP (1 << 26u)126#define EMC_DBG_CFG_SWAP_ASSEMBLY_ONLY (2 << 26u)127#define EMC_DBG_CFG_SWAP_MASK (3 << 26u)128#define EMC_DBG_WRITE_ACTIVE_ONLY BIT(30)129#define EMC_CFG 0xC130#define EMC_PIN 0x24131#define EMC_TIMING_CONTROL 0x28132#define EMC_RC 0x2C133#define EMC_RFC 0x30134#define EMC_RAS 0x34135#define EMC_RP 0x38136#define EMC_R2W 0x3C137#define EMC_W2R 0x40138#define EMC_R2P 0x44139#define EMC_W2P 0x48140#define EMC_RD_RCD 0x4C141#define EMC_WR_RCD 0x50142#define EMC_RRD 0x54143#define EMC_REXT 0x58144#define EMC_WDV 0x5C145#define EMC_QUSE 0x60146#define EMC_QRST 0x64147#define EMC_QSAFE 0x68148#define EMC_RDV 0x6C149#define EMC_REFRESH 0x70150#define EMC_BURST_REFRESH_NUM 0x74151#define EMC_PDEX2WR 0x78152#define EMC_PDEX2RD 0x7C153#define EMC_PCHG2PDEN 0x80154#define EMC_ACT2PDEN 0x84155#define EMC_AR2PDEN 0x88156#define EMC_RW2PDEN 0x8C157#define EMC_TXSR 0x90158#define EMC_TCKE 0x94159#define EMC_TFAW 0x98160#define EMC_TRPAB 0x9C161#define EMC_TCLKSTABLE 0xA0162#define EMC_TCLKSTOP 0xA4163#define EMC_TREFBW 0xA8164#define EMC_TPPD 0xAC165#define EMC_ODT_WRITE 0xB0166#define EMC_PDEX2MRR 0xB4167#define EMC_WEXT 0xB8168#define EMC_RFC_SLR 0xC0169#define EMC_MRS_WAIT_CNT2 0xC4170#define EMC_MRS_WAIT_CNT 0xC8171#define EMC_MRS 0xCC172#define EMC_EMRS 0xD0173#define EMC_REF 0xD4174#define EMC_MRW 0xE8175#define EMC_SELF_REF 0xE0176#define EMC_MRR 0xEC177#define EMC_FBIO_SPARE 0x100178#define EMC_FBIO_CFG5 0x104179#define EMC_PDEX2CKE 0x118180#define EMC_CKE2PDEN 0x11C181#define EMC_MPC 0x128182#define EMC_EMRS2 0x12C183#define EMC_MRW2 0x134184#define EMC_MRW3 0x138185#define EMC_MRW4 0x13C186#define EMC_R2R 0x144187#define EMC_EINPUT 0x14C188#define EMC_EINPUT_DURATION 0x150189#define EMC_PUTERM_EXTRA 0x154190#define EMC_TCKESR 0x158191#define EMC_TPD 0x15C192#define EMC_AUTO_CAL_CONFIG 0x2A4193194#define EMC_EMC_STATUS 0x2B4195#define TIMING_UPDATE_STALLED (1 << 23)196#define MRR_DIVLD (1 << 20)197#define IN_SELF_REFRESH_MASK (3 << 8)198#define IN_POWERDOWN_BOTH_MASK (3 << 4)199#define IN_POWERDOWN_1DEV_MASK (1 << 4)200#define REQ_FIFO_EMPTY (1 << 0)201202#define EMC_CFG_2 0x2B8203#define EMC_CFG_DIG_DLL 0x2BC204#define EMC_CFG_DIG_DLL_PERIOD 0x2C0205#define EMC_DIG_DLL_STATUS 0x2C4206#define EMC_RDV_MASK 0x2CC207#define EMC_WDV_MASK 0x2D0208#define EMC_RDV_EARLY_MASK 0x2D4209#define EMC_RDV_EARLY 0x2D8210#define EMC_AUTO_CAL_CONFIG8 0x2DC211#define EMC_ZCAL_INTERVAL 0x2E0212#define EMC_ZCAL_WAIT_CNT 0x2E4213#define EMC_ZQ_CAL 0x2EC214#define EMC_FDPD_CTRL_DQ 0x310215#define EMC_FDPD_CTRL_CMD 0x314216#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318217#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31C218#define EMC_SCRATCH0 0x324219#define EMC_PMACRO_BRICK_CTRL_RFU1 0x330220#define EMC_PMACRO_BRICK_CTRL_RFU2 0x334221#define EMC_TR_TIMING_0 0x3B4222#define EMC_TR_CTRL_0 0x3B8223#define EMC_TR_CTRL_1 0x3BC224#define EMC_SWITCH_BACK_CTRL 0x3C0225#define EMC_TR_RDV 0x3C4226#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3CC227#define EMC_SEL_DPD_CTRL 0x3D8228#define EMC_PRE_REFRESH_REQ_CNT 0x3DC229#define EMC_DYN_SELF_REF_CONTROL 0x3E0230#define EMC_TXSRDLL 0x3E4231#define EMC_CCFIFO_ADDR 0x3E8232#define EMC_CCFIFO_DATA 0x3EC233#define EMC_CCFIFO_STATUS 0x3F0234#define EMC_TR_QPOP 0x3F4235#define EMC_TR_RDV_MASK 0x3F8236#define EMC_TR_QSAFE 0x3FC237#define EMC_TR_QRST 0x400238#define EMC_AUTO_CAL_CONFIG2 0x458239#define EMC_AUTO_CAL_CONFIG3 0x45C240#define EMC_TR_DVFS 0x460241#define EMC_AUTO_CAL_CHANNEL 0x464242#define EMC_IBDLY 0x468243#define EMC_OBDLY 0x46c244#define EMC_TXDSRVTTGEN 0x480245#define EMC_WE_DURATION 0x48C246#define EMC_WS_DURATION 0x490247#define EMC_WEV 0x494248#define EMC_WSV 0x498249#define EMC_CFG_3 0x49C250#define EMC_MRW6 0x4A4251#define EMC_MRW7 0x4A8252#define EMC_MRW8 0x4AC253#define EMC_MRW14 0x4C4254#define EMC_MRW15 0x4D0255#define EMC_CFG_SYNC 0x4D4256#define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4D8257#define EMC_WDV_CHK 0x4E0258#define EMC_CFG_PIPE_2 0x554259#define EMC_CFG_PIPE_CLK 0x558260#define EMC_CFG_PIPE_1 0x55C261#define EMC_CFG_PIPE 0x560262#define EMC_QPOP 0x564263#define EMC_QUSE_WIDTH 0x568264#define EMC_PUTERM_WIDTH 0x56C265#define EMC_AUTO_CAL_CONFIG7 0x574266#define EMC_REFCTRL2 0x580267#define EMC_FBIO_CFG7 0x584268269#define EMC_DATA_BRLSHFT_0 0x588270#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0271#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3272#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT 6273#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT 9274#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT 12275#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT 15276#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT 18277#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT 21278279#define EMC_DATA_BRLSHFT_1 0x58C280#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0281#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3282#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT 6283#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT 9284#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT 12285#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT 15286#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT 18287#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT 21288289#define EMC_RFCPB 0x590290#define EMC_DQS_BRLSHFT_0 0x594291#define EMC_DQS_BRLSHFT_1 0x598292#define EMC_CMD_BRLSHFT_0 0x59C293#define EMC_CMD_BRLSHFT_1 0x5A0294#define EMC_CMD_BRLSHFT_2 0x5A4295#define EMC_CMD_BRLSHFT_3 0x5A8296#define EMC_QUSE_BRLSHFT_0 0x5AC297#define EMC_AUTO_CAL_CONFIG4 0x5B0298#define EMC_AUTO_CAL_CONFIG5 0x5B4299#define EMC_QUSE_BRLSHFT_1 0x5B8300#define EMC_QUSE_BRLSHFT_2 0x5BC301#define EMC_CCDMW 0x5C0302#define EMC_QUSE_BRLSHFT_3 0x5C4303#define EMC_AUTO_CAL_CONFIG6 0x5CC304#define EMC_DLL_CFG_0 0x5E4305#define EMC_DLL_CFG_1 0x5E8306#define EMC_CONFIG_SAMPLE_DELAY 0x5F0307#define EMC_CFG_UPDATE 0x5F4308309#define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600310#define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604311#define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608312#define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60C313#define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610314#define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614315#define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630316#define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634317#define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620318#define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624319#define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628320#define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62C321322#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640323#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644324#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648325#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64C326#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650327#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654328#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660329#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664330#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668331#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66C332#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670333#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674334335#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680336#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684337#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688338#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68C339#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690340#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694341#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6A0342#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6A4343#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6A8344#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6AC345#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6B0346#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6B4347348#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6C0349#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6C4350#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6C8351#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6CC352#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6E0353#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6E4354#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6E8355#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6EC356357#define EMC_PMACRO_TX_PWRD_0 0x720358#define EMC_PMACRO_TX_PWRD_1 0x724359#define EMC_PMACRO_TX_PWRD_2 0x728360#define EMC_PMACRO_TX_PWRD_3 0x72C361#define EMC_PMACRO_TX_PWRD_4 0x730362#define EMC_PMACRO_TX_PWRD_5 0x734363364#define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740365#define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744366#define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74C367#define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748368#define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750369#define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754370371#define EMC_PMACRO_DDLL_BYPASS 0x760372#define EMC_PMACRO_DDLL_PWRD_0 0x770373#define EMC_PMACRO_DDLL_PWRD_1 0x774374#define EMC_PMACRO_DDLL_PWRD_2 0x778375376#define EMC_PMACRO_CMD_CTRL_0 0x780377#define EMC_PMACRO_CMD_CTRL_1 0x784378#define EMC_PMACRO_CMD_CTRL_2 0x788379380#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800381#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804382#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808383#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80C384#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810385#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814386#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818387#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81C388#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820389#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824390#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828391#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82C392#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830393#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834394#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838395#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83C396#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840397#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844398#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848399#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84C400#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850401#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854402#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858403#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85C404#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860405#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864406#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868407#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86C408#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870409#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874410#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878411#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87C412413#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880414#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884415#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888416#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88C417#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890418#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894419#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898420#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89C421#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8A0422#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8A4423#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8A8424#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8AC425#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8B0426#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8B4427#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8B8428#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8BC429430#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900431#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904432#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908433#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90C434#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910435#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914436#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918437#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91C438#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920439#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924440#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928441#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92C442#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930443#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934444#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938445#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93C446#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940447#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944448#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948449#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94C450#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950451#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954452#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958453#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95C454#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960455#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964456#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968457#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96C458#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970459#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974460#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978461#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97C462463#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980464#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984465#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988466#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98C467#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990468#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994469#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998470#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99C471#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9A0472#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9A4473#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9A8474#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9AC475#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9B0476#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9B4477#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9B8478#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9BC479480#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xA00481#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xA04482#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xA08483#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xA10484#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xA14485#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xA18486#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xA20487#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xA24488#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xA28489#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xA30490#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xA34491#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xA38492#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xA40493#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xA44494#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xA48495#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xA50496#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xA54497#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xA58498#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xA60499#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xA64500#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xA68501#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xA70502#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xA74503#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xA78504505#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xB00506#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xB04507#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xB08508#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xB10509#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xB14510#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xB18511#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xB20512#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xB24513#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xB28514#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xB30515#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xB34516#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xB38517#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xB40518#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xB44519#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xB48520#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xB50521#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xB54522#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xB58523#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xB60524#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xB64525#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xB68526#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xB70527#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xB74528#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xB78529530#define EMC_PMACRO_IB_VREF_DQ_0 0xBE0531#define EMC_PMACRO_IB_VREF_DQ_1 0xBE4532#define EMC_PMACRO_IB_VREF_DQS_0 0xBF0533#define EMC_PMACRO_IB_VREF_DQS_1 0xBF4534535#define EMC_PMACRO_DDLL_LONG_CMD_0 0xC00536#define EMC_PMACRO_DDLL_LONG_CMD_1 0xC04537#define EMC_PMACRO_DDLL_LONG_CMD_2 0xC08538#define EMC_PMACRO_DDLL_LONG_CMD_3 0xC0C539#define EMC_PMACRO_DDLL_LONG_CMD_4 0xC10540541#define EMC_PMACRO_DDLL_SHORT_CMD_0 0xC20542#define EMC_PMACRO_DDLL_SHORT_CMD_1 0xC24543#define EMC_PMACRO_DDLL_SHORT_CMD_2 0xC28544545#define EMC_PMACRO_CFG_PM_GLOBAL_0 0xC30546#define EMC_PMACRO_VTTGEN_CTRL_0 0xC34547#define EMC_PMACRO_VTTGEN_CTRL_1 0xC38548#define EMC_PMACRO_BG_BIAS_CTRL_0 0xC3C549#define EMC_PMACRO_PAD_CFG_CTRL 0xC40550#define EMC_PMACRO_ZCTRL 0xC44551#define EMC_PMACRO_CMD_PAD_RX_CTRL 0xC50552#define EMC_PMACRO_DATA_PAD_RX_CTRL 0xC54553#define EMC_PMACRO_CMD_RX_TERM_MODE 0xC58554#define EMC_PMACRO_DATA_RX_TERM_MODE 0xC5C555#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xC60556#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xC64557#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xC68558#define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xC78559#define EMC_PMACRO_VTTGEN_CTRL_2 0xCF0560#define EMC_PMACRO_IB_RXRT 0xCF4561#define EMC_PMACRO_TRAINING_CTRL_0 0xCF8562#define CH0_TRAINING_E_WRPTR (1 << 3)563#define EMC_PMACRO_TRAINING_CTRL_1 0xCFC564565#define EMC_TRAINING_CMD 0xE00566#define EMC_TRAINING_CTRL 0xE04567#define EMC_TRAINING_STATUS 0xE08568#define EMC_TRAINING_QUSE_CORS_CTRL 0xE0C569#define EMC_TRAINING_QUSE_FINE_CTRL 0xE10570#define EMC_TRAINING_QUSE_CTRL_MISC 0xE14571#define EMC_TRAINING_WRITE_FINE_CTRL 0xE18572#define EMC_TRAINING_WRITE_CTRL_MISC 0xE1C573#define EMC_TRAINING_WRITE_VREF_CTRL 0xE20574#define EMC_TRAINING_READ_FINE_CTRL 0xE24575#define EMC_TRAINING_READ_CTRL_MISC 0xE28576#define EMC_TRAINING_READ_VREF_CTRL 0xE2C577#define EMC_TRAINING_CA_FINE_CTRL 0xE30578#define EMC_TRAINING_CA_CTRL_MISC 0xE34579#define EMC_TRAINING_CA_CTRL_MISC1 0xE38580#define EMC_TRAINING_CA_VREF_CTRL 0xE3C581#define EMC_TRAINING_SETTLE 0xE44582#define EMC_TRAINING_MPC 0xE5C583#define EMC_TRAINING_PATRAM_CTRL 0xE60584#define EMC_TRAINING_PATRAM_DQ 0xE64585#define EMC_TRAINING_PATRAM_DMI 0xE68586#define EMC_TRAINING_VREF_SETTLE 0xE6C587#define EMC_TRAINING_OPT_CA_VREF 0xEC0588#define EMC_TRAINING_OPT_DQ_OB_VREF 0xEC4589#define EMC_TRAINING_QUSE_VREF_CTRL 0xED0590#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xED4591#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xED8592593/* Per channel registers offsets. Should be used with EMC_BASE */594#define EMC0_MRW10 0x34B4595#define EMC0_MRW11 0x34B8596#define EMC0_MRW12 0x34BC597#define EMC0_MRW13 0x34C0598#define EMC0_DATA_BRLSHFT_0 0x3588599#define EMC0_DATA_BRLSHFT_1 0x358C600#define EMC0_CMD_BRLSHFT_0 0x359C601#define EMC0_QUSE_BRLSHFT_0 0x35AC602#define EMC0_QUSE_BRLSHFT_2 0x35BC603#define EMC0_TRAINING_RW_OFFSET_IB_BYTE0 0x3E98604#define EMC0_TRAINING_RW_OFFSET_IB_BYTE1 0x3E9C605#define EMC0_TRAINING_RW_OFFSET_IB_BYTE2 0x3EA0606#define EMC0_TRAINING_RW_OFFSET_IB_BYTE3 0x3EA4607#define EMC0_TRAINING_RW_OFFSET_IB_MISC 0x3EA8608#define EMC0_TRAINING_RW_OFFSET_OB_BYTE0 0x3EAC609#define EMC0_TRAINING_RW_OFFSET_OB_BYTE1 0x3EB0610#define EMC0_TRAINING_RW_OFFSET_OB_BYTE2 0x3EB4611#define EMC0_TRAINING_RW_OFFSET_OB_BYTE3 0x3EB8612#define EMC0_TRAINING_RW_OFFSET_OB_MISC 0x3EBC613#define EMC0_TRAINING_OPT_DQS_IB_VREF_RANK0 0x3ED4614#define EMC0_TRAINING_OPT_DQS_IB_VREF_RANK1 0x3ED8615616#define EMC1_MRW10 0x44B4617#define EMC1_MRW11 0x44B8618#define EMC1_MRW12 0x44BC619#define EMC1_MRW13 0x44C0620#define EMC1_DATA_BRLSHFT_0 0x4588621#define EMC1_DATA_BRLSHFT_1 0x458C622#define EMC1_CMD_BRLSHFT_1 0x45A0623#define EMC1_QUSE_BRLSHFT_1 0x45B8624#define EMC1_QUSE_BRLSHFT_3 0x45C4625#define EMC1_TRAINING_RW_OFFSET_IB_BYTE0 0x4E98626#define EMC1_TRAINING_RW_OFFSET_IB_BYTE1 0x4E9C627#define EMC1_TRAINING_RW_OFFSET_IB_BYTE2 0x4EA0628#define EMC1_TRAINING_RW_OFFSET_IB_BYTE3 0x4EA4629#define EMC1_TRAINING_RW_OFFSET_IB_MISC 0x4EA8630#define EMC1_TRAINING_RW_OFFSET_OB_BYTE0 0x4EAC631#define EMC1_TRAINING_RW_OFFSET_OB_BYTE1 0x4EB0632#define EMC1_TRAINING_RW_OFFSET_OB_BYTE2 0x4EB4633#define EMC1_TRAINING_RW_OFFSET_OB_BYTE3 0x4EB8634#define EMC1_TRAINING_RW_OFFSET_OB_MISC 0x4EBC635#define EMC1_TRAINING_OPT_DQS_IB_VREF_RANK0 0x4ED4636#define EMC1_TRAINING_OPT_DQS_IB_VREF_RANK1 0x4ED8637638#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE0_SHIFT 0639#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE1_SHIFT 16640#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE2_SHIFT 0641#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE3_SHIFT 16642#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE4_SHIFT 0643#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE5_SHIFT 16644#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE6_SHIFT 0645#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE7_SHIFT 16646647#endif648649650