icache_bsd_aarch64.hpp

/*
 * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved.
 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
 * Copyright (c) 2021, Azul Systems, Inc. All rights reserved.
 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 *
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 * under the terms of the GNU General Public License version 2 only, as
 * published by the Free Software Foundation.
 *
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * version 2 for more details (a copy is included in the LICENSE file that
 * accompanied this code).
 *
 * You should have received a copy of the GNU General Public License version
 * 2 along with this work; if not, write to the Free Software Foundation,
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#ifndef OS_CPU_BSD_AARCH64_ICACHE_AARCH64_HPP
#define OS_CPU_BSD_AARCH64_ICACHE_AARCH64_HPP

#include <libkern/OSCacheControl.h>

// Interface for updating the instruction cache.  Whenever the VM
// modifies code, part of the processor instruction cache potentially
// has to be flushed.

class ICache : public AbstractICache {
 public:
  static void initialize();
  static void __clear_cache_(void *start, void *end) {
    sys_icache_invalidate(start, (char *)end-(char *)start);
  }
  static void invalidate_word(address addr) {
    __clear_cache_((char *)addr, (char *)(addr + 4));
  }
  static void invalidate_range(address start, int nbytes) {
    __clear_cache_((char *)start, (char *)(start + nbytes));
  }
};

#endif // OS_CPU_BSD_AARCH64_ICACHE_AARCH64_HPP