Path: blob/master/test/hotspot/gtest/aarch64/asmtest.out.h
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// BEGIN Generated code -- do not edit1// Generated by aarch64-asmtest.py2Label back, forth;3__ bind(back);45// ArithOp6__ add(r26, r23, r13, Assembler::LSL, 32); // add x26, x23, x13, LSL #327__ sub(r12, r24, r9, Assembler::LSR, 37); // sub x12, x24, x9, LSR #378__ adds(r28, r15, r8, Assembler::ASR, 39); // adds x28, x15, x8, ASR #399__ subs(r7, r28, r30, Assembler::ASR, 57); // subs x7, x28, x30, ASR #5710__ addw(r9, r22, r27, Assembler::ASR, 15); // add w9, w22, w27, ASR #1511__ subw(r3, r13, r17, Assembler::ASR, 30); // sub w3, w13, w17, ASR #3012__ addsw(r14, r26, r8, Assembler::ASR, 17); // adds w14, w26, w8, ASR #1713__ subsw(r0, r22, r12, Assembler::ASR, 21); // subs w0, w22, w12, ASR #2114__ andr(r0, r15, r26, Assembler::LSL, 20); // and x0, x15, x26, LSL #2015__ orr(r26, r5, r17, Assembler::LSL, 61); // orr x26, x5, x17, LSL #6116__ eor(r24, r13, r2, Assembler::LSL, 32); // eor x24, x13, x2, LSL #3217__ ands(r28, r3, r17, Assembler::ASR, 35); // ands x28, x3, x17, ASR #3518__ andw(r25, r16, r29, Assembler::LSR, 18); // and w25, w16, w29, LSR #1819__ orrw(r13, r17, r11, Assembler::LSR, 9); // orr w13, w17, w11, LSR #920__ eorw(r5, r5, r17, Assembler::LSR, 15); // eor w5, w5, w17, LSR #1521__ andsw(r2, r23, r27, Assembler::ASR, 26); // ands w2, w23, w27, ASR #2622__ bic(r27, r28, r16, Assembler::LSR, 45); // bic x27, x28, x16, LSR #4523__ orn(r8, r25, r26, Assembler::ASR, 37); // orn x8, x25, x26, ASR #3724__ eon(r29, r17, r13, Assembler::LSR, 63); // eon x29, x17, x13, LSR #6325__ bics(r28, r24, r2, Assembler::LSR, 31); // bics x28, x24, x2, LSR #3126__ bicw(r19, r26, r7, Assembler::ASR, 3); // bic w19, w26, w7, ASR #327__ ornw(r6, r24, r10, Assembler::ASR, 3); // orn w6, w24, w10, ASR #328__ eonw(r4, r21, r1, Assembler::LSR, 29); // eon w4, w21, w1, LSR #2929__ bicsw(r16, r21, r0, Assembler::LSR, 19); // bics w16, w21, w0, LSR #193031// AddSubImmOp32__ addw(r17, r12, 379u); // add w17, w12, #37933__ addsw(r30, r1, 22u); // adds w30, w1, #2234__ subw(r29, r5, 126u); // sub w29, w5, #12635__ subsw(r6, r24, 960u); // subs w6, w24, #96036__ add(r0, r13, 104u); // add x0, x13, #10437__ adds(r8, r6, 663u); // adds x8, x6, #66338__ sub(r10, r5, 516u); // sub x10, x5, #51639__ subs(r1, r3, 1012u); // subs x1, x3, #10124041// LogicalImmOp42__ andw(r6, r11, 4294049777ull); // and w6, w11, #0xfff1fff143__ orrw(r28, r5, 4294966791ull); // orr w28, w5, #0xfffffe0744__ eorw(r1, r20, 134217216ull); // eor w1, w20, #0x7fffe0045__ andsw(r7, r17, 1048576ull); // ands w7, w17, #0x10000046__ andr(r14, r12, 9223372036854775808ull); // and x14, x12, #0x800000000000000047__ orr(r9, r11, 562675075514368ull); // orr x9, x11, #0x1ffc00000000048__ eor(r17, r0, 18014398509481728ull); // eor x17, x0, #0x3fffffffffff0049__ ands(r1, r8, 18446744073705357315ull); // ands x1, x8, #0xffffffffffc000035051// AbsOp52__ b(__ pc()); // b .53__ b(back); // b back54__ b(forth); // b forth55__ bl(__ pc()); // bl .56__ bl(back); // bl back57__ bl(forth); // bl forth5859// RegAndAbsOp60__ cbzw(r10, __ pc()); // cbz w10, .61__ cbzw(r10, back); // cbz w10, back62__ cbzw(r10, forth); // cbz w10, forth63__ cbnzw(r8, __ pc()); // cbnz w8, .64__ cbnzw(r8, back); // cbnz w8, back65__ cbnzw(r8, forth); // cbnz w8, forth66__ cbz(r11, __ pc()); // cbz x11, .67__ cbz(r11, back); // cbz x11, back68__ cbz(r11, forth); // cbz x11, forth69__ cbnz(r29, __ pc()); // cbnz x29, .70__ cbnz(r29, back); // cbnz x29, back71__ cbnz(r29, forth); // cbnz x29, forth72__ adr(r19, __ pc()); // adr x19, .73__ adr(r19, back); // adr x19, back74__ adr(r19, forth); // adr x19, forth75__ _adrp(r19, __ pc()); // adrp x19, .7677// RegImmAbsOp78__ tbz(r22, 6, __ pc()); // tbz x22, #6, .79__ tbz(r22, 6, back); // tbz x22, #6, back80__ tbz(r22, 6, forth); // tbz x22, #6, forth81__ tbnz(r12, 11, __ pc()); // tbnz x12, #11, .82__ tbnz(r12, 11, back); // tbnz x12, #11, back83__ tbnz(r12, 11, forth); // tbnz x12, #11, forth8485// MoveWideImmOp86__ movnw(r0, 6301, 0); // movn w0, #6301, lsl 087__ movzw(r7, 20886, 0); // movz w7, #20886, lsl 088__ movkw(r27, 18617, 0); // movk w27, #18617, lsl 089__ movn(r12, 22998, 16); // movn x12, #22998, lsl 1690__ movz(r20, 1532, 16); // movz x20, #1532, lsl 1691__ movk(r8, 5167, 32); // movk x8, #5167, lsl 329293// BitfieldOp94__ sbfm(r15, r17, 24, 28); // sbfm x15, x17, #24, #2895__ bfmw(r15, r9, 14, 25); // bfm w15, w9, #14, #2596__ ubfmw(r27, r25, 6, 31); // ubfm w27, w25, #6, #3197__ sbfm(r19, r2, 23, 31); // sbfm x19, x2, #23, #3198__ bfm(r12, r21, 10, 6); // bfm x12, x21, #10, #699__ ubfm(r22, r0, 26, 16); // ubfm x22, x0, #26, #16100101// ExtractOp102__ extrw(r3, r3, r20, 27); // extr w3, w3, w20, #27103__ extr(r8, r30, r3, 54); // extr x8, x30, x3, #54104105// CondBranchOp106__ br(Assembler::EQ, __ pc()); // b.EQ .107__ br(Assembler::EQ, back); // b.EQ back108__ br(Assembler::EQ, forth); // b.EQ forth109__ br(Assembler::NE, __ pc()); // b.NE .110__ br(Assembler::NE, back); // b.NE back111__ br(Assembler::NE, forth); // b.NE forth112__ br(Assembler::HS, __ pc()); // b.HS .113__ br(Assembler::HS, back); // b.HS back114__ br(Assembler::HS, forth); // b.HS forth115__ br(Assembler::CS, __ pc()); // b.CS .116__ br(Assembler::CS, back); // b.CS back117__ br(Assembler::CS, forth); // b.CS forth118__ br(Assembler::LO, __ pc()); // b.LO .119__ br(Assembler::LO, back); // b.LO back120__ br(Assembler::LO, forth); // b.LO forth121__ br(Assembler::CC, __ pc()); // b.CC .122__ br(Assembler::CC, back); // b.CC back123__ br(Assembler::CC, forth); // b.CC forth124__ br(Assembler::MI, __ pc()); // b.MI .125__ br(Assembler::MI, back); // b.MI back126__ br(Assembler::MI, forth); // b.MI forth127__ br(Assembler::PL, __ pc()); // b.PL .128__ br(Assembler::PL, back); // b.PL back129__ br(Assembler::PL, forth); // b.PL forth130__ br(Assembler::VS, __ pc()); // b.VS .131__ br(Assembler::VS, back); // b.VS back132__ br(Assembler::VS, forth); // b.VS forth133__ br(Assembler::VC, __ pc()); // b.VC .134__ br(Assembler::VC, back); // b.VC back135__ br(Assembler::VC, forth); // b.VC forth136__ br(Assembler::HI, __ pc()); // b.HI .137__ br(Assembler::HI, back); // b.HI back138__ br(Assembler::HI, forth); // b.HI forth139__ br(Assembler::LS, __ pc()); // b.LS .140__ br(Assembler::LS, back); // b.LS back141__ br(Assembler::LS, forth); // b.LS forth142__ br(Assembler::GE, __ pc()); // b.GE .143__ br(Assembler::GE, back); // b.GE back144__ br(Assembler::GE, forth); // b.GE forth145__ br(Assembler::LT, __ pc()); // b.LT .146__ br(Assembler::LT, back); // b.LT back147__ br(Assembler::LT, forth); // b.LT forth148__ br(Assembler::GT, __ pc()); // b.GT .149__ br(Assembler::GT, back); // b.GT back150__ br(Assembler::GT, forth); // b.GT forth151__ br(Assembler::LE, __ pc()); // b.LE .152__ br(Assembler::LE, back); // b.LE back153__ br(Assembler::LE, forth); // b.LE forth154__ br(Assembler::AL, __ pc()); // b.AL .155__ br(Assembler::AL, back); // b.AL back156__ br(Assembler::AL, forth); // b.AL forth157__ br(Assembler::NV, __ pc()); // b.NV .158__ br(Assembler::NV, back); // b.NV back159__ br(Assembler::NV, forth); // b.NV forth160161// ImmOp162__ svc(12999); // svc #12999163__ hvc(2665); // hvc #2665164__ smc(9002); // smc #9002165__ brk(14843); // brk #14843166__ hlt(25964); // hlt #25964167168// Op169__ nop(); // nop170__ eret(); // eret171__ drps(); // drps172__ isb(); // isb173174// SystemOp175__ dsb(Assembler::ST); // dsb ST176__ dmb(Assembler::OSHST); // dmb OSHST177178// OneRegOp179__ br(r16); // br x16180__ blr(r20); // blr x20181182// LoadStoreExclusiveOp183__ stxr(r10, r27, r8); // stxr w10, x27, [x8]184__ stlxr(r0, r1, r21); // stlxr w0, x1, [x21]185__ ldxr(r17, r29); // ldxr x17, [x29]186__ ldaxr(r29, r28); // ldaxr x29, [x28]187__ stlr(r1, r23); // stlr x1, [x23]188__ ldar(r21, r20); // ldar x21, [x20]189190// LoadStoreExclusiveOp191__ stxrw(r22, r27, r19); // stxr w22, w27, [x19]192__ stlxrw(r11, r16, r6); // stlxr w11, w16, [x6]193__ ldxrw(r17, r0); // ldxr w17, [x0]194__ ldaxrw(r4, r10); // ldaxr w4, [x10]195__ stlrw(r24, r22); // stlr w24, [x22]196__ ldarw(r10, r19); // ldar w10, [x19]197198// LoadStoreExclusiveOp199__ stxrh(r1, r5, r30); // stxrh w1, w5, [x30]200__ stlxrh(r8, r12, r17); // stlxrh w8, w12, [x17]201__ ldxrh(r9, r14); // ldxrh w9, [x14]202__ ldaxrh(r7, r1); // ldaxrh w7, [x1]203__ stlrh(r5, r16); // stlrh w5, [x16]204__ ldarh(r2, r12); // ldarh w2, [x12]205206// LoadStoreExclusiveOp207__ stxrb(r10, r12, r3); // stxrb w10, w12, [x3]208__ stlxrb(r28, r14, r26); // stlxrb w28, w14, [x26]209__ ldxrb(r30, r10); // ldxrb w30, [x10]210__ ldaxrb(r14, r21); // ldaxrb w14, [x21]211__ stlrb(r13, r9); // stlrb w13, [x9]212__ ldarb(r22, r27); // ldarb w22, [x27]213214// LoadStoreExclusiveOp215__ ldxp(r28, r19, r11); // ldxp x28, x19, [x11]216__ ldaxp(r30, r19, r2); // ldaxp x30, x19, [x2]217__ stxp(r2, r23, r1, r0); // stxp w2, x23, x1, [x0]218__ stlxp(r12, r16, r13, r15); // stlxp w12, x16, x13, [x15]219220// LoadStoreExclusiveOp221__ ldxpw(r17, r21, r13); // ldxp w17, w21, [x13]222__ ldaxpw(r11, r30, r8); // ldaxp w11, w30, [x8]223__ stxpw(r24, r13, r11, r1); // stxp w24, w13, w11, [x1]224__ stlxpw(r26, r21, r27, r13); // stlxp w26, w21, w27, [x13]225226// base_plus_unscaled_offset227// LoadStoreOp228__ str(r11, Address(r20, -103)); // str x11, [x20, -103]229__ strw(r28, Address(r16, 62)); // str w28, [x16, 62]230__ strb(r27, Address(r9, -9)); // strb w27, [x9, -9]231__ strh(r2, Address(r25, -50)); // strh w2, [x25, -50]232__ ldr(r4, Address(r2, -241)); // ldr x4, [x2, -241]233__ ldrw(r30, Address(r20, -31)); // ldr w30, [x20, -31]234__ ldrb(r17, Address(r23, -23)); // ldrb w17, [x23, -23]235__ ldrh(r29, Address(r26, -1)); // ldrh w29, [x26, -1]236__ ldrsb(r1, Address(r9, 6)); // ldrsb x1, [x9, 6]237__ ldrsh(r11, Address(r12, 19)); // ldrsh x11, [x12, 19]238__ ldrshw(r11, Address(r1, -50)); // ldrsh w11, [x1, -50]239__ ldrsw(r19, Address(r24, 41)); // ldrsw x19, [x24, 41]240__ ldrd(v24, Address(r24, 95)); // ldr d24, [x24, 95]241__ ldrs(v15, Address(r5, -43)); // ldr s15, [x5, -43]242__ strd(v21, Address(r27, 1)); // str d21, [x27, 1]243__ strs(v23, Address(r13, -107)); // str s23, [x13, -107]244245// pre246// LoadStoreOp247__ str(r10, Address(__ pre(r0, 8))); // str x10, [x0, 8]!248__ strw(r3, Address(__ pre(r0, 29))); // str w3, [x0, 29]!249__ strb(r10, Address(__ pre(r14, 9))); // strb w10, [x14, 9]!250__ strh(r29, Address(__ pre(r25, -3))); // strh w29, [x25, -3]!251__ ldr(r12, Address(__ pre(r16, -144))); // ldr x12, [x16, -144]!252__ ldrw(r12, Address(__ pre(r22, -6))); // ldr w12, [x22, -6]!253__ ldrb(r13, Address(__ pre(r11, -10))); // ldrb w13, [x11, -10]!254__ ldrh(r0, Address(__ pre(r21, -21))); // ldrh w0, [x21, -21]!255__ ldrsb(r23, Address(__ pre(r6, 4))); // ldrsb x23, [x6, 4]!256__ ldrsh(r3, Address(__ pre(r7, -53))); // ldrsh x3, [x7, -53]!257__ ldrshw(r28, Address(__ pre(r4, -7))); // ldrsh w28, [x4, -7]!258__ ldrsw(r24, Address(__ pre(r8, -18))); // ldrsw x24, [x8, -18]!259__ ldrd(v14, Address(__ pre(r11, 12))); // ldr d14, [x11, 12]!260__ ldrs(v19, Address(__ pre(r12, -67))); // ldr s19, [x12, -67]!261__ strd(v20, Address(__ pre(r0, -253))); // str d20, [x0, -253]!262__ strs(v8, Address(__ pre(r0, 64))); // str s8, [x0, 64]!263264// post265// LoadStoreOp266__ str(r3, Address(__ post(r28, -94))); // str x3, [x28], -94267__ strw(r11, Address(__ post(r7, -54))); // str w11, [x7], -54268__ strb(r27, Address(__ post(r10, -24))); // strb w27, [x10], -24269__ strh(r6, Address(__ post(r7, 27))); // strh w6, [x7], 27270__ ldr(r13, Address(__ post(r10, -202))); // ldr x13, [x10], -202271__ ldrw(r15, Address(__ post(r5, -41))); // ldr w15, [x5], -41272__ ldrb(r2, Address(__ post(r13, 9))); // ldrb w2, [x13], 9273__ ldrh(r28, Address(__ post(r13, -20))); // ldrh w28, [x13], -20274__ ldrsb(r9, Address(__ post(r13, -31))); // ldrsb x9, [x13], -31275__ ldrsh(r3, Address(__ post(r24, -36))); // ldrsh x3, [x24], -36276__ ldrshw(r20, Address(__ post(r3, 6))); // ldrsh w20, [x3], 6277__ ldrsw(r7, Address(__ post(r19, -1))); // ldrsw x7, [x19], -1278__ ldrd(v30, Address(__ post(r8, -130))); // ldr d30, [x8], -130279__ ldrs(v25, Address(__ post(r15, 21))); // ldr s25, [x15], 21280__ strd(v14, Address(__ post(r23, 90))); // str d14, [x23], 90281__ strs(v8, Address(__ post(r0, -33))); // str s8, [x0], -33282283// base_plus_reg284// LoadStoreOp285__ str(r10, Address(r17, r21, Address::sxtw(3))); // str x10, [x17, w21, sxtw #3]286__ strw(r4, Address(r13, r22, Address::sxtw(2))); // str w4, [x13, w22, sxtw #2]287__ strb(r13, Address(r0, r19, Address::uxtw(0))); // strb w13, [x0, w19, uxtw #0]288__ strh(r12, Address(r27, r6, Address::sxtw(0))); // strh w12, [x27, w6, sxtw #0]289__ ldr(r0, Address(r8, r16, Address::lsl(0))); // ldr x0, [x8, x16, lsl #0]290__ ldrw(r0, Address(r4, r26, Address::sxtx(0))); // ldr w0, [x4, x26, sxtx #0]291__ ldrb(r14, Address(r25, r5, Address::sxtw(0))); // ldrb w14, [x25, w5, sxtw #0]292__ ldrh(r9, Address(r4, r17, Address::uxtw(0))); // ldrh w9, [x4, w17, uxtw #0]293__ ldrsb(r27, Address(r4, r7, Address::lsl(0))); // ldrsb x27, [x4, x7, lsl #0]294__ ldrsh(r15, Address(r17, r30, Address::sxtw(0))); // ldrsh x15, [x17, w30, sxtw #0]295__ ldrshw(r16, Address(r0, r22, Address::sxtw(0))); // ldrsh w16, [x0, w22, sxtw #0]296__ ldrsw(r22, Address(r10, r30, Address::sxtx(2))); // ldrsw x22, [x10, x30, sxtx #2]297__ ldrd(v29, Address(r21, r10, Address::sxtx(3))); // ldr d29, [x21, x10, sxtx #3]298__ ldrs(v3, Address(r11, r19, Address::uxtw(0))); // ldr s3, [x11, w19, uxtw #0]299__ strd(v13, Address(r28, r29, Address::uxtw(3))); // str d13, [x28, w29, uxtw #3]300__ strs(v23, Address(r29, r5, Address::sxtx(2))); // str s23, [x29, x5, sxtx #2]301302// base_plus_scaled_offset303// LoadStoreOp304__ str(r5, Address(r8, 12600)); // str x5, [x8, 12600]305__ strw(r29, Address(r24, 7880)); // str w29, [x24, 7880]306__ strb(r19, Address(r17, 1566)); // strb w19, [x17, 1566]307__ strh(r13, Address(r19, 3984)); // strh w13, [x19, 3984]308__ ldr(r19, Address(r23, 13632)); // ldr x19, [x23, 13632]309__ ldrw(r23, Address(r29, 6264)); // ldr w23, [x29, 6264]310__ ldrb(r22, Address(r11, 2012)); // ldrb w22, [x11, 2012]311__ ldrh(r3, Address(r10, 3784)); // ldrh w3, [x10, 3784]312__ ldrsb(r8, Address(r16, 1951)); // ldrsb x8, [x16, 1951]313__ ldrsh(r23, Address(r20, 3346)); // ldrsh x23, [x20, 3346]314__ ldrshw(r2, Address(r1, 3994)); // ldrsh w2, [x1, 3994]315__ ldrsw(r4, Address(r17, 7204)); // ldrsw x4, [x17, 7204]316__ ldrd(v20, Address(r27, 14400)); // ldr d20, [x27, 14400]317__ ldrs(v25, Address(r14, 8096)); // ldr s25, [x14, 8096]318__ strd(v26, Address(r10, 15024)); // str d26, [x10, 15024]319__ strs(v9, Address(r3, 6936)); // str s9, [x3, 6936]320321// pcrel322// LoadStoreOp323__ ldr(r27, forth); // ldr x27, forth324__ ldrw(r11, __ pc()); // ldr w11, .325326// LoadStoreOp327__ prfm(Address(r3, -187)); // prfm PLDL1KEEP, [x3, -187]328329// LoadStoreOp330__ prfm(__ pc()); // prfm PLDL1KEEP, .331332// LoadStoreOp333__ prfm(Address(r29, r14, Address::lsl(0))); // prfm PLDL1KEEP, [x29, x14, lsl #0]334335// LoadStoreOp336__ prfm(Address(r4, 13312)); // prfm PLDL1KEEP, [x4, 13312]337338// AddSubCarryOp339__ adcw(r21, r1, r7); // adc w21, w1, w7340__ adcsw(r8, r5, r7); // adcs w8, w5, w7341__ sbcw(r7, r27, r14); // sbc w7, w27, w14342__ sbcsw(r27, r4, r17); // sbcs w27, w4, w17343__ adc(r0, r28, r0); // adc x0, x28, x0344__ adcs(r12, r24, r30); // adcs x12, x24, x30345__ sbc(r0, r25, r15); // sbc x0, x25, x15346__ sbcs(r1, r24, r3); // sbcs x1, x24, x3347348// AddSubExtendedOp349__ addw(r17, r24, r20, ext::uxtb, 2); // add w17, w24, w20, uxtb #2350__ addsw(r13, r28, r10, ext::uxth, 1); // adds w13, w28, w10, uxth #1351__ sub(r15, r16, r2, ext::sxth, 2); // sub x15, x16, x2, sxth #2352__ subsw(r29, r13, r13, ext::uxth, 2); // subs w29, w13, w13, uxth #2353__ add(r12, r20, r12, ext::sxtw, 3); // add x12, x20, x12, sxtw #3354__ adds(r30, r27, r11, ext::sxtb, 1); // adds x30, x27, x11, sxtb #1355__ sub(r14, r7, r1, ext::sxtw, 2); // sub x14, x7, x1, sxtw #2356__ subs(r29, r3, r27, ext::sxth, 1); // subs x29, x3, x27, sxth #1357358// ConditionalCompareOp359__ ccmnw(r0, r13, 14u, Assembler::MI); // ccmn w0, w13, #14, MI360__ ccmpw(r22, r17, 6u, Assembler::CC); // ccmp w22, w17, #6, CC361__ ccmn(r17, r30, 14u, Assembler::VS); // ccmn x17, x30, #14, VS362__ ccmp(r10, r19, 12u, Assembler::HI); // ccmp x10, x19, #12, HI363364// ConditionalCompareImmedOp365__ ccmnw(r6, 18, 2, Assembler::LE); // ccmn w6, #18, #2, LE366__ ccmpw(r9, 13, 4, Assembler::HI); // ccmp w9, #13, #4, HI367__ ccmn(r21, 11, 11, Assembler::LO); // ccmn x21, #11, #11, LO368__ ccmp(r4, 13, 2, Assembler::VC); // ccmp x4, #13, #2, VC369370// ConditionalSelectOp371__ cselw(r12, r2, r22, Assembler::HI); // csel w12, w2, w22, HI372__ csincw(r24, r16, r17, Assembler::HS); // csinc w24, w16, w17, HS373__ csinvw(r6, r7, r16, Assembler::LT); // csinv w6, w7, w16, LT374__ csnegw(r11, r27, r22, Assembler::LS); // csneg w11, w27, w22, LS375__ csel(r10, r3, r29, Assembler::LT); // csel x10, x3, x29, LT376__ csinc(r12, r26, r27, Assembler::CC); // csinc x12, x26, x27, CC377__ csinv(r15, r10, r21, Assembler::GT); // csinv x15, x10, x21, GT378__ csneg(r30, r23, r9, Assembler::GT); // csneg x30, x23, x9, GT379380// TwoRegOp381__ rbitw(r30, r10); // rbit w30, w10382__ rev16w(r29, r15); // rev16 w29, w15383__ revw(r29, r30); // rev w29, w30384__ clzw(r25, r21); // clz w25, w21385__ clsw(r4, r0); // cls w4, w0386__ rbit(r17, r21); // rbit x17, x21387__ rev16(r29, r16); // rev16 x29, x16388__ rev32(r21, r20); // rev32 x21, x20389__ rev(r6, r19); // rev x6, x19390__ clz(r30, r3); // clz x30, x3391__ cls(r21, r19); // cls x21, x19392393// ThreeRegOp394__ udivw(r11, r24, r0); // udiv w11, w24, w0395__ sdivw(r27, r25, r14); // sdiv w27, w25, w14396__ lslvw(r3, r14, r17); // lslv w3, w14, w17397__ lsrvw(r7, r15, r24); // lsrv w7, w15, w24398__ asrvw(r28, r17, r25); // asrv w28, w17, w25399__ rorvw(r2, r26, r28); // rorv w2, w26, w28400__ udiv(r5, r25, r26); // udiv x5, x25, x26401__ sdiv(r27, r16, r17); // sdiv x27, x16, x17402__ lslv(r6, r21, r12); // lslv x6, x21, x12403__ lsrv(r0, r4, r12); // lsrv x0, x4, x12404__ asrv(r27, r17, r28); // asrv x27, x17, x28405__ rorv(r28, r2, r17); // rorv x28, x2, x17406__ umulh(r10, r15, r14); // umulh x10, x15, x14407__ smulh(r14, r3, r25); // smulh x14, x3, x25408409// FourRegMulOp410__ maddw(r15, r19, r14, r5); // madd w15, w19, w14, w5411__ msubw(r16, r4, r26, r25); // msub w16, w4, w26, w25412__ madd(r4, r2, r2, r12); // madd x4, x2, x2, x12413__ msub(r29, r17, r8, r7); // msub x29, x17, x8, x7414__ smaddl(r3, r4, r25, r4); // smaddl x3, w4, w25, x4415__ smsubl(r26, r25, r4, r17); // smsubl x26, w25, w4, x17416__ umaddl(r0, r26, r17, r23); // umaddl x0, w26, w17, x23417__ umsubl(r15, r21, r28, r17); // umsubl x15, w21, w28, x17418419// ThreeRegFloatOp420__ fabds(v27, v10, v3); // fabd s27, s10, s3421__ fmuls(v0, v7, v25); // fmul s0, s7, s25422__ fdivs(v9, v6, v15); // fdiv s9, s6, s15423__ fadds(v29, v15, v10); // fadd s29, s15, s10424__ fsubs(v2, v17, v7); // fsub s2, s17, s7425__ fabdd(v11, v11, v23); // fabd d11, d11, d23426__ fmuld(v7, v29, v23); // fmul d7, d29, d23427__ fdivd(v14, v27, v11); // fdiv d14, d27, d11428__ faddd(v11, v4, v24); // fadd d11, d4, d24429__ fsubd(v12, v15, v14); // fsub d12, d15, d14430431// FourRegFloatOp432__ fmadds(v20, v11, v28, v13); // fmadd s20, s11, s28, s13433__ fmsubs(v11, v12, v23, v30); // fmsub s11, s12, s23, s30434__ fnmadds(v26, v14, v9, v13); // fnmadd s26, s14, s9, s13435__ fnmadds(v10, v7, v5, v29); // fnmadd s10, s7, s5, s29436__ fmaddd(v15, v3, v11, v12); // fmadd d15, d3, d11, d12437__ fmsubd(v15, v30, v30, v17); // fmsub d15, d30, d30, d17438__ fnmaddd(v19, v20, v15, v15); // fnmadd d19, d20, d15, d15439__ fnmaddd(v9, v21, v2, v9); // fnmadd d9, d21, d2, d9440441// TwoRegFloatOp442__ fmovs(v27, v7); // fmov s27, s7443__ fabss(v29, v30); // fabs s29, s30444__ fnegs(v17, v1); // fneg s17, s1445__ fsqrts(v2, v6); // fsqrt s2, s6446__ fcvts(v10, v3); // fcvt d10, s3447__ fmovd(v24, v11); // fmov d24, d11448__ fabsd(v7, v1); // fabs d7, d1449__ fnegd(v11, v0); // fneg d11, d0450__ fsqrtd(v3, v17); // fsqrt d3, d17451__ fcvtd(v28, v6); // fcvt s28, d6452453// FloatConvertOp454__ fcvtzsw(r22, v6); // fcvtzs w22, s6455__ fcvtzs(r0, v27); // fcvtzs x0, s27456__ fcvtzdw(r26, v2); // fcvtzs w26, d2457__ fcvtzd(r5, v7); // fcvtzs x5, d7458__ scvtfws(v28, r11); // scvtf s28, w11459__ scvtfs(v25, r13); // scvtf s25, x13460__ scvtfwd(v11, r23); // scvtf d11, w23461__ scvtfd(v19, r8); // scvtf d19, x8462__ fmovs(r17, v21); // fmov w17, s21463__ fmovd(r25, v20); // fmov x25, d20464__ fmovs(v19, r17); // fmov s19, w17465__ fmovd(v2, r29); // fmov d2, x29466467// TwoRegFloatOp468__ fcmps(v22, v8); // fcmp s22, s8469__ fcmpd(v21, v19); // fcmp d21, d19470__ fcmps(v20, 0.0); // fcmp s20, #0.0471__ fcmpd(v11, 0.0); // fcmp d11, #0.0472473// LoadStorePairOp474__ stpw(r20, r6, Address(r15, -32)); // stp w20, w6, [x15, #-32]475__ ldpw(r27, r14, Address(r3, -208)); // ldp w27, w14, [x3, #-208]476__ ldpsw(r16, r10, Address(r11, -80)); // ldpsw x16, x10, [x11, #-80]477__ stp(r7, r7, Address(r14, 64)); // stp x7, x7, [x14, #64]478__ ldp(r12, r23, Address(r0, 112)); // ldp x12, x23, [x0, #112]479480// LoadStorePairOp481__ stpw(r13, r7, Address(__ pre(r6, -80))); // stp w13, w7, [x6, #-80]!482__ ldpw(r30, r15, Address(__ pre(r2, -144))); // ldp w30, w15, [x2, #-144]!483__ ldpsw(r4, r1, Address(__ pre(r27, -144))); // ldpsw x4, x1, [x27, #-144]!484__ stp(r23, r14, Address(__ pre(r11, 64))); // stp x23, x14, [x11, #64]!485__ ldp(r29, r27, Address(__ pre(r21, -192))); // ldp x29, x27, [x21, #-192]!486487// LoadStorePairOp488__ stpw(r22, r5, Address(__ post(r21, -48))); // stp w22, w5, [x21], #-48489__ ldpw(r27, r17, Address(__ post(r6, -32))); // ldp w27, w17, [x6], #-32490__ ldpsw(r16, r5, Address(__ post(r1, -80))); // ldpsw x16, x5, [x1], #-80491__ stp(r13, r20, Address(__ post(r22, -208))); // stp x13, x20, [x22], #-208492__ ldp(r30, r27, Address(__ post(r10, 80))); // ldp x30, x27, [x10], #80493494// LoadStorePairOp495__ stnpw(r5, r17, Address(r11, 16)); // stnp w5, w17, [x11, #16]496__ ldnpw(r14, r4, Address(r26, -96)); // ldnp w14, w4, [x26, #-96]497__ stnp(r23, r29, Address(r12, 32)); // stnp x23, x29, [x12, #32]498__ ldnp(r0, r6, Address(r21, -80)); // ldnp x0, x6, [x21, #-80]499500// LdStNEONOp501__ ld1(v15, __ T8B, Address(r26)); // ld1 {v15.8B}, [x26]502__ ld1(v23, v24, __ T16B, Address(__ post(r11, 32))); // ld1 {v23.16B, v24.16B}, [x11], 32503__ ld1(v8, v9, v10, __ T1D, Address(__ post(r23, r7))); // ld1 {v8.1D, v9.1D, v10.1D}, [x23], x7504__ ld1(v19, v20, v21, v22, __ T8H, Address(__ post(r25, 64))); // ld1 {v19.8H, v20.8H, v21.8H, v22.8H}, [x25], 64505__ ld1r(v29, __ T8B, Address(r17)); // ld1r {v29.8B}, [x17]506__ ld1r(v24, __ T4S, Address(__ post(r23, 4))); // ld1r {v24.4S}, [x23], 4507__ ld1r(v10, __ T1D, Address(__ post(r5, r25))); // ld1r {v10.1D}, [x5], x25508__ ld2(v17, v18, __ T2D, Address(r10)); // ld2 {v17.2D, v18.2D}, [x10]509__ ld2(v12, v13, __ T4H, Address(__ post(r15, 16))); // ld2 {v12.4H, v13.4H}, [x15], 16510__ ld2r(v25, v26, __ T16B, Address(r17)); // ld2r {v25.16B, v26.16B}, [x17]511__ ld2r(v1, v2, __ T2S, Address(__ post(r30, 8))); // ld2r {v1.2S, v2.2S}, [x30], 8512__ ld2r(v16, v17, __ T2D, Address(__ post(r17, r9))); // ld2r {v16.2D, v17.2D}, [x17], x9513__ ld3(v25, v26, v27, __ T4S, Address(__ post(r12, r2))); // ld3 {v25.4S, v26.4S, v27.4S}, [x12], x2514__ ld3(v26, v27, v28, __ T2S, Address(r19)); // ld3 {v26.2S, v27.2S, v28.2S}, [x19]515__ ld3r(v15, v16, v17, __ T8H, Address(r21)); // ld3r {v15.8H, v16.8H, v17.8H}, [x21]516__ ld3r(v25, v26, v27, __ T4S, Address(__ post(r13, 12))); // ld3r {v25.4S, v26.4S, v27.4S}, [x13], 12517__ ld3r(v14, v15, v16, __ T1D, Address(__ post(r28, r29))); // ld3r {v14.1D, v15.1D, v16.1D}, [x28], x29518__ ld4(v17, v18, v19, v20, __ T8H, Address(__ post(r29, 64))); // ld4 {v17.8H, v18.8H, v19.8H, v20.8H}, [x29], 64519__ ld4(v27, v28, v29, v30, __ T8B, Address(__ post(r7, r0))); // ld4 {v27.8B, v28.8B, v29.8B, v30.8B}, [x7], x0520__ ld4r(v24, v25, v26, v27, __ T8B, Address(r17)); // ld4r {v24.8B, v25.8B, v26.8B, v27.8B}, [x17]521__ ld4r(v0, v1, v2, v3, __ T4H, Address(__ post(r26, 8))); // ld4r {v0.4H, v1.4H, v2.4H, v3.4H}, [x26], 8522__ ld4r(v12, v13, v14, v15, __ T2S, Address(__ post(r25, r2))); // ld4r {v12.2S, v13.2S, v14.2S, v15.2S}, [x25], x2523524// NEONReduceInstruction525__ addv(v22, __ T8B, v23); // addv b22, v23.8B526__ addv(v27, __ T16B, v28); // addv b27, v28.16B527__ addv(v4, __ T4H, v5); // addv h4, v5.4H528__ addv(v7, __ T8H, v8); // addv h7, v8.8H529__ addv(v6, __ T4S, v7); // addv s6, v7.4S530__ smaxv(v1, __ T8B, v2); // smaxv b1, v2.8B531__ smaxv(v26, __ T16B, v27); // smaxv b26, v27.16B532__ smaxv(v15, __ T4H, v16); // smaxv h15, v16.4H533__ smaxv(v2, __ T8H, v3); // smaxv h2, v3.8H534__ smaxv(v13, __ T4S, v14); // smaxv s13, v14.4S535__ fmaxv(v13, __ T4S, v14); // fmaxv s13, v14.4S536__ sminv(v24, __ T8B, v25); // sminv b24, v25.8B537__ uminv(v23, __ T8B, v24); // uminv b23, v24.8B538__ sminv(v4, __ T16B, v5); // sminv b4, v5.16B539__ uminv(v19, __ T16B, v20); // uminv b19, v20.16B540__ sminv(v15, __ T4H, v16); // sminv h15, v16.4H541__ uminv(v0, __ T4H, v1); // uminv h0, v1.4H542__ sminv(v4, __ T8H, v5); // sminv h4, v5.8H543__ uminv(v20, __ T8H, v21); // uminv h20, v21.8H544__ sminv(v11, __ T4S, v12); // sminv s11, v12.4S545__ uminv(v29, __ T4S, v30); // uminv s29, v30.4S546__ fminv(v15, __ T4S, v16); // fminv s15, v16.4S547__ fmaxp(v21, v22, __ S); // fmaxp s21, v22.2S548__ fmaxp(v4, v5, __ D); // fmaxp d4, v5.2D549__ fminp(v14, v15, __ S); // fminp s14, v15.2S550__ fminp(v22, v23, __ D); // fminp d22, v23.2D551552// TwoRegNEONOp553__ absr(v25, __ T8B, v26); // abs v25.8B, v26.8B554__ absr(v6, __ T16B, v7); // abs v6.16B, v7.16B555__ absr(v12, __ T4H, v13); // abs v12.4H, v13.4H556__ absr(v14, __ T8H, v15); // abs v14.8H, v15.8H557__ absr(v13, __ T2S, v14); // abs v13.2S, v14.2S558__ absr(v14, __ T4S, v15); // abs v14.4S, v15.4S559__ absr(v9, __ T2D, v10); // abs v9.2D, v10.2D560__ fabs(v25, __ T2S, v26); // fabs v25.2S, v26.2S561__ fabs(v28, __ T4S, v29); // fabs v28.4S, v29.4S562__ fabs(v10, __ T2D, v11); // fabs v10.2D, v11.2D563__ fneg(v19, __ T2S, v20); // fneg v19.2S, v20.2S564__ fneg(v11, __ T4S, v12); // fneg v11.4S, v12.4S565__ fneg(v17, __ T2D, v18); // fneg v17.2D, v18.2D566__ fsqrt(v21, __ T2S, v22); // fsqrt v21.2S, v22.2S567__ fsqrt(v15, __ T4S, v16); // fsqrt v15.4S, v16.4S568__ fsqrt(v20, __ T2D, v21); // fsqrt v20.2D, v21.2D569__ notr(v23, __ T8B, v24); // not v23.8B, v24.8B570__ notr(v26, __ T16B, v27); // not v26.16B, v27.16B571572// ThreeRegNEONOp573__ andr(v5, __ T8B, v6, v7); // and v5.8B, v6.8B, v7.8B574__ andr(v6, __ T16B, v7, v8); // and v6.16B, v7.16B, v8.16B575__ orr(v15, __ T8B, v16, v17); // orr v15.8B, v16.8B, v17.8B576__ orr(v15, __ T16B, v16, v17); // orr v15.16B, v16.16B, v17.16B577__ eor(v25, __ T8B, v26, v27); // eor v25.8B, v26.8B, v27.8B578__ eor(v16, __ T16B, v17, v18); // eor v16.16B, v17.16B, v18.16B579__ addv(v27, __ T8B, v28, v29); // add v27.8B, v28.8B, v29.8B580__ addv(v24, __ T16B, v25, v26); // add v24.16B, v25.16B, v26.16B581__ addv(v15, __ T4H, v16, v17); // add v15.4H, v16.4H, v17.4H582__ addv(v25, __ T8H, v26, v27); // add v25.8H, v26.8H, v27.8H583__ addv(v14, __ T2S, v15, v16); // add v14.2S, v15.2S, v16.2S584__ addv(v10, __ T4S, v11, v12); // add v10.4S, v11.4S, v12.4S585__ addv(v13, __ T2D, v14, v15); // add v13.2D, v14.2D, v15.2D586__ fadd(v14, __ T2S, v15, v16); // fadd v14.2S, v15.2S, v16.2S587__ fadd(v20, __ T4S, v21, v22); // fadd v20.4S, v21.4S, v22.4S588__ fadd(v1, __ T2D, v2, v3); // fadd v1.2D, v2.2D, v3.2D589__ subv(v22, __ T8B, v23, v24); // sub v22.8B, v23.8B, v24.8B590__ subv(v30, __ T16B, v31, v0); // sub v30.16B, v31.16B, v0.16B591__ subv(v14, __ T4H, v15, v16); // sub v14.4H, v15.4H, v16.4H592__ subv(v2, __ T8H, v3, v4); // sub v2.8H, v3.8H, v4.8H593__ subv(v6, __ T2S, v7, v8); // sub v6.2S, v7.2S, v8.2S594__ subv(v3, __ T4S, v4, v5); // sub v3.4S, v4.4S, v5.4S595__ subv(v7, __ T2D, v8, v9); // sub v7.2D, v8.2D, v9.2D596__ fsub(v24, __ T2S, v25, v26); // fsub v24.2S, v25.2S, v26.2S597__ fsub(v0, __ T4S, v1, v2); // fsub v0.4S, v1.4S, v2.4S598__ fsub(v27, __ T2D, v28, v29); // fsub v27.2D, v28.2D, v29.2D599__ mulv(v29, __ T8B, v30, v31); // mul v29.8B, v30.8B, v31.8B600__ mulv(v5, __ T16B, v6, v7); // mul v5.16B, v6.16B, v7.16B601__ mulv(v5, __ T4H, v6, v7); // mul v5.4H, v6.4H, v7.4H602__ mulv(v29, __ T8H, v30, v31); // mul v29.8H, v30.8H, v31.8H603__ mulv(v11, __ T2S, v12, v13); // mul v11.2S, v12.2S, v13.2S604__ mulv(v25, __ T4S, v26, v27); // mul v25.4S, v26.4S, v27.4S605__ fabd(v0, __ T2S, v1, v2); // fabd v0.2S, v1.2S, v2.2S606__ fabd(v30, __ T4S, v31, v0); // fabd v30.4S, v31.4S, v0.4S607__ fabd(v0, __ T2D, v1, v2); // fabd v0.2D, v1.2D, v2.2D608__ fmul(v17, __ T2S, v18, v19); // fmul v17.2S, v18.2S, v19.2S609__ fmul(v28, __ T4S, v29, v30); // fmul v28.4S, v29.4S, v30.4S610__ fmul(v25, __ T2D, v26, v27); // fmul v25.2D, v26.2D, v27.2D611__ mlav(v9, __ T4H, v10, v11); // mla v9.4H, v10.4H, v11.4H612__ mlav(v25, __ T8H, v26, v27); // mla v25.8H, v26.8H, v27.8H613__ mlav(v12, __ T2S, v13, v14); // mla v12.2S, v13.2S, v14.2S614__ mlav(v15, __ T4S, v16, v17); // mla v15.4S, v16.4S, v17.4S615__ fmla(v11, __ T2S, v12, v13); // fmla v11.2S, v12.2S, v13.2S616__ fmla(v10, __ T4S, v11, v12); // fmla v10.4S, v11.4S, v12.4S617__ fmla(v17, __ T2D, v18, v19); // fmla v17.2D, v18.2D, v19.2D618__ mlsv(v24, __ T4H, v25, v26); // mls v24.4H, v25.4H, v26.4H619__ mlsv(v21, __ T8H, v22, v23); // mls v21.8H, v22.8H, v23.8H620__ mlsv(v23, __ T2S, v24, v25); // mls v23.2S, v24.2S, v25.2S621__ mlsv(v0, __ T4S, v1, v2); // mls v0.4S, v1.4S, v2.4S622__ fmls(v16, __ T2S, v17, v18); // fmls v16.2S, v17.2S, v18.2S623__ fmls(v10, __ T4S, v11, v12); // fmls v10.4S, v11.4S, v12.4S624__ fmls(v6, __ T2D, v7, v8); // fmls v6.2D, v7.2D, v8.2D625__ fdiv(v28, __ T2S, v29, v30); // fdiv v28.2S, v29.2S, v30.2S626__ fdiv(v6, __ T4S, v7, v8); // fdiv v6.4S, v7.4S, v8.4S627__ fdiv(v5, __ T2D, v6, v7); // fdiv v5.2D, v6.2D, v7.2D628__ maxv(v5, __ T8B, v6, v7); // smax v5.8B, v6.8B, v7.8B629__ maxv(v20, __ T16B, v21, v22); // smax v20.16B, v21.16B, v22.16B630__ maxv(v17, __ T4H, v18, v19); // smax v17.4H, v18.4H, v19.4H631__ maxv(v15, __ T8H, v16, v17); // smax v15.8H, v16.8H, v17.8H632__ maxv(v17, __ T2S, v18, v19); // smax v17.2S, v18.2S, v19.2S633__ maxv(v29, __ T4S, v30, v31); // smax v29.4S, v30.4S, v31.4S634__ smaxp(v26, __ T8B, v27, v28); // smaxp v26.8B, v27.8B, v28.8B635__ smaxp(v28, __ T16B, v29, v30); // smaxp v28.16B, v29.16B, v30.16B636__ smaxp(v1, __ T4H, v2, v3); // smaxp v1.4H, v2.4H, v3.4H637__ smaxp(v27, __ T8H, v28, v29); // smaxp v27.8H, v28.8H, v29.8H638__ smaxp(v0, __ T2S, v1, v2); // smaxp v0.2S, v1.2S, v2.2S639__ smaxp(v20, __ T4S, v21, v22); // smaxp v20.4S, v21.4S, v22.4S640__ fmax(v28, __ T2S, v29, v30); // fmax v28.2S, v29.2S, v30.2S641__ fmax(v15, __ T4S, v16, v17); // fmax v15.4S, v16.4S, v17.4S642__ fmax(v12, __ T2D, v13, v14); // fmax v12.2D, v13.2D, v14.2D643__ minv(v10, __ T8B, v11, v12); // smin v10.8B, v11.8B, v12.8B644__ minv(v28, __ T16B, v29, v30); // smin v28.16B, v29.16B, v30.16B645__ minv(v28, __ T4H, v29, v30); // smin v28.4H, v29.4H, v30.4H646__ minv(v19, __ T8H, v20, v21); // smin v19.8H, v20.8H, v21.8H647__ minv(v22, __ T2S, v23, v24); // smin v22.2S, v23.2S, v24.2S648__ minv(v10, __ T4S, v11, v12); // smin v10.4S, v11.4S, v12.4S649__ sminp(v4, __ T8B, v5, v6); // sminp v4.8B, v5.8B, v6.8B650__ sminp(v30, __ T16B, v31, v0); // sminp v30.16B, v31.16B, v0.16B651__ sminp(v20, __ T4H, v21, v22); // sminp v20.4H, v21.4H, v22.4H652__ sminp(v8, __ T8H, v9, v10); // sminp v8.8H, v9.8H, v10.8H653__ sminp(v30, __ T2S, v31, v0); // sminp v30.2S, v31.2S, v0.2S654__ sminp(v17, __ T4S, v18, v19); // sminp v17.4S, v18.4S, v19.4S655__ fmin(v10, __ T2S, v11, v12); // fmin v10.2S, v11.2S, v12.2S656__ fmin(v27, __ T4S, v28, v29); // fmin v27.4S, v28.4S, v29.4S657__ fmin(v2, __ T2D, v3, v4); // fmin v2.2D, v3.2D, v4.2D658__ cmeq(v24, __ T8B, v25, v26); // cmeq v24.8B, v25.8B, v26.8B659__ cmeq(v4, __ T16B, v5, v6); // cmeq v4.16B, v5.16B, v6.16B660__ cmeq(v3, __ T4H, v4, v5); // cmeq v3.4H, v4.4H, v5.4H661__ cmeq(v8, __ T8H, v9, v10); // cmeq v8.8H, v9.8H, v10.8H662__ cmeq(v22, __ T2S, v23, v24); // cmeq v22.2S, v23.2S, v24.2S663__ cmeq(v17, __ T4S, v18, v19); // cmeq v17.4S, v18.4S, v19.4S664__ cmeq(v13, __ T2D, v14, v15); // cmeq v13.2D, v14.2D, v15.2D665__ fcmeq(v4, __ T2S, v5, v6); // fcmeq v4.2S, v5.2S, v6.2S666__ fcmeq(v28, __ T4S, v29, v30); // fcmeq v28.4S, v29.4S, v30.4S667__ fcmeq(v23, __ T2D, v24, v25); // fcmeq v23.2D, v24.2D, v25.2D668__ cmgt(v21, __ T8B, v22, v23); // cmgt v21.8B, v22.8B, v23.8B669__ cmgt(v25, __ T16B, v26, v27); // cmgt v25.16B, v26.16B, v27.16B670__ cmgt(v24, __ T4H, v25, v26); // cmgt v24.4H, v25.4H, v26.4H671__ cmgt(v3, __ T8H, v4, v5); // cmgt v3.8H, v4.8H, v5.8H672__ cmgt(v23, __ T2S, v24, v25); // cmgt v23.2S, v24.2S, v25.2S673__ cmgt(v26, __ T4S, v27, v28); // cmgt v26.4S, v27.4S, v28.4S674__ cmgt(v23, __ T2D, v24, v25); // cmgt v23.2D, v24.2D, v25.2D675__ cmhi(v14, __ T8B, v15, v16); // cmhi v14.8B, v15.8B, v16.8B676__ cmhi(v21, __ T16B, v22, v23); // cmhi v21.16B, v22.16B, v23.16B677__ cmhi(v3, __ T4H, v4, v5); // cmhi v3.4H, v4.4H, v5.4H678__ cmhi(v23, __ T8H, v24, v25); // cmhi v23.8H, v24.8H, v25.8H679__ cmhi(v8, __ T2S, v9, v10); // cmhi v8.2S, v9.2S, v10.2S680__ cmhi(v24, __ T4S, v25, v26); // cmhi v24.4S, v25.4S, v26.4S681__ cmhi(v19, __ T2D, v20, v21); // cmhi v19.2D, v20.2D, v21.2D682__ cmhs(v15, __ T8B, v16, v17); // cmhs v15.8B, v16.8B, v17.8B683__ cmhs(v16, __ T16B, v17, v18); // cmhs v16.16B, v17.16B, v18.16B684__ cmhs(v2, __ T4H, v3, v4); // cmhs v2.4H, v3.4H, v4.4H685__ cmhs(v1, __ T8H, v2, v3); // cmhs v1.8H, v2.8H, v3.8H686__ cmhs(v0, __ T2S, v1, v2); // cmhs v0.2S, v1.2S, v2.2S687__ cmhs(v24, __ T4S, v25, v26); // cmhs v24.4S, v25.4S, v26.4S688__ cmhs(v4, __ T2D, v5, v6); // cmhs v4.2D, v5.2D, v6.2D689__ fcmgt(v3, __ T2S, v4, v5); // fcmgt v3.2S, v4.2S, v5.2S690__ fcmgt(v11, __ T4S, v12, v13); // fcmgt v11.4S, v12.4S, v13.4S691__ fcmgt(v30, __ T2D, v31, v0); // fcmgt v30.2D, v31.2D, v0.2D692__ cmge(v27, __ T8B, v28, v29); // cmge v27.8B, v28.8B, v29.8B693__ cmge(v9, __ T16B, v10, v11); // cmge v9.16B, v10.16B, v11.16B694__ cmge(v25, __ T4H, v26, v27); // cmge v25.4H, v26.4H, v27.4H695__ cmge(v2, __ T8H, v3, v4); // cmge v2.8H, v3.8H, v4.8H696__ cmge(v12, __ T2S, v13, v14); // cmge v12.2S, v13.2S, v14.2S697__ cmge(v17, __ T4S, v18, v19); // cmge v17.4S, v18.4S, v19.4S698__ cmge(v30, __ T2D, v31, v0); // cmge v30.2D, v31.2D, v0.2D699__ fcmge(v1, __ T2S, v2, v3); // fcmge v1.2S, v2.2S, v3.2S700__ fcmge(v12, __ T4S, v13, v14); // fcmge v12.4S, v13.4S, v14.4S701__ fcmge(v28, __ T2D, v29, v30); // fcmge v28.2D, v29.2D, v30.2D702703// SpecialCases704__ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE705__ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ706__ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE707__ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT708__ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0709__ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp]710__ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3]711__ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5]712__ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp]713__ dup(v0, __ T16B, zr); // dup v0.16b, wzr714__ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr715__ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr716__ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr717__ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr718__ smov(r0, v1, __ S, 0); // smov x0, v1.s[0]719__ smov(r0, v1, __ H, 1); // smov x0, v1.h[1]720__ smov(r0, v1, __ B, 2); // smov x0, v1.b[2]721__ umov(r0, v1, __ D, 0); // umov x0, v1.d[0]722__ umov(r0, v1, __ S, 1); // umov w0, v1.s[1]723__ umov(r0, v1, __ H, 2); // umov w0, v1.h[2]724__ umov(r0, v1, __ B, 3); // umov w0, v1.b[3]725__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0726__ sve_cpy(z0, __ S, p0, v1); // mov z0.s, p0/m, s1727__ sve_inc(r0, __ S); // incw x0728__ sve_dec(r1, __ H); // dech x1729__ sve_lsl(z0, __ B, z1, 7); // lsl z0.b, z1.b, #7730__ sve_lsl(z21, __ H, z1, 15); // lsl z21.h, z1.h, #15731__ sve_lsl(z0, __ S, z1, 31); // lsl z0.s, z1.s, #31732__ sve_lsl(z0, __ D, z1, 63); // lsl z0.d, z1.d, #63733__ sve_lsr(z0, __ B, z1, 7); // lsr z0.b, z1.b, #7734__ sve_asr(z0, __ H, z11, 15); // asr z0.h, z11.h, #15735__ sve_lsr(z30, __ S, z1, 31); // lsr z30.s, z1.s, #31736__ sve_asr(z0, __ D, z1, 63); // asr z0.d, z1.d, #63737__ sve_addvl(sp, r0, 31); // addvl sp, x0, #31738__ sve_addpl(r1, sp, -32); // addpl x1, sp, -32739__ sve_cntp(r8, __ B, p0, p1); // cntp x8, p0, p1.b740__ sve_dup(z0, __ B, 127); // dup z0.b, 127741__ sve_dup(z1, __ H, -128); // dup z1.h, -128742__ sve_dup(z2, __ S, 32512); // dup z2.s, 32512743__ sve_dup(z7, __ D, -32768); // dup z7.d, -32768744__ sve_ld1b(z0, __ B, p0, Address(sp)); // ld1b {z0.b}, p0/z, [sp]745__ sve_ld1h(z10, __ H, p1, Address(sp, -8)); // ld1h {z10.h}, p1/z, [sp, #-8, MUL VL]746__ sve_ld1w(z20, __ S, p2, Address(r0, 7)); // ld1w {z20.s}, p2/z, [x0, #7, MUL VL]747__ sve_ld1b(z30, __ B, p3, Address(sp, r8)); // ld1b {z30.b}, p3/z, [sp, x8]748__ sve_ld1w(z0, __ S, p4, Address(sp, r28)); // ld1w {z0.s}, p4/z, [sp, x28, LSL #2]749__ sve_ld1d(z11, __ D, p5, Address(r0, r1)); // ld1d {z11.d}, p5/z, [x0, x1, LSL #3]750__ sve_st1b(z22, __ B, p6, Address(sp)); // st1b {z22.b}, p6, [sp]751__ sve_st1b(z31, __ B, p7, Address(sp, -8)); // st1b {z31.b}, p7, [sp, #-8, MUL VL]752__ sve_st1w(z0, __ S, p1, Address(r0, 7)); // st1w {z0.s}, p1, [x0, #7, MUL VL]753__ sve_st1b(z0, __ B, p2, Address(sp, r1)); // st1b {z0.b}, p2, [sp, x1]754__ sve_st1h(z0, __ H, p3, Address(sp, r8)); // st1h {z0.h}, p3, [sp, x8, LSL #1]755__ sve_st1d(z0, __ D, p4, Address(r0, r17)); // st1d {z0.d}, p4, [x0, x17, LSL #3]756__ sve_ldr(z0, Address(sp)); // ldr z0, [sp]757__ sve_ldr(z31, Address(sp, -256)); // ldr z31, [sp, #-256, MUL VL]758__ sve_str(z8, Address(r8, 255)); // str z8, [x8, #255, MUL VL]759760// FloatImmediateOp761__ fmovd(v0, 2.0); // fmov d0, #2.0762__ fmovd(v0, 2.125); // fmov d0, #2.125763__ fmovd(v0, 4.0); // fmov d0, #4.0764__ fmovd(v0, 4.25); // fmov d0, #4.25765__ fmovd(v0, 8.0); // fmov d0, #8.0766__ fmovd(v0, 8.5); // fmov d0, #8.5767__ fmovd(v0, 16.0); // fmov d0, #16.0768__ fmovd(v0, 17.0); // fmov d0, #17.0769__ fmovd(v0, 0.125); // fmov d0, #0.125770__ fmovd(v0, 0.1328125); // fmov d0, #0.1328125771__ fmovd(v0, 0.25); // fmov d0, #0.25772__ fmovd(v0, 0.265625); // fmov d0, #0.265625773__ fmovd(v0, 0.5); // fmov d0, #0.5774__ fmovd(v0, 0.53125); // fmov d0, #0.53125775__ fmovd(v0, 1.0); // fmov d0, #1.0776__ fmovd(v0, 1.0625); // fmov d0, #1.0625777__ fmovd(v0, -2.0); // fmov d0, #-2.0778__ fmovd(v0, -2.125); // fmov d0, #-2.125779__ fmovd(v0, -4.0); // fmov d0, #-4.0780__ fmovd(v0, -4.25); // fmov d0, #-4.25781__ fmovd(v0, -8.0); // fmov d0, #-8.0782__ fmovd(v0, -8.5); // fmov d0, #-8.5783__ fmovd(v0, -16.0); // fmov d0, #-16.0784__ fmovd(v0, -17.0); // fmov d0, #-17.0785__ fmovd(v0, -0.125); // fmov d0, #-0.125786__ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125787__ fmovd(v0, -0.25); // fmov d0, #-0.25788__ fmovd(v0, -0.265625); // fmov d0, #-0.265625789__ fmovd(v0, -0.5); // fmov d0, #-0.5790__ fmovd(v0, -0.53125); // fmov d0, #-0.53125791__ fmovd(v0, -1.0); // fmov d0, #-1.0792__ fmovd(v0, -1.0625); // fmov d0, #-1.0625793794// LSEOp795__ swp(Assembler::xword, r0, r19, r12); // swp x0, x19, [x12]796__ ldadd(Assembler::xword, r17, r22, r13); // ldadd x17, x22, [x13]797__ ldbic(Assembler::xword, r28, r30, sp); // ldclr x28, x30, [sp]798__ ldeor(Assembler::xword, r1, r26, r28); // ldeor x1, x26, [x28]799__ ldorr(Assembler::xword, r4, r30, r4); // ldset x4, x30, [x4]800__ ldsmin(Assembler::xword, r6, r30, r26); // ldsmin x6, x30, [x26]801__ ldsmax(Assembler::xword, r16, r9, r8); // ldsmax x16, x9, [x8]802__ ldumin(Assembler::xword, r12, r0, r20); // ldumin x12, x0, [x20]803__ ldumax(Assembler::xword, r1, r24, r2); // ldumax x1, x24, [x2]804805// LSEOp806__ swpa(Assembler::xword, r0, r9, r24); // swpa x0, x9, [x24]807__ ldadda(Assembler::xword, r26, r16, r30); // ldadda x26, x16, [x30]808__ ldbica(Assembler::xword, r3, r10, r23); // ldclra x3, x10, [x23]809__ ldeora(Assembler::xword, r10, r4, r15); // ldeora x10, x4, [x15]810__ ldorra(Assembler::xword, r2, r11, r8); // ldseta x2, x11, [x8]811__ ldsmina(Assembler::xword, r10, r15, r17); // ldsmina x10, x15, [x17]812__ ldsmaxa(Assembler::xword, r2, r10, r12); // ldsmaxa x2, x10, [x12]813__ ldumina(Assembler::xword, r12, r15, r13); // ldumina x12, x15, [x13]814__ ldumaxa(Assembler::xword, r2, r7, r20); // ldumaxa x2, x7, [x20]815816// LSEOp817__ swpal(Assembler::xword, r26, r16, r4); // swpal x26, x16, [x4]818__ ldaddal(Assembler::xword, r2, r4, r12); // ldaddal x2, x4, [x12]819__ ldbical(Assembler::xword, r16, r21, r16); // ldclral x16, x21, [x16]820__ ldeoral(Assembler::xword, r16, r11, r21); // ldeoral x16, x11, [x21]821__ ldorral(Assembler::xword, r23, r12, r26); // ldsetal x23, x12, [x26]822__ ldsminal(Assembler::xword, r23, r28, r14); // ldsminal x23, x28, [x14]823__ ldsmaxal(Assembler::xword, r11, r24, r1); // ldsmaxal x11, x24, [x1]824__ lduminal(Assembler::xword, r12, zr, r10); // lduminal x12, xzr, [x10]825__ ldumaxal(Assembler::xword, r16, r7, r2); // ldumaxal x16, x7, [x2]826827// LSEOp828__ swpl(Assembler::xword, r3, r13, r19); // swpl x3, x13, [x19]829__ ldaddl(Assembler::xword, r17, r16, r3); // ldaddl x17, x16, [x3]830__ ldbicl(Assembler::xword, r1, r11, r30); // ldclrl x1, x11, [x30]831__ ldeorl(Assembler::xword, r5, r8, r15); // ldeorl x5, x8, [x15]832__ ldorrl(Assembler::xword, r29, r30, r0); // ldsetl x29, x30, [x0]833__ ldsminl(Assembler::xword, r20, r7, r20); // ldsminl x20, x7, [x20]834__ ldsmaxl(Assembler::xword, r23, r28, r21); // ldsmaxl x23, x28, [x21]835__ lduminl(Assembler::xword, r27, r25, r5); // lduminl x27, x25, [x5]836__ ldumaxl(Assembler::xword, r1, r23, r16); // ldumaxl x1, x23, [x16]837838// LSEOp839__ swp(Assembler::word, zr, r5, r12); // swp wzr, w5, [x12]840__ ldadd(Assembler::word, r9, r28, r15); // ldadd w9, w28, [x15]841__ ldbic(Assembler::word, r29, r22, sp); // ldclr w29, w22, [sp]842__ ldeor(Assembler::word, r19, zr, r5); // ldeor w19, wzr, [x5]843__ ldorr(Assembler::word, r14, r16, sp); // ldset w14, w16, [sp]844__ ldsmin(Assembler::word, r16, r27, r20); // ldsmin w16, w27, [x20]845__ ldsmax(Assembler::word, r16, r12, r11); // ldsmax w16, w12, [x11]846__ ldumin(Assembler::word, r9, r6, r30); // ldumin w9, w6, [x30]847__ ldumax(Assembler::word, r17, r27, r28); // ldumax w17, w27, [x28]848849// LSEOp850__ swpa(Assembler::word, r30, r7, r10); // swpa w30, w7, [x10]851__ ldadda(Assembler::word, r20, r10, r4); // ldadda w20, w10, [x4]852__ ldbica(Assembler::word, r24, r17, r17); // ldclra w24, w17, [x17]853__ ldeora(Assembler::word, r22, r3, r29); // ldeora w22, w3, [x29]854__ ldorra(Assembler::word, r15, r22, r19); // ldseta w15, w22, [x19]855__ ldsmina(Assembler::word, r19, r22, r2); // ldsmina w19, w22, [x2]856__ ldsmaxa(Assembler::word, r15, r6, r12); // ldsmaxa w15, w6, [x12]857__ ldumina(Assembler::word, r16, r11, r13); // ldumina w16, w11, [x13]858__ ldumaxa(Assembler::word, r23, r1, r30); // ldumaxa w23, w1, [x30]859860// LSEOp861__ swpal(Assembler::word, r19, r5, r17); // swpal w19, w5, [x17]862__ ldaddal(Assembler::word, r2, r16, r22); // ldaddal w2, w16, [x22]863__ ldbical(Assembler::word, r13, r10, r21); // ldclral w13, w10, [x21]864__ ldeoral(Assembler::word, r29, r27, r12); // ldeoral w29, w27, [x12]865__ ldorral(Assembler::word, r27, r3, r1); // ldsetal w27, w3, [x1]866__ ldsminal(Assembler::word, zr, r24, r19); // ldsminal wzr, w24, [x19]867__ ldsmaxal(Assembler::word, r17, r9, r28); // ldsmaxal w17, w9, [x28]868__ lduminal(Assembler::word, r27, r15, r7); // lduminal w27, w15, [x7]869__ ldumaxal(Assembler::word, r21, r23, sp); // ldumaxal w21, w23, [sp]870871// LSEOp872__ swpl(Assembler::word, r25, r2, sp); // swpl w25, w2, [sp]873__ ldaddl(Assembler::word, r27, r16, r10); // ldaddl w27, w16, [x10]874__ ldbicl(Assembler::word, r23, r19, r3); // ldclrl w23, w19, [x3]875__ ldeorl(Assembler::word, r16, r0, r25); // ldeorl w16, w0, [x25]876__ ldorrl(Assembler::word, r26, r23, r2); // ldsetl w26, w23, [x2]877__ ldsminl(Assembler::word, r16, r12, r4); // ldsminl w16, w12, [x4]878__ ldsmaxl(Assembler::word, r28, r30, r29); // ldsmaxl w28, w30, [x29]879__ lduminl(Assembler::word, r16, r27, r6); // lduminl w16, w27, [x6]880__ ldumaxl(Assembler::word, r9, r29, r15); // ldumaxl w9, w29, [x15]881882// SHA3SIMDOp883__ bcax(v7, __ T16B, v4, v7, v15); // bcax v7.16B, v4.16B, v7.16B, v15.16B884__ eor3(v9, __ T16B, v22, v8, v2); // eor3 v9.16B, v22.16B, v8.16B, v2.16B885__ rax1(v27, __ T2D, v20, v30); // rax1 v27.2D, v20.2D, v30.2D886__ xar(v5, __ T2D, v26, v0, 34); // xar v5.2D, v26.2D, v0.2D, #34887888// SHA512SIMDOp889__ sha512h(v14, __ T2D, v3, v25); // sha512h q14, q3, v25.2D890__ sha512h2(v8, __ T2D, v27, v21); // sha512h2 q8, q27, v21.2D891__ sha512su0(v26, __ T2D, v26); // sha512su0 v26.2D, v26.2D892__ sha512su1(v24, __ T2D, v22, v0); // sha512su1 v24.2D, v22.2D, v0.2D893894// SVEVectorOp895__ sve_add(z4, __ B, z6, z17); // add z4.b, z6.b, z17.b896__ sve_sub(z3, __ H, z15, z1); // sub z3.h, z15.h, z1.h897__ sve_fadd(z6, __ D, z5, z9); // fadd z6.d, z5.d, z9.d898__ sve_fmul(z7, __ D, z20, z22); // fmul z7.d, z20.d, z22.d899__ sve_fsub(z5, __ D, z10, z8); // fsub z5.d, z10.d, z8.d900__ sve_abs(z30, __ B, p1, z17); // abs z30.b, p1/m, z17.b901__ sve_add(z11, __ B, p7, z28); // add z11.b, p7/m, z11.b, z28.b902__ sve_asr(z26, __ H, p5, z28); // asr z26.h, p5/m, z26.h, z28.h903__ sve_cnt(z13, __ D, p7, z16); // cnt z13.d, p7/m, z16.d904__ sve_lsl(z5, __ H, p0, z13); // lsl z5.h, p0/m, z5.h, z13.h905__ sve_lsr(z15, __ S, p2, z26); // lsr z15.s, p2/m, z15.s, z26.s906__ sve_mul(z11, __ S, p1, z22); // mul z11.s, p1/m, z11.s, z22.s907__ sve_neg(z4, __ S, p0, z19); // neg z4.s, p0/m, z19.s908__ sve_not(z17, __ H, p3, z14); // not z17.h, p3/m, z14.h909__ sve_smax(z2, __ S, p4, z3); // smax z2.s, p4/m, z2.s, z3.s910__ sve_smin(z23, __ B, p1, z6); // smin z23.b, p1/m, z23.b, z6.b911__ sve_sub(z17, __ S, p3, z27); // sub z17.s, p3/m, z17.s, z27.s912__ sve_fabs(z16, __ D, p1, z2); // fabs z16.d, p1/m, z2.d913__ sve_fadd(z3, __ D, p1, z6); // fadd z3.d, p1/m, z3.d, z6.d914__ sve_fdiv(z19, __ D, p3, z12); // fdiv z19.d, p3/m, z19.d, z12.d915__ sve_fmax(z8, __ D, p6, z19); // fmax z8.d, p6/m, z8.d, z19.d916__ sve_fmin(z0, __ S, p2, z23); // fmin z0.s, p2/m, z0.s, z23.s917__ sve_fmul(z19, __ D, p7, z13); // fmul z19.d, p7/m, z19.d, z13.d918__ sve_fneg(z6, __ S, p0, z7); // fneg z6.s, p0/m, z7.s919__ sve_frintm(z17, __ S, p6, z8); // frintm z17.s, p6/m, z8.s920__ sve_frintn(z22, __ D, p5, z22); // frintn z22.d, p5/m, z22.d921__ sve_frintp(z2, __ D, p0, z15); // frintp z2.d, p0/m, z15.d922__ sve_fsqrt(z20, __ D, p1, z4); // fsqrt z20.d, p1/m, z4.d923__ sve_fsub(z7, __ D, p0, z8); // fsub z7.d, p0/m, z7.d, z8.d924__ sve_fmla(z19, __ S, p5, z4, z15); // fmla z19.s, p5/m, z4.s, z15.s925__ sve_fmls(z22, __ D, p2, z25, z5); // fmls z22.d, p2/m, z25.d, z5.d926__ sve_fnmla(z16, __ S, p3, z22, z11); // fnmla z16.s, p3/m, z22.s, z11.s927__ sve_fnmls(z13, __ D, p2, z20, z16); // fnmls z13.d, p2/m, z20.d, z16.d928__ sve_mla(z15, __ H, p1, z4, z17); // mla z15.h, p1/m, z4.h, z17.h929__ sve_mls(z6, __ S, p7, z4, z28); // mls z6.s, p7/m, z4.s, z28.s930__ sve_and(z29, z26, z9); // and z29.d, z26.d, z9.d931__ sve_eor(z2, z11, z28); // eor z2.d, z11.d, z28.d932__ sve_orr(z7, z1, z26); // orr z7.d, z1.d, z26.d933__ sve_bic(z17, z14, z8); // bic z17.d, z14.d, z8.d934935// SVEReductionOp936__ sve_andv(v21, __ S, p6, z5); // andv s21, p6, z5.s937__ sve_orv(v21, __ S, p4, z22); // orv s21, p4, z22.s938__ sve_eorv(v29, __ B, p5, z19); // eorv b29, p5, z19.b939__ sve_smaxv(v4, __ B, p4, z23); // smaxv b4, p4, z23.b940__ sve_sminv(v19, __ D, p1, z23); // sminv d19, p1, z23.d941__ sve_fminv(v19, __ S, p0, z8); // fminv s19, p0, z8.s942__ sve_fmaxv(v14, __ D, p6, z17); // fmaxv d14, p6, z17.d943__ sve_fadda(v21, __ S, p1, z30); // fadda s21, p1, s21, z30.s944__ sve_uaddv(v10, __ B, p5, z12); // uaddv d10, p5, z12.b945946__ bind(forth);947948/*949*/950951static const unsigned int insns[] =952{9530x8b0d82fa, 0xcb49970c, 0xab889dfc, 0xeb9ee787,9540x0b9b3ec9, 0x4b9179a3, 0x2b88474e, 0x6b8c56c0,9550x8a1a51e0, 0xaa11f4ba, 0xca0281b8, 0xea918c7c,9560x0a5d4a19, 0x2a4b262d, 0x4a513ca5, 0x6a9b6ae2,9570x8a70b79b, 0xaaba9728, 0xca6dfe3d, 0xea627f1c,9580x0aa70f53, 0x2aaa0f06, 0x4a6176a4, 0x6a604eb0,9590x1105ed91, 0x3100583e, 0x5101f8bd, 0x710f0306,9600x9101a1a0, 0xb10a5cc8, 0xd10810aa, 0xf10fd061,9610x120cb166, 0x321764bc, 0x52174681, 0x720c0227,9620x9241018e, 0xb25a2969, 0xd278b411, 0xf26aad01,9630x14000000, 0x17ffffd7, 0x140002fb, 0x94000000,9640x97ffffd4, 0x940002f8, 0x3400000a, 0x34fffa2a,9650x34005eaa, 0x35000008, 0x35fff9c8, 0x35005e48,9660xb400000b, 0xb4fff96b, 0xb4005deb, 0xb500001d,9670xb5fff91d, 0xb5005d9d, 0x10000013, 0x10fff8b3,9680x10005d33, 0x90000013, 0x36300016, 0x3637f836,9690x36305cb6, 0x3758000c, 0x375ff7cc, 0x37585c4c,9700x128313a0, 0x528a32c7, 0x7289173b, 0x92ab3acc,9710xd2a0bf94, 0xf2c285e8, 0x9358722f, 0x330e652f,9720x53067f3b, 0x93577c53, 0xb34a1aac, 0xd35a4016,9730x13946c63, 0x93c3dbc8, 0x54000000, 0x54fff5a0,9740x54005a20, 0x54000001, 0x54fff541, 0x540059c1,9750x54000002, 0x54fff4e2, 0x54005962, 0x54000002,9760x54fff482, 0x54005902, 0x54000003, 0x54fff423,9770x540058a3, 0x54000003, 0x54fff3c3, 0x54005843,9780x54000004, 0x54fff364, 0x540057e4, 0x54000005,9790x54fff305, 0x54005785, 0x54000006, 0x54fff2a6,9800x54005726, 0x54000007, 0x54fff247, 0x540056c7,9810x54000008, 0x54fff1e8, 0x54005668, 0x54000009,9820x54fff189, 0x54005609, 0x5400000a, 0x54fff12a,9830x540055aa, 0x5400000b, 0x54fff0cb, 0x5400554b,9840x5400000c, 0x54fff06c, 0x540054ec, 0x5400000d,9850x54fff00d, 0x5400548d, 0x5400000e, 0x54ffefae,9860x5400542e, 0x5400000f, 0x54ffef4f, 0x540053cf,9870xd40658e1, 0xd4014d22, 0xd4046543, 0xd4273f60,9880xd44cad80, 0xd503201f, 0xd69f03e0, 0xd6bf03e0,9890xd5033fdf, 0xd5033e9f, 0xd50332bf, 0xd61f0200,9900xd63f0280, 0xc80a7d1b, 0xc800fea1, 0xc85f7fb1,9910xc85fff9d, 0xc89ffee1, 0xc8dffe95, 0x88167e7b,9920x880bfcd0, 0x885f7c11, 0x885ffd44, 0x889ffed8,9930x88dffe6a, 0x48017fc5, 0x4808fe2c, 0x485f7dc9,9940x485ffc27, 0x489ffe05, 0x48dffd82, 0x080a7c6c,9950x081cff4e, 0x085f7d5e, 0x085ffeae, 0x089ffd2d,9960x08dfff76, 0xc87f4d7c, 0xc87fcc5e, 0xc8220417,9970xc82cb5f0, 0x887f55b1, 0x887ff90b, 0x88382c2d,9980x883aedb5, 0xf819928b, 0xb803e21c, 0x381f713b,9990x781ce322, 0xf850f044, 0xb85e129e, 0x385e92f1,10000x785ff35d, 0x39801921, 0x7881318b, 0x78dce02b,10010xb8829313, 0xfc45f318, 0xbc5d50af, 0xfc001375,10020xbc1951b7, 0xf8008c0a, 0xb801dc03, 0x38009dca,10030x781fdf3d, 0xf8570e0c, 0xb85faecc, 0x385f6d6d,10040x785ebea0, 0x38804cd7, 0x789cbce3, 0x78df9c9c,10050xb89eed18, 0xfc40cd6e, 0xbc5bdd93, 0xfc103c14,10060xbc040c08, 0xf81a2783, 0xb81ca4eb, 0x381e855b,10070x7801b4e6, 0xf853654d, 0xb85d74af, 0x384095a2,10080x785ec5bc, 0x389e15a9, 0x789dc703, 0x78c06474,10090xb89ff667, 0xfc57e51e, 0xbc4155f9, 0xfc05a6ee,10100xbc1df408, 0xf835da2a, 0xb836d9a4, 0x3833580d,10110x7826cb6c, 0xf8706900, 0xb87ae880, 0x3865db2e,10120x78714889, 0x38a7789b, 0x78beca2f, 0x78f6c810,10130xb8bef956, 0xfc6afabd, 0xbc734963, 0xfc3d5b8d,10140xbc25fbb7, 0xf9189d05, 0xb91ecb1d, 0x39187a33,10150x791f226d, 0xf95aa2f3, 0xb9587bb7, 0x395f7176,10160x795d9143, 0x399e7e08, 0x799a2697, 0x79df3422,10170xb99c2624, 0xfd5c2374, 0xbd5fa1d9, 0xfd1d595a,10180xbd1b1869, 0x5800441b, 0x1800000b, 0xf8945060,10190xd8000000, 0xf8ae6ba0, 0xf99a0080, 0x1a070035,10200x3a0700a8, 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0x1e6e1000,11180x1e6e3000, 0x1e701000, 0x1e703000, 0x1e721000,11190x1e723000, 0x1e741000, 0x1e743000, 0x1e761000,11200x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000,11210x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000,11220x1e7e3000, 0xf8208193, 0xf83101b6, 0xf83c13fe,11230xf821239a, 0xf824309e, 0xf826535e, 0xf8304109,11240xf82c7280, 0xf8216058, 0xf8a08309, 0xf8ba03d0,11250xf8a312ea, 0xf8aa21e4, 0xf8a2310b, 0xf8aa522f,11260xf8a2418a, 0xf8ac71af, 0xf8a26287, 0xf8fa8090,11270xf8e20184, 0xf8f01215, 0xf8f022ab, 0xf8f7334c,11280xf8f751dc, 0xf8eb4038, 0xf8ec715f, 0xf8f06047,11290xf863826d, 0xf8710070, 0xf86113cb, 0xf86521e8,11300xf87d301e, 0xf8745287, 0xf87742bc, 0xf87b70b9,11310xf8616217, 0xb83f8185, 0xb82901fc, 0xb83d13f6,11320xb83320bf, 0xb82e33f0, 0xb830529b, 0xb830416c,11330xb82973c6, 0xb831639b, 0xb8be8147, 0xb8b4008a,11340xb8b81231, 0xb8b623a3, 0xb8af3276, 0xb8b35056,11350xb8af4186, 0xb8b071ab, 0xb8b763c1, 0xb8f38225,11360xb8e202d0, 0xb8ed12aa, 0xb8fd219b, 0xb8fb3023,11370xb8ff5278, 0xb8f14389, 0xb8fb70ef, 0xb8f563f7,11380xb87983e2, 0xb87b0150, 0xb8771073, 0xb8702320,11390xb87a3057, 0xb870508c, 0xb87c43be, 0xb87070db,11400xb86961fd, 0xce273c87, 0xce080ac9, 0xce7e8e9b,11410xce808b45, 0xce79806e, 0xce758768, 0xcec0835a,11420xce608ad8, 0x043100c4, 0x046105e3, 0x65c900a6,11430x65d60a87, 0x65c80545, 0x0416a63e, 0x04001f8b,11440x0450979a, 0x04dabe0d, 0x045381a5, 0x04918b4f,11450x049006cb, 0x0497a264, 0x045eadd1, 0x04881062,11460x040a04d7, 0x04810f71, 0x04dca450, 0x65c084c3,11470x65cd8d93, 0x65c69a68, 0x65878ae0, 0x65c29db3,11480x049da0e6, 0x6582b911, 0x65c0b6d6, 0x65c1a1e2,11490x65cda494, 0x65c18107, 0x65af1493, 0x65e52b36,11500x65ab4ed0, 0x65f06a8d, 0x0451448f, 0x049c7c86,11510x0429335d, 0x04bc3162, 0x047a3027, 0x04e831d1,11520x049a38b5, 0x049832d5, 0x0419367d, 0x040832e4,11530x04ca26f3, 0x65872113, 0x65c63a2e, 0x659827d5,11540x0401358a,1155};1156// END Generated code -- do not edit115711581159