Path: blob/21.2-virgl/include/drm-uapi/virtgpu_drm.h
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/*1* Copyright 2013 Red Hat2* All Rights Reserved.3*4* Permission is hereby granted, free of charge, to any person obtaining a5* copy of this software and associated documentation files (the "Software"),6* to deal in the Software without restriction, including without limitation7* the rights to use, copy, modify, merge, publish, distribute, sublicense,8* and/or sell copies of the Software, and to permit persons to whom the9* Software is furnished to do so, subject to the following conditions:10*11* The above copyright notice and this permission notice (including the next12* paragraph) shall be included in all copies or substantial portions of the13* Software.14*15* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18* THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR19* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21* OTHER DEALINGS IN THE SOFTWARE.22*/23#ifndef VIRTGPU_DRM_H24#define VIRTGPU_DRM_H2526#include "drm.h"2728#if defined(__cplusplus)29extern "C" {30#endif3132/* Please note that modifications to all structs defined here are33* subject to backwards-compatibility constraints.34*35* Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel36* compatibility Keep fields aligned to their size37*/3839#define DRM_VIRTGPU_MAP 0x0140#define DRM_VIRTGPU_EXECBUFFER 0x0241#define DRM_VIRTGPU_GETPARAM 0x0342#define DRM_VIRTGPU_RESOURCE_CREATE 0x0443#define DRM_VIRTGPU_RESOURCE_INFO 0x0544#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x0645#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x0746#define DRM_VIRTGPU_WAIT 0x0847#define DRM_VIRTGPU_GET_CAPS 0x0948#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a4950#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x0151#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x0252#define VIRTGPU_EXECBUF_FLAGS (\53VIRTGPU_EXECBUF_FENCE_FD_IN |\54VIRTGPU_EXECBUF_FENCE_FD_OUT |\550)5657struct drm_virtgpu_map {58__u64 offset; /* use for mmap system call */59__u32 handle;60__u32 pad;61};6263struct drm_virtgpu_execbuffer {64__u32 flags;65__u32 size;66__u64 command; /* void* */67__u64 bo_handles;68__u32 num_bo_handles;69__s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */70};7172#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */73#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */74#define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */75#define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */76#define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */7778struct drm_virtgpu_getparam {79__u64 param;80__u64 value;81};8283/* NO_BO flags? NO resource flag? */84/* resource flag for y_0_top */85struct drm_virtgpu_resource_create {86__u32 target;87__u32 format;88__u32 bind;89__u32 width;90__u32 height;91__u32 depth;92__u32 array_size;93__u32 last_level;94__u32 nr_samples;95__u32 flags;96__u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */97__u32 res_handle; /* returned by kernel */98__u32 size; /* validate transfer in the host */99__u32 stride; /* validate transfer in the host */100};101102struct drm_virtgpu_resource_info {103__u32 bo_handle;104__u32 res_handle;105__u32 size;106__u32 blob_mem;107};108109struct drm_virtgpu_3d_box {110__u32 x;111__u32 y;112__u32 z;113__u32 w;114__u32 h;115__u32 d;116};117118struct drm_virtgpu_3d_transfer_to_host {119__u32 bo_handle;120struct drm_virtgpu_3d_box box;121__u32 level;122__u32 offset;123__u32 stride;124__u32 layer_stride;125};126127struct drm_virtgpu_3d_transfer_from_host {128__u32 bo_handle;129struct drm_virtgpu_3d_box box;130__u32 level;131__u32 offset;132__u32 stride;133__u32 layer_stride;134};135136#define VIRTGPU_WAIT_NOWAIT 1 /* like it */137struct drm_virtgpu_3d_wait {138__u32 handle; /* 0 is an invalid handle */139__u32 flags;140};141142struct drm_virtgpu_get_caps {143__u32 cap_set_id;144__u32 cap_set_ver;145__u64 addr;146__u32 size;147__u32 pad;148};149150struct drm_virtgpu_resource_create_blob {151#define VIRTGPU_BLOB_MEM_GUEST 0x0001152#define VIRTGPU_BLOB_MEM_HOST3D 0x0002153#define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003154155#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001156#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002157#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004158/* zero is invalid blob_mem */159__u32 blob_mem;160__u32 blob_flags;161__u32 bo_handle;162__u32 res_handle;163__u64 size;164165/*166* for 3D contexts with VIRTGPU_BLOB_MEM_HOST3D_GUEST and167* VIRTGPU_BLOB_MEM_HOST3D otherwise, must be zero.168*/169__u32 pad;170__u32 cmd_size;171__u64 cmd;172__u64 blob_id;173};174175#define DRM_IOCTL_VIRTGPU_MAP \176DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)177178#define DRM_IOCTL_VIRTGPU_EXECBUFFER \179DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\180struct drm_virtgpu_execbuffer)181182#define DRM_IOCTL_VIRTGPU_GETPARAM \183DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\184struct drm_virtgpu_getparam)185186#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \187DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \188struct drm_virtgpu_resource_create)189190#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \191DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \192struct drm_virtgpu_resource_info)193194#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \195DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \196struct drm_virtgpu_3d_transfer_from_host)197198#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \199DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \200struct drm_virtgpu_3d_transfer_to_host)201202#define DRM_IOCTL_VIRTGPU_WAIT \203DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \204struct drm_virtgpu_3d_wait)205206#define DRM_IOCTL_VIRTGPU_GET_CAPS \207DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \208struct drm_virtgpu_get_caps)209210#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB \211DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \212struct drm_virtgpu_resource_create_blob)213214#if defined(__cplusplus)215}216#endif217218#endif219220221