Path: blob/21.2-virgl/src/amd/addrlib/inc/addrinterface.h
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/*1* Copyright © 2007-2019 Advanced Micro Devices, Inc.2* All Rights Reserved.3*4* Permission is hereby granted, free of charge, to any person obtaining5* a copy of this software and associated documentation files (the6* "Software"), to deal in the Software without restriction, including7* without limitation the rights to use, copy, modify, merge, publish,8* distribute, sub license, and/or sell copies of the Software, and to9* permit persons to whom the Software is furnished to do so, subject to10* the following conditions:11*12* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES14* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND15* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS16* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER17* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,18* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE19* USE OR OTHER DEALINGS IN THE SOFTWARE.20*21* The above copyright notice and this permission notice (including the22* next paragraph) shall be included in all copies or substantial portions23* of the Software.24*/2526/**27****************************************************************************************************28* @file addrinterface.h29* @brief Contains the addrlib interfaces declaration and parameter defines30****************************************************************************************************31*/32#ifndef __ADDR_INTERFACE_H__33#define __ADDR_INTERFACE_H__3435// Includes should be before extern "C"36#include "addrtypes.h"3738#if defined(__cplusplus)39extern "C"40{41#endif4243#define ADDRLIB_VERSION_MAJOR 644#define ADDRLIB_VERSION_MINOR 245#define ADDRLIB_VERSION ((ADDRLIB_VERSION_MAJOR << 16) | ADDRLIB_VERSION_MINOR)4647/// Virtually all interface functions need ADDR_HANDLE as first parameter48typedef VOID* ADDR_HANDLE;4950/// Client handle used in callbacks51typedef VOID* ADDR_CLIENT_HANDLE;5253/**54* /////////////////////////////////////////////////////////////////////////////////////////////////55* // Callback functions56* /////////////////////////////////////////////////////////////////////////////////////////////////57* typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(58* const ADDR_ALLOCSYSMEM_INPUT* pInput);59* typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(60* VOID* pVirtAddr);61* typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(62* const ADDR_DEBUGPRINT_INPUT* pInput);63*64* /////////////////////////////////////////////////////////////////////////////////////////////////65* // Create/Destroy/Config functions66* /////////////////////////////////////////////////////////////////////////////////////////////////67* AddrCreate()68* AddrDestroy()69*70* /////////////////////////////////////////////////////////////////////////////////////////////////71* // Surface functions72* /////////////////////////////////////////////////////////////////////////////////////////////////73* AddrComputeSurfaceInfo()74* AddrComputeSurfaceAddrFromCoord()75* AddrComputeSurfaceCoordFromAddr()76*77* /////////////////////////////////////////////////////////////////////////////////////////////////78* // HTile functions79* /////////////////////////////////////////////////////////////////////////////////////////////////80* AddrComputeHtileInfo()81* AddrComputeHtileAddrFromCoord()82* AddrComputeHtileCoordFromAddr()83*84* /////////////////////////////////////////////////////////////////////////////////////////////////85* // C-mask functions86* /////////////////////////////////////////////////////////////////////////////////////////////////87* AddrComputeCmaskInfo()88* AddrComputeCmaskAddrFromCoord()89* AddrComputeCmaskCoordFromAddr()90*91* /////////////////////////////////////////////////////////////////////////////////////////////////92* // F-mask functions93* /////////////////////////////////////////////////////////////////////////////////////////////////94* AddrComputeFmaskInfo()95* AddrComputeFmaskAddrFromCoord()96* AddrComputeFmaskCoordFromAddr()97*98* /////////////////////////////////////////////////////////////////////////////////////////////////99* // Element/Utility functions100* /////////////////////////////////////////////////////////////////////////////////////////////////101* ElemFlt32ToDepthPixel()102* ElemFlt32ToColorPixel()103* AddrExtractBankPipeSwizzle()104* AddrCombineBankPipeSwizzle()105* AddrComputeSliceSwizzle()106* AddrConvertTileInfoToHW()107* AddrConvertTileIndex()108* AddrConvertTileIndex1()109* AddrGetTileIndex()110* AddrComputeBaseSwizzle()111* AddrUseTileIndex()112* AddrUseCombinedSwizzle()113*114**/115116////////////////////////////////////////////////////////////////////////////////////////////////////117// Callback functions118////////////////////////////////////////////////////////////////////////////////////////////////////119120/**121****************************************************************************************************122* @brief channel setting structure123****************************************************************************************************124*/125typedef union _ADDR_CHANNEL_SETTING126{127struct128{129UINT_8 valid : 1; ///< Indicate whehter this channel setting is valid130UINT_8 channel : 2; ///< 0 for x channel, 1 for y channel, 2 for z channel131UINT_8 index : 5; ///< Channel index132};133UINT_8 value; ///< Value134} ADDR_CHANNEL_SETTING;135136/**137****************************************************************************************************138* @brief address equation key structure139****************************************************************************************************140*/141typedef union _ADDR_EQUATION_KEY142{143struct144{145UINT_32 log2ElementBytes : 3; ///< Log2 of Bytes per pixel146UINT_32 tileMode : 5; ///< Tile mode147UINT_32 microTileType : 3; ///< Micro tile type148UINT_32 pipeConfig : 5; ///< pipe config149UINT_32 numBanksLog2 : 3; ///< Number of banks log2150UINT_32 bankWidth : 4; ///< Bank width151UINT_32 bankHeight : 4; ///< Bank height152UINT_32 macroAspectRatio : 3; ///< Macro tile aspect ratio153UINT_32 prt : 1; ///< SI only, indicate whether this equation is for prt154UINT_32 reserved : 1; ///< Reserved bit155} fields;156UINT_32 value;157} ADDR_EQUATION_KEY;158159/**160****************************************************************************************************161* @brief address equation structure162****************************************************************************************************163*/164#define ADDR_MAX_EQUATION_BIT 20u165166// Invalid equation index167#define ADDR_INVALID_EQUATION_INDEX 0xFFFFFFFF168169typedef struct _ADDR_EQUATION170{171ADDR_CHANNEL_SETTING addr[ADDR_MAX_EQUATION_BIT]; ///< addr setting172///< each bit is result of addr ^ xor ^ xor2173ADDR_CHANNEL_SETTING xor1[ADDR_MAX_EQUATION_BIT]; ///< xor setting174ADDR_CHANNEL_SETTING xor2[ADDR_MAX_EQUATION_BIT]; ///< xor2 setting175UINT_32 numBits; ///< The number of bits in equation176BOOL_32 stackedDepthSlices; ///< TRUE if depth slices are treated as being177///< stacked vertically prior to swizzling178} ADDR_EQUATION;179180181/**182****************************************************************************************************183* @brief Alloc system memory flags.184* @note These flags are reserved for future use and if flags are added will minimize the impact185* of the client.186****************************************************************************************************187*/188typedef union _ADDR_ALLOCSYSMEM_FLAGS189{190struct191{192UINT_32 reserved : 32; ///< Reserved for future use.193} fields;194UINT_32 value;195196} ADDR_ALLOCSYSMEM_FLAGS;197198/**199****************************************************************************************************200* @brief Alloc system memory input structure201****************************************************************************************************202*/203typedef struct _ADDR_ALLOCSYSMEM_INPUT204{205UINT_32 size; ///< Size of this structure in bytes206207ADDR_ALLOCSYSMEM_FLAGS flags; ///< System memory flags.208UINT_32 sizeInBytes; ///< System memory allocation size in bytes.209ADDR_CLIENT_HANDLE hClient; ///< Client handle210} ADDR_ALLOCSYSMEM_INPUT;211212/**213****************************************************************************************************214* ADDR_ALLOCSYSMEM215* @brief216* Allocate system memory callback function. Returns valid pointer on success.217****************************************************************************************************218*/219typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(220const ADDR_ALLOCSYSMEM_INPUT* pInput);221222/**223****************************************************************************************************224* @brief Free system memory input structure225****************************************************************************************************226*/227typedef struct _ADDR_FREESYSMEM_INPUT228{229UINT_32 size; ///< Size of this structure in bytes230231VOID* pVirtAddr; ///< Virtual address232ADDR_CLIENT_HANDLE hClient; ///< Client handle233} ADDR_FREESYSMEM_INPUT;234235/**236****************************************************************************************************237* ADDR_FREESYSMEM238* @brief239* Free system memory callback function.240* Returns ADDR_OK on success.241****************************************************************************************************242*/243typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(244const ADDR_FREESYSMEM_INPUT* pInput);245246/**247****************************************************************************************************248* @brief Print debug message input structure249****************************************************************************************************250*/251typedef struct _ADDR_DEBUGPRINT_INPUT252{253UINT_32 size; ///< Size of this structure in bytes254255CHAR* pDebugString; ///< Debug print string256va_list ap; ///< Variable argument list257ADDR_CLIENT_HANDLE hClient; ///< Client handle258} ADDR_DEBUGPRINT_INPUT;259260/**261****************************************************************************************************262* ADDR_DEBUGPRINT263* @brief264* Print debug message callback function.265* Returns ADDR_OK on success.266****************************************************************************************************267*/268typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(269const ADDR_DEBUGPRINT_INPUT* pInput);270271/**272****************************************************************************************************273* ADDR_CALLBACKS274*275* @brief276* Address Library needs client to provide system memory alloc/free routines.277****************************************************************************************************278*/279typedef struct _ADDR_CALLBACKS280{281ADDR_ALLOCSYSMEM allocSysMem; ///< Routine to allocate system memory282ADDR_FREESYSMEM freeSysMem; ///< Routine to free system memory283ADDR_DEBUGPRINT debugPrint; ///< Routine to print debug message284} ADDR_CALLBACKS;285286////////////////////////////////////////////////////////////////////////////////////////////////////287// Create/Destroy functions288////////////////////////////////////////////////////////////////////////////////////////////////////289290/**291****************************************************************************************************292* ADDR_CREATE_FLAGS293*294* @brief295* This structure is used to pass some setup in creation of AddrLib296* @note297****************************************************************************************************298*/299typedef union _ADDR_CREATE_FLAGS300{301struct302{303UINT_32 noCubeMipSlicesPad : 1; ///< Turn cubemap faces padding off304UINT_32 fillSizeFields : 1; ///< If clients fill size fields in all input and305/// output structure306UINT_32 useTileIndex : 1; ///< Make tileIndex field in input valid307UINT_32 useCombinedSwizzle : 1; ///< Use combined tile swizzle308UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level309UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment310UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize311UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility312UINT_32 nonPower2MemConfig : 1; ///< Video memory bit width is not power of 2313UINT_32 enableAltTiling : 1; ///< Enable alt tile mode314UINT_32 reserved : 22; ///< Reserved bits for future use315};316317UINT_32 value;318} ADDR_CREATE_FLAGS;319320/**321****************************************************************************************************322* ADDR_REGISTER_VALUE323*324* @brief325* Data from registers to setup AddrLib global data, used in AddrCreate326****************************************************************************************************327*/328typedef struct _ADDR_REGISTER_VALUE329{330UINT_32 gbAddrConfig; ///< For R8xx, use GB_ADDR_CONFIG register value.331/// For R6xx/R7xx, use GB_TILING_CONFIG.332/// But they can be treated as the same.333/// if this value is 0, use chip to set default value334UINT_32 backendDisables; ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled.335/// Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE336337/// R800 registers-----------------------------------------------338UINT_32 noOfBanks; ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK339/// No enums for this value in h/w header files340/// 0: 4341/// 1: 8342/// 2: 16343UINT_32 noOfRanks; /// MC_ARB_RAMCFG.NOOFRANK344/// 0: 1345/// 1: 2346/// SI (R1000) registers-----------------------------------------347const UINT_32* pTileConfig; ///< Global tile setting tables348UINT_32 noOfEntries; ///< Number of entries in pTileConfig349350///< CI registers-------------------------------------------------351const UINT_32* pMacroTileConfig; ///< Global macro tile mode table352UINT_32 noOfMacroEntries; ///< Number of entries in pMacroTileConfig353} ADDR_REGISTER_VALUE;354355/**356****************************************************************************************************357* ADDR_CREATE_INPUT358*359* @brief360* Parameters use to create an AddrLib Object. Caller must provide all fields.361*362****************************************************************************************************363*/364typedef struct _ADDR_CREATE_INPUT365{366UINT_32 size; ///< Size of this structure in bytes367368UINT_32 chipEngine; ///< Chip Engine369UINT_32 chipFamily; ///< Chip Family370UINT_32 chipRevision; ///< Chip Revision371ADDR_CALLBACKS callbacks; ///< Callbacks for sysmem alloc/free/print372ADDR_CREATE_FLAGS createFlags; ///< Flags to setup AddrLib373ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data374ADDR_CLIENT_HANDLE hClient; ///< Client handle375UINT_32 minPitchAlignPixels; ///< Minimum pitch alignment in pixels376} ADDR_CREATE_INPUT;377378/**379****************************************************************************************************380* ADDR_CREATEINFO_OUTPUT381*382* @brief383* Return AddrLib handle to client driver384*385****************************************************************************************************386*/387typedef struct _ADDR_CREATE_OUTPUT388{389UINT_32 size; ///< Size of this structure in bytes390391ADDR_HANDLE hLib; ///< Address lib handle392393UINT_32 numEquations; ///< Number of equations in the table394const ADDR_EQUATION* pEquationTable; ///< Pointer to the equation table395} ADDR_CREATE_OUTPUT;396397/**398****************************************************************************************************399* AddrCreate400*401* @brief402* Create AddrLib object, must be called before any interface calls403*404* @return405* ADDR_OK if successful406****************************************************************************************************407*/408ADDR_E_RETURNCODE ADDR_API AddrCreate(409const ADDR_CREATE_INPUT* pAddrCreateIn,410ADDR_CREATE_OUTPUT* pAddrCreateOut);411412413414/**415****************************************************************************************************416* AddrDestroy417*418* @brief419* Destroy AddrLib object, must be called to free internally allocated resources.420*421* @return422* ADDR_OK if successful423****************************************************************************************************424*/425ADDR_E_RETURNCODE ADDR_API AddrDestroy(426ADDR_HANDLE hLib);427428429430////////////////////////////////////////////////////////////////////////////////////////////////////431// Surface functions432////////////////////////////////////////////////////////////////////////////////////////////////////433434/**435****************************************************************************************************436* @brief437* Bank/tiling parameters. On function input, these can be set as desired or438* left 0 for AddrLib to calculate/default. On function output, these are the actual439* parameters used.440* @note441* Valid bankWidth/bankHeight value:442* 1,2,4,8. They are factors instead of pixels or bytes.443*444* The bank number remains constant across each row of the445* macro tile as each pipe is selected, so the number of446* tiles in the x direction with the same bank number will447* be bank_width * num_pipes.448****************************************************************************************************449*/450typedef struct _ADDR_TILEINFO451{452/// Any of these parameters can be set to 0 to use the HW default.453UINT_32 banks; ///< Number of banks, numerical value454UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank455UINT_32 bankHeight; ///< Number of tiles in the Y direction in the same bank456UINT_32 macroAspectRatio; ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1457UINT_32 tileSplitBytes; ///< Tile split size, in bytes458AddrPipeCfg pipeConfig; ///< Pipe Config = HW enum + 1459} ADDR_TILEINFO;460461// Create a define to avoid client change. The removal of R800 is because we plan to implement SI462// within 800 HWL - An AddrPipeCfg is added in above data structure463typedef ADDR_TILEINFO ADDR_R800_TILEINFO;464465/**466****************************************************************************************************467* @brief468* Information needed by quad buffer stereo support469****************************************************************************************************470*/471typedef struct _ADDR_QBSTEREOINFO472{473UINT_32 eyeHeight; ///< Height (in pixel rows) to right eye474UINT_32 rightOffset; ///< Offset (in bytes) to right eye475UINT_32 rightSwizzle; ///< TileSwizzle for right eyes476} ADDR_QBSTEREOINFO;477478/**479****************************************************************************************************480* ADDR_SURFACE_FLAGS481*482* @brief483* Surface flags484****************************************************************************************************485*/486typedef union _ADDR_SURFACE_FLAGS487{488struct489{490UINT_32 color : 1; ///< Flag indicates this is a color buffer491UINT_32 depth : 1; ///< Flag indicates this is a depth/stencil buffer492UINT_32 stencil : 1; ///< Flag indicates this is a stencil buffer493UINT_32 texture : 1; ///< Flag indicates this is a texture494UINT_32 cube : 1; ///< Flag indicates this is a cubemap495UINT_32 volume : 1; ///< Flag indicates this is a volume texture496UINT_32 fmask : 1; ///< Flag indicates this is an fmask497UINT_32 cubeAsArray : 1; ///< Flag indicates if treat cubemap as arrays498UINT_32 compressZ : 1; ///< Flag indicates z buffer is compressed499UINT_32 overlay : 1; ///< Flag indicates this is an overlay surface500UINT_32 noStencil : 1; ///< Flag indicates this depth has no separate stencil501UINT_32 display : 1; ///< Flag indicates this should match display controller req.502UINT_32 opt4Space : 1; ///< Flag indicates this surface should be optimized for space503/// i.e. save some memory but may lose performance504UINT_32 prt : 1; ///< Flag for partially resident texture505UINT_32 qbStereo : 1; ///< Quad buffer stereo surface506UINT_32 pow2Pad : 1; ///< SI: Pad to pow2, must set for mipmap (include level0)507UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding508UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable509UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce510UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear511UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that512/// dcc can't be enabled if pipe config of tile mode513/// is different from that of ASIC, this flag514/// is address lib internal flag, client should ignore it515UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment.516/// This flag indicates we need to follow the517/// alignment with CZ families or other ASICs under518/// PX configuration + CZ.519UINT_32 nonSplit : 1; ///< CI: depth texture should not be split520UINT_32 disableLinearOpt : 1; ///< Disable tile mode optimization to linear521UINT_32 needEquation : 1; ///< Make the surface tile setting equation compatible.522/// This flag indicates we need to override tile523/// mode to PRT_* tile mode to disable slice rotation,524/// which is needed by swizzle pattern equation.525UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output.526UINT_32 rotateDisplay : 1; ///< Rotate micro tile type527UINT_32 minimizeAlignment : 1; ///< Minimize alignment528UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode529UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface530/// to make sure they share same tile config parameters531UINT_32 disallowLargeThickDegrade : 1; ///< Disallow large thick tile degrade532UINT_32 reserved : 1; ///< Reserved bits533};534535UINT_32 value;536} ADDR_SURFACE_FLAGS;537538/**539****************************************************************************************************540* ADDR_COMPUTE_SURFACE_INFO_INPUT541*542* @brief543* Input structure for AddrComputeSurfaceInfo544****************************************************************************************************545*/546typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT547{548UINT_32 size; ///< Size of this structure in bytes549550AddrTileMode tileMode; ///< Tile mode551AddrFormat format; ///< If format is set to valid one, bpp/width/height552/// might be overwritten553UINT_32 bpp; ///< Bits per pixel554UINT_32 numSamples; ///< Number of samples555UINT_32 width; ///< Width, in pixels556UINT_32 height; ///< Height, in pixels557UINT_32 numSlices; ///< Number of surface slices or depth558UINT_32 slice; ///< Slice index559UINT_32 mipLevel; ///< Current mipmap level560UINT_32 numMipLevels; ///< Number of mips in mip chain561ADDR_SURFACE_FLAGS flags; ///< Surface type flags562UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as563/// number of samples for normal AA; Set it to the564/// number of fragments for EQAA565/// r800 and later HWL parameters566// Needed by 2D tiling, for linear and 1D tiling, just keep them 0's567ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate568AddrTileType tileType; ///< Micro tiling type, not needed when tileIndex != -1569INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it570/// while the global useTileIndex is set to 1571UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a572/// must for mip levels from SI+.573/// Don't use pitch in blocks for compressed formats!574UINT_32 maxBaseAlign; ///< Max base alignment request from client575UINT_32 pitchAlign; ///< Pitch alignment request from client576UINT_32 heightAlign; ///< Height alignment request from client577} ADDR_COMPUTE_SURFACE_INFO_INPUT;578579/**580****************************************************************************************************581* ADDR_COMPUTE_SURFACE_INFO_OUTPUT582*583* @brief584* Output structure for AddrComputeSurfInfo585* @note586Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch587Pixel: Original pixel588****************************************************************************************************589*/590typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT591{592UINT_32 size; ///< Size of this structure in bytes593594UINT_32 pitch; ///< Pitch in elements (in blocks for compressed formats)595UINT_32 height; ///< Height in elements (in blocks for compressed formats)596UINT_32 depth; ///< Number of slice/depth597UINT_64 surfSize; ///< Surface size in bytes598AddrTileMode tileMode; ///< Actual tile mode. May differ from that in input599UINT_32 baseAlign; ///< Base address alignment600UINT_32 pitchAlign; ///< Pitch alignment, in elements601UINT_32 heightAlign; ///< Height alignment, in elements602UINT_32 depthAlign; ///< Depth alignment, aligned to thickness, for 3d texture603UINT_32 bpp; ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit)604UINT_32 pixelPitch; ///< Pitch in original pixels605UINT_32 pixelHeight; ///< Height in original pixels606UINT_32 pixelBits; ///< Original bits per pixel, passed from input607UINT_64 sliceSize; ///< Size of slice specified by input's slice608/// The result is controlled by surface flags & createFlags609/// By default this value equals to surfSize for volume610UINT_32 pitchTileMax; ///< PITCH_TILE_MAX value for h/w register611UINT_32 heightTileMax; ///< HEIGHT_TILE_MAX value for h/w register612UINT_32 sliceTileMax; ///< SLICE_TILE_MAX value for h/w register613614UINT_32 numSamples; ///< Pass the effective numSamples processed in this call615616/// r800 and later HWL parameters617ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input618AddrTileType tileType; ///< Micro tiling type, only valid when tileIndex != -1619INT_32 tileIndex; ///< Tile index, MAY be "downgraded"620621INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)622/// Output flags623struct624{625/// Special information to work around SI mipmap swizzle bug UBTS #317508626UINT_32 last2DLevel : 1; ///< TRUE if this is the last 2D(3D) tiled627///< Only meaningful when create flag checkLast2DLevel is set628UINT_32 tcCompatible : 1; ///< If the surface can be shader compatible629UINT_32 dccUnsupport : 1; ///< If the surface can support DCC compressed rendering630UINT_32 prtTileIndex : 1; ///< SI only, indicate the returned tile index is for PRT631///< If address lib return true for mip 0, client should set prt flag632///< for child mips in subsequent compute surface info calls633UINT_32 reserved :28; ///< Reserved bits634};635636UINT_32 equationIndex; ///< Equation index in the equation table;637638UINT_32 blockWidth; ///< Width in element inside one block(1D->Micro, 2D->Macro)639UINT_32 blockHeight; ///< Height in element inside one block(1D->Micro, 2D->Macro)640UINT_32 blockSlices; ///< Slice number inside one block(1D->Micro, 2D->Macro)641642/// Stereo info643ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE644645INT_32 stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set646} ADDR_COMPUTE_SURFACE_INFO_OUTPUT;647648/**649****************************************************************************************************650* AddrComputeSurfaceInfo651*652* @brief653* Compute surface width/height/depth/alignments and suitable tiling mode654****************************************************************************************************655*/656ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo(657ADDR_HANDLE hLib,658const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,659ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut);660661662663/**664****************************************************************************************************665* ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT666*667* @brief668* Input structure for AddrComputeSurfaceAddrFromCoord669****************************************************************************************************670*/671typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT672{673UINT_32 size; ///< Size of this structure in bytes674675UINT_32 x; ///< X coordinate676UINT_32 y; ///< Y coordinate677UINT_32 slice; ///< Slice index678UINT_32 sample; ///< Sample index, use fragment index for EQAA679680UINT_32 bpp; ///< Bits per pixel681UINT_32 pitch; ///< Surface pitch, in pixels682UINT_32 height; ///< Surface height, in pixels683UINT_32 numSlices; ///< Surface depth684UINT_32 numSamples; ///< Number of samples685686AddrTileMode tileMode; ///< Tile mode687BOOL_32 isDepth; ///< TRUE if the surface uses depth sample ordering within688/// micro tile. Textures can also choose depth sample order689UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles690/// the case that components are stored separately691UINT_32 compBits; ///< The component bits actually needed(for planar surface)692693UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as694/// number of samples for normal AA; Set it to the695/// number of fragments for EQAA696/// r800 and later HWL parameters697// Used for 1D tiling above698AddrTileType tileType; ///< See defintion of AddrTileType699struct700{701UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture702/// only flag. Only non-RT texture can set this to TRUE703UINT_32 reserved :31; ///< Reserved for future use.704};705// 2D tiling needs following structure706ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data707INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it708/// while the global useTileIndex is set to 1709union710{711struct712{713UINT_32 bankSwizzle; ///< Bank swizzle714UINT_32 pipeSwizzle; ///< Pipe swizzle715};716UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE717};718} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;719720/**721****************************************************************************************************722* ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT723*724* @brief725* Output structure for AddrComputeSurfaceAddrFromCoord726****************************************************************************************************727*/728typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT729{730UINT_32 size; ///< Size of this structure in bytes731732UINT_64 addr; ///< Byte address733UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7.734/// For surface bpp < 8, e.g. FMT_1.735UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block)736} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT;737738/**739****************************************************************************************************740* AddrComputeSurfaceAddrFromCoord741*742* @brief743* Compute surface address from a given coordinate.744****************************************************************************************************745*/746ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord(747ADDR_HANDLE hLib,748const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,749ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);750751752753/**754****************************************************************************************************755* ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT756*757* @brief758* Input structure for AddrComputeSurfaceCoordFromAddr759****************************************************************************************************760*/761typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT762{763UINT_32 size; ///< Size of this structure in bytes764765UINT_64 addr; ///< Address in bytes766UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8,767/// e.g. FMT_1;768UINT_32 bpp; ///< Bits per pixel769UINT_32 pitch; ///< Pitch, in pixels770UINT_32 height; ///< Height in pixels771UINT_32 numSlices; ///< Surface depth772UINT_32 numSamples; ///< Number of samples773774AddrTileMode tileMode; ///< Tile mode775BOOL_32 isDepth; ///< Surface uses depth sample ordering within micro tile.776/// Note: Textures can choose depth sample order as well.777UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles778/// the case that components are stored separately779UINT_32 compBits; ///< The component bits actually needed(for planar surface)780781UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as782/// number of samples for normal AA; Set it to the783/// number of fragments for EQAA784/// r800 and later HWL parameters785// Used for 1D tiling above786AddrTileType tileType; ///< See defintion of AddrTileType787struct788{789UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture790/// only flag. Only non-RT texture can set this to TRUE791UINT_32 reserved :31; ///< Reserved for future use.792};793// 2D tiling needs following structure794ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data795INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it796/// while the global useTileIndex is set to 1797union798{799struct800{801UINT_32 bankSwizzle; ///< Bank swizzle802UINT_32 pipeSwizzle; ///< Pipe swizzle803};804UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE805};806} ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT;807808/**809****************************************************************************************************810* ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT811*812* @brief813* Output structure for AddrComputeSurfaceCoordFromAddr814****************************************************************************************************815*/816typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT817{818UINT_32 size; ///< Size of this structure in bytes819820UINT_32 x; ///< X coordinate821UINT_32 y; ///< Y coordinate822UINT_32 slice; ///< Index of slices823UINT_32 sample; ///< Index of samples, means fragment index for EQAA824} ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT;825826/**827****************************************************************************************************828* AddrComputeSurfaceCoordFromAddr829*830* @brief831* Compute coordinate from a given surface address832****************************************************************************************************833*/834ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr(835ADDR_HANDLE hLib,836const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,837ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut);838839////////////////////////////////////////////////////////////////////////////////////////////////////840// HTile functions841////////////////////////////////////////////////////////////////////////////////////////////////////842843/**844****************************************************************************************************845* ADDR_HTILE_FLAGS846*847* @brief848* HTILE flags849****************************************************************************************************850*/851typedef union _ADDR_HTILE_FLAGS852{853struct854{855UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable856UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile857/// size to 256xBankxPipe when computing tc-compatible858/// htile info.859UINT_32 reserved : 30; ///< Reserved bits860};861862UINT_32 value;863} ADDR_HTILE_FLAGS;864865/**866****************************************************************************************************867* ADDR_COMPUTE_HTILE_INFO_INPUT868*869* @brief870* Input structure of AddrComputeHtileInfo871****************************************************************************************************872*/873typedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT874{875UINT_32 size; ///< Size of this structure in bytes876877ADDR_HTILE_FLAGS flags; ///< HTILE flags878UINT_32 pitch; ///< Surface pitch, in pixels879UINT_32 height; ///< Surface height, in pixels880UINT_32 numSlices; ///< Number of slices881BOOL_32 isLinear; ///< Linear or tiled HTILE layout882AddrHtileBlockSize blockWidth; ///< 4 or 8. EG above only support 8883AddrHtileBlockSize blockHeight; ///< 4 or 8. EG above only support 8884ADDR_TILEINFO* pTileInfo; ///< Tile info885886INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it887/// while the global useTileIndex is set to 1888INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)889///< README: When tileIndex is not -1, this must be valid890} ADDR_COMPUTE_HTILE_INFO_INPUT;891892/**893****************************************************************************************************894* ADDR_COMPUTE_HTILE_INFO_OUTPUT895*896* @brief897* Output structure of AddrComputeHtileInfo898****************************************************************************************************899*/900typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT901{902UINT_32 size; ///< Size of this structure in bytes903904UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this905/// HTile buffer. This might be larger than original depth906/// buffer pitch when called with an unaligned pitch.907UINT_32 height; ///< Height in pixels, as above908UINT_64 htileBytes; ///< Size of HTILE buffer, in bytes909UINT_32 baseAlign; ///< Base alignment910UINT_32 bpp; ///< Bits per pixel for HTILE is how many bits for an 8x8 block!911UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape912UINT_32 macroHeight; ///< Macro height in pixels913UINT_64 sliceSize; ///< Slice size, in bytes.914BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved915/// Compute engine clear can't be used if htile is interleaved916BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in917/// next mip level, it also indicates if memory set based918/// fast clear can be used for current mip level.919} ADDR_COMPUTE_HTILE_INFO_OUTPUT;920921/**922****************************************************************************************************923* AddrComputeHtileInfo924*925* @brief926* Compute Htile pitch, height, base alignment and size in bytes927****************************************************************************************************928*/929ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo(930ADDR_HANDLE hLib,931const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn,932ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut);933934935936/**937****************************************************************************************************938* ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT939*940* @brief941* Input structure for AddrComputeHtileAddrFromCoord942****************************************************************************************************943*/944typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT945{946UINT_32 size; ///< Size of this structure in bytes947948UINT_32 pitch; ///< Pitch, in pixels949UINT_32 height; ///< Height in pixels950UINT_32 x; ///< X coordinate951UINT_32 y; ///< Y coordinate952UINT_32 slice; ///< Index of slice953UINT_32 numSlices; ///< Number of slices954BOOL_32 isLinear; ///< Linear or tiled HTILE layout955ADDR_HTILE_FLAGS flags; ///< htile flags956AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8957AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8958ADDR_TILEINFO* pTileInfo; ///< Tile info959960INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it961/// while the global useTileIndex is set to 1962INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)963///< README: When tileIndex is not -1, this must be valid964UINT_32 bpp; ///< depth/stencil buffer bit per pixel size965UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address966} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;967968/**969****************************************************************************************************970* ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT971*972* @brief973* Output structure for AddrComputeHtileAddrFromCoord974****************************************************************************************************975*/976typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT977{978UINT_32 size; ///< Size of this structure in bytes979980UINT_64 addr; ///< Address in bytes981UINT_32 bitPosition; ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method.982/// So we keep bitPosition for HTILE as well983} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT;984985/**986****************************************************************************************************987* AddrComputeHtileAddrFromCoord988*989* @brief990* Compute Htile address according to coordinates (of depth buffer)991****************************************************************************************************992*/993ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord(994ADDR_HANDLE hLib,995const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,996ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);9979989991000/**1001****************************************************************************************************1002* ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT1003*1004* @brief1005* Input structure for AddrComputeHtileCoordFromAddr1006****************************************************************************************************1007*/1008typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT1009{1010UINT_32 size; ///< Size of this structure in bytes10111012UINT_64 addr; ///< Address1013UINT_32 bitPosition; ///< Bit position 0 or 4. CMASK and HTILE share some methods1014/// so we keep bitPosition for HTILE as well1015UINT_32 pitch; ///< Pitch, in pixels1016UINT_32 height; ///< Height, in pixels1017UINT_32 numSlices; ///< Number of slices1018BOOL_32 isLinear; ///< Linear or tiled HTILE layout1019AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 81020AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 81021ADDR_TILEINFO* pTileInfo; ///< Tile info10221023INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it1024/// while the global useTileIndex is set to 11025INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)1026///< README: When tileIndex is not -1, this must be valid1027} ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT;10281029/**1030****************************************************************************************************1031* ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT1032*1033* @brief1034* Output structure for AddrComputeHtileCoordFromAddr1035****************************************************************************************************1036*/1037typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT1038{1039UINT_32 size; ///< Size of this structure in bytes10401041UINT_32 x; ///< X coordinate1042UINT_32 y; ///< Y coordinate1043UINT_32 slice; ///< Slice index1044} ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT;10451046/**1047****************************************************************************************************1048* AddrComputeHtileCoordFromAddr1049*1050* @brief1051* Compute coordinates within depth buffer (1st pixel of a micro tile) according to1052* Htile address1053****************************************************************************************************1054*/1055ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr(1056ADDR_HANDLE hLib,1057const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,1058ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);1059106010611062////////////////////////////////////////////////////////////////////////////////////////////////////1063// C-mask functions1064////////////////////////////////////////////////////////////////////////////////////////////////////10651066/**1067****************************************************************************************************1068* ADDR_CMASK_FLAGS1069*1070* @brief1071* CMASK flags1072****************************************************************************************************1073*/1074typedef union _ADDR_CMASK_FLAGS1075{1076struct1077{1078UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable1079UINT_32 reserved :31; ///< Reserved bits1080};10811082UINT_32 value;1083} ADDR_CMASK_FLAGS;10841085/**1086****************************************************************************************************1087* ADDR_COMPUTE_CMASK_INFO_INPUT1088*1089* @brief1090* Input structure of AddrComputeCmaskInfo1091****************************************************************************************************1092*/1093typedef struct _ADDR_COMPUTE_CMASKINFO_INPUT1094{1095UINT_32 size; ///< Size of this structure in bytes10961097ADDR_CMASK_FLAGS flags; ///< CMASK flags1098UINT_32 pitch; ///< Pitch, in pixels, of color buffer1099UINT_32 height; ///< Height, in pixels, of color buffer1100UINT_32 numSlices; ///< Number of slices, of color buffer1101BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear1102ADDR_TILEINFO* pTileInfo; ///< Tile info11031104INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it1105/// while the global useTileIndex is set to 11106INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)1107///< README: When tileIndex is not -1, this must be valid1108} ADDR_COMPUTE_CMASK_INFO_INPUT;11091110/**1111****************************************************************************************************1112* ADDR_COMPUTE_CMASK_INFO_OUTPUT1113*1114* @brief1115* Output structure of AddrComputeCmaskInfo1116****************************************************************************************************1117*/1118typedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT1119{1120UINT_32 size; ///< Size of this structure in bytes11211122UINT_32 pitch; ///< Pitch in pixels of color buffer which1123/// this Cmask matches. The size might be larger than1124/// original color buffer pitch when called with1125/// an unaligned pitch.1126UINT_32 height; ///< Height in pixels, as above1127UINT_64 cmaskBytes; ///< Size in bytes of CMask buffer1128UINT_32 baseAlign; ///< Base alignment1129UINT_32 blockMax; ///< Cmask block size. Need this to set CB_COLORn_MASK register1130UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape1131UINT_32 macroHeight; ///< Macro height in pixels1132UINT_64 sliceSize; ///< Slice size, in bytes.1133} ADDR_COMPUTE_CMASK_INFO_OUTPUT;11341135/**1136****************************************************************************************************1137* AddrComputeCmaskInfo1138*1139* @brief1140* Compute Cmask pitch, height, base alignment and size in bytes from color buffer1141* info1142****************************************************************************************************1143*/1144ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo(1145ADDR_HANDLE hLib,1146const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn,1147ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut);1148114911501151/**1152****************************************************************************************************1153* ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT1154*1155* @brief1156* Input structure for AddrComputeCmaskAddrFromCoord1157*1158****************************************************************************************************1159*/1160typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT1161{1162UINT_32 size; ///< Size of this structure in bytes1163UINT_32 x; ///< X coordinate1164UINT_32 y; ///< Y coordinate1165UINT_64 fmaskAddr; ///< Fmask addr for tc compatible Cmask1166UINT_32 slice; ///< Slice index1167UINT_32 pitch; ///< Pitch in pixels, of color buffer1168UINT_32 height; ///< Height in pixels, of color buffer1169UINT_32 numSlices; ///< Number of slices1170UINT_32 bpp;1171BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear1172ADDR_CMASK_FLAGS flags; ///< CMASK flags1173ADDR_TILEINFO* pTileInfo; ///< Tile info11741175INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it1176///< while the global useTileIndex is set to 11177INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)1178///< README: When tileIndex is not -1, this must be valid1179} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT;11801181/**1182****************************************************************************************************1183* ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT1184*1185* @brief1186* Output structure for AddrComputeCmaskAddrFromCoord1187****************************************************************************************************1188*/1189typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT1190{1191UINT_32 size; ///< Size of this structure in bytes11921193UINT_64 addr; ///< CMASK address in bytes1194UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp,1195/// so the address may be located in bit 0 (0) or 4 (4)1196} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT;11971198/**1199****************************************************************************************************1200* AddrComputeCmaskAddrFromCoord1201*1202* @brief1203* Compute Cmask address according to coordinates (of MSAA color buffer)1204****************************************************************************************************1205*/1206ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord(1207ADDR_HANDLE hLib,1208const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,1209ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);1210121112121213/**1214****************************************************************************************************1215* ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT1216*1217* @brief1218* Input structure for AddrComputeCmaskCoordFromAddr1219****************************************************************************************************1220*/1221typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT1222{1223UINT_32 size; ///< Size of this structure in bytes12241225UINT_64 addr; ///< CMASK address in bytes1226UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp,1227/// so the address may be located in bit 0 (0) or 4 (4)1228UINT_32 pitch; ///< Pitch, in pixels1229UINT_32 height; ///< Height in pixels1230UINT_32 numSlices; ///< Number of slices1231BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear1232ADDR_TILEINFO* pTileInfo; ///< Tile info12331234INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it1235/// while the global useTileIndex is set to 11236INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)1237///< README: When tileIndex is not -1, this must be valid1238} ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT;12391240/**1241****************************************************************************************************1242* ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT1243*1244* @brief1245* Output structure for AddrComputeCmaskCoordFromAddr1246****************************************************************************************************1247*/1248typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT1249{1250UINT_32 size; ///< Size of this structure in bytes12511252UINT_32 x; ///< X coordinate1253UINT_32 y; ///< Y coordinate1254UINT_32 slice; ///< Slice index1255} ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT;12561257/**1258****************************************************************************************************1259* AddrComputeCmaskCoordFromAddr1260*1261* @brief1262* Compute coordinates within color buffer (1st pixel of a micro tile) according to1263* Cmask address1264****************************************************************************************************1265*/1266ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr(1267ADDR_HANDLE hLib,1268const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,1269ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);1270127112721273////////////////////////////////////////////////////////////////////////////////////////////////////1274// F-mask functions1275////////////////////////////////////////////////////////////////////////////////////////////////////12761277/**1278****************************************************************************************************1279* ADDR_COMPUTE_FMASK_INFO_INPUT1280*1281* @brief1282* Input structure for AddrComputeFmaskInfo1283****************************************************************************************************1284*/1285typedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT1286{1287UINT_32 size; ///< Size of this structure in bytes12881289AddrTileMode tileMode; ///< Tile mode1290UINT_32 pitch; ///< Surface pitch, in pixels1291UINT_32 height; ///< Surface height, in pixels1292UINT_32 numSlices; ///< Number of slice/depth1293UINT_32 numSamples; ///< Number of samples1294UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as1295/// number of samples for normal AA; Set it to the1296/// number of fragments for EQAA1297/// r800 and later HWL parameters1298struct1299{1300UINT_32 resolved: 1; ///< TRUE if the surface is for resolved fmask, only used1301/// by H/W clients. S/W should always set it to FALSE.1302UINT_32 reserved: 31; ///< Reserved for future use.1303};1304ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Clients must give valid data1305INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it1306/// while the global useTileIndex is set to 11307} ADDR_COMPUTE_FMASK_INFO_INPUT;13081309/**1310****************************************************************************************************1311* ADDR_COMPUTE_FMASK_INFO_OUTPUT1312*1313* @brief1314* Output structure for AddrComputeFmaskInfo1315****************************************************************************************************1316*/1317typedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT1318{1319UINT_32 size; ///< Size of this structure in bytes13201321UINT_32 pitch; ///< Pitch of fmask in pixels1322UINT_32 height; ///< Height of fmask in pixels1323UINT_32 numSlices; ///< Slices of fmask1324UINT_64 fmaskBytes; ///< Size of fmask in bytes1325UINT_32 baseAlign; ///< Base address alignment1326UINT_32 pitchAlign; ///< Pitch alignment1327UINT_32 heightAlign; ///< Height alignment1328UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes1329UINT_32 numSamples; ///< Number of samples, used for dump, export this since input1330/// may be changed in 9xx and above1331/// r800 and later HWL parameters1332ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Fmask can have different1333/// bank_height from color buffer1334INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it1335/// while the global useTileIndex is set to 11336INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)1337UINT_64 sliceSize; ///< Size of slice in bytes1338} ADDR_COMPUTE_FMASK_INFO_OUTPUT;13391340/**1341****************************************************************************************************1342* AddrComputeFmaskInfo1343*1344* @brief1345* Compute Fmask pitch/height/depth/alignments and size in bytes1346****************************************************************************************************1347*/1348ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo(1349ADDR_HANDLE hLib,1350const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,1351ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);1352135313541355/**1356****************************************************************************************************1357* ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT1358*1359* @brief1360* Input structure for AddrComputeFmaskAddrFromCoord1361****************************************************************************************************1362*/1363typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT1364{1365UINT_32 size; ///< Size of this structure in bytes13661367UINT_32 x; ///< X coordinate1368UINT_32 y; ///< Y coordinate1369UINT_32 slice; ///< Slice index1370UINT_32 plane; ///< Plane number1371UINT_32 sample; ///< Sample index (fragment index for EQAA)13721373UINT_32 pitch; ///< Surface pitch, in pixels1374UINT_32 height; ///< Surface height, in pixels1375UINT_32 numSamples; ///< Number of samples1376UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as1377/// number of samples for normal AA; Set it to the1378/// number of fragments for EQAA13791380AddrTileMode tileMode; ///< Tile mode1381union1382{1383struct1384{1385UINT_32 bankSwizzle; ///< Bank swizzle1386UINT_32 pipeSwizzle; ///< Pipe swizzle1387};1388UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE1389};13901391/// r800 and later HWL parameters1392struct1393{1394UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by H/W clients1395UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored.1396UINT_32 reserved: 30; ///< Reserved for future use.1397};1398ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Client must provide all data13991400} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT;14011402/**1403****************************************************************************************************1404* ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT1405*1406* @brief1407* Output structure for AddrComputeFmaskAddrFromCoord1408****************************************************************************************************1409*/1410typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT1411{1412UINT_32 size; ///< Size of this structure in bytes14131414UINT_64 addr; ///< Fmask address1415UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7.1416} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT;14171418/**1419****************************************************************************************************1420* AddrComputeFmaskAddrFromCoord1421*1422* @brief1423* Compute Fmask address according to coordinates (x,y,slice,sample,plane)1424****************************************************************************************************1425*/1426ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord(1427ADDR_HANDLE hLib,1428const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,1429ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);1430143114321433/**1434****************************************************************************************************1435* ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT1436*1437* @brief1438* Input structure for AddrComputeFmaskCoordFromAddr1439****************************************************************************************************1440*/1441typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT1442{1443UINT_32 size; ///< Size of this structure in bytes14441445UINT_64 addr; ///< Address1446UINT_32 bitPosition; ///< Bit position within addr, 0-7.14471448UINT_32 pitch; ///< Pitch, in pixels1449UINT_32 height; ///< Height in pixels1450UINT_32 numSamples; ///< Number of samples1451UINT_32 numFrags; ///< Number of fragments1452AddrTileMode tileMode; ///< Tile mode1453union1454{1455struct1456{1457UINT_32 bankSwizzle; ///< Bank swizzle1458UINT_32 pipeSwizzle; ///< Pipe swizzle1459};1460UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE1461};14621463/// r800 and later HWL parameters1464struct1465{1466UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by HW components1467UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored.1468UINT_32 reserved: 30; ///< Reserved for future use.1469};1470ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data14711472} ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT;14731474/**1475****************************************************************************************************1476* ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT1477*1478* @brief1479* Output structure for AddrComputeFmaskCoordFromAddr1480****************************************************************************************************1481*/1482typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT1483{1484UINT_32 size; ///< Size of this structure in bytes14851486UINT_32 x; ///< X coordinate1487UINT_32 y; ///< Y coordinate1488UINT_32 slice; ///< Slice index1489UINT_32 plane; ///< Plane number1490UINT_32 sample; ///< Sample index (fragment index for EQAA)1491} ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT;14921493/**1494****************************************************************************************************1495* AddrComputeFmaskCoordFromAddr1496*1497* @brief1498* Compute FMASK coordinate from an given address1499****************************************************************************************************1500*/1501ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr(1502ADDR_HANDLE hLib,1503const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,1504ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);1505150615071508////////////////////////////////////////////////////////////////////////////////////////////////////1509// Element/utility functions1510////////////////////////////////////////////////////////////////////////////////////////////////////15111512/**1513****************************************************************************************************1514* AddrGetVersion1515*1516* @brief1517* Get AddrLib version number1518****************************************************************************************************1519*/1520UINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib);15211522/**1523****************************************************************************************************1524* AddrUseTileIndex1525*1526* @brief1527* Return TRUE if tileIndex is enabled in this address library1528****************************************************************************************************1529*/1530BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib);15311532/**1533****************************************************************************************************1534* AddrUseCombinedSwizzle1535*1536* @brief1537* Return TRUE if combined swizzle is enabled in this address library1538****************************************************************************************************1539*/1540BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib);15411542/**1543****************************************************************************************************1544* ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT1545*1546* @brief1547* Input structure of AddrExtractBankPipeSwizzle1548****************************************************************************************************1549*/1550typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT1551{1552UINT_32 size; ///< Size of this structure in bytes15531554UINT_32 base256b; ///< Base256b value15551556/// r800 and later HWL parameters1557ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data15581559INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it1560/// while the global useTileIndex is set to 11561INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)1562///< README: When tileIndex is not -1, this must be valid1563} ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT;15641565/**1566****************************************************************************************************1567* ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT1568*1569* @brief1570* Output structure of AddrExtractBankPipeSwizzle1571****************************************************************************************************1572*/1573typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT1574{1575UINT_32 size; ///< Size of this structure in bytes15761577UINT_32 bankSwizzle; ///< Bank swizzle1578UINT_32 pipeSwizzle; ///< Pipe swizzle1579} ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT;15801581/**1582****************************************************************************************************1583* AddrExtractBankPipeSwizzle1584*1585* @brief1586* Extract Bank and Pipe swizzle from base256b1587* @return1588* ADDR_OK if no error1589****************************************************************************************************1590*/1591ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle(1592ADDR_HANDLE hLib,1593const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,1594ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut);159515961597/**1598****************************************************************************************************1599* ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT1600*1601* @brief1602* Input structure of AddrCombineBankPipeSwizzle1603****************************************************************************************************1604*/1605typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT1606{1607UINT_32 size; ///< Size of this structure in bytes16081609UINT_32 bankSwizzle; ///< Bank swizzle1610UINT_32 pipeSwizzle; ///< Pipe swizzle1611UINT_64 baseAddr; ///< Base address (leave it zero for driver clients)16121613/// r800 and later HWL parameters1614ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data16151616INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it1617/// while the global useTileIndex is set to 11618INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)1619///< README: When tileIndex is not -1, this must be valid1620} ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT;16211622/**1623****************************************************************************************************1624* ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT1625*1626* @brief1627* Output structure of AddrCombineBankPipeSwizzle1628****************************************************************************************************1629*/1630typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT1631{1632UINT_32 size; ///< Size of this structure in bytes16331634UINT_32 tileSwizzle; ///< Combined swizzle1635} ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT;16361637/**1638****************************************************************************************************1639* AddrCombineBankPipeSwizzle1640*1641* @brief1642* Combine Bank and Pipe swizzle1643* @return1644* ADDR_OK if no error1645* @note1646* baseAddr here is full MCAddress instead of base256b1647****************************************************************************************************1648*/1649ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle(1650ADDR_HANDLE hLib,1651const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn,1652ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut);1653165416551656/**1657****************************************************************************************************1658* ADDR_COMPUTE_SLICESWIZZLE_INPUT1659*1660* @brief1661* Input structure of AddrComputeSliceSwizzle1662****************************************************************************************************1663*/1664typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT1665{1666UINT_32 size; ///< Size of this structure in bytes16671668AddrTileMode tileMode; ///< Tile Mode1669UINT_32 baseSwizzle; ///< Base tile swizzle1670UINT_32 slice; ///< Slice index1671UINT_64 baseAddr; ///< Base address, driver should leave it 0 in most cases16721673/// r800 and later HWL parameters1674ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here!16751676INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it1677/// while the global useTileIndex is set to 11678INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)1679///< README: When tileIndex is not -1, this must be valid1680} ADDR_COMPUTE_SLICESWIZZLE_INPUT;1681168216831684/**1685****************************************************************************************************1686* ADDR_COMPUTE_SLICESWIZZLE_OUTPUT1687*1688* @brief1689* Output structure of AddrComputeSliceSwizzle1690****************************************************************************************************1691*/1692typedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT1693{1694UINT_32 size; ///< Size of this structure in bytes16951696UINT_32 tileSwizzle; ///< Recalculated tileSwizzle value1697} ADDR_COMPUTE_SLICESWIZZLE_OUTPUT;16981699/**1700****************************************************************************************************1701* AddrComputeSliceSwizzle1702*1703* @brief1704* Extract Bank and Pipe swizzle from base256b1705* @return1706* ADDR_OK if no error1707****************************************************************************************************1708*/1709ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle(1710ADDR_HANDLE hLib,1711const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,1712ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut);171317141715/**1716****************************************************************************************************1717* AddrSwizzleGenOption1718*1719* @brief1720* Which swizzle generating options: legacy or linear1721****************************************************************************************************1722*/1723typedef enum _AddrSwizzleGenOption1724{1725ADDR_SWIZZLE_GEN_DEFAULT = 0, ///< As is in client driver implemention for swizzle1726ADDR_SWIZZLE_GEN_LINEAR = 1, ///< Using a linear increment of swizzle1727} AddrSwizzleGenOption;17281729/**1730****************************************************************************************************1731* AddrSwizzleOption1732*1733* @brief1734* Controls how swizzle is generated1735****************************************************************************************************1736*/1737typedef union _ADDR_SWIZZLE_OPTION1738{1739struct1740{1741UINT_32 genOption : 1; ///< The way swizzle is generated, see AddrSwizzleGenOption1742UINT_32 reduceBankBit : 1; ///< TRUE if we need reduce swizzle bits1743UINT_32 reserved :30; ///< Reserved bits1744};17451746UINT_32 value;17471748} ADDR_SWIZZLE_OPTION;17491750/**1751****************************************************************************************************1752* ADDR_COMPUTE_BASE_SWIZZLE_INPUT1753*1754* @brief1755* Input structure of AddrComputeBaseSwizzle1756****************************************************************************************************1757*/1758typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT1759{1760UINT_32 size; ///< Size of this structure in bytes17611762ADDR_SWIZZLE_OPTION option; ///< Swizzle option1763UINT_32 surfIndex; ///< Index of this surface type1764AddrTileMode tileMode; ///< Tile Mode17651766/// r800 and later HWL parameters1767ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here!17681769INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it1770/// while the global useTileIndex is set to 11771INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)1772///< README: When tileIndex is not -1, this must be valid1773} ADDR_COMPUTE_BASE_SWIZZLE_INPUT;17741775/**1776****************************************************************************************************1777* ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT1778*1779* @brief1780* Output structure of AddrComputeBaseSwizzle1781****************************************************************************************************1782*/1783typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT1784{1785UINT_32 size; ///< Size of this structure in bytes17861787UINT_32 tileSwizzle; ///< Combined swizzle1788} ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT;17891790/**1791****************************************************************************************************1792* AddrComputeBaseSwizzle1793*1794* @brief1795* Return a Combined Bank and Pipe swizzle base on surface based on surface type/index1796* @return1797* ADDR_OK if no error1798****************************************************************************************************1799*/1800ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle(1801ADDR_HANDLE hLib,1802const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,1803ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut);1804180518061807/**1808****************************************************************************************************1809* ELEM_GETEXPORTNORM_INPUT1810*1811* @brief1812* Input structure for ElemGetExportNorm1813*1814****************************************************************************************************1815*/1816typedef struct _ELEM_GETEXPORTNORM_INPUT1817{1818UINT_32 size; ///< Size of this structure in bytes18191820AddrColorFormat format; ///< Color buffer format; Client should use ColorFormat1821AddrSurfaceNumber num; ///< Surface number type; Client should use NumberType1822AddrSurfaceSwap swap; ///< Surface swap byte swap; Client should use SurfaceSwap1823UINT_32 numSamples; ///< Number of samples1824} ELEM_GETEXPORTNORM_INPUT;18251826/**1827****************************************************************************************************1828* ElemGetExportNorm1829*1830* @brief1831* Helper function to check one format can be EXPORT_NUM, which is a register1832* CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r6001833* family1834* @note1835* The implementation is only for r600.1836* 00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two1837* clocks per export)1838* 01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one1839* clock per export)1840*1841****************************************************************************************************1842*/1843BOOL_32 ADDR_API ElemGetExportNorm(1844ADDR_HANDLE hLib,1845const ELEM_GETEXPORTNORM_INPUT* pIn);1846184718481849/**1850****************************************************************************************************1851* ELEM_FLT32TODEPTHPIXEL_INPUT1852*1853* @brief1854* Input structure for addrFlt32ToDepthPixel1855*1856****************************************************************************************************1857*/1858typedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT1859{1860UINT_32 size; ///< Size of this structure in bytes18611862AddrDepthFormat format; ///< Depth buffer format1863ADDR_FLT_32 comps[2]; ///< Component values (Z/stencil)1864} ELEM_FLT32TODEPTHPIXEL_INPUT;18651866/**1867****************************************************************************************************1868* ELEM_FLT32TODEPTHPIXEL_INPUT1869*1870* @brief1871* Output structure for ElemFlt32ToDepthPixel1872*1873****************************************************************************************************1874*/1875typedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT1876{1877UINT_32 size; ///< Size of this structure in bytes18781879UINT_8* pPixel; ///< Real depth value. Same data type as depth buffer.1880/// Client must provide enough storage for this type.1881UINT_32 depthBase; ///< Tile base in bits for depth bits1882UINT_32 stencilBase; ///< Tile base in bits for stencil bits1883UINT_32 depthBits; ///< Bits for depth1884UINT_32 stencilBits; ///< Bits for stencil1885} ELEM_FLT32TODEPTHPIXEL_OUTPUT;18861887/**1888****************************************************************************************************1889* ElemFlt32ToDepthPixel1890*1891* @brief1892* Convert a FLT_32 value to a depth/stencil pixel value1893*1894* @return1895* Return code1896*1897****************************************************************************************************1898*/1899ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel(1900ADDR_HANDLE hLib,1901const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,1902ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut);1903190419051906/**1907****************************************************************************************************1908* ELEM_FLT32TOCOLORPIXEL_INPUT1909*1910* @brief1911* Input structure for addrFlt32ToColorPixel1912*1913****************************************************************************************************1914*/1915typedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT1916{1917UINT_32 size; ///< Size of this structure in bytes19181919AddrColorFormat format; ///< Color buffer format1920AddrSurfaceNumber surfNum; ///< Surface number1921AddrSurfaceSwap surfSwap; ///< Surface swap1922ADDR_FLT_32 comps[4]; ///< Component values (r/g/b/a)1923} ELEM_FLT32TOCOLORPIXEL_INPUT;19241925/**1926****************************************************************************************************1927* ELEM_FLT32TOCOLORPIXEL_INPUT1928*1929* @brief1930* Output structure for ElemFlt32ToColorPixel1931*1932****************************************************************************************************1933*/1934typedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT1935{1936UINT_32 size; ///< Size of this structure in bytes19371938UINT_8* pPixel; ///< Real color value. Same data type as color buffer.1939/// Client must provide enough storage for this type.1940} ELEM_FLT32TOCOLORPIXEL_OUTPUT;19411942/**1943****************************************************************************************************1944* ElemFlt32ToColorPixel1945*1946* @brief1947* Convert a FLT_32 value to a red/green/blue/alpha pixel value1948*1949* @return1950* Return code1951*1952****************************************************************************************************1953*/1954ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel(1955ADDR_HANDLE hLib,1956const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,1957ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut);19581959/**1960****************************************************************************************************1961* ElemSize1962*1963* @brief1964* Get bits-per-element for specified format1965*1966* @return1967* Bits-per-element of specified format1968*1969****************************************************************************************************1970*/1971UINT_32 ADDR_API ElemSize(1972ADDR_HANDLE hLib,1973AddrFormat format);19741975/**1976****************************************************************************************************1977* ADDR_CONVERT_TILEINFOTOHW_INPUT1978*1979* @brief1980* Input structure for AddrConvertTileInfoToHW1981* @note1982* When reverse is TRUE, indices are igonred1983****************************************************************************************************1984*/1985typedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT1986{1987UINT_32 size; ///< Size of this structure in bytes1988BOOL_32 reverse; ///< Convert control flag.1989/// FALSE: convert from real value to HW value;1990/// TRUE: convert from HW value to real value.19911992/// r800 and later HWL parameters1993ADDR_TILEINFO* pTileInfo; ///< Tile parameters with real value19941995INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it1996/// while the global useTileIndex is set to 11997INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)1998///< README: When tileIndex is not -1, this must be valid1999UINT_32 bpp; ///< Bits per pixel2000} ADDR_CONVERT_TILEINFOTOHW_INPUT;20012002/**2003****************************************************************************************************2004* ADDR_CONVERT_TILEINFOTOHW_OUTPUT2005*2006* @brief2007* Output structure for AddrConvertTileInfoToHW2008****************************************************************************************************2009*/2010typedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT2011{2012UINT_32 size; ///< Size of this structure in bytes20132014/// r800 and later HWL parameters2015ADDR_TILEINFO* pTileInfo; ///< Tile parameters with hardware register value20162017} ADDR_CONVERT_TILEINFOTOHW_OUTPUT;20182019/**2020****************************************************************************************************2021* AddrConvertTileInfoToHW2022*2023* @brief2024* Convert tile info from real value to hardware register value2025****************************************************************************************************2026*/2027ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW(2028ADDR_HANDLE hLib,2029const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,2030ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut);2031203220332034/**2035****************************************************************************************************2036* ADDR_CONVERT_TILEINDEX_INPUT2037*2038* @brief2039* Input structure for AddrConvertTileIndex2040****************************************************************************************************2041*/2042typedef struct _ADDR_CONVERT_TILEINDEX_INPUT2043{2044UINT_32 size; ///< Size of this structure in bytes20452046INT_32 tileIndex; ///< Tile index2047INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)2048UINT_32 bpp; ///< Bits per pixel2049BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual2050} ADDR_CONVERT_TILEINDEX_INPUT;20512052/**2053****************************************************************************************************2054* ADDR_CONVERT_TILEINDEX_OUTPUT2055*2056* @brief2057* Output structure for AddrConvertTileIndex2058****************************************************************************************************2059*/2060typedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT2061{2062UINT_32 size; ///< Size of this structure in bytes20632064AddrTileMode tileMode; ///< Tile mode2065AddrTileType tileType; ///< Tile type2066ADDR_TILEINFO* pTileInfo; ///< Tile info20672068} ADDR_CONVERT_TILEINDEX_OUTPUT;20692070/**2071****************************************************************************************************2072* AddrConvertTileIndex2073*2074* @brief2075* Convert tile index to tile mode/type/info2076****************************************************************************************************2077*/2078ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex(2079ADDR_HANDLE hLib,2080const ADDR_CONVERT_TILEINDEX_INPUT* pIn,2081ADDR_CONVERT_TILEINDEX_OUTPUT* pOut);20822083/**2084****************************************************************************************************2085* ADDR_GET_MACROMODEINDEX_INPUT2086*2087* @brief2088* Input structure for AddrGetMacroModeIndex2089****************************************************************************************************2090*/2091typedef struct _ADDR_GET_MACROMODEINDEX_INPUT2092{2093UINT_32 size; ///< Size of this structure in bytes2094ADDR_SURFACE_FLAGS flags; ///< Surface flag2095INT_32 tileIndex; ///< Tile index2096UINT_32 bpp; ///< Bits per pixel2097UINT_32 numFrags; ///< Number of color fragments2098} ADDR_GET_MACROMODEINDEX_INPUT;20992100/**2101****************************************************************************************************2102* ADDR_GET_MACROMODEINDEX_OUTPUT2103*2104* @brief2105* Output structure for AddrGetMacroModeIndex2106****************************************************************************************************2107*/2108typedef struct _ADDR_GET_MACROMODEINDEX_OUTPUT2109{2110UINT_32 size; ///< Size of this structure in bytes2111INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)2112} ADDR_GET_MACROMODEINDEX_OUTPUT;21132114/**2115****************************************************************************************************2116* AddrGetMacroModeIndex2117*2118* @brief2119* Get macro mode index based on input parameters2120****************************************************************************************************2121*/2122ADDR_E_RETURNCODE ADDR_API AddrGetMacroModeIndex(2123ADDR_HANDLE hLib,2124const ADDR_GET_MACROMODEINDEX_INPUT* pIn,2125ADDR_GET_MACROMODEINDEX_OUTPUT* pOut);21262127/**2128****************************************************************************************************2129* ADDR_CONVERT_TILEINDEX1_INPUT2130*2131* @brief2132* Input structure for AddrConvertTileIndex1 (without macro mode index)2133****************************************************************************************************2134*/2135typedef struct _ADDR_CONVERT_TILEINDEX1_INPUT2136{2137UINT_32 size; ///< Size of this structure in bytes21382139INT_32 tileIndex; ///< Tile index2140UINT_32 bpp; ///< Bits per pixel2141UINT_32 numSamples; ///< Number of samples2142BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual2143} ADDR_CONVERT_TILEINDEX1_INPUT;21442145/**2146****************************************************************************************************2147* AddrConvertTileIndex12148*2149* @brief2150* Convert tile index to tile mode/type/info2151****************************************************************************************************2152*/2153ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1(2154ADDR_HANDLE hLib,2155const ADDR_CONVERT_TILEINDEX1_INPUT* pIn,2156ADDR_CONVERT_TILEINDEX_OUTPUT* pOut);2157215821592160/**2161****************************************************************************************************2162* ADDR_GET_TILEINDEX_INPUT2163*2164* @brief2165* Input structure for AddrGetTileIndex2166****************************************************************************************************2167*/2168typedef struct _ADDR_GET_TILEINDEX_INPUT2169{2170UINT_32 size; ///< Size of this structure in bytes21712172AddrTileMode tileMode; ///< Tile mode2173AddrTileType tileType; ///< Tile-type: disp/non-disp/...2174ADDR_TILEINFO* pTileInfo; ///< Pointer to tile-info structure, can be NULL for linear/1D2175} ADDR_GET_TILEINDEX_INPUT;21762177/**2178****************************************************************************************************2179* ADDR_GET_TILEINDEX_OUTPUT2180*2181* @brief2182* Output structure for AddrGetTileIndex2183****************************************************************************************************2184*/2185typedef struct _ADDR_GET_TILEINDEX_OUTPUT2186{2187UINT_32 size; ///< Size of this structure in bytes21882189INT_32 index; ///< index in table2190} ADDR_GET_TILEINDEX_OUTPUT;21912192/**2193****************************************************************************************************2194* AddrGetTileIndex2195*2196* @brief2197* Get the tiling mode index in table2198****************************************************************************************************2199*/2200ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex(2201ADDR_HANDLE hLib,2202const ADDR_GET_TILEINDEX_INPUT* pIn,2203ADDR_GET_TILEINDEX_OUTPUT* pOut);2204220522062207/**2208****************************************************************************************************2209* ADDR_PRT_INFO_INPUT2210*2211* @brief2212* Input structure for AddrComputePrtInfo2213****************************************************************************************************2214*/2215typedef struct _ADDR_PRT_INFO_INPUT2216{2217AddrFormat format; ///< Surface format2218UINT_32 baseMipWidth; ///< Base mipmap width2219UINT_32 baseMipHeight; ///< Base mipmap height2220UINT_32 baseMipDepth; ///< Base mipmap depth2221UINT_32 numFrags; ///< Number of fragments,2222} ADDR_PRT_INFO_INPUT;22232224/**2225****************************************************************************************************2226* ADDR_PRT_INFO_OUTPUT2227*2228* @brief2229* Input structure for AddrComputePrtInfo2230****************************************************************************************************2231*/2232typedef struct _ADDR_PRT_INFO_OUTPUT2233{2234UINT_32 prtTileWidth;2235UINT_32 prtTileHeight;2236} ADDR_PRT_INFO_OUTPUT;22372238/**2239****************************************************************************************************2240* AddrComputePrtInfo2241*2242* @brief2243* Compute prt surface related information2244****************************************************************************************************2245*/2246ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(2247ADDR_HANDLE hLib,2248const ADDR_PRT_INFO_INPUT* pIn,2249ADDR_PRT_INFO_OUTPUT* pOut);2250225122522253////////////////////////////////////////////////////////////////////////////////////////////////////2254// DCC key functions2255////////////////////////////////////////////////////////////////////////////////////////////////////22562257/**2258****************************************************************************************************2259* _ADDR_COMPUTE_DCCINFO_INPUT2260*2261* @brief2262* Input structure of AddrComputeDccInfo2263****************************************************************************************************2264*/2265typedef struct _ADDR_COMPUTE_DCCINFO_INPUT2266{2267UINT_32 size; ///< Size of this structure in bytes2268UINT_32 bpp; ///< BitPP of color surface2269UINT_32 numSamples; ///< Sample number of color surface2270UINT_64 colorSurfSize; ///< Size of color surface to which dcc key is bound2271AddrTileMode tileMode; ///< Tile mode of color surface2272ADDR_TILEINFO tileInfo; ///< Tile info of color surface2273UINT_32 tileSwizzle; ///< Tile swizzle2274INT_32 tileIndex; ///< Tile index of color surface,2275///< MUST be -1 if you don't want to use it2276///< while the global useTileIndex is set to 12277INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)2278///< README: When tileIndex is not -1, this must be valid2279} ADDR_COMPUTE_DCCINFO_INPUT;22802281/**2282****************************************************************************************************2283* ADDR_COMPUTE_DCCINFO_OUTPUT2284*2285* @brief2286* Output structure of AddrComputeDccInfo2287****************************************************************************************************2288*/2289typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT2290{2291UINT_32 size; ///< Size of this structure in bytes2292UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key2293UINT_64 dccRamSize; ///< Size of dcc key2294UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared2295BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable2296BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned2297} ADDR_COMPUTE_DCCINFO_OUTPUT;22982299/**2300****************************************************************************************************2301* AddrComputeDccInfo2302*2303* @brief2304* Compute DCC key size, base alignment2305* info2306****************************************************************************************************2307*/2308ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(2309ADDR_HANDLE hLib,2310const ADDR_COMPUTE_DCCINFO_INPUT* pIn,2311ADDR_COMPUTE_DCCINFO_OUTPUT* pOut);2312231323142315/**2316****************************************************************************************************2317* ADDR_GET_MAX_ALIGNMENTS_OUTPUT2318*2319* @brief2320* Output structure of AddrGetMaxAlignments2321****************************************************************************************************2322*/2323typedef struct ADDR_GET_MAX_ALINGMENTS_OUTPUT2324{2325UINT_32 size; ///< Size of this structure in bytes2326UINT_32 baseAlign; ///< Maximum base alignment in bytes2327} ADDR_GET_MAX_ALIGNMENTS_OUTPUT;23282329/**2330****************************************************************************************************2331* AddrGetMaxAlignments2332*2333* @brief2334* Gets maximnum alignments2335****************************************************************************************************2336*/2337ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(2338ADDR_HANDLE hLib,2339ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut);23402341/**2342****************************************************************************************************2343* AddrGetMaxMetaAlignments2344*2345* @brief2346* Gets maximnum alignments for metadata2347****************************************************************************************************2348*/2349ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(2350ADDR_HANDLE hLib,2351ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut);23522353/**2354****************************************************************************************************2355* Address library interface version 22356* available from Gfx9 hardware2357****************************************************************************************************2358* Addr2ComputeSurfaceInfo()2359* Addr2ComputeSurfaceAddrFromCoord()2360* Addr2ComputeSurfaceCoordFromAddr()23612362* Addr2ComputeHtileInfo()2363* Addr2ComputeHtileAddrFromCoord()2364* Addr2ComputeHtileCoordFromAddr()2365*2366* Addr2ComputeCmaskInfo()2367* Addr2ComputeCmaskAddrFromCoord()2368* Addr2ComputeCmaskCoordFromAddr()2369*2370* Addr2ComputeFmaskInfo()2371* Addr2ComputeFmaskAddrFromCoord()2372* Addr2ComputeFmaskCoordFromAddr()2373*2374* Addr2ComputeDccInfo()2375*2376**/237723782379////////////////////////////////////////////////////////////////////////////////////////////////////2380// Surface functions for Gfx92381////////////////////////////////////////////////////////////////////////////////////////////////////23822383/**2384****************************************************************************************************2385* ADDR2_SURFACE_FLAGS2386*2387* @brief2388* Surface flags2389****************************************************************************************************2390*/2391typedef union _ADDR2_SURFACE_FLAGS2392{2393struct2394{2395UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV2396UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV2397UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV2398UINT_32 fmask : 1; ///< This is an fmask surface2399UINT_32 overlay : 1; ///< This is an overlay surface2400UINT_32 display : 1; ///< This resource is displable, can be used with DRV2401UINT_32 prt : 1; ///< This is a partially resident texture2402UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface2403UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding2404UINT_32 texture : 1; ///< This resource can be used with SRV2405UINT_32 unordered : 1; ///< This resource can be used with UAV2406UINT_32 rotated : 1; ///< This resource is rotated and displable2407UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible2408UINT_32 opt4space : 1; ///< This resource should be optimized for space2409UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment2410UINT_32 noMetadata : 1; ///< This resource has no metadata2411UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata2412UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata2413UINT_32 view3dAs2dArray : 1; ///< This resource is a 3D resource viewed as 2D array2414UINT_32 reserved : 13; ///< Reserved bits2415};24162417UINT_32 value;2418} ADDR2_SURFACE_FLAGS;24192420/**2421****************************************************************************************************2422* ADDR2_COMPUTE_SURFACE_INFO_INPUT2423*2424* @brief2425* Input structure for Addr2ComputeSurfaceInfo2426****************************************************************************************************2427*/2428typedef struct _ADDR2_COMPUTE_SURFACE_INFO_INPUT2429{2430UINT_32 size; ///< Size of this structure in bytes24312432ADDR2_SURFACE_FLAGS flags; ///< Surface flags2433AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx92434AddrResourceType resourceType; ///< Surface type2435AddrFormat format; ///< Surface format2436UINT_32 bpp; ///< bits per pixel2437UINT_32 width; ///< Width (of mip0), in pixels2438UINT_32 height; ///< Height (of mip0), in pixels2439UINT_32 numSlices; ///< Number surface slice/depth (of mip0),2440UINT_32 numMipLevels; ///< Total mipmap levels.2441UINT_32 numSamples; ///< Number of samples2442UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as2443/// number of samples for normal AA; Set it to the2444/// number of fragments for EQAA2445UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)2446UINT_32 sliceAlign; ///< Required slice size in bytes2447} ADDR2_COMPUTE_SURFACE_INFO_INPUT;24482449/**2450****************************************************************************************************2451* ADDR2_MIP_INFO2452*2453* @brief2454* Structure that contains information for mip level2455*2456****************************************************************************************************2457*/2458typedef struct _ADDR2_MIP_INFO2459{2460UINT_32 pitch; ///< Pitch in elements2461UINT_32 height; ///< Padded height in elements2462UINT_32 depth; ///< Padded depth2463UINT_32 pixelPitch; ///< Pitch in pixels2464UINT_32 pixelHeight; ///< Padded height in pixels2465UINT_32 equationIndex; ///< Equation index in the equation table2466UINT_64 offset; ///< Offset in bytes from mip base, should only be used2467///< to setup vam surface descriptor, can't be used2468///< to setup swizzle pattern2469UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base2470UINT_32 mipTailOffset; ///< mip tail offset in bytes2471UINT_32 mipTailCoordX; ///< mip tail coord x2472UINT_32 mipTailCoordY; ///< mip tail coord y2473UINT_32 mipTailCoordZ; ///< mip tail coord z2474} ADDR2_MIP_INFO;24752476/**2477****************************************************************************************************2478* ADDR2_COMPUTE_SURFACE_INFO_OUTPUT2479*2480* @brief2481* Output structure for Addr2ComputeSurfInfo2482* @note2483Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch2484Pixel: Original pixel2485****************************************************************************************************2486*/2487typedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT2488{2489UINT_32 size; ///< Size of this structure in bytes24902491UINT_32 pitch; ///< Pitch in elements (blocks for compressed formats)2492UINT_32 height; ///< Padded height (of mip0) in elements2493UINT_32 numSlices; ///< Padded depth for 3d resource2494///< or padded number of slices for 2d array resource2495UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements2496UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements2497UINT_32 mipChainSlice; ///< Padded depth (of total mip chain)2498UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes2499UINT_64 surfSize; ///< Surface (total mip chain) size in bytes2500UINT_32 baseAlign; ///< Base address alignment2501UINT_32 bpp; ///< Bits per elements2502/// (e.g. blocks for BCn, 1/3 for 96bit)2503UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels2504UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels2505UINT_32 pixelPitch; ///< Pitch in original pixels2506UINT_32 pixelHeight; ///< Height in original pixels2507UINT_32 pixelBits; ///< Original bits per pixel, passed from input25082509UINT_32 blockWidth; ///< Width in element inside one block2510UINT_32 blockHeight; ///< Height in element inside one block2511UINT_32 blockSlices; ///< Slice number inside one block2512///< Prt tile is one block, its width/height/slice2513///< equals to blcok width/height/slice25142515BOOL_32 epitchIsHeight; ///< Whether to use height to program epitch register2516/// Stereo info2517ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE2518/// Mip info2519ADDR2_MIP_INFO* pMipInfo; ///< Pointer to mip information array2520/// if it is not NULL, the array is assumed to2521/// contain numMipLevels entries25222523UINT_32 equationIndex; ///< Equation index in the equation table of mip02524BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block2525UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip2526/// in tail, it will be set to number of mip levels2527} ADDR2_COMPUTE_SURFACE_INFO_OUTPUT;25282529/**2530****************************************************************************************************2531* Addr2ComputeSurfaceInfo2532*2533* @brief2534* Compute surface width/height/slices/alignments and suitable tiling mode2535****************************************************************************************************2536*/2537ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo(2538ADDR_HANDLE hLib,2539const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,2540ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut);2541254225432544/**2545****************************************************************************************************2546* ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT2547*2548* @brief2549* Input structure for Addr2ComputeSurfaceAddrFromCoord2550****************************************************************************************************2551*/2552typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT2553{2554UINT_32 size; ///< Size of this structure in bytes25552556UINT_32 x; ///< X coordinate2557UINT_32 y; ///< Y coordinate2558UINT_32 slice; ///< Slice index2559UINT_32 sample; ///< Sample index, use fragment index for EQAA2560UINT_32 mipId; ///< the mip ID in mip chain25612562AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx92563ADDR2_SURFACE_FLAGS flags; ///< Surface flags2564AddrResourceType resourceType; ///< Surface type2565UINT_32 bpp; ///< Bits per pixel2566UINT_32 unalignedWidth; ///< Surface original width (of mip0)2567UINT_32 unalignedHeight; ///< Surface original height (of mip0)2568UINT_32 numSlices; ///< Surface original slices (of mip0)2569UINT_32 numMipLevels; ///< Total mipmap levels2570UINT_32 numSamples; ///< Number of samples2571UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as2572/// number of samples for normal AA; Set it to the2573/// number of fragments for EQAA25742575UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation2576UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)2577} ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;25782579/**2580****************************************************************************************************2581* ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT2582*2583* @brief2584* Output structure for Addr2ComputeSurfaceAddrFromCoord2585****************************************************************************************************2586*/2587typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT2588{2589UINT_32 size; ///< Size of this structure in bytes25902591UINT_64 addr; ///< Byte address2592UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7.2593/// For surface bpp < 8, e.g. FMT_1.2594UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block)2595} ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT;25962597/**2598****************************************************************************************************2599* Addr2ComputeSurfaceAddrFromCoord2600*2601* @brief2602* Compute surface address from a given coordinate.2603****************************************************************************************************2604*/2605ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord(2606ADDR_HANDLE hLib,2607const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,2608ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);2609261026112612/**2613****************************************************************************************************2614* ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT2615*2616* @brief2617* Input structure for Addr2ComputeSurfaceCoordFromAddr2618****************************************************************************************************2619*/2620typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT2621{2622UINT_32 size; ///< Size of this structure in bytes26232624UINT_64 addr; ///< Address in bytes2625UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8,2626/// e.g. FMT_1;26272628AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx92629ADDR2_SURFACE_FLAGS flags; ///< Surface flags2630AddrResourceType resourceType; ///< Surface type2631UINT_32 bpp; ///< Bits per pixel2632UINT_32 unalignedWidth; ///< Surface original width (of mip0)2633UINT_32 unalignedHeight; ///< Surface original height (of mip0)2634UINT_32 numSlices; ///< Surface original slices (of mip0)2635UINT_32 numMipLevels; ///< Total mipmap levels.2636UINT_32 numSamples; ///< Number of samples2637UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as2638/// number of samples for normal AA; Set it to the2639/// number of fragments for EQAA26402641UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation2642UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)2643} ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT;26442645/**2646****************************************************************************************************2647* ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT2648*2649* @brief2650* Output structure for Addr2ComputeSurfaceCoordFromAddr2651****************************************************************************************************2652*/2653typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT2654{2655UINT_32 size; ///< Size of this structure in bytes26562657UINT_32 x; ///< X coordinate2658UINT_32 y; ///< Y coordinate2659UINT_32 slice; ///< Index of slices2660UINT_32 sample; ///< Index of samples, means fragment index for EQAA2661UINT_32 mipId; ///< mipmap level id2662} ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT;26632664/**2665****************************************************************************************************2666* Addr2ComputeSurfaceCoordFromAddr2667*2668* @brief2669* Compute coordinate from a given surface address2670****************************************************************************************************2671*/2672ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr(2673ADDR_HANDLE hLib,2674const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,2675ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut);2676267726782679////////////////////////////////////////////////////////////////////////////////////////////////////2680// HTile functions for Gfx92681////////////////////////////////////////////////////////////////////////////////////////////////////26822683/**2684****************************************************************************************************2685* ADDR2_META_FLAGS2686*2687* @brief2688* Metadata flags2689****************************************************************************************************2690*/2691typedef union _ADDR2_META_FLAGS2692{2693struct2694{2695UINT_32 pipeAligned : 1; ///< if Metadata being pipe aligned2696UINT_32 rbAligned : 1; ///< if Metadata being RB aligned2697UINT_32 linear : 1; ///< if Metadata linear, GFX9 does not suppord this!2698UINT_32 reserved : 29; ///< Reserved bits2699};27002701UINT_32 value;2702} ADDR2_META_FLAGS;27032704/**2705****************************************************************************************************2706* ADDR2_META_MIP_INFO2707*2708* @brief2709* Structure to store per mip metadata information2710****************************************************************************************************2711*/2712typedef struct _ADDR2_META_MIP_INFO2713{2714BOOL_32 inMiptail;2715union2716{2717struct2718{2719UINT_32 startX;2720UINT_32 startY;2721UINT_32 startZ;2722UINT_32 width;2723UINT_32 height;2724UINT_32 depth;2725};27262727// GFX102728struct2729{2730UINT_32 offset; ///< Metadata offset within one slice,2731/// the thickness of a slice is meta block depth.2732UINT_32 sliceSize; ///< Metadata size within one slice,2733/// the thickness of a slice is meta block depth.2734};2735};2736} ADDR2_META_MIP_INFO;27372738/**2739****************************************************************************************************2740* ADDR2_COMPUTE_HTILE_INFO_INPUT2741*2742* @brief2743* Input structure of Addr2ComputeHtileInfo2744****************************************************************************************************2745*/2746typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT2747{2748UINT_32 size; ///< Size of this structure in bytes27492750ADDR2_META_FLAGS hTileFlags; ///< HTILE flags2751ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags2752AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode2753UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)2754UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)2755UINT_32 numSlices; ///< Number of slices of depth surface (of mip0)2756UINT_32 numMipLevels; ///< Total mipmap levels of color surface2757UINT_32 firstMipIdInTail; /// Id of the first mip in tail,2758/// if no mip is in tail, it should be set to2759/// number of mip levels2760/// Only for GFX102761} ADDR2_COMPUTE_HTILE_INFO_INPUT;27622763/**2764****************************************************************************************************2765* ADDR2_COMPUTE_HTILE_INFO_OUTPUT2766*2767* @brief2768* Output structure of Addr2ComputeHtileInfo2769****************************************************************************************************2770*/2771typedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT2772{2773UINT_32 size; ///< Size of this structure in bytes27742775UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this2776/// HTile buffer. This might be larger than original depth2777/// buffer pitch when called with an unaligned pitch.2778UINT_32 height; ///< Height in pixels, as above2779UINT_32 baseAlign; ///< Base alignment2780UINT_32 sliceSize; ///< Slice size, in bytes.2781UINT_32 htileBytes; ///< Size of HTILE buffer, in bytes2782UINT_32 metaBlkWidth; ///< Meta block width2783UINT_32 metaBlkHeight; ///< Meta block height2784UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice27852786ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information27872788struct {2789UINT_16* gfx10_bits; /* 72 2-byte elements */2790} equation;2791} ADDR2_COMPUTE_HTILE_INFO_OUTPUT;27922793/**2794****************************************************************************************************2795* Addr2ComputeHtileInfo2796*2797* @brief2798* Compute Htile pitch, height, base alignment and size in bytes2799****************************************************************************************************2800*/2801ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo(2802ADDR_HANDLE hLib,2803const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,2804ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut);2805280628072808/**2809****************************************************************************************************2810* ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT2811*2812* @brief2813* Input structure for Addr2ComputeHtileAddrFromCoord2814****************************************************************************************************2815*/2816typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT2817{2818UINT_32 size; ///< Size of this structure in bytes28192820UINT_32 x; ///< X coordinate2821UINT_32 y; ///< Y coordinate2822UINT_32 slice; ///< Index of slices2823UINT_32 mipId; ///< mipmap level id28242825ADDR2_META_FLAGS hTileFlags; ///< HTILE flags2826ADDR2_SURFACE_FLAGS depthflags; ///< Depth surface flags2827AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode2828UINT_32 bpp; ///< Depth surface bits per pixel2829UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)2830UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)2831UINT_32 numSlices; ///< Depth surface original depth (of mip0)2832UINT_32 numMipLevels; ///< Depth surface total mipmap levels2833UINT_32 numSamples; ///< Depth surface number of samples2834UINT_32 pipeXor; ///< Pipe xor setting2835} ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;28362837/**2838****************************************************************************************************2839* ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT2840*2841* @brief2842* Output structure for Addr2ComputeHtileAddrFromCoord2843****************************************************************************************************2844*/2845typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT2846{2847UINT_32 size; ///< Size of this structure in bytes28482849UINT_64 addr; ///< Address in bytes2850} ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT;28512852/**2853****************************************************************************************************2854* Addr2ComputeHtileAddrFromCoord2855*2856* @brief2857* Compute Htile address according to coordinates (of depth buffer)2858****************************************************************************************************2859*/2860ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord(2861ADDR_HANDLE hLib,2862const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,2863ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);2864286528662867/**2868****************************************************************************************************2869* ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT2870*2871* @brief2872* Input structure for Addr2ComputeHtileCoordFromAddr2873****************************************************************************************************2874*/2875typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT2876{2877UINT_32 size; ///< Size of this structure in bytes28782879UINT_64 addr; ///< Address28802881ADDR2_META_FLAGS hTileFlags; ///< HTILE flags2882ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags2883AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode2884UINT_32 bpp; ///< Depth surface bits per pixel2885UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)2886UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)2887UINT_32 numSlices; ///< Depth surface original depth (of mip0)2888UINT_32 numMipLevels; ///< Depth surface total mipmap levels2889UINT_32 numSamples; ///< Depth surface number of samples2890UINT_32 pipeXor; ///< Pipe xor setting2891} ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT;28922893/**2894****************************************************************************************************2895* ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT2896*2897* @brief2898* Output structure for Addr2ComputeHtileCoordFromAddr2899****************************************************************************************************2900*/2901typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT2902{2903UINT_32 size; ///< Size of this structure in bytes29042905UINT_32 x; ///< X coordinate2906UINT_32 y; ///< Y coordinate2907UINT_32 slice; ///< Index of slices2908UINT_32 mipId; ///< mipmap level id2909} ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT;29102911/**2912****************************************************************************************************2913* Addr2ComputeHtileCoordFromAddr2914*2915* @brief2916* Compute coordinates within depth buffer (1st pixel of a micro tile) according to2917* Htile address2918****************************************************************************************************2919*/2920ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr(2921ADDR_HANDLE hLib,2922const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,2923ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);2924292529262927////////////////////////////////////////////////////////////////////////////////////////////////////2928// C-mask functions for Gfx92929////////////////////////////////////////////////////////////////////////////////////////////////////29302931/**2932****************************************************************************************************2933* ADDR2_COMPUTE_CMASK_INFO_INPUT2934*2935* @brief2936* Input structure of Addr2ComputeCmaskInfo2937****************************************************************************************************2938*/2939typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT2940{2941UINT_32 size; ///< Size of this structure in bytes29422943ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags2944ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags2945AddrResourceType resourceType; ///< Color surface type2946AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode2947UINT_32 unalignedWidth; ///< Color surface original width2948UINT_32 unalignedHeight; ///< Color surface original height2949UINT_32 numSlices; ///< Number of slices of color buffer2950UINT_32 numMipLevels; ///< Number of mip levels2951UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,2952/// it should be number of mip levels2953/// Only for GFX102954} ADDR2_COMPUTE_CMASK_INFO_INPUT;29552956/**2957****************************************************************************************************2958* ADDR2_COMPUTE_CMASK_INFO_OUTPUT2959*2960* @brief2961* Output structure of Addr2ComputeCmaskInfo2962****************************************************************************************************2963*/2964typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT2965{2966UINT_32 size; ///< Size of this structure in bytes29672968UINT_32 pitch; ///< Pitch in pixels of color buffer which2969/// this Cmask matches. The size might be larger than2970/// original color buffer pitch when called with2971/// an unaligned pitch.2972UINT_32 height; ///< Height in pixels, as above2973UINT_32 baseAlign; ///< Base alignment2974UINT_32 sliceSize; ///< Slice size, in bytes.2975UINT_32 cmaskBytes; ///< Size in bytes of CMask buffer2976UINT_32 metaBlkWidth; ///< Meta block width2977UINT_32 metaBlkHeight; ///< Meta block height29782979UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice29802981ADDR2_META_MIP_INFO* pMipInfo; ///< CMASK mip information2982} ADDR2_COMPUTE_CMASK_INFO_OUTPUT;29832984/**2985****************************************************************************************************2986* Addr2ComputeCmaskInfo2987*2988* @brief2989* Compute Cmask pitch, height, base alignment and size in bytes from color buffer2990* info2991****************************************************************************************************2992*/2993ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo(2994ADDR_HANDLE hLib,2995const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,2996ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut);2997299829993000/**3001****************************************************************************************************3002* ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT3003*3004* @brief3005* Input structure for Addr2ComputeCmaskAddrFromCoord3006*3007****************************************************************************************************3008*/3009typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT3010{3011UINT_32 size; ///< Size of this structure in bytes30123013UINT_32 x; ///< X coordinate3014UINT_32 y; ///< Y coordinate3015UINT_32 slice; ///< Index of slices30163017ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags3018ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags3019AddrResourceType resourceType; ///< Color surface type3020AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode30213022UINT_32 unalignedWidth; ///< Color surface original width (of mip0)3023UINT_32 unalignedHeight; ///< Color surface original height (of mip0)3024UINT_32 numSlices; ///< Color surface original slices (of mip0)30253026UINT_32 numSamples; ///< Color surfae sample number3027UINT_32 numFrags; ///< Color surface fragment number30283029UINT_32 pipeXor; ///< pipe Xor setting3030} ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT;30313032/**3033****************************************************************************************************3034* ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT3035*3036* @brief3037* Output structure for Addr2ComputeCmaskAddrFromCoord3038****************************************************************************************************3039*/3040typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT3041{3042UINT_32 size; ///< Size of this structure in bytes30433044UINT_64 addr; ///< CMASK address in bytes3045UINT_32 bitPosition; ///< Bit position within addr, 0 or 43046} ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT;30473048/**3049****************************************************************************************************3050* Addr2ComputeCmaskAddrFromCoord3051*3052* @brief3053* Compute Cmask address according to coordinates (of MSAA color buffer)3054****************************************************************************************************3055*/3056ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord(3057ADDR_HANDLE hLib,3058const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,3059ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);3060306130623063/**3064****************************************************************************************************3065* ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT3066*3067* @brief3068* Input structure for Addr2ComputeCmaskCoordFromAddr3069****************************************************************************************************3070*/3071typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT3072{3073UINT_32 size; ///< Size of this structure in bytes30743075UINT_64 addr; ///< CMASK address in bytes3076UINT_32 bitPosition; ///< Bit position within addr, 0 or 430773078ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags3079ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags3080AddrResourceType resourceType; ///< Color surface type3081AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode30823083UINT_32 unalignedWidth; ///< Color surface original width (of mip0)3084UINT_32 unalignedHeight; ///< Color surface original height (of mip0)3085UINT_32 numSlices; ///< Color surface original slices (of mip0)3086UINT_32 numMipLevels; ///< Color surface total mipmap levels.3087} ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT;30883089/**3090****************************************************************************************************3091* ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT3092*3093* @brief3094* Output structure for Addr2ComputeCmaskCoordFromAddr3095****************************************************************************************************3096*/3097typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT3098{3099UINT_32 size; ///< Size of this structure in bytes31003101UINT_32 x; ///< X coordinate3102UINT_32 y; ///< Y coordinate3103UINT_32 slice; ///< Index of slices3104UINT_32 mipId; ///< mipmap level id3105} ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT;31063107/**3108****************************************************************************************************3109* Addr2ComputeCmaskCoordFromAddr3110*3111* @brief3112* Compute coordinates within color buffer (1st pixel of a micro tile) according to3113* Cmask address3114****************************************************************************************************3115*/3116ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr(3117ADDR_HANDLE hLib,3118const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,3119ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);3120312131223123////////////////////////////////////////////////////////////////////////////////////////////////////3124// F-mask functions for Gfx93125////////////////////////////////////////////////////////////////////////////////////////////////////31263127/**3128****************************************************************************************************3129* ADDR2_FMASK_FLAGS3130*3131* @brief3132* FMASK flags3133****************************************************************************************************3134*/3135typedef union _ADDR2_FMASK_FLAGS3136{3137struct3138{3139UINT_32 resolved : 1; ///< TRUE if this is a resolved fmask, used by H/W clients3140/// by H/W clients. S/W should always set it to FALSE.3141UINT_32 reserved : 31; ///< Reserved for future use.3142};31433144UINT_32 value;3145} ADDR2_FMASK_FLAGS;31463147/**3148****************************************************************************************************3149* ADDR2_COMPUTE_FMASK_INFO_INPUT3150*3151* @brief3152* Input structure for Addr2ComputeFmaskInfo3153****************************************************************************************************3154*/3155typedef struct _ADDR2_COMPUTE_FMASK_INFO_INPUT3156{3157UINT_32 size; ///< Size of this structure in bytes31583159AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode3160UINT_32 unalignedWidth; ///< Color surface original width3161UINT_32 unalignedHeight; ///< Color surface original height3162UINT_32 numSlices; ///< Number of slices/depth3163UINT_32 numSamples; ///< Number of samples3164UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as3165/// number of samples for normal AA; Set it to the3166/// number of fragments for EQAA3167ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags3168} ADDR2_COMPUTE_FMASK_INFO_INPUT;31693170/**3171****************************************************************************************************3172* ADDR2_COMPUTE_FMASK_INFO_OUTPUT3173*3174* @brief3175* Output structure for Addr2ComputeFmaskInfo3176****************************************************************************************************3177*/3178typedef struct _ADDR2_COMPUTE_FMASK_INFO_OUTPUT3179{3180UINT_32 size; ///< Size of this structure in bytes31813182UINT_32 pitch; ///< Pitch of fmask in pixels3183UINT_32 height; ///< Height of fmask in pixels3184UINT_32 baseAlign; ///< Base alignment3185UINT_32 numSlices; ///< Slices of fmask3186UINT_32 fmaskBytes; ///< Size of fmask in bytes3187UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes3188UINT_32 numSamples; ///< Number of samples3189UINT_32 sliceSize; ///< Size of slice in bytes3190} ADDR2_COMPUTE_FMASK_INFO_OUTPUT;31913192/**3193****************************************************************************************************3194* Addr2ComputeFmaskInfo3195*3196* @brief3197* Compute Fmask pitch/height/slices/alignments and size in bytes3198****************************************************************************************************3199*/3200ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo(3201ADDR_HANDLE hLib,3202const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn,3203ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut);3204320532063207/**3208****************************************************************************************************3209* ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT3210*3211* @brief3212* Input structure for Addr2ComputeFmaskAddrFromCoord3213****************************************************************************************************3214*/3215typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT3216{3217UINT_32 size; ///< Size of this structure in bytes32183219AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode3220UINT_32 x; ///< X coordinate3221UINT_32 y; ///< Y coordinate3222UINT_32 slice; ///< Slice index3223UINT_32 sample; ///< Sample index (fragment index for EQAA)3224UINT_32 plane; ///< Plane number32253226UINT_32 unalignedWidth; ///< Color surface original width3227UINT_32 unalignedHeight; ///< Color surface original height3228UINT_32 numSamples; ///< Number of samples3229UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as3230/// number of samples for normal AA; Set it to the3231/// number of fragments for EQAA3232UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation32333234ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags3235} ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT;32363237/**3238****************************************************************************************************3239* ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT3240*3241* @brief3242* Output structure for Addr2ComputeFmaskAddrFromCoord3243****************************************************************************************************3244*/3245typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT3246{3247UINT_32 size; ///< Size of this structure in bytes32483249UINT_64 addr; ///< Fmask address3250UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7.3251} ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT;32523253/**3254****************************************************************************************************3255* Addr2ComputeFmaskAddrFromCoord3256*3257* @brief3258* Compute Fmask address according to coordinates (x,y,slice,sample,plane)3259****************************************************************************************************3260*/3261ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord(3262ADDR_HANDLE hLib,3263const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,3264ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);3265326632673268/**3269****************************************************************************************************3270* ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT3271*3272* @brief3273* Input structure for Addr2ComputeFmaskCoordFromAddr3274****************************************************************************************************3275*/3276typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT3277{3278UINT_32 size; ///< Size of this structure in bytes32793280UINT_64 addr; ///< Address3281UINT_32 bitPosition; ///< Bit position within addr, 0-7.3282AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode32833284UINT_32 unalignedWidth; ///< Color surface original width3285UINT_32 unalignedHeight; ///< Color surface original height3286UINT_32 numSamples; ///< Number of samples3287UINT_32 numFrags; ///< Number of fragments32883289UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation32903291ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags3292} ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT;32933294/**3295****************************************************************************************************3296* ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT3297*3298* @brief3299* Output structure for Addr2ComputeFmaskCoordFromAddr3300****************************************************************************************************3301*/3302typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT3303{3304UINT_32 size; ///< Size of this structure in bytes33053306UINT_32 x; ///< X coordinate3307UINT_32 y; ///< Y coordinate3308UINT_32 slice; ///< Slice index3309UINT_32 sample; ///< Sample index (fragment index for EQAA)3310UINT_32 plane; ///< Plane number3311} ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT;33123313/**3314****************************************************************************************************3315* Addr2ComputeFmaskCoordFromAddr3316*3317* @brief3318* Compute FMASK coordinate from an given address3319****************************************************************************************************3320*/3321ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr(3322ADDR_HANDLE hLib,3323const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,3324ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);3325332633273328////////////////////////////////////////////////////////////////////////////////////////////////////3329// DCC key functions for Gfx93330////////////////////////////////////////////////////////////////////////////////////////////////////33313332/**3333****************************************************************************************************3334* _ADDR2_COMPUTE_DCCINFO_INPUT3335*3336* @brief3337* Input structure of Addr2ComputeDccInfo3338****************************************************************************************************3339*/3340typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT3341{3342UINT_32 size; ///< Size of this structure in bytes33433344ADDR2_META_FLAGS dccKeyFlags; ///< DCC key flags3345ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags3346AddrResourceType resourceType; ///< Color surface type3347AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode3348UINT_32 bpp; ///< bits per pixel3349UINT_32 unalignedWidth; ///< Color surface original width (of mip0)3350UINT_32 unalignedHeight; ///< Color surface original height (of mip0)3351UINT_32 numSlices; ///< Number of slices, of color surface (of mip0)3352UINT_32 numFrags; ///< Fragment number of color surface3353UINT_32 numMipLevels; ///< Total mipmap levels of color surface3354UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels3355///< useful in meta linear case3356UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,3357/// it should be number of mip levels3358/// Only for GFX103359} ADDR2_COMPUTE_DCCINFO_INPUT;33603361/**3362****************************************************************************************************3363* ADDR2_COMPUTE_DCCINFO_OUTPUT3364*3365* @brief3366* Output structure of Addr2ComputeDccInfo3367****************************************************************************************************3368*/3369typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT3370{3371UINT_32 size; ///< Size of this structure in bytes33723373UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key3374UINT_32 dccRamSize; ///< Size of dcc key33753376UINT_32 pitch; ///< DCC surface mip chain pitch3377UINT_32 height; ///< DCC surface mip chain height3378UINT_32 depth; ///< DCC surface mip chain depth33793380UINT_32 compressBlkWidth; ///< DCC compress block width3381UINT_32 compressBlkHeight; ///< DCC compress block height3382UINT_32 compressBlkDepth; ///< DCC compress block depth33833384UINT_32 metaBlkWidth; ///< DCC meta block width3385UINT_32 metaBlkHeight; ///< DCC meta block height3386UINT_32 metaBlkDepth; ///< DCC meta block depth3387UINT_32 metaBlkSize; ///< DCC meta block size in bytes3388UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice33893390union3391{3392UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared3393UINT_32 dccRamSliceSize; ///< DCC ram size per slice. For mipmap, it's3394/// the slize size of a mip chain, the thickness of a3395/// a slice is meta block depth3396/// Only for GFX103397};33983399ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information34003401/* The equation for doing DCC address computations in shaders. */3402union {3403/* This is chip-specific, and it varies with:3404* - resource type3405* - swizzle_mode3406* - bpp3407* - number of fragments3408* - pipe_aligned3409* - rb_aligned3410*/3411struct {3412UINT_8 num_bits;34133414struct {3415struct {3416UINT_8 dim; /* 0..4 as index, 5 means invalid */3417UINT_8 ord; /* 0..31 */3418} coord[8]; /* 0..num_coords */3419} bit[32]; /* 0..num_bits */3420UINT_8 numPipeBits;3421} gfx9;34223423/* This is chip-specific, it requires 64KB_R_X, and it varies with:3424* - bpp3425* - pipe_aligned3426*/3427UINT_16 *gfx10_bits; /* 68 2-byte elements */3428} equation;3429} ADDR2_COMPUTE_DCCINFO_OUTPUT;34303431/**3432****************************************************************************************************3433* Addr2ComputeDccInfo3434*3435* @brief3436* Compute DCC key size, base alignment3437* info3438****************************************************************************************************3439*/3440ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo(3441ADDR_HANDLE hLib,3442const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,3443ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut);344434453446/**3447****************************************************************************************************3448* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT3449*3450* @brief3451* Input structure for Addr2ComputeDccAddrFromCoord3452*3453****************************************************************************************************3454*/3455typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT3456{3457UINT_32 size; ///< Size of this structure in bytes34583459UINT_32 x; ///< X coordinate3460UINT_32 y; ///< Y coordinate3461UINT_32 slice; ///< Index of slices3462UINT_32 sample; ///< Index of samples, means fragment index for EQAA3463UINT_32 mipId; ///< mipmap level id34643465ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags3466ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags3467AddrResourceType resourceType; ///< Color surface type3468AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode3469UINT_32 bpp; ///< Color surface bits per pixel3470UINT_32 unalignedWidth; ///< Color surface original width (of mip0)3471UINT_32 unalignedHeight; ///< Color surface original height (of mip0)3472UINT_32 numSlices; ///< Color surface original slices (of mip0)3473UINT_32 numMipLevels; ///< Color surface mipmap levels3474UINT_32 numFrags; ///< Color surface fragment number34753476UINT_32 pipeXor; ///< pipe Xor setting3477UINT_32 pitch; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::pitch3478UINT_32 height; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::height3479UINT_32 compressBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkWidth3480UINT_32 compressBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkHeight3481UINT_32 compressBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkDepth3482UINT_32 metaBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkWidth3483UINT_32 metaBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkHeight3484UINT_32 metaBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkDepth3485UINT_32 dccRamSliceSize; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::dccRamSliceSize3486} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT;34873488/**3489****************************************************************************************************3490* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT3491*3492* @brief3493* Output structure for Addr2ComputeDccAddrFromCoord3494****************************************************************************************************3495*/3496typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT3497{3498UINT_32 size; ///< Size of this structure in bytes34993500UINT_64 addr; ///< DCC address in bytes3501} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT;35023503/**3504****************************************************************************************************3505* Addr2ComputeDccAddrFromCoord3506*3507* @brief3508* Compute DCC address according to coordinates (of MSAA color buffer)3509****************************************************************************************************3510*/3511ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord(3512ADDR_HANDLE hLib,3513const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,3514ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);35153516////////////////////////////////////////////////////////////////////////////////////////////////////3517// Misc functions for Gfx93518////////////////////////////////////////////////////////////////////////////////////////////////////35193520/**3521****************************************************************************************************3522* ADDR2_COMPUTE_PIPEBANKXOR_INPUT3523*3524* @brief3525* Input structure of Addr2ComputePipebankXor3526****************************************************************************************************3527*/3528typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT3529{3530UINT_32 size; ///< Size of this structure in bytes3531UINT_32 surfIndex; ///< Input surface index3532ADDR2_SURFACE_FLAGS flags; ///< Surface flag3533AddrSwizzleMode swizzleMode; ///< Surface swizzle mode3534AddrResourceType resourceType; ///< Surface resource type3535AddrFormat format; ///< Surface format3536UINT_32 numSamples; ///< Number of samples3537UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as3538/// number of samples for normal AA; Set it to the3539/// number of fragments for EQAA3540} ADDR2_COMPUTE_PIPEBANKXOR_INPUT;35413542/**3543****************************************************************************************************3544* ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT3545*3546* @brief3547* Output structure of Addr2ComputePipebankXor3548****************************************************************************************************3549*/3550typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT3551{3552UINT_32 size; ///< Size of this structure in bytes3553UINT_32 pipeBankXor; ///< Pipe bank xor3554} ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT;35553556/**3557****************************************************************************************************3558* Addr2ComputePipeBankXor3559*3560* @brief3561* Calculate a valid bank pipe xor value for client to use.3562****************************************************************************************************3563*/3564ADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor(3565ADDR_HANDLE hLib,3566const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,3567ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut);35683569/**3570****************************************************************************************************3571* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT3572*3573* @brief3574* Input structure of Addr2ComputeSlicePipeBankXor3575****************************************************************************************************3576*/3577typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT3578{3579UINT_32 size; ///< Size of this structure in bytes3580AddrSwizzleMode swizzleMode; ///< Surface swizzle mode3581AddrResourceType resourceType; ///< Surface resource type3582UINT_32 bpe; ///< bits per element (e.g. block size for BCn format)3583UINT_32 basePipeBankXor; ///< Base pipe bank xor3584UINT_32 slice; ///< Slice id3585UINT_32 numSamples; ///< Number of samples3586} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT;35873588/**3589****************************************************************************************************3590* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT3591*3592* @brief3593* Output structure of Addr2ComputeSlicePipeBankXor3594****************************************************************************************************3595*/3596typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT3597{3598UINT_32 size; ///< Size of this structure in bytes3599UINT_32 pipeBankXor; ///< Pipe bank xor3600} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT;36013602/**3603****************************************************************************************************3604* Addr2ComputeSlicePipeBankXor3605*3606* @brief3607* Calculate slice pipe bank xor value based on base pipe bank xor and slice id.3608****************************************************************************************************3609*/3610ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor(3611ADDR_HANDLE hLib,3612const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,3613ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut);36143615/**3616****************************************************************************************************3617* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT3618*3619* @brief3620* Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern3621****************************************************************************************************3622*/3623typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT3624{3625UINT_32 size; ///< Size of this structure in bytes3626AddrSwizzleMode swizzleMode; ///< Surface swizzle mode3627AddrResourceType resourceType; ///< Surface resource type3628UINT_32 pipeBankXor; ///< Per resource xor3629UINT_32 slice; ///< Slice id3630UINT_64 sliceSize; ///< Slice size of a mip chain3631UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO3632UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO3633} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT;36343635/**3636****************************************************************************************************3637* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT3638*3639* @brief3640* Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern3641****************************************************************************************************3642*/3643typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT3644{3645UINT_32 size; ///< Size of this structure in bytes3646UINT_64 offset; ///< offset3647} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT;36483649/**3650****************************************************************************************************3651* Addr2ComputeSubResourceOffsetForSwizzlePattern3652*3653* @brief3654* Calculate sub resource offset to support swizzle pattern.3655****************************************************************************************************3656*/3657ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern(3658ADDR_HANDLE hLib,3659const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,3660ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut);36613662/**3663****************************************************************************************************3664* ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT3665*3666* @brief3667* Input structure of Addr2ComputeNonBlockCompressedView3668****************************************************************************************************3669*/3670typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT3671{3672UINT_32 size; ///< Size of this structure in bytes3673ADDR2_SURFACE_FLAGS flags; ///< Surface flags3674AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx93675AddrResourceType resourceType; ///< Surface type3676AddrFormat format; ///< Surface format3677UINT_32 width; ///< Width of mip0 in texels (not in compressed block)3678UINT_32 height; ///< Height of mip0 in texels (not in compressed block)3679UINT_32 numSlices; ///< Number surface slice/depth of mip03680UINT_32 numMipLevels; ///< Total mipmap levels.3681UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation3682UINT_32 slice; ///< Index of slice to view3683UINT_32 mipId; ///< Id of mip to view3684} ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT;36853686/**3687****************************************************************************************************3688* ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT3689*3690* @brief3691* Output structure of Addr2ComputeNonBlockCompressedView3692****************************************************************************************************3693*/3694typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT3695{3696UINT_32 size; ///< Size of this structure in bytes3697UINT_64 offset; ///< Offset shifted from resource base for the view3698UINT_32 pipeBankXor; ///< Pipe bank xor for the view3699UINT_32 unalignedWidth; ///< Mip0 width (in element) for the view3700UINT_32 unalignedHeight; ///< Mip0 height (in element) for the view3701UINT_32 numMipLevels; ///< Total mipmap levels for the view3702UINT_32 mipId; ///< Mip ID for the view3703} ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT;37043705/**3706****************************************************************************************************3707* Addr2ComputeNonBlockCompressedView3708*3709* @brief3710* Compute non-block-compressed view for a given mipmap level/slice3711****************************************************************************************************3712*/3713ADDR_E_RETURNCODE ADDR_API Addr2ComputeNonBlockCompressedView(3714ADDR_HANDLE hLib,3715const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn,3716ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut);37173718/**3719****************************************************************************************************3720* ADDR2_BLOCK_SET3721*3722* @brief3723* Bit field that defines block type3724****************************************************************************************************3725*/3726typedef union _ADDR2_BLOCK_SET3727{3728struct3729{3730UINT_32 micro : 1; // 256B block for 2D resource3731UINT_32 macroThin4KB : 1; // Thin 4KB for 2D/3D resource3732UINT_32 macroThick4KB : 1; // Thick 4KB for 3D resource3733UINT_32 macroThin64KB : 1; // Thin 64KB for 2D/3D resource3734UINT_32 macroThick64KB : 1; // Thick 64KB for 3D resource3735UINT_32 var : 1; // VAR block3736UINT_32 : 1;3737UINT_32 linear : 1; // Linear block3738UINT_32 reserved : 24;3739};37403741UINT_32 value;3742} ADDR2_BLOCK_SET;37433744/**3745****************************************************************************************************3746* ADDR2_SWTYPE_SET3747*3748* @brief3749* Bit field that defines swizzle type3750****************************************************************************************************3751*/3752typedef union _ADDR2_SWTYPE_SET3753{3754struct3755{3756UINT_32 sw_Z : 1; // SW_*_Z_*3757UINT_32 sw_S : 1; // SW_*_S_*3758UINT_32 sw_D : 1; // SW_*_D_*3759UINT_32 sw_R : 1; // SW_*_R_*3760UINT_32 reserved : 28;3761};37623763UINT_32 value;3764} ADDR2_SWTYPE_SET;37653766/**3767****************************************************************************************************3768* ADDR2_SWMODE_SET3769*3770* @brief3771* Bit field that defines swizzle type3772****************************************************************************************************3773*/3774typedef union _ADDR2_SWMODE_SET3775{3776struct3777{3778UINT_32 swLinear : 1;3779UINT_32 sw256B_S : 1;3780UINT_32 sw256B_D : 1;3781UINT_32 sw256B_R : 1;3782UINT_32 sw4KB_Z : 1;3783UINT_32 sw4KB_S : 1;3784UINT_32 sw4KB_D : 1;3785UINT_32 sw4KB_R : 1;3786UINT_32 sw64KB_Z : 1;3787UINT_32 sw64KB_S : 1;3788UINT_32 sw64KB_D : 1;3789UINT_32 sw64KB_R : 1;3790UINT_32 swMiscDef12 : 1;3791UINT_32 swMiscDef13 : 1;3792UINT_32 swMiscDef14 : 1;3793UINT_32 swMiscDef15 : 1;3794UINT_32 sw64KB_Z_T : 1;3795UINT_32 sw64KB_S_T : 1;3796UINT_32 sw64KB_D_T : 1;3797UINT_32 sw64KB_R_T : 1;3798UINT_32 sw4KB_Z_X : 1;3799UINT_32 sw4KB_S_X : 1;3800UINT_32 sw4KB_D_X : 1;3801UINT_32 sw4KB_R_X : 1;3802UINT_32 sw64KB_Z_X : 1;3803UINT_32 sw64KB_S_X : 1;3804UINT_32 sw64KB_D_X : 1;3805UINT_32 sw64KB_R_X : 1;3806UINT_32 swMiscDef28 : 1;3807UINT_32 swMiscDef29 : 1;3808UINT_32 swMiscDef30 : 1;3809UINT_32 swMiscDef31 : 1;3810};38113812struct3813{3814UINT_32 : 28;3815UINT_32 swVar_Z_X : 1;3816UINT_32 : 2;3817UINT_32 swVar_R_X : 1;3818} gfx10;38193820UINT_32 value;3821} ADDR2_SWMODE_SET;38223823/**3824****************************************************************************************************3825* ADDR2_GET_PREFERRED_SURF_SETTING_INPUT3826*3827* @brief3828* Input structure of Addr2GetPreferredSurfaceSetting3829****************************************************************************************************3830*/3831typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT3832{3833UINT_32 size; ///< Size of this structure in bytes38343835ADDR2_SURFACE_FLAGS flags; ///< Surface flags3836AddrResourceType resourceType; ///< Surface type3837AddrFormat format; ///< Surface format3838AddrResrouceLocation resourceLoction; ///< Surface heap choice3839ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting3840///< such as linear for DXTn, tiled for YUV3841ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted3842BOOL_32 noXor; ///< Do not use xor mode for this resource3843UINT_32 bpp; ///< bits per pixel3844UINT_32 width; ///< Width (of mip0), in pixels3845UINT_32 height; ///< Height (of mip0), in pixels3846UINT_32 numSlices; ///< Number surface slice/depth (of mip0),3847UINT_32 numMipLevels; ///< Total mipmap levels.3848UINT_32 numSamples; ///< Number of samples3849UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as3850/// number of samples for normal AA; Set it to the3851/// number of fragments for EQAA3852UINT_32 maxAlign; ///< maximum base/size alignment requested by client3853UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will3854/// be padded to multiple of this value (in bytes)3855DOUBLE memoryBudget; ///< Memory consumption ratio based on minimum possible3856/// size.3857} ADDR2_GET_PREFERRED_SURF_SETTING_INPUT;38583859/**3860****************************************************************************************************3861* ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT3862*3863* @brief3864* Output structure of Addr2GetPreferredSurfaceSetting3865****************************************************************************************************3866*/3867typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT3868{3869UINT_32 size; ///< Size of this structure in bytes38703871AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used3872AddrResourceType resourceType; ///< Suggested resource type to program HW3873ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination3874BOOL_32 canXor; ///< If client can use xor on a valid macro block3875/// type3876ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination3877ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination3878ADDR2_SWMODE_SET validSwModeSet; ///< Valid swizzle mode bit combination3879} ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT;38803881/**3882****************************************************************************************************3883* Addr2GetPreferredSurfaceSetting3884*3885* @brief3886* Suggest a preferred setting for client driver to program HW register3887****************************************************************************************************3888*/3889ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting(3890ADDR_HANDLE hLib,3891const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,3892ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut);38933894/**3895****************************************************************************************************3896* Addr2IsValidDisplaySwizzleMode3897*3898* @brief3899* Return whether the swizzle mode is supported by display engine3900****************************************************************************************************3901*/3902ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode(3903ADDR_HANDLE hLib,3904AddrSwizzleMode swizzleMode,3905UINT_32 bpp,3906BOOL_32 *pResult);39073908#if defined(__cplusplus)3909}3910#endif39113912#endif // __ADDR_INTERFACE_H__391339143915