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GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/amd/addrlib/inc/addrinterface.h
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/*
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* Copyright © 2007-2019 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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/**
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****************************************************************************************************
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* @file addrinterface.h
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* @brief Contains the addrlib interfaces declaration and parameter defines
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****************************************************************************************************
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*/
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#ifndef __ADDR_INTERFACE_H__
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#define __ADDR_INTERFACE_H__
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// Includes should be before extern "C"
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#include "addrtypes.h"
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#if defined(__cplusplus)
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extern "C"
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{
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#endif
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#define ADDRLIB_VERSION_MAJOR 6
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#define ADDRLIB_VERSION_MINOR 2
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#define ADDRLIB_VERSION ((ADDRLIB_VERSION_MAJOR << 16) | ADDRLIB_VERSION_MINOR)
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/// Virtually all interface functions need ADDR_HANDLE as first parameter
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typedef VOID* ADDR_HANDLE;
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/// Client handle used in callbacks
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typedef VOID* ADDR_CLIENT_HANDLE;
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/**
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* // Callback functions
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(
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* const ADDR_ALLOCSYSMEM_INPUT* pInput);
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* typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(
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* VOID* pVirtAddr);
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* typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(
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* const ADDR_DEBUGPRINT_INPUT* pInput);
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*
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* // Create/Destroy/Config functions
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* AddrCreate()
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* AddrDestroy()
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*
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* // Surface functions
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* AddrComputeSurfaceInfo()
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* AddrComputeSurfaceAddrFromCoord()
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* AddrComputeSurfaceCoordFromAddr()
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*
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* // HTile functions
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* AddrComputeHtileInfo()
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* AddrComputeHtileAddrFromCoord()
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* AddrComputeHtileCoordFromAddr()
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*
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* // C-mask functions
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* AddrComputeCmaskInfo()
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* AddrComputeCmaskAddrFromCoord()
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* AddrComputeCmaskCoordFromAddr()
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*
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* // F-mask functions
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* AddrComputeFmaskInfo()
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* AddrComputeFmaskAddrFromCoord()
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* AddrComputeFmaskCoordFromAddr()
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*
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* // Element/Utility functions
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* /////////////////////////////////////////////////////////////////////////////////////////////////
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* ElemFlt32ToDepthPixel()
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* ElemFlt32ToColorPixel()
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* AddrExtractBankPipeSwizzle()
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* AddrCombineBankPipeSwizzle()
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* AddrComputeSliceSwizzle()
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* AddrConvertTileInfoToHW()
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* AddrConvertTileIndex()
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* AddrConvertTileIndex1()
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* AddrGetTileIndex()
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* AddrComputeBaseSwizzle()
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* AddrUseTileIndex()
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* AddrUseCombinedSwizzle()
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*
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**/
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Callback functions
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////////////////////////////////////////////////////////////////////////////////////////////////////
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/**
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****************************************************************************************************
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* @brief channel setting structure
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****************************************************************************************************
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*/
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typedef union _ADDR_CHANNEL_SETTING
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{
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struct
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{
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UINT_8 valid : 1; ///< Indicate whehter this channel setting is valid
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UINT_8 channel : 2; ///< 0 for x channel, 1 for y channel, 2 for z channel
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UINT_8 index : 5; ///< Channel index
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};
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UINT_8 value; ///< Value
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} ADDR_CHANNEL_SETTING;
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/**
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****************************************************************************************************
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* @brief address equation key structure
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****************************************************************************************************
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*/
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typedef union _ADDR_EQUATION_KEY
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{
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struct
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{
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UINT_32 log2ElementBytes : 3; ///< Log2 of Bytes per pixel
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UINT_32 tileMode : 5; ///< Tile mode
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UINT_32 microTileType : 3; ///< Micro tile type
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UINT_32 pipeConfig : 5; ///< pipe config
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UINT_32 numBanksLog2 : 3; ///< Number of banks log2
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UINT_32 bankWidth : 4; ///< Bank width
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UINT_32 bankHeight : 4; ///< Bank height
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UINT_32 macroAspectRatio : 3; ///< Macro tile aspect ratio
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UINT_32 prt : 1; ///< SI only, indicate whether this equation is for prt
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UINT_32 reserved : 1; ///< Reserved bit
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} fields;
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UINT_32 value;
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} ADDR_EQUATION_KEY;
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/**
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****************************************************************************************************
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* @brief address equation structure
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****************************************************************************************************
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*/
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#define ADDR_MAX_EQUATION_BIT 20u
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// Invalid equation index
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#define ADDR_INVALID_EQUATION_INDEX 0xFFFFFFFF
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typedef struct _ADDR_EQUATION
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{
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ADDR_CHANNEL_SETTING addr[ADDR_MAX_EQUATION_BIT]; ///< addr setting
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///< each bit is result of addr ^ xor ^ xor2
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ADDR_CHANNEL_SETTING xor1[ADDR_MAX_EQUATION_BIT]; ///< xor setting
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ADDR_CHANNEL_SETTING xor2[ADDR_MAX_EQUATION_BIT]; ///< xor2 setting
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UINT_32 numBits; ///< The number of bits in equation
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BOOL_32 stackedDepthSlices; ///< TRUE if depth slices are treated as being
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///< stacked vertically prior to swizzling
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} ADDR_EQUATION;
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/**
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****************************************************************************************************
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* @brief Alloc system memory flags.
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* @note These flags are reserved for future use and if flags are added will minimize the impact
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* of the client.
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****************************************************************************************************
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*/
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typedef union _ADDR_ALLOCSYSMEM_FLAGS
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{
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struct
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{
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UINT_32 reserved : 32; ///< Reserved for future use.
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} fields;
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UINT_32 value;
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} ADDR_ALLOCSYSMEM_FLAGS;
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/**
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****************************************************************************************************
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* @brief Alloc system memory input structure
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****************************************************************************************************
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*/
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typedef struct _ADDR_ALLOCSYSMEM_INPUT
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{
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UINT_32 size; ///< Size of this structure in bytes
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ADDR_ALLOCSYSMEM_FLAGS flags; ///< System memory flags.
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UINT_32 sizeInBytes; ///< System memory allocation size in bytes.
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ADDR_CLIENT_HANDLE hClient; ///< Client handle
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} ADDR_ALLOCSYSMEM_INPUT;
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/**
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****************************************************************************************************
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* ADDR_ALLOCSYSMEM
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* @brief
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* Allocate system memory callback function. Returns valid pointer on success.
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****************************************************************************************************
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*/
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typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(
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const ADDR_ALLOCSYSMEM_INPUT* pInput);
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/**
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****************************************************************************************************
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* @brief Free system memory input structure
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****************************************************************************************************
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*/
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typedef struct _ADDR_FREESYSMEM_INPUT
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{
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UINT_32 size; ///< Size of this structure in bytes
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VOID* pVirtAddr; ///< Virtual address
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ADDR_CLIENT_HANDLE hClient; ///< Client handle
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} ADDR_FREESYSMEM_INPUT;
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/**
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****************************************************************************************************
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* ADDR_FREESYSMEM
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* @brief
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* Free system memory callback function.
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* Returns ADDR_OK on success.
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****************************************************************************************************
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*/
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typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(
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const ADDR_FREESYSMEM_INPUT* pInput);
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/**
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****************************************************************************************************
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* @brief Print debug message input structure
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****************************************************************************************************
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*/
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typedef struct _ADDR_DEBUGPRINT_INPUT
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{
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UINT_32 size; ///< Size of this structure in bytes
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CHAR* pDebugString; ///< Debug print string
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va_list ap; ///< Variable argument list
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ADDR_CLIENT_HANDLE hClient; ///< Client handle
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} ADDR_DEBUGPRINT_INPUT;
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/**
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****************************************************************************************************
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* ADDR_DEBUGPRINT
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* @brief
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* Print debug message callback function.
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* Returns ADDR_OK on success.
267
****************************************************************************************************
268
*/
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typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(
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const ADDR_DEBUGPRINT_INPUT* pInput);
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272
/**
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****************************************************************************************************
274
* ADDR_CALLBACKS
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*
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* @brief
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* Address Library needs client to provide system memory alloc/free routines.
278
****************************************************************************************************
279
*/
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typedef struct _ADDR_CALLBACKS
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{
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ADDR_ALLOCSYSMEM allocSysMem; ///< Routine to allocate system memory
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ADDR_FREESYSMEM freeSysMem; ///< Routine to free system memory
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ADDR_DEBUGPRINT debugPrint; ///< Routine to print debug message
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} ADDR_CALLBACKS;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Create/Destroy functions
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////////////////////////////////////////////////////////////////////////////////////////////////////
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/**
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****************************************************************************************************
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* ADDR_CREATE_FLAGS
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*
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* @brief
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* This structure is used to pass some setup in creation of AddrLib
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* @note
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****************************************************************************************************
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*/
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typedef union _ADDR_CREATE_FLAGS
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{
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struct
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{
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UINT_32 noCubeMipSlicesPad : 1; ///< Turn cubemap faces padding off
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UINT_32 fillSizeFields : 1; ///< If clients fill size fields in all input and
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/// output structure
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UINT_32 useTileIndex : 1; ///< Make tileIndex field in input valid
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UINT_32 useCombinedSwizzle : 1; ///< Use combined tile swizzle
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UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level
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UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment
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UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize
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UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility
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UINT_32 nonPower2MemConfig : 1; ///< Video memory bit width is not power of 2
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UINT_32 enableAltTiling : 1; ///< Enable alt tile mode
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UINT_32 reserved : 22; ///< Reserved bits for future use
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};
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UINT_32 value;
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} ADDR_CREATE_FLAGS;
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321
/**
322
****************************************************************************************************
323
* ADDR_REGISTER_VALUE
324
*
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* @brief
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* Data from registers to setup AddrLib global data, used in AddrCreate
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****************************************************************************************************
328
*/
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typedef struct _ADDR_REGISTER_VALUE
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{
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UINT_32 gbAddrConfig; ///< For R8xx, use GB_ADDR_CONFIG register value.
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/// For R6xx/R7xx, use GB_TILING_CONFIG.
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/// But they can be treated as the same.
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/// if this value is 0, use chip to set default value
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UINT_32 backendDisables; ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled.
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/// Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE
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/// R800 registers-----------------------------------------------
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UINT_32 noOfBanks; ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK
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/// No enums for this value in h/w header files
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/// 0: 4
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/// 1: 8
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/// 2: 16
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UINT_32 noOfRanks; /// MC_ARB_RAMCFG.NOOFRANK
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/// 0: 1
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/// 1: 2
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/// SI (R1000) registers-----------------------------------------
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const UINT_32* pTileConfig; ///< Global tile setting tables
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UINT_32 noOfEntries; ///< Number of entries in pTileConfig
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///< CI registers-------------------------------------------------
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const UINT_32* pMacroTileConfig; ///< Global macro tile mode table
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UINT_32 noOfMacroEntries; ///< Number of entries in pMacroTileConfig
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} ADDR_REGISTER_VALUE;
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356
/**
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****************************************************************************************************
358
* ADDR_CREATE_INPUT
359
*
360
* @brief
361
* Parameters use to create an AddrLib Object. Caller must provide all fields.
362
*
363
****************************************************************************************************
364
*/
365
typedef struct _ADDR_CREATE_INPUT
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{
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UINT_32 size; ///< Size of this structure in bytes
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369
UINT_32 chipEngine; ///< Chip Engine
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UINT_32 chipFamily; ///< Chip Family
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UINT_32 chipRevision; ///< Chip Revision
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ADDR_CALLBACKS callbacks; ///< Callbacks for sysmem alloc/free/print
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ADDR_CREATE_FLAGS createFlags; ///< Flags to setup AddrLib
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ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data
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ADDR_CLIENT_HANDLE hClient; ///< Client handle
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UINT_32 minPitchAlignPixels; ///< Minimum pitch alignment in pixels
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} ADDR_CREATE_INPUT;
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379
/**
380
****************************************************************************************************
381
* ADDR_CREATEINFO_OUTPUT
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*
383
* @brief
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* Return AddrLib handle to client driver
385
*
386
****************************************************************************************************
387
*/
388
typedef struct _ADDR_CREATE_OUTPUT
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{
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UINT_32 size; ///< Size of this structure in bytes
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392
ADDR_HANDLE hLib; ///< Address lib handle
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UINT_32 numEquations; ///< Number of equations in the table
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const ADDR_EQUATION* pEquationTable; ///< Pointer to the equation table
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} ADDR_CREATE_OUTPUT;
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398
/**
399
****************************************************************************************************
400
* AddrCreate
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*
402
* @brief
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* Create AddrLib object, must be called before any interface calls
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*
405
* @return
406
* ADDR_OK if successful
407
****************************************************************************************************
408
*/
409
ADDR_E_RETURNCODE ADDR_API AddrCreate(
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const ADDR_CREATE_INPUT* pAddrCreateIn,
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ADDR_CREATE_OUTPUT* pAddrCreateOut);
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413
414
415
/**
416
****************************************************************************************************
417
* AddrDestroy
418
*
419
* @brief
420
* Destroy AddrLib object, must be called to free internally allocated resources.
421
*
422
* @return
423
* ADDR_OK if successful
424
****************************************************************************************************
425
*/
426
ADDR_E_RETURNCODE ADDR_API AddrDestroy(
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ADDR_HANDLE hLib);
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429
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431
////////////////////////////////////////////////////////////////////////////////////////////////////
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// Surface functions
433
////////////////////////////////////////////////////////////////////////////////////////////////////
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435
/**
436
****************************************************************************************************
437
* @brief
438
* Bank/tiling parameters. On function input, these can be set as desired or
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* left 0 for AddrLib to calculate/default. On function output, these are the actual
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* parameters used.
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* @note
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* Valid bankWidth/bankHeight value:
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* 1,2,4,8. They are factors instead of pixels or bytes.
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*
445
* The bank number remains constant across each row of the
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* macro tile as each pipe is selected, so the number of
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* tiles in the x direction with the same bank number will
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* be bank_width * num_pipes.
449
****************************************************************************************************
450
*/
451
typedef struct _ADDR_TILEINFO
452
{
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/// Any of these parameters can be set to 0 to use the HW default.
454
UINT_32 banks; ///< Number of banks, numerical value
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UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank
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UINT_32 bankHeight; ///< Number of tiles in the Y direction in the same bank
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UINT_32 macroAspectRatio; ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1
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UINT_32 tileSplitBytes; ///< Tile split size, in bytes
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AddrPipeCfg pipeConfig; ///< Pipe Config = HW enum + 1
460
} ADDR_TILEINFO;
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462
// Create a define to avoid client change. The removal of R800 is because we plan to implement SI
463
// within 800 HWL - An AddrPipeCfg is added in above data structure
464
typedef ADDR_TILEINFO ADDR_R800_TILEINFO;
465
466
/**
467
****************************************************************************************************
468
* @brief
469
* Information needed by quad buffer stereo support
470
****************************************************************************************************
471
*/
472
typedef struct _ADDR_QBSTEREOINFO
473
{
474
UINT_32 eyeHeight; ///< Height (in pixel rows) to right eye
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UINT_32 rightOffset; ///< Offset (in bytes) to right eye
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UINT_32 rightSwizzle; ///< TileSwizzle for right eyes
477
} ADDR_QBSTEREOINFO;
478
479
/**
480
****************************************************************************************************
481
* ADDR_SURFACE_FLAGS
482
*
483
* @brief
484
* Surface flags
485
****************************************************************************************************
486
*/
487
typedef union _ADDR_SURFACE_FLAGS
488
{
489
struct
490
{
491
UINT_32 color : 1; ///< Flag indicates this is a color buffer
492
UINT_32 depth : 1; ///< Flag indicates this is a depth/stencil buffer
493
UINT_32 stencil : 1; ///< Flag indicates this is a stencil buffer
494
UINT_32 texture : 1; ///< Flag indicates this is a texture
495
UINT_32 cube : 1; ///< Flag indicates this is a cubemap
496
UINT_32 volume : 1; ///< Flag indicates this is a volume texture
497
UINT_32 fmask : 1; ///< Flag indicates this is an fmask
498
UINT_32 cubeAsArray : 1; ///< Flag indicates if treat cubemap as arrays
499
UINT_32 compressZ : 1; ///< Flag indicates z buffer is compressed
500
UINT_32 overlay : 1; ///< Flag indicates this is an overlay surface
501
UINT_32 noStencil : 1; ///< Flag indicates this depth has no separate stencil
502
UINT_32 display : 1; ///< Flag indicates this should match display controller req.
503
UINT_32 opt4Space : 1; ///< Flag indicates this surface should be optimized for space
504
/// i.e. save some memory but may lose performance
505
UINT_32 prt : 1; ///< Flag for partially resident texture
506
UINT_32 qbStereo : 1; ///< Quad buffer stereo surface
507
UINT_32 pow2Pad : 1; ///< SI: Pad to pow2, must set for mipmap (include level0)
508
UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding
509
UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
510
UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce
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UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear
512
UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that
513
/// dcc can't be enabled if pipe config of tile mode
514
/// is different from that of ASIC, this flag
515
/// is address lib internal flag, client should ignore it
516
UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment.
517
/// This flag indicates we need to follow the
518
/// alignment with CZ families or other ASICs under
519
/// PX configuration + CZ.
520
UINT_32 nonSplit : 1; ///< CI: depth texture should not be split
521
UINT_32 disableLinearOpt : 1; ///< Disable tile mode optimization to linear
522
UINT_32 needEquation : 1; ///< Make the surface tile setting equation compatible.
523
/// This flag indicates we need to override tile
524
/// mode to PRT_* tile mode to disable slice rotation,
525
/// which is needed by swizzle pattern equation.
526
UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output.
527
UINT_32 rotateDisplay : 1; ///< Rotate micro tile type
528
UINT_32 minimizeAlignment : 1; ///< Minimize alignment
529
UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode
530
UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface
531
/// to make sure they share same tile config parameters
532
UINT_32 disallowLargeThickDegrade : 1; ///< Disallow large thick tile degrade
533
UINT_32 reserved : 1; ///< Reserved bits
534
};
535
536
UINT_32 value;
537
} ADDR_SURFACE_FLAGS;
538
539
/**
540
****************************************************************************************************
541
* ADDR_COMPUTE_SURFACE_INFO_INPUT
542
*
543
* @brief
544
* Input structure for AddrComputeSurfaceInfo
545
****************************************************************************************************
546
*/
547
typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT
548
{
549
UINT_32 size; ///< Size of this structure in bytes
550
551
AddrTileMode tileMode; ///< Tile mode
552
AddrFormat format; ///< If format is set to valid one, bpp/width/height
553
/// might be overwritten
554
UINT_32 bpp; ///< Bits per pixel
555
UINT_32 numSamples; ///< Number of samples
556
UINT_32 width; ///< Width, in pixels
557
UINT_32 height; ///< Height, in pixels
558
UINT_32 numSlices; ///< Number of surface slices or depth
559
UINT_32 slice; ///< Slice index
560
UINT_32 mipLevel; ///< Current mipmap level
561
UINT_32 numMipLevels; ///< Number of mips in mip chain
562
ADDR_SURFACE_FLAGS flags; ///< Surface type flags
563
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
564
/// number of samples for normal AA; Set it to the
565
/// number of fragments for EQAA
566
/// r800 and later HWL parameters
567
// Needed by 2D tiling, for linear and 1D tiling, just keep them 0's
568
ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate
569
AddrTileType tileType; ///< Micro tiling type, not needed when tileIndex != -1
570
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
571
/// while the global useTileIndex is set to 1
572
UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a
573
/// must for mip levels from SI+.
574
/// Don't use pitch in blocks for compressed formats!
575
UINT_32 maxBaseAlign; ///< Max base alignment request from client
576
UINT_32 pitchAlign; ///< Pitch alignment request from client
577
UINT_32 heightAlign; ///< Height alignment request from client
578
} ADDR_COMPUTE_SURFACE_INFO_INPUT;
579
580
/**
581
****************************************************************************************************
582
* ADDR_COMPUTE_SURFACE_INFO_OUTPUT
583
*
584
* @brief
585
* Output structure for AddrComputeSurfInfo
586
* @note
587
Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch
588
Pixel: Original pixel
589
****************************************************************************************************
590
*/
591
typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT
592
{
593
UINT_32 size; ///< Size of this structure in bytes
594
595
UINT_32 pitch; ///< Pitch in elements (in blocks for compressed formats)
596
UINT_32 height; ///< Height in elements (in blocks for compressed formats)
597
UINT_32 depth; ///< Number of slice/depth
598
UINT_64 surfSize; ///< Surface size in bytes
599
AddrTileMode tileMode; ///< Actual tile mode. May differ from that in input
600
UINT_32 baseAlign; ///< Base address alignment
601
UINT_32 pitchAlign; ///< Pitch alignment, in elements
602
UINT_32 heightAlign; ///< Height alignment, in elements
603
UINT_32 depthAlign; ///< Depth alignment, aligned to thickness, for 3d texture
604
UINT_32 bpp; ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit)
605
UINT_32 pixelPitch; ///< Pitch in original pixels
606
UINT_32 pixelHeight; ///< Height in original pixels
607
UINT_32 pixelBits; ///< Original bits per pixel, passed from input
608
UINT_64 sliceSize; ///< Size of slice specified by input's slice
609
/// The result is controlled by surface flags & createFlags
610
/// By default this value equals to surfSize for volume
611
UINT_32 pitchTileMax; ///< PITCH_TILE_MAX value for h/w register
612
UINT_32 heightTileMax; ///< HEIGHT_TILE_MAX value for h/w register
613
UINT_32 sliceTileMax; ///< SLICE_TILE_MAX value for h/w register
614
615
UINT_32 numSamples; ///< Pass the effective numSamples processed in this call
616
617
/// r800 and later HWL parameters
618
ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input
619
AddrTileType tileType; ///< Micro tiling type, only valid when tileIndex != -1
620
INT_32 tileIndex; ///< Tile index, MAY be "downgraded"
621
622
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
623
/// Output flags
624
struct
625
{
626
/// Special information to work around SI mipmap swizzle bug UBTS #317508
627
UINT_32 last2DLevel : 1; ///< TRUE if this is the last 2D(3D) tiled
628
///< Only meaningful when create flag checkLast2DLevel is set
629
UINT_32 tcCompatible : 1; ///< If the surface can be shader compatible
630
UINT_32 dccUnsupport : 1; ///< If the surface can support DCC compressed rendering
631
UINT_32 prtTileIndex : 1; ///< SI only, indicate the returned tile index is for PRT
632
///< If address lib return true for mip 0, client should set prt flag
633
///< for child mips in subsequent compute surface info calls
634
UINT_32 reserved :28; ///< Reserved bits
635
};
636
637
UINT_32 equationIndex; ///< Equation index in the equation table;
638
639
UINT_32 blockWidth; ///< Width in element inside one block(1D->Micro, 2D->Macro)
640
UINT_32 blockHeight; ///< Height in element inside one block(1D->Micro, 2D->Macro)
641
UINT_32 blockSlices; ///< Slice number inside one block(1D->Micro, 2D->Macro)
642
643
/// Stereo info
644
ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE
645
646
INT_32 stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set
647
} ADDR_COMPUTE_SURFACE_INFO_OUTPUT;
648
649
/**
650
****************************************************************************************************
651
* AddrComputeSurfaceInfo
652
*
653
* @brief
654
* Compute surface width/height/depth/alignments and suitable tiling mode
655
****************************************************************************************************
656
*/
657
ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo(
658
ADDR_HANDLE hLib,
659
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
660
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut);
661
662
663
664
/**
665
****************************************************************************************************
666
* ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
667
*
668
* @brief
669
* Input structure for AddrComputeSurfaceAddrFromCoord
670
****************************************************************************************************
671
*/
672
typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
673
{
674
UINT_32 size; ///< Size of this structure in bytes
675
676
UINT_32 x; ///< X coordinate
677
UINT_32 y; ///< Y coordinate
678
UINT_32 slice; ///< Slice index
679
UINT_32 sample; ///< Sample index, use fragment index for EQAA
680
681
UINT_32 bpp; ///< Bits per pixel
682
UINT_32 pitch; ///< Surface pitch, in pixels
683
UINT_32 height; ///< Surface height, in pixels
684
UINT_32 numSlices; ///< Surface depth
685
UINT_32 numSamples; ///< Number of samples
686
687
AddrTileMode tileMode; ///< Tile mode
688
BOOL_32 isDepth; ///< TRUE if the surface uses depth sample ordering within
689
/// micro tile. Textures can also choose depth sample order
690
UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles
691
/// the case that components are stored separately
692
UINT_32 compBits; ///< The component bits actually needed(for planar surface)
693
694
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
695
/// number of samples for normal AA; Set it to the
696
/// number of fragments for EQAA
697
/// r800 and later HWL parameters
698
// Used for 1D tiling above
699
AddrTileType tileType; ///< See defintion of AddrTileType
700
struct
701
{
702
UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture
703
/// only flag. Only non-RT texture can set this to TRUE
704
UINT_32 reserved :31; ///< Reserved for future use.
705
};
706
// 2D tiling needs following structure
707
ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
708
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
709
/// while the global useTileIndex is set to 1
710
union
711
{
712
struct
713
{
714
UINT_32 bankSwizzle; ///< Bank swizzle
715
UINT_32 pipeSwizzle; ///< Pipe swizzle
716
};
717
UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
718
};
719
} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
720
721
/**
722
****************************************************************************************************
723
* ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
724
*
725
* @brief
726
* Output structure for AddrComputeSurfaceAddrFromCoord
727
****************************************************************************************************
728
*/
729
typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
730
{
731
UINT_32 size; ///< Size of this structure in bytes
732
733
UINT_64 addr; ///< Byte address
734
UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7.
735
/// For surface bpp < 8, e.g. FMT_1.
736
UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block)
737
} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT;
738
739
/**
740
****************************************************************************************************
741
* AddrComputeSurfaceAddrFromCoord
742
*
743
* @brief
744
* Compute surface address from a given coordinate.
745
****************************************************************************************************
746
*/
747
ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord(
748
ADDR_HANDLE hLib,
749
const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
750
ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);
751
752
753
754
/**
755
****************************************************************************************************
756
* ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
757
*
758
* @brief
759
* Input structure for AddrComputeSurfaceCoordFromAddr
760
****************************************************************************************************
761
*/
762
typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
763
{
764
UINT_32 size; ///< Size of this structure in bytes
765
766
UINT_64 addr; ///< Address in bytes
767
UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8,
768
/// e.g. FMT_1;
769
UINT_32 bpp; ///< Bits per pixel
770
UINT_32 pitch; ///< Pitch, in pixels
771
UINT_32 height; ///< Height in pixels
772
UINT_32 numSlices; ///< Surface depth
773
UINT_32 numSamples; ///< Number of samples
774
775
AddrTileMode tileMode; ///< Tile mode
776
BOOL_32 isDepth; ///< Surface uses depth sample ordering within micro tile.
777
/// Note: Textures can choose depth sample order as well.
778
UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles
779
/// the case that components are stored separately
780
UINT_32 compBits; ///< The component bits actually needed(for planar surface)
781
782
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
783
/// number of samples for normal AA; Set it to the
784
/// number of fragments for EQAA
785
/// r800 and later HWL parameters
786
// Used for 1D tiling above
787
AddrTileType tileType; ///< See defintion of AddrTileType
788
struct
789
{
790
UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture
791
/// only flag. Only non-RT texture can set this to TRUE
792
UINT_32 reserved :31; ///< Reserved for future use.
793
};
794
// 2D tiling needs following structure
795
ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
796
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
797
/// while the global useTileIndex is set to 1
798
union
799
{
800
struct
801
{
802
UINT_32 bankSwizzle; ///< Bank swizzle
803
UINT_32 pipeSwizzle; ///< Pipe swizzle
804
};
805
UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
806
};
807
} ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT;
808
809
/**
810
****************************************************************************************************
811
* ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
812
*
813
* @brief
814
* Output structure for AddrComputeSurfaceCoordFromAddr
815
****************************************************************************************************
816
*/
817
typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
818
{
819
UINT_32 size; ///< Size of this structure in bytes
820
821
UINT_32 x; ///< X coordinate
822
UINT_32 y; ///< Y coordinate
823
UINT_32 slice; ///< Index of slices
824
UINT_32 sample; ///< Index of samples, means fragment index for EQAA
825
} ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT;
826
827
/**
828
****************************************************************************************************
829
* AddrComputeSurfaceCoordFromAddr
830
*
831
* @brief
832
* Compute coordinate from a given surface address
833
****************************************************************************************************
834
*/
835
ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr(
836
ADDR_HANDLE hLib,
837
const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
838
ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut);
839
840
////////////////////////////////////////////////////////////////////////////////////////////////////
841
// HTile functions
842
////////////////////////////////////////////////////////////////////////////////////////////////////
843
844
/**
845
****************************************************************************************************
846
* ADDR_HTILE_FLAGS
847
*
848
* @brief
849
* HTILE flags
850
****************************************************************************************************
851
*/
852
typedef union _ADDR_HTILE_FLAGS
853
{
854
struct
855
{
856
UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
857
UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile
858
/// size to 256xBankxPipe when computing tc-compatible
859
/// htile info.
860
UINT_32 reserved : 30; ///< Reserved bits
861
};
862
863
UINT_32 value;
864
} ADDR_HTILE_FLAGS;
865
866
/**
867
****************************************************************************************************
868
* ADDR_COMPUTE_HTILE_INFO_INPUT
869
*
870
* @brief
871
* Input structure of AddrComputeHtileInfo
872
****************************************************************************************************
873
*/
874
typedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT
875
{
876
UINT_32 size; ///< Size of this structure in bytes
877
878
ADDR_HTILE_FLAGS flags; ///< HTILE flags
879
UINT_32 pitch; ///< Surface pitch, in pixels
880
UINT_32 height; ///< Surface height, in pixels
881
UINT_32 numSlices; ///< Number of slices
882
BOOL_32 isLinear; ///< Linear or tiled HTILE layout
883
AddrHtileBlockSize blockWidth; ///< 4 or 8. EG above only support 8
884
AddrHtileBlockSize blockHeight; ///< 4 or 8. EG above only support 8
885
ADDR_TILEINFO* pTileInfo; ///< Tile info
886
887
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
888
/// while the global useTileIndex is set to 1
889
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
890
///< README: When tileIndex is not -1, this must be valid
891
} ADDR_COMPUTE_HTILE_INFO_INPUT;
892
893
/**
894
****************************************************************************************************
895
* ADDR_COMPUTE_HTILE_INFO_OUTPUT
896
*
897
* @brief
898
* Output structure of AddrComputeHtileInfo
899
****************************************************************************************************
900
*/
901
typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT
902
{
903
UINT_32 size; ///< Size of this structure in bytes
904
905
UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this
906
/// HTile buffer. This might be larger than original depth
907
/// buffer pitch when called with an unaligned pitch.
908
UINT_32 height; ///< Height in pixels, as above
909
UINT_64 htileBytes; ///< Size of HTILE buffer, in bytes
910
UINT_32 baseAlign; ///< Base alignment
911
UINT_32 bpp; ///< Bits per pixel for HTILE is how many bits for an 8x8 block!
912
UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape
913
UINT_32 macroHeight; ///< Macro height in pixels
914
UINT_64 sliceSize; ///< Slice size, in bytes.
915
BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved
916
/// Compute engine clear can't be used if htile is interleaved
917
BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in
918
/// next mip level, it also indicates if memory set based
919
/// fast clear can be used for current mip level.
920
} ADDR_COMPUTE_HTILE_INFO_OUTPUT;
921
922
/**
923
****************************************************************************************************
924
* AddrComputeHtileInfo
925
*
926
* @brief
927
* Compute Htile pitch, height, base alignment and size in bytes
928
****************************************************************************************************
929
*/
930
ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo(
931
ADDR_HANDLE hLib,
932
const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn,
933
ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut);
934
935
936
937
/**
938
****************************************************************************************************
939
* ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
940
*
941
* @brief
942
* Input structure for AddrComputeHtileAddrFromCoord
943
****************************************************************************************************
944
*/
945
typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
946
{
947
UINT_32 size; ///< Size of this structure in bytes
948
949
UINT_32 pitch; ///< Pitch, in pixels
950
UINT_32 height; ///< Height in pixels
951
UINT_32 x; ///< X coordinate
952
UINT_32 y; ///< Y coordinate
953
UINT_32 slice; ///< Index of slice
954
UINT_32 numSlices; ///< Number of slices
955
BOOL_32 isLinear; ///< Linear or tiled HTILE layout
956
ADDR_HTILE_FLAGS flags; ///< htile flags
957
AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
958
AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
959
ADDR_TILEINFO* pTileInfo; ///< Tile info
960
961
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
962
/// while the global useTileIndex is set to 1
963
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
964
///< README: When tileIndex is not -1, this must be valid
965
UINT_32 bpp; ///< depth/stencil buffer bit per pixel size
966
UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address
967
} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;
968
969
/**
970
****************************************************************************************************
971
* ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
972
*
973
* @brief
974
* Output structure for AddrComputeHtileAddrFromCoord
975
****************************************************************************************************
976
*/
977
typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
978
{
979
UINT_32 size; ///< Size of this structure in bytes
980
981
UINT_64 addr; ///< Address in bytes
982
UINT_32 bitPosition; ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method.
983
/// So we keep bitPosition for HTILE as well
984
} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT;
985
986
/**
987
****************************************************************************************************
988
* AddrComputeHtileAddrFromCoord
989
*
990
* @brief
991
* Compute Htile address according to coordinates (of depth buffer)
992
****************************************************************************************************
993
*/
994
ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord(
995
ADDR_HANDLE hLib,
996
const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
997
ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
998
999
1000
1001
/**
1002
****************************************************************************************************
1003
* ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
1004
*
1005
* @brief
1006
* Input structure for AddrComputeHtileCoordFromAddr
1007
****************************************************************************************************
1008
*/
1009
typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
1010
{
1011
UINT_32 size; ///< Size of this structure in bytes
1012
1013
UINT_64 addr; ///< Address
1014
UINT_32 bitPosition; ///< Bit position 0 or 4. CMASK and HTILE share some methods
1015
/// so we keep bitPosition for HTILE as well
1016
UINT_32 pitch; ///< Pitch, in pixels
1017
UINT_32 height; ///< Height, in pixels
1018
UINT_32 numSlices; ///< Number of slices
1019
BOOL_32 isLinear; ///< Linear or tiled HTILE layout
1020
AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8
1021
AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8
1022
ADDR_TILEINFO* pTileInfo; ///< Tile info
1023
1024
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1025
/// while the global useTileIndex is set to 1
1026
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1027
///< README: When tileIndex is not -1, this must be valid
1028
} ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT;
1029
1030
/**
1031
****************************************************************************************************
1032
* ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
1033
*
1034
* @brief
1035
* Output structure for AddrComputeHtileCoordFromAddr
1036
****************************************************************************************************
1037
*/
1038
typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
1039
{
1040
UINT_32 size; ///< Size of this structure in bytes
1041
1042
UINT_32 x; ///< X coordinate
1043
UINT_32 y; ///< Y coordinate
1044
UINT_32 slice; ///< Slice index
1045
} ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT;
1046
1047
/**
1048
****************************************************************************************************
1049
* AddrComputeHtileCoordFromAddr
1050
*
1051
* @brief
1052
* Compute coordinates within depth buffer (1st pixel of a micro tile) according to
1053
* Htile address
1054
****************************************************************************************************
1055
*/
1056
ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr(
1057
ADDR_HANDLE hLib,
1058
const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
1059
ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
1060
1061
1062
1063
////////////////////////////////////////////////////////////////////////////////////////////////////
1064
// C-mask functions
1065
////////////////////////////////////////////////////////////////////////////////////////////////////
1066
1067
/**
1068
****************************************************************************************************
1069
* ADDR_CMASK_FLAGS
1070
*
1071
* @brief
1072
* CMASK flags
1073
****************************************************************************************************
1074
*/
1075
typedef union _ADDR_CMASK_FLAGS
1076
{
1077
struct
1078
{
1079
UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
1080
UINT_32 reserved :31; ///< Reserved bits
1081
};
1082
1083
UINT_32 value;
1084
} ADDR_CMASK_FLAGS;
1085
1086
/**
1087
****************************************************************************************************
1088
* ADDR_COMPUTE_CMASK_INFO_INPUT
1089
*
1090
* @brief
1091
* Input structure of AddrComputeCmaskInfo
1092
****************************************************************************************************
1093
*/
1094
typedef struct _ADDR_COMPUTE_CMASKINFO_INPUT
1095
{
1096
UINT_32 size; ///< Size of this structure in bytes
1097
1098
ADDR_CMASK_FLAGS flags; ///< CMASK flags
1099
UINT_32 pitch; ///< Pitch, in pixels, of color buffer
1100
UINT_32 height; ///< Height, in pixels, of color buffer
1101
UINT_32 numSlices; ///< Number of slices, of color buffer
1102
BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1103
ADDR_TILEINFO* pTileInfo; ///< Tile info
1104
1105
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1106
/// while the global useTileIndex is set to 1
1107
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1108
///< README: When tileIndex is not -1, this must be valid
1109
} ADDR_COMPUTE_CMASK_INFO_INPUT;
1110
1111
/**
1112
****************************************************************************************************
1113
* ADDR_COMPUTE_CMASK_INFO_OUTPUT
1114
*
1115
* @brief
1116
* Output structure of AddrComputeCmaskInfo
1117
****************************************************************************************************
1118
*/
1119
typedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT
1120
{
1121
UINT_32 size; ///< Size of this structure in bytes
1122
1123
UINT_32 pitch; ///< Pitch in pixels of color buffer which
1124
/// this Cmask matches. The size might be larger than
1125
/// original color buffer pitch when called with
1126
/// an unaligned pitch.
1127
UINT_32 height; ///< Height in pixels, as above
1128
UINT_64 cmaskBytes; ///< Size in bytes of CMask buffer
1129
UINT_32 baseAlign; ///< Base alignment
1130
UINT_32 blockMax; ///< Cmask block size. Need this to set CB_COLORn_MASK register
1131
UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape
1132
UINT_32 macroHeight; ///< Macro height in pixels
1133
UINT_64 sliceSize; ///< Slice size, in bytes.
1134
} ADDR_COMPUTE_CMASK_INFO_OUTPUT;
1135
1136
/**
1137
****************************************************************************************************
1138
* AddrComputeCmaskInfo
1139
*
1140
* @brief
1141
* Compute Cmask pitch, height, base alignment and size in bytes from color buffer
1142
* info
1143
****************************************************************************************************
1144
*/
1145
ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo(
1146
ADDR_HANDLE hLib,
1147
const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn,
1148
ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut);
1149
1150
1151
1152
/**
1153
****************************************************************************************************
1154
* ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
1155
*
1156
* @brief
1157
* Input structure for AddrComputeCmaskAddrFromCoord
1158
*
1159
****************************************************************************************************
1160
*/
1161
typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
1162
{
1163
UINT_32 size; ///< Size of this structure in bytes
1164
UINT_32 x; ///< X coordinate
1165
UINT_32 y; ///< Y coordinate
1166
UINT_64 fmaskAddr; ///< Fmask addr for tc compatible Cmask
1167
UINT_32 slice; ///< Slice index
1168
UINT_32 pitch; ///< Pitch in pixels, of color buffer
1169
UINT_32 height; ///< Height in pixels, of color buffer
1170
UINT_32 numSlices; ///< Number of slices
1171
UINT_32 bpp;
1172
BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1173
ADDR_CMASK_FLAGS flags; ///< CMASK flags
1174
ADDR_TILEINFO* pTileInfo; ///< Tile info
1175
1176
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1177
///< while the global useTileIndex is set to 1
1178
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1179
///< README: When tileIndex is not -1, this must be valid
1180
} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT;
1181
1182
/**
1183
****************************************************************************************************
1184
* ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
1185
*
1186
* @brief
1187
* Output structure for AddrComputeCmaskAddrFromCoord
1188
****************************************************************************************************
1189
*/
1190
typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
1191
{
1192
UINT_32 size; ///< Size of this structure in bytes
1193
1194
UINT_64 addr; ///< CMASK address in bytes
1195
UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp,
1196
/// so the address may be located in bit 0 (0) or 4 (4)
1197
} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT;
1198
1199
/**
1200
****************************************************************************************************
1201
* AddrComputeCmaskAddrFromCoord
1202
*
1203
* @brief
1204
* Compute Cmask address according to coordinates (of MSAA color buffer)
1205
****************************************************************************************************
1206
*/
1207
ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord(
1208
ADDR_HANDLE hLib,
1209
const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
1210
ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
1211
1212
1213
1214
/**
1215
****************************************************************************************************
1216
* ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
1217
*
1218
* @brief
1219
* Input structure for AddrComputeCmaskCoordFromAddr
1220
****************************************************************************************************
1221
*/
1222
typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
1223
{
1224
UINT_32 size; ///< Size of this structure in bytes
1225
1226
UINT_64 addr; ///< CMASK address in bytes
1227
UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp,
1228
/// so the address may be located in bit 0 (0) or 4 (4)
1229
UINT_32 pitch; ///< Pitch, in pixels
1230
UINT_32 height; ///< Height in pixels
1231
UINT_32 numSlices; ///< Number of slices
1232
BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1233
ADDR_TILEINFO* pTileInfo; ///< Tile info
1234
1235
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1236
/// while the global useTileIndex is set to 1
1237
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1238
///< README: When tileIndex is not -1, this must be valid
1239
} ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT;
1240
1241
/**
1242
****************************************************************************************************
1243
* ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
1244
*
1245
* @brief
1246
* Output structure for AddrComputeCmaskCoordFromAddr
1247
****************************************************************************************************
1248
*/
1249
typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
1250
{
1251
UINT_32 size; ///< Size of this structure in bytes
1252
1253
UINT_32 x; ///< X coordinate
1254
UINT_32 y; ///< Y coordinate
1255
UINT_32 slice; ///< Slice index
1256
} ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT;
1257
1258
/**
1259
****************************************************************************************************
1260
* AddrComputeCmaskCoordFromAddr
1261
*
1262
* @brief
1263
* Compute coordinates within color buffer (1st pixel of a micro tile) according to
1264
* Cmask address
1265
****************************************************************************************************
1266
*/
1267
ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr(
1268
ADDR_HANDLE hLib,
1269
const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
1270
ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);
1271
1272
1273
1274
////////////////////////////////////////////////////////////////////////////////////////////////////
1275
// F-mask functions
1276
////////////////////////////////////////////////////////////////////////////////////////////////////
1277
1278
/**
1279
****************************************************************************************************
1280
* ADDR_COMPUTE_FMASK_INFO_INPUT
1281
*
1282
* @brief
1283
* Input structure for AddrComputeFmaskInfo
1284
****************************************************************************************************
1285
*/
1286
typedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT
1287
{
1288
UINT_32 size; ///< Size of this structure in bytes
1289
1290
AddrTileMode tileMode; ///< Tile mode
1291
UINT_32 pitch; ///< Surface pitch, in pixels
1292
UINT_32 height; ///< Surface height, in pixels
1293
UINT_32 numSlices; ///< Number of slice/depth
1294
UINT_32 numSamples; ///< Number of samples
1295
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
1296
/// number of samples for normal AA; Set it to the
1297
/// number of fragments for EQAA
1298
/// r800 and later HWL parameters
1299
struct
1300
{
1301
UINT_32 resolved: 1; ///< TRUE if the surface is for resolved fmask, only used
1302
/// by H/W clients. S/W should always set it to FALSE.
1303
UINT_32 reserved: 31; ///< Reserved for future use.
1304
};
1305
ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Clients must give valid data
1306
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1307
/// while the global useTileIndex is set to 1
1308
} ADDR_COMPUTE_FMASK_INFO_INPUT;
1309
1310
/**
1311
****************************************************************************************************
1312
* ADDR_COMPUTE_FMASK_INFO_OUTPUT
1313
*
1314
* @brief
1315
* Output structure for AddrComputeFmaskInfo
1316
****************************************************************************************************
1317
*/
1318
typedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT
1319
{
1320
UINT_32 size; ///< Size of this structure in bytes
1321
1322
UINT_32 pitch; ///< Pitch of fmask in pixels
1323
UINT_32 height; ///< Height of fmask in pixels
1324
UINT_32 numSlices; ///< Slices of fmask
1325
UINT_64 fmaskBytes; ///< Size of fmask in bytes
1326
UINT_32 baseAlign; ///< Base address alignment
1327
UINT_32 pitchAlign; ///< Pitch alignment
1328
UINT_32 heightAlign; ///< Height alignment
1329
UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes
1330
UINT_32 numSamples; ///< Number of samples, used for dump, export this since input
1331
/// may be changed in 9xx and above
1332
/// r800 and later HWL parameters
1333
ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Fmask can have different
1334
/// bank_height from color buffer
1335
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1336
/// while the global useTileIndex is set to 1
1337
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1338
UINT_64 sliceSize; ///< Size of slice in bytes
1339
} ADDR_COMPUTE_FMASK_INFO_OUTPUT;
1340
1341
/**
1342
****************************************************************************************************
1343
* AddrComputeFmaskInfo
1344
*
1345
* @brief
1346
* Compute Fmask pitch/height/depth/alignments and size in bytes
1347
****************************************************************************************************
1348
*/
1349
ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo(
1350
ADDR_HANDLE hLib,
1351
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
1352
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
1353
1354
1355
1356
/**
1357
****************************************************************************************************
1358
* ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
1359
*
1360
* @brief
1361
* Input structure for AddrComputeFmaskAddrFromCoord
1362
****************************************************************************************************
1363
*/
1364
typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
1365
{
1366
UINT_32 size; ///< Size of this structure in bytes
1367
1368
UINT_32 x; ///< X coordinate
1369
UINT_32 y; ///< Y coordinate
1370
UINT_32 slice; ///< Slice index
1371
UINT_32 plane; ///< Plane number
1372
UINT_32 sample; ///< Sample index (fragment index for EQAA)
1373
1374
UINT_32 pitch; ///< Surface pitch, in pixels
1375
UINT_32 height; ///< Surface height, in pixels
1376
UINT_32 numSamples; ///< Number of samples
1377
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
1378
/// number of samples for normal AA; Set it to the
1379
/// number of fragments for EQAA
1380
1381
AddrTileMode tileMode; ///< Tile mode
1382
union
1383
{
1384
struct
1385
{
1386
UINT_32 bankSwizzle; ///< Bank swizzle
1387
UINT_32 pipeSwizzle; ///< Pipe swizzle
1388
};
1389
UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
1390
};
1391
1392
/// r800 and later HWL parameters
1393
struct
1394
{
1395
UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by H/W clients
1396
UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored.
1397
UINT_32 reserved: 30; ///< Reserved for future use.
1398
};
1399
ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Client must provide all data
1400
1401
} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT;
1402
1403
/**
1404
****************************************************************************************************
1405
* ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
1406
*
1407
* @brief
1408
* Output structure for AddrComputeFmaskAddrFromCoord
1409
****************************************************************************************************
1410
*/
1411
typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
1412
{
1413
UINT_32 size; ///< Size of this structure in bytes
1414
1415
UINT_64 addr; ///< Fmask address
1416
UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7.
1417
} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT;
1418
1419
/**
1420
****************************************************************************************************
1421
* AddrComputeFmaskAddrFromCoord
1422
*
1423
* @brief
1424
* Compute Fmask address according to coordinates (x,y,slice,sample,plane)
1425
****************************************************************************************************
1426
*/
1427
ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord(
1428
ADDR_HANDLE hLib,
1429
const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
1430
ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);
1431
1432
1433
1434
/**
1435
****************************************************************************************************
1436
* ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
1437
*
1438
* @brief
1439
* Input structure for AddrComputeFmaskCoordFromAddr
1440
****************************************************************************************************
1441
*/
1442
typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
1443
{
1444
UINT_32 size; ///< Size of this structure in bytes
1445
1446
UINT_64 addr; ///< Address
1447
UINT_32 bitPosition; ///< Bit position within addr, 0-7.
1448
1449
UINT_32 pitch; ///< Pitch, in pixels
1450
UINT_32 height; ///< Height in pixels
1451
UINT_32 numSamples; ///< Number of samples
1452
UINT_32 numFrags; ///< Number of fragments
1453
AddrTileMode tileMode; ///< Tile mode
1454
union
1455
{
1456
struct
1457
{
1458
UINT_32 bankSwizzle; ///< Bank swizzle
1459
UINT_32 pipeSwizzle; ///< Pipe swizzle
1460
};
1461
UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
1462
};
1463
1464
/// r800 and later HWL parameters
1465
struct
1466
{
1467
UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by HW components
1468
UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored.
1469
UINT_32 reserved: 30; ///< Reserved for future use.
1470
};
1471
ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
1472
1473
} ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT;
1474
1475
/**
1476
****************************************************************************************************
1477
* ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
1478
*
1479
* @brief
1480
* Output structure for AddrComputeFmaskCoordFromAddr
1481
****************************************************************************************************
1482
*/
1483
typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
1484
{
1485
UINT_32 size; ///< Size of this structure in bytes
1486
1487
UINT_32 x; ///< X coordinate
1488
UINT_32 y; ///< Y coordinate
1489
UINT_32 slice; ///< Slice index
1490
UINT_32 plane; ///< Plane number
1491
UINT_32 sample; ///< Sample index (fragment index for EQAA)
1492
} ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT;
1493
1494
/**
1495
****************************************************************************************************
1496
* AddrComputeFmaskCoordFromAddr
1497
*
1498
* @brief
1499
* Compute FMASK coordinate from an given address
1500
****************************************************************************************************
1501
*/
1502
ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr(
1503
ADDR_HANDLE hLib,
1504
const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
1505
ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);
1506
1507
1508
1509
////////////////////////////////////////////////////////////////////////////////////////////////////
1510
// Element/utility functions
1511
////////////////////////////////////////////////////////////////////////////////////////////////////
1512
1513
/**
1514
****************************************************************************************************
1515
* AddrGetVersion
1516
*
1517
* @brief
1518
* Get AddrLib version number
1519
****************************************************************************************************
1520
*/
1521
UINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib);
1522
1523
/**
1524
****************************************************************************************************
1525
* AddrUseTileIndex
1526
*
1527
* @brief
1528
* Return TRUE if tileIndex is enabled in this address library
1529
****************************************************************************************************
1530
*/
1531
BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib);
1532
1533
/**
1534
****************************************************************************************************
1535
* AddrUseCombinedSwizzle
1536
*
1537
* @brief
1538
* Return TRUE if combined swizzle is enabled in this address library
1539
****************************************************************************************************
1540
*/
1541
BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib);
1542
1543
/**
1544
****************************************************************************************************
1545
* ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT
1546
*
1547
* @brief
1548
* Input structure of AddrExtractBankPipeSwizzle
1549
****************************************************************************************************
1550
*/
1551
typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT
1552
{
1553
UINT_32 size; ///< Size of this structure in bytes
1554
1555
UINT_32 base256b; ///< Base256b value
1556
1557
/// r800 and later HWL parameters
1558
ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
1559
1560
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1561
/// while the global useTileIndex is set to 1
1562
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1563
///< README: When tileIndex is not -1, this must be valid
1564
} ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT;
1565
1566
/**
1567
****************************************************************************************************
1568
* ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT
1569
*
1570
* @brief
1571
* Output structure of AddrExtractBankPipeSwizzle
1572
****************************************************************************************************
1573
*/
1574
typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT
1575
{
1576
UINT_32 size; ///< Size of this structure in bytes
1577
1578
UINT_32 bankSwizzle; ///< Bank swizzle
1579
UINT_32 pipeSwizzle; ///< Pipe swizzle
1580
} ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT;
1581
1582
/**
1583
****************************************************************************************************
1584
* AddrExtractBankPipeSwizzle
1585
*
1586
* @brief
1587
* Extract Bank and Pipe swizzle from base256b
1588
* @return
1589
* ADDR_OK if no error
1590
****************************************************************************************************
1591
*/
1592
ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle(
1593
ADDR_HANDLE hLib,
1594
const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
1595
ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut);
1596
1597
1598
/**
1599
****************************************************************************************************
1600
* ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
1601
*
1602
* @brief
1603
* Input structure of AddrCombineBankPipeSwizzle
1604
****************************************************************************************************
1605
*/
1606
typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
1607
{
1608
UINT_32 size; ///< Size of this structure in bytes
1609
1610
UINT_32 bankSwizzle; ///< Bank swizzle
1611
UINT_32 pipeSwizzle; ///< Pipe swizzle
1612
UINT_64 baseAddr; ///< Base address (leave it zero for driver clients)
1613
1614
/// r800 and later HWL parameters
1615
ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
1616
1617
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1618
/// while the global useTileIndex is set to 1
1619
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1620
///< README: When tileIndex is not -1, this must be valid
1621
} ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT;
1622
1623
/**
1624
****************************************************************************************************
1625
* ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT
1626
*
1627
* @brief
1628
* Output structure of AddrCombineBankPipeSwizzle
1629
****************************************************************************************************
1630
*/
1631
typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT
1632
{
1633
UINT_32 size; ///< Size of this structure in bytes
1634
1635
UINT_32 tileSwizzle; ///< Combined swizzle
1636
} ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT;
1637
1638
/**
1639
****************************************************************************************************
1640
* AddrCombineBankPipeSwizzle
1641
*
1642
* @brief
1643
* Combine Bank and Pipe swizzle
1644
* @return
1645
* ADDR_OK if no error
1646
* @note
1647
* baseAddr here is full MCAddress instead of base256b
1648
****************************************************************************************************
1649
*/
1650
ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle(
1651
ADDR_HANDLE hLib,
1652
const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn,
1653
ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut);
1654
1655
1656
1657
/**
1658
****************************************************************************************************
1659
* ADDR_COMPUTE_SLICESWIZZLE_INPUT
1660
*
1661
* @brief
1662
* Input structure of AddrComputeSliceSwizzle
1663
****************************************************************************************************
1664
*/
1665
typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT
1666
{
1667
UINT_32 size; ///< Size of this structure in bytes
1668
1669
AddrTileMode tileMode; ///< Tile Mode
1670
UINT_32 baseSwizzle; ///< Base tile swizzle
1671
UINT_32 slice; ///< Slice index
1672
UINT_64 baseAddr; ///< Base address, driver should leave it 0 in most cases
1673
1674
/// r800 and later HWL parameters
1675
ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here!
1676
1677
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1678
/// while the global useTileIndex is set to 1
1679
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1680
///< README: When tileIndex is not -1, this must be valid
1681
} ADDR_COMPUTE_SLICESWIZZLE_INPUT;
1682
1683
1684
1685
/**
1686
****************************************************************************************************
1687
* ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
1688
*
1689
* @brief
1690
* Output structure of AddrComputeSliceSwizzle
1691
****************************************************************************************************
1692
*/
1693
typedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
1694
{
1695
UINT_32 size; ///< Size of this structure in bytes
1696
1697
UINT_32 tileSwizzle; ///< Recalculated tileSwizzle value
1698
} ADDR_COMPUTE_SLICESWIZZLE_OUTPUT;
1699
1700
/**
1701
****************************************************************************************************
1702
* AddrComputeSliceSwizzle
1703
*
1704
* @brief
1705
* Extract Bank and Pipe swizzle from base256b
1706
* @return
1707
* ADDR_OK if no error
1708
****************************************************************************************************
1709
*/
1710
ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle(
1711
ADDR_HANDLE hLib,
1712
const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
1713
ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut);
1714
1715
1716
/**
1717
****************************************************************************************************
1718
* AddrSwizzleGenOption
1719
*
1720
* @brief
1721
* Which swizzle generating options: legacy or linear
1722
****************************************************************************************************
1723
*/
1724
typedef enum _AddrSwizzleGenOption
1725
{
1726
ADDR_SWIZZLE_GEN_DEFAULT = 0, ///< As is in client driver implemention for swizzle
1727
ADDR_SWIZZLE_GEN_LINEAR = 1, ///< Using a linear increment of swizzle
1728
} AddrSwizzleGenOption;
1729
1730
/**
1731
****************************************************************************************************
1732
* AddrSwizzleOption
1733
*
1734
* @brief
1735
* Controls how swizzle is generated
1736
****************************************************************************************************
1737
*/
1738
typedef union _ADDR_SWIZZLE_OPTION
1739
{
1740
struct
1741
{
1742
UINT_32 genOption : 1; ///< The way swizzle is generated, see AddrSwizzleGenOption
1743
UINT_32 reduceBankBit : 1; ///< TRUE if we need reduce swizzle bits
1744
UINT_32 reserved :30; ///< Reserved bits
1745
};
1746
1747
UINT_32 value;
1748
1749
} ADDR_SWIZZLE_OPTION;
1750
1751
/**
1752
****************************************************************************************************
1753
* ADDR_COMPUTE_BASE_SWIZZLE_INPUT
1754
*
1755
* @brief
1756
* Input structure of AddrComputeBaseSwizzle
1757
****************************************************************************************************
1758
*/
1759
typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT
1760
{
1761
UINT_32 size; ///< Size of this structure in bytes
1762
1763
ADDR_SWIZZLE_OPTION option; ///< Swizzle option
1764
UINT_32 surfIndex; ///< Index of this surface type
1765
AddrTileMode tileMode; ///< Tile Mode
1766
1767
/// r800 and later HWL parameters
1768
ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here!
1769
1770
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1771
/// while the global useTileIndex is set to 1
1772
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1773
///< README: When tileIndex is not -1, this must be valid
1774
} ADDR_COMPUTE_BASE_SWIZZLE_INPUT;
1775
1776
/**
1777
****************************************************************************************************
1778
* ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
1779
*
1780
* @brief
1781
* Output structure of AddrComputeBaseSwizzle
1782
****************************************************************************************************
1783
*/
1784
typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
1785
{
1786
UINT_32 size; ///< Size of this structure in bytes
1787
1788
UINT_32 tileSwizzle; ///< Combined swizzle
1789
} ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT;
1790
1791
/**
1792
****************************************************************************************************
1793
* AddrComputeBaseSwizzle
1794
*
1795
* @brief
1796
* Return a Combined Bank and Pipe swizzle base on surface based on surface type/index
1797
* @return
1798
* ADDR_OK if no error
1799
****************************************************************************************************
1800
*/
1801
ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle(
1802
ADDR_HANDLE hLib,
1803
const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
1804
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut);
1805
1806
1807
1808
/**
1809
****************************************************************************************************
1810
* ELEM_GETEXPORTNORM_INPUT
1811
*
1812
* @brief
1813
* Input structure for ElemGetExportNorm
1814
*
1815
****************************************************************************************************
1816
*/
1817
typedef struct _ELEM_GETEXPORTNORM_INPUT
1818
{
1819
UINT_32 size; ///< Size of this structure in bytes
1820
1821
AddrColorFormat format; ///< Color buffer format; Client should use ColorFormat
1822
AddrSurfaceNumber num; ///< Surface number type; Client should use NumberType
1823
AddrSurfaceSwap swap; ///< Surface swap byte swap; Client should use SurfaceSwap
1824
UINT_32 numSamples; ///< Number of samples
1825
} ELEM_GETEXPORTNORM_INPUT;
1826
1827
/**
1828
****************************************************************************************************
1829
* ElemGetExportNorm
1830
*
1831
* @brief
1832
* Helper function to check one format can be EXPORT_NUM, which is a register
1833
* CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r600
1834
* family
1835
* @note
1836
* The implementation is only for r600.
1837
* 00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two
1838
* clocks per export)
1839
* 01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one
1840
* clock per export)
1841
*
1842
****************************************************************************************************
1843
*/
1844
BOOL_32 ADDR_API ElemGetExportNorm(
1845
ADDR_HANDLE hLib,
1846
const ELEM_GETEXPORTNORM_INPUT* pIn);
1847
1848
1849
1850
/**
1851
****************************************************************************************************
1852
* ELEM_FLT32TODEPTHPIXEL_INPUT
1853
*
1854
* @brief
1855
* Input structure for addrFlt32ToDepthPixel
1856
*
1857
****************************************************************************************************
1858
*/
1859
typedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT
1860
{
1861
UINT_32 size; ///< Size of this structure in bytes
1862
1863
AddrDepthFormat format; ///< Depth buffer format
1864
ADDR_FLT_32 comps[2]; ///< Component values (Z/stencil)
1865
} ELEM_FLT32TODEPTHPIXEL_INPUT;
1866
1867
/**
1868
****************************************************************************************************
1869
* ELEM_FLT32TODEPTHPIXEL_INPUT
1870
*
1871
* @brief
1872
* Output structure for ElemFlt32ToDepthPixel
1873
*
1874
****************************************************************************************************
1875
*/
1876
typedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT
1877
{
1878
UINT_32 size; ///< Size of this structure in bytes
1879
1880
UINT_8* pPixel; ///< Real depth value. Same data type as depth buffer.
1881
/// Client must provide enough storage for this type.
1882
UINT_32 depthBase; ///< Tile base in bits for depth bits
1883
UINT_32 stencilBase; ///< Tile base in bits for stencil bits
1884
UINT_32 depthBits; ///< Bits for depth
1885
UINT_32 stencilBits; ///< Bits for stencil
1886
} ELEM_FLT32TODEPTHPIXEL_OUTPUT;
1887
1888
/**
1889
****************************************************************************************************
1890
* ElemFlt32ToDepthPixel
1891
*
1892
* @brief
1893
* Convert a FLT_32 value to a depth/stencil pixel value
1894
*
1895
* @return
1896
* Return code
1897
*
1898
****************************************************************************************************
1899
*/
1900
ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel(
1901
ADDR_HANDLE hLib,
1902
const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
1903
ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut);
1904
1905
1906
1907
/**
1908
****************************************************************************************************
1909
* ELEM_FLT32TOCOLORPIXEL_INPUT
1910
*
1911
* @brief
1912
* Input structure for addrFlt32ToColorPixel
1913
*
1914
****************************************************************************************************
1915
*/
1916
typedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT
1917
{
1918
UINT_32 size; ///< Size of this structure in bytes
1919
1920
AddrColorFormat format; ///< Color buffer format
1921
AddrSurfaceNumber surfNum; ///< Surface number
1922
AddrSurfaceSwap surfSwap; ///< Surface swap
1923
ADDR_FLT_32 comps[4]; ///< Component values (r/g/b/a)
1924
} ELEM_FLT32TOCOLORPIXEL_INPUT;
1925
1926
/**
1927
****************************************************************************************************
1928
* ELEM_FLT32TOCOLORPIXEL_INPUT
1929
*
1930
* @brief
1931
* Output structure for ElemFlt32ToColorPixel
1932
*
1933
****************************************************************************************************
1934
*/
1935
typedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT
1936
{
1937
UINT_32 size; ///< Size of this structure in bytes
1938
1939
UINT_8* pPixel; ///< Real color value. Same data type as color buffer.
1940
/// Client must provide enough storage for this type.
1941
} ELEM_FLT32TOCOLORPIXEL_OUTPUT;
1942
1943
/**
1944
****************************************************************************************************
1945
* ElemFlt32ToColorPixel
1946
*
1947
* @brief
1948
* Convert a FLT_32 value to a red/green/blue/alpha pixel value
1949
*
1950
* @return
1951
* Return code
1952
*
1953
****************************************************************************************************
1954
*/
1955
ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel(
1956
ADDR_HANDLE hLib,
1957
const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
1958
ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut);
1959
1960
/**
1961
****************************************************************************************************
1962
* ElemSize
1963
*
1964
* @brief
1965
* Get bits-per-element for specified format
1966
*
1967
* @return
1968
* Bits-per-element of specified format
1969
*
1970
****************************************************************************************************
1971
*/
1972
UINT_32 ADDR_API ElemSize(
1973
ADDR_HANDLE hLib,
1974
AddrFormat format);
1975
1976
/**
1977
****************************************************************************************************
1978
* ADDR_CONVERT_TILEINFOTOHW_INPUT
1979
*
1980
* @brief
1981
* Input structure for AddrConvertTileInfoToHW
1982
* @note
1983
* When reverse is TRUE, indices are igonred
1984
****************************************************************************************************
1985
*/
1986
typedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT
1987
{
1988
UINT_32 size; ///< Size of this structure in bytes
1989
BOOL_32 reverse; ///< Convert control flag.
1990
/// FALSE: convert from real value to HW value;
1991
/// TRUE: convert from HW value to real value.
1992
1993
/// r800 and later HWL parameters
1994
ADDR_TILEINFO* pTileInfo; ///< Tile parameters with real value
1995
1996
INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1997
/// while the global useTileIndex is set to 1
1998
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1999
///< README: When tileIndex is not -1, this must be valid
2000
UINT_32 bpp; ///< Bits per pixel
2001
} ADDR_CONVERT_TILEINFOTOHW_INPUT;
2002
2003
/**
2004
****************************************************************************************************
2005
* ADDR_CONVERT_TILEINFOTOHW_OUTPUT
2006
*
2007
* @brief
2008
* Output structure for AddrConvertTileInfoToHW
2009
****************************************************************************************************
2010
*/
2011
typedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT
2012
{
2013
UINT_32 size; ///< Size of this structure in bytes
2014
2015
/// r800 and later HWL parameters
2016
ADDR_TILEINFO* pTileInfo; ///< Tile parameters with hardware register value
2017
2018
} ADDR_CONVERT_TILEINFOTOHW_OUTPUT;
2019
2020
/**
2021
****************************************************************************************************
2022
* AddrConvertTileInfoToHW
2023
*
2024
* @brief
2025
* Convert tile info from real value to hardware register value
2026
****************************************************************************************************
2027
*/
2028
ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW(
2029
ADDR_HANDLE hLib,
2030
const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
2031
ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut);
2032
2033
2034
2035
/**
2036
****************************************************************************************************
2037
* ADDR_CONVERT_TILEINDEX_INPUT
2038
*
2039
* @brief
2040
* Input structure for AddrConvertTileIndex
2041
****************************************************************************************************
2042
*/
2043
typedef struct _ADDR_CONVERT_TILEINDEX_INPUT
2044
{
2045
UINT_32 size; ///< Size of this structure in bytes
2046
2047
INT_32 tileIndex; ///< Tile index
2048
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
2049
UINT_32 bpp; ///< Bits per pixel
2050
BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual
2051
} ADDR_CONVERT_TILEINDEX_INPUT;
2052
2053
/**
2054
****************************************************************************************************
2055
* ADDR_CONVERT_TILEINDEX_OUTPUT
2056
*
2057
* @brief
2058
* Output structure for AddrConvertTileIndex
2059
****************************************************************************************************
2060
*/
2061
typedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT
2062
{
2063
UINT_32 size; ///< Size of this structure in bytes
2064
2065
AddrTileMode tileMode; ///< Tile mode
2066
AddrTileType tileType; ///< Tile type
2067
ADDR_TILEINFO* pTileInfo; ///< Tile info
2068
2069
} ADDR_CONVERT_TILEINDEX_OUTPUT;
2070
2071
/**
2072
****************************************************************************************************
2073
* AddrConvertTileIndex
2074
*
2075
* @brief
2076
* Convert tile index to tile mode/type/info
2077
****************************************************************************************************
2078
*/
2079
ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex(
2080
ADDR_HANDLE hLib,
2081
const ADDR_CONVERT_TILEINDEX_INPUT* pIn,
2082
ADDR_CONVERT_TILEINDEX_OUTPUT* pOut);
2083
2084
/**
2085
****************************************************************************************************
2086
* ADDR_GET_MACROMODEINDEX_INPUT
2087
*
2088
* @brief
2089
* Input structure for AddrGetMacroModeIndex
2090
****************************************************************************************************
2091
*/
2092
typedef struct _ADDR_GET_MACROMODEINDEX_INPUT
2093
{
2094
UINT_32 size; ///< Size of this structure in bytes
2095
ADDR_SURFACE_FLAGS flags; ///< Surface flag
2096
INT_32 tileIndex; ///< Tile index
2097
UINT_32 bpp; ///< Bits per pixel
2098
UINT_32 numFrags; ///< Number of color fragments
2099
} ADDR_GET_MACROMODEINDEX_INPUT;
2100
2101
/**
2102
****************************************************************************************************
2103
* ADDR_GET_MACROMODEINDEX_OUTPUT
2104
*
2105
* @brief
2106
* Output structure for AddrGetMacroModeIndex
2107
****************************************************************************************************
2108
*/
2109
typedef struct _ADDR_GET_MACROMODEINDEX_OUTPUT
2110
{
2111
UINT_32 size; ///< Size of this structure in bytes
2112
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
2113
} ADDR_GET_MACROMODEINDEX_OUTPUT;
2114
2115
/**
2116
****************************************************************************************************
2117
* AddrGetMacroModeIndex
2118
*
2119
* @brief
2120
* Get macro mode index based on input parameters
2121
****************************************************************************************************
2122
*/
2123
ADDR_E_RETURNCODE ADDR_API AddrGetMacroModeIndex(
2124
ADDR_HANDLE hLib,
2125
const ADDR_GET_MACROMODEINDEX_INPUT* pIn,
2126
ADDR_GET_MACROMODEINDEX_OUTPUT* pOut);
2127
2128
/**
2129
****************************************************************************************************
2130
* ADDR_CONVERT_TILEINDEX1_INPUT
2131
*
2132
* @brief
2133
* Input structure for AddrConvertTileIndex1 (without macro mode index)
2134
****************************************************************************************************
2135
*/
2136
typedef struct _ADDR_CONVERT_TILEINDEX1_INPUT
2137
{
2138
UINT_32 size; ///< Size of this structure in bytes
2139
2140
INT_32 tileIndex; ///< Tile index
2141
UINT_32 bpp; ///< Bits per pixel
2142
UINT_32 numSamples; ///< Number of samples
2143
BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual
2144
} ADDR_CONVERT_TILEINDEX1_INPUT;
2145
2146
/**
2147
****************************************************************************************************
2148
* AddrConvertTileIndex1
2149
*
2150
* @brief
2151
* Convert tile index to tile mode/type/info
2152
****************************************************************************************************
2153
*/
2154
ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1(
2155
ADDR_HANDLE hLib,
2156
const ADDR_CONVERT_TILEINDEX1_INPUT* pIn,
2157
ADDR_CONVERT_TILEINDEX_OUTPUT* pOut);
2158
2159
2160
2161
/**
2162
****************************************************************************************************
2163
* ADDR_GET_TILEINDEX_INPUT
2164
*
2165
* @brief
2166
* Input structure for AddrGetTileIndex
2167
****************************************************************************************************
2168
*/
2169
typedef struct _ADDR_GET_TILEINDEX_INPUT
2170
{
2171
UINT_32 size; ///< Size of this structure in bytes
2172
2173
AddrTileMode tileMode; ///< Tile mode
2174
AddrTileType tileType; ///< Tile-type: disp/non-disp/...
2175
ADDR_TILEINFO* pTileInfo; ///< Pointer to tile-info structure, can be NULL for linear/1D
2176
} ADDR_GET_TILEINDEX_INPUT;
2177
2178
/**
2179
****************************************************************************************************
2180
* ADDR_GET_TILEINDEX_OUTPUT
2181
*
2182
* @brief
2183
* Output structure for AddrGetTileIndex
2184
****************************************************************************************************
2185
*/
2186
typedef struct _ADDR_GET_TILEINDEX_OUTPUT
2187
{
2188
UINT_32 size; ///< Size of this structure in bytes
2189
2190
INT_32 index; ///< index in table
2191
} ADDR_GET_TILEINDEX_OUTPUT;
2192
2193
/**
2194
****************************************************************************************************
2195
* AddrGetTileIndex
2196
*
2197
* @brief
2198
* Get the tiling mode index in table
2199
****************************************************************************************************
2200
*/
2201
ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex(
2202
ADDR_HANDLE hLib,
2203
const ADDR_GET_TILEINDEX_INPUT* pIn,
2204
ADDR_GET_TILEINDEX_OUTPUT* pOut);
2205
2206
2207
2208
/**
2209
****************************************************************************************************
2210
* ADDR_PRT_INFO_INPUT
2211
*
2212
* @brief
2213
* Input structure for AddrComputePrtInfo
2214
****************************************************************************************************
2215
*/
2216
typedef struct _ADDR_PRT_INFO_INPUT
2217
{
2218
AddrFormat format; ///< Surface format
2219
UINT_32 baseMipWidth; ///< Base mipmap width
2220
UINT_32 baseMipHeight; ///< Base mipmap height
2221
UINT_32 baseMipDepth; ///< Base mipmap depth
2222
UINT_32 numFrags; ///< Number of fragments,
2223
} ADDR_PRT_INFO_INPUT;
2224
2225
/**
2226
****************************************************************************************************
2227
* ADDR_PRT_INFO_OUTPUT
2228
*
2229
* @brief
2230
* Input structure for AddrComputePrtInfo
2231
****************************************************************************************************
2232
*/
2233
typedef struct _ADDR_PRT_INFO_OUTPUT
2234
{
2235
UINT_32 prtTileWidth;
2236
UINT_32 prtTileHeight;
2237
} ADDR_PRT_INFO_OUTPUT;
2238
2239
/**
2240
****************************************************************************************************
2241
* AddrComputePrtInfo
2242
*
2243
* @brief
2244
* Compute prt surface related information
2245
****************************************************************************************************
2246
*/
2247
ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
2248
ADDR_HANDLE hLib,
2249
const ADDR_PRT_INFO_INPUT* pIn,
2250
ADDR_PRT_INFO_OUTPUT* pOut);
2251
2252
2253
2254
////////////////////////////////////////////////////////////////////////////////////////////////////
2255
// DCC key functions
2256
////////////////////////////////////////////////////////////////////////////////////////////////////
2257
2258
/**
2259
****************************************************************************************************
2260
* _ADDR_COMPUTE_DCCINFO_INPUT
2261
*
2262
* @brief
2263
* Input structure of AddrComputeDccInfo
2264
****************************************************************************************************
2265
*/
2266
typedef struct _ADDR_COMPUTE_DCCINFO_INPUT
2267
{
2268
UINT_32 size; ///< Size of this structure in bytes
2269
UINT_32 bpp; ///< BitPP of color surface
2270
UINT_32 numSamples; ///< Sample number of color surface
2271
UINT_64 colorSurfSize; ///< Size of color surface to which dcc key is bound
2272
AddrTileMode tileMode; ///< Tile mode of color surface
2273
ADDR_TILEINFO tileInfo; ///< Tile info of color surface
2274
UINT_32 tileSwizzle; ///< Tile swizzle
2275
INT_32 tileIndex; ///< Tile index of color surface,
2276
///< MUST be -1 if you don't want to use it
2277
///< while the global useTileIndex is set to 1
2278
INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
2279
///< README: When tileIndex is not -1, this must be valid
2280
} ADDR_COMPUTE_DCCINFO_INPUT;
2281
2282
/**
2283
****************************************************************************************************
2284
* ADDR_COMPUTE_DCCINFO_OUTPUT
2285
*
2286
* @brief
2287
* Output structure of AddrComputeDccInfo
2288
****************************************************************************************************
2289
*/
2290
typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT
2291
{
2292
UINT_32 size; ///< Size of this structure in bytes
2293
UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key
2294
UINT_64 dccRamSize; ///< Size of dcc key
2295
UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared
2296
BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable
2297
BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned
2298
} ADDR_COMPUTE_DCCINFO_OUTPUT;
2299
2300
/**
2301
****************************************************************************************************
2302
* AddrComputeDccInfo
2303
*
2304
* @brief
2305
* Compute DCC key size, base alignment
2306
* info
2307
****************************************************************************************************
2308
*/
2309
ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
2310
ADDR_HANDLE hLib,
2311
const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
2312
ADDR_COMPUTE_DCCINFO_OUTPUT* pOut);
2313
2314
2315
2316
/**
2317
****************************************************************************************************
2318
* ADDR_GET_MAX_ALIGNMENTS_OUTPUT
2319
*
2320
* @brief
2321
* Output structure of AddrGetMaxAlignments
2322
****************************************************************************************************
2323
*/
2324
typedef struct ADDR_GET_MAX_ALINGMENTS_OUTPUT
2325
{
2326
UINT_32 size; ///< Size of this structure in bytes
2327
UINT_32 baseAlign; ///< Maximum base alignment in bytes
2328
} ADDR_GET_MAX_ALIGNMENTS_OUTPUT;
2329
2330
/**
2331
****************************************************************************************************
2332
* AddrGetMaxAlignments
2333
*
2334
* @brief
2335
* Gets maximnum alignments
2336
****************************************************************************************************
2337
*/
2338
ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
2339
ADDR_HANDLE hLib,
2340
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut);
2341
2342
/**
2343
****************************************************************************************************
2344
* AddrGetMaxMetaAlignments
2345
*
2346
* @brief
2347
* Gets maximnum alignments for metadata
2348
****************************************************************************************************
2349
*/
2350
ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
2351
ADDR_HANDLE hLib,
2352
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut);
2353
2354
/**
2355
****************************************************************************************************
2356
* Address library interface version 2
2357
* available from Gfx9 hardware
2358
****************************************************************************************************
2359
* Addr2ComputeSurfaceInfo()
2360
* Addr2ComputeSurfaceAddrFromCoord()
2361
* Addr2ComputeSurfaceCoordFromAddr()
2362
2363
* Addr2ComputeHtileInfo()
2364
* Addr2ComputeHtileAddrFromCoord()
2365
* Addr2ComputeHtileCoordFromAddr()
2366
*
2367
* Addr2ComputeCmaskInfo()
2368
* Addr2ComputeCmaskAddrFromCoord()
2369
* Addr2ComputeCmaskCoordFromAddr()
2370
*
2371
* Addr2ComputeFmaskInfo()
2372
* Addr2ComputeFmaskAddrFromCoord()
2373
* Addr2ComputeFmaskCoordFromAddr()
2374
*
2375
* Addr2ComputeDccInfo()
2376
*
2377
**/
2378
2379
2380
////////////////////////////////////////////////////////////////////////////////////////////////////
2381
// Surface functions for Gfx9
2382
////////////////////////////////////////////////////////////////////////////////////////////////////
2383
2384
/**
2385
****************************************************************************************************
2386
* ADDR2_SURFACE_FLAGS
2387
*
2388
* @brief
2389
* Surface flags
2390
****************************************************************************************************
2391
*/
2392
typedef union _ADDR2_SURFACE_FLAGS
2393
{
2394
struct
2395
{
2396
UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV
2397
UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV
2398
UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV
2399
UINT_32 fmask : 1; ///< This is an fmask surface
2400
UINT_32 overlay : 1; ///< This is an overlay surface
2401
UINT_32 display : 1; ///< This resource is displable, can be used with DRV
2402
UINT_32 prt : 1; ///< This is a partially resident texture
2403
UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface
2404
UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding
2405
UINT_32 texture : 1; ///< This resource can be used with SRV
2406
UINT_32 unordered : 1; ///< This resource can be used with UAV
2407
UINT_32 rotated : 1; ///< This resource is rotated and displable
2408
UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible
2409
UINT_32 opt4space : 1; ///< This resource should be optimized for space
2410
UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment
2411
UINT_32 noMetadata : 1; ///< This resource has no metadata
2412
UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata
2413
UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata
2414
UINT_32 view3dAs2dArray : 1; ///< This resource is a 3D resource viewed as 2D array
2415
UINT_32 reserved : 13; ///< Reserved bits
2416
};
2417
2418
UINT_32 value;
2419
} ADDR2_SURFACE_FLAGS;
2420
2421
/**
2422
****************************************************************************************************
2423
* ADDR2_COMPUTE_SURFACE_INFO_INPUT
2424
*
2425
* @brief
2426
* Input structure for Addr2ComputeSurfaceInfo
2427
****************************************************************************************************
2428
*/
2429
typedef struct _ADDR2_COMPUTE_SURFACE_INFO_INPUT
2430
{
2431
UINT_32 size; ///< Size of this structure in bytes
2432
2433
ADDR2_SURFACE_FLAGS flags; ///< Surface flags
2434
AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9
2435
AddrResourceType resourceType; ///< Surface type
2436
AddrFormat format; ///< Surface format
2437
UINT_32 bpp; ///< bits per pixel
2438
UINT_32 width; ///< Width (of mip0), in pixels
2439
UINT_32 height; ///< Height (of mip0), in pixels
2440
UINT_32 numSlices; ///< Number surface slice/depth (of mip0),
2441
UINT_32 numMipLevels; ///< Total mipmap levels.
2442
UINT_32 numSamples; ///< Number of samples
2443
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
2444
/// number of samples for normal AA; Set it to the
2445
/// number of fragments for EQAA
2446
UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)
2447
UINT_32 sliceAlign; ///< Required slice size in bytes
2448
} ADDR2_COMPUTE_SURFACE_INFO_INPUT;
2449
2450
/**
2451
****************************************************************************************************
2452
* ADDR2_MIP_INFO
2453
*
2454
* @brief
2455
* Structure that contains information for mip level
2456
*
2457
****************************************************************************************************
2458
*/
2459
typedef struct _ADDR2_MIP_INFO
2460
{
2461
UINT_32 pitch; ///< Pitch in elements
2462
UINT_32 height; ///< Padded height in elements
2463
UINT_32 depth; ///< Padded depth
2464
UINT_32 pixelPitch; ///< Pitch in pixels
2465
UINT_32 pixelHeight; ///< Padded height in pixels
2466
UINT_32 equationIndex; ///< Equation index in the equation table
2467
UINT_64 offset; ///< Offset in bytes from mip base, should only be used
2468
///< to setup vam surface descriptor, can't be used
2469
///< to setup swizzle pattern
2470
UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base
2471
UINT_32 mipTailOffset; ///< mip tail offset in bytes
2472
UINT_32 mipTailCoordX; ///< mip tail coord x
2473
UINT_32 mipTailCoordY; ///< mip tail coord y
2474
UINT_32 mipTailCoordZ; ///< mip tail coord z
2475
} ADDR2_MIP_INFO;
2476
2477
/**
2478
****************************************************************************************************
2479
* ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
2480
*
2481
* @brief
2482
* Output structure for Addr2ComputeSurfInfo
2483
* @note
2484
Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch
2485
Pixel: Original pixel
2486
****************************************************************************************************
2487
*/
2488
typedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
2489
{
2490
UINT_32 size; ///< Size of this structure in bytes
2491
2492
UINT_32 pitch; ///< Pitch in elements (blocks for compressed formats)
2493
UINT_32 height; ///< Padded height (of mip0) in elements
2494
UINT_32 numSlices; ///< Padded depth for 3d resource
2495
///< or padded number of slices for 2d array resource
2496
UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements
2497
UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements
2498
UINT_32 mipChainSlice; ///< Padded depth (of total mip chain)
2499
UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes
2500
UINT_64 surfSize; ///< Surface (total mip chain) size in bytes
2501
UINT_32 baseAlign; ///< Base address alignment
2502
UINT_32 bpp; ///< Bits per elements
2503
/// (e.g. blocks for BCn, 1/3 for 96bit)
2504
UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels
2505
UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels
2506
UINT_32 pixelPitch; ///< Pitch in original pixels
2507
UINT_32 pixelHeight; ///< Height in original pixels
2508
UINT_32 pixelBits; ///< Original bits per pixel, passed from input
2509
2510
UINT_32 blockWidth; ///< Width in element inside one block
2511
UINT_32 blockHeight; ///< Height in element inside one block
2512
UINT_32 blockSlices; ///< Slice number inside one block
2513
///< Prt tile is one block, its width/height/slice
2514
///< equals to blcok width/height/slice
2515
2516
BOOL_32 epitchIsHeight; ///< Whether to use height to program epitch register
2517
/// Stereo info
2518
ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE
2519
/// Mip info
2520
ADDR2_MIP_INFO* pMipInfo; ///< Pointer to mip information array
2521
/// if it is not NULL, the array is assumed to
2522
/// contain numMipLevels entries
2523
2524
UINT_32 equationIndex; ///< Equation index in the equation table of mip0
2525
BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block
2526
UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip
2527
/// in tail, it will be set to number of mip levels
2528
} ADDR2_COMPUTE_SURFACE_INFO_OUTPUT;
2529
2530
/**
2531
****************************************************************************************************
2532
* Addr2ComputeSurfaceInfo
2533
*
2534
* @brief
2535
* Compute surface width/height/slices/alignments and suitable tiling mode
2536
****************************************************************************************************
2537
*/
2538
ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo(
2539
ADDR_HANDLE hLib,
2540
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
2541
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut);
2542
2543
2544
2545
/**
2546
****************************************************************************************************
2547
* ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
2548
*
2549
* @brief
2550
* Input structure for Addr2ComputeSurfaceAddrFromCoord
2551
****************************************************************************************************
2552
*/
2553
typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
2554
{
2555
UINT_32 size; ///< Size of this structure in bytes
2556
2557
UINT_32 x; ///< X coordinate
2558
UINT_32 y; ///< Y coordinate
2559
UINT_32 slice; ///< Slice index
2560
UINT_32 sample; ///< Sample index, use fragment index for EQAA
2561
UINT_32 mipId; ///< the mip ID in mip chain
2562
2563
AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9
2564
ADDR2_SURFACE_FLAGS flags; ///< Surface flags
2565
AddrResourceType resourceType; ///< Surface type
2566
UINT_32 bpp; ///< Bits per pixel
2567
UINT_32 unalignedWidth; ///< Surface original width (of mip0)
2568
UINT_32 unalignedHeight; ///< Surface original height (of mip0)
2569
UINT_32 numSlices; ///< Surface original slices (of mip0)
2570
UINT_32 numMipLevels; ///< Total mipmap levels
2571
UINT_32 numSamples; ///< Number of samples
2572
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
2573
/// number of samples for normal AA; Set it to the
2574
/// number of fragments for EQAA
2575
2576
UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation
2577
UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)
2578
} ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
2579
2580
/**
2581
****************************************************************************************************
2582
* ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
2583
*
2584
* @brief
2585
* Output structure for Addr2ComputeSurfaceAddrFromCoord
2586
****************************************************************************************************
2587
*/
2588
typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
2589
{
2590
UINT_32 size; ///< Size of this structure in bytes
2591
2592
UINT_64 addr; ///< Byte address
2593
UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7.
2594
/// For surface bpp < 8, e.g. FMT_1.
2595
UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block)
2596
} ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT;
2597
2598
/**
2599
****************************************************************************************************
2600
* Addr2ComputeSurfaceAddrFromCoord
2601
*
2602
* @brief
2603
* Compute surface address from a given coordinate.
2604
****************************************************************************************************
2605
*/
2606
ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord(
2607
ADDR_HANDLE hLib,
2608
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
2609
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);
2610
2611
2612
2613
/**
2614
****************************************************************************************************
2615
* ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
2616
*
2617
* @brief
2618
* Input structure for Addr2ComputeSurfaceCoordFromAddr
2619
****************************************************************************************************
2620
*/
2621
typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
2622
{
2623
UINT_32 size; ///< Size of this structure in bytes
2624
2625
UINT_64 addr; ///< Address in bytes
2626
UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8,
2627
/// e.g. FMT_1;
2628
2629
AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9
2630
ADDR2_SURFACE_FLAGS flags; ///< Surface flags
2631
AddrResourceType resourceType; ///< Surface type
2632
UINT_32 bpp; ///< Bits per pixel
2633
UINT_32 unalignedWidth; ///< Surface original width (of mip0)
2634
UINT_32 unalignedHeight; ///< Surface original height (of mip0)
2635
UINT_32 numSlices; ///< Surface original slices (of mip0)
2636
UINT_32 numMipLevels; ///< Total mipmap levels.
2637
UINT_32 numSamples; ///< Number of samples
2638
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
2639
/// number of samples for normal AA; Set it to the
2640
/// number of fragments for EQAA
2641
2642
UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation
2643
UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)
2644
} ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT;
2645
2646
/**
2647
****************************************************************************************************
2648
* ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
2649
*
2650
* @brief
2651
* Output structure for Addr2ComputeSurfaceCoordFromAddr
2652
****************************************************************************************************
2653
*/
2654
typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
2655
{
2656
UINT_32 size; ///< Size of this structure in bytes
2657
2658
UINT_32 x; ///< X coordinate
2659
UINT_32 y; ///< Y coordinate
2660
UINT_32 slice; ///< Index of slices
2661
UINT_32 sample; ///< Index of samples, means fragment index for EQAA
2662
UINT_32 mipId; ///< mipmap level id
2663
} ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT;
2664
2665
/**
2666
****************************************************************************************************
2667
* Addr2ComputeSurfaceCoordFromAddr
2668
*
2669
* @brief
2670
* Compute coordinate from a given surface address
2671
****************************************************************************************************
2672
*/
2673
ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr(
2674
ADDR_HANDLE hLib,
2675
const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
2676
ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut);
2677
2678
2679
2680
////////////////////////////////////////////////////////////////////////////////////////////////////
2681
// HTile functions for Gfx9
2682
////////////////////////////////////////////////////////////////////////////////////////////////////
2683
2684
/**
2685
****************************************************************************************************
2686
* ADDR2_META_FLAGS
2687
*
2688
* @brief
2689
* Metadata flags
2690
****************************************************************************************************
2691
*/
2692
typedef union _ADDR2_META_FLAGS
2693
{
2694
struct
2695
{
2696
UINT_32 pipeAligned : 1; ///< if Metadata being pipe aligned
2697
UINT_32 rbAligned : 1; ///< if Metadata being RB aligned
2698
UINT_32 linear : 1; ///< if Metadata linear, GFX9 does not suppord this!
2699
UINT_32 reserved : 29; ///< Reserved bits
2700
};
2701
2702
UINT_32 value;
2703
} ADDR2_META_FLAGS;
2704
2705
/**
2706
****************************************************************************************************
2707
* ADDR2_META_MIP_INFO
2708
*
2709
* @brief
2710
* Structure to store per mip metadata information
2711
****************************************************************************************************
2712
*/
2713
typedef struct _ADDR2_META_MIP_INFO
2714
{
2715
BOOL_32 inMiptail;
2716
union
2717
{
2718
struct
2719
{
2720
UINT_32 startX;
2721
UINT_32 startY;
2722
UINT_32 startZ;
2723
UINT_32 width;
2724
UINT_32 height;
2725
UINT_32 depth;
2726
};
2727
2728
// GFX10
2729
struct
2730
{
2731
UINT_32 offset; ///< Metadata offset within one slice,
2732
/// the thickness of a slice is meta block depth.
2733
UINT_32 sliceSize; ///< Metadata size within one slice,
2734
/// the thickness of a slice is meta block depth.
2735
};
2736
};
2737
} ADDR2_META_MIP_INFO;
2738
2739
/**
2740
****************************************************************************************************
2741
* ADDR2_COMPUTE_HTILE_INFO_INPUT
2742
*
2743
* @brief
2744
* Input structure of Addr2ComputeHtileInfo
2745
****************************************************************************************************
2746
*/
2747
typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT
2748
{
2749
UINT_32 size; ///< Size of this structure in bytes
2750
2751
ADDR2_META_FLAGS hTileFlags; ///< HTILE flags
2752
ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags
2753
AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode
2754
UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)
2755
UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
2756
UINT_32 numSlices; ///< Number of slices of depth surface (of mip0)
2757
UINT_32 numMipLevels; ///< Total mipmap levels of color surface
2758
UINT_32 firstMipIdInTail; /// Id of the first mip in tail,
2759
/// if no mip is in tail, it should be set to
2760
/// number of mip levels
2761
/// Only for GFX10
2762
} ADDR2_COMPUTE_HTILE_INFO_INPUT;
2763
2764
/**
2765
****************************************************************************************************
2766
* ADDR2_COMPUTE_HTILE_INFO_OUTPUT
2767
*
2768
* @brief
2769
* Output structure of Addr2ComputeHtileInfo
2770
****************************************************************************************************
2771
*/
2772
typedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT
2773
{
2774
UINT_32 size; ///< Size of this structure in bytes
2775
2776
UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this
2777
/// HTile buffer. This might be larger than original depth
2778
/// buffer pitch when called with an unaligned pitch.
2779
UINT_32 height; ///< Height in pixels, as above
2780
UINT_32 baseAlign; ///< Base alignment
2781
UINT_32 sliceSize; ///< Slice size, in bytes.
2782
UINT_32 htileBytes; ///< Size of HTILE buffer, in bytes
2783
UINT_32 metaBlkWidth; ///< Meta block width
2784
UINT_32 metaBlkHeight; ///< Meta block height
2785
UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
2786
2787
ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information
2788
2789
struct {
2790
UINT_16* gfx10_bits; /* 72 2-byte elements */
2791
} equation;
2792
} ADDR2_COMPUTE_HTILE_INFO_OUTPUT;
2793
2794
/**
2795
****************************************************************************************************
2796
* Addr2ComputeHtileInfo
2797
*
2798
* @brief
2799
* Compute Htile pitch, height, base alignment and size in bytes
2800
****************************************************************************************************
2801
*/
2802
ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo(
2803
ADDR_HANDLE hLib,
2804
const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
2805
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut);
2806
2807
2808
2809
/**
2810
****************************************************************************************************
2811
* ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
2812
*
2813
* @brief
2814
* Input structure for Addr2ComputeHtileAddrFromCoord
2815
****************************************************************************************************
2816
*/
2817
typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
2818
{
2819
UINT_32 size; ///< Size of this structure in bytes
2820
2821
UINT_32 x; ///< X coordinate
2822
UINT_32 y; ///< Y coordinate
2823
UINT_32 slice; ///< Index of slices
2824
UINT_32 mipId; ///< mipmap level id
2825
2826
ADDR2_META_FLAGS hTileFlags; ///< HTILE flags
2827
ADDR2_SURFACE_FLAGS depthflags; ///< Depth surface flags
2828
AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode
2829
UINT_32 bpp; ///< Depth surface bits per pixel
2830
UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)
2831
UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
2832
UINT_32 numSlices; ///< Depth surface original depth (of mip0)
2833
UINT_32 numMipLevels; ///< Depth surface total mipmap levels
2834
UINT_32 numSamples; ///< Depth surface number of samples
2835
UINT_32 pipeXor; ///< Pipe xor setting
2836
} ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;
2837
2838
/**
2839
****************************************************************************************************
2840
* ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
2841
*
2842
* @brief
2843
* Output structure for Addr2ComputeHtileAddrFromCoord
2844
****************************************************************************************************
2845
*/
2846
typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
2847
{
2848
UINT_32 size; ///< Size of this structure in bytes
2849
2850
UINT_64 addr; ///< Address in bytes
2851
} ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT;
2852
2853
/**
2854
****************************************************************************************************
2855
* Addr2ComputeHtileAddrFromCoord
2856
*
2857
* @brief
2858
* Compute Htile address according to coordinates (of depth buffer)
2859
****************************************************************************************************
2860
*/
2861
ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord(
2862
ADDR_HANDLE hLib,
2863
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
2864
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
2865
2866
2867
2868
/**
2869
****************************************************************************************************
2870
* ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
2871
*
2872
* @brief
2873
* Input structure for Addr2ComputeHtileCoordFromAddr
2874
****************************************************************************************************
2875
*/
2876
typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
2877
{
2878
UINT_32 size; ///< Size of this structure in bytes
2879
2880
UINT_64 addr; ///< Address
2881
2882
ADDR2_META_FLAGS hTileFlags; ///< HTILE flags
2883
ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags
2884
AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode
2885
UINT_32 bpp; ///< Depth surface bits per pixel
2886
UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)
2887
UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
2888
UINT_32 numSlices; ///< Depth surface original depth (of mip0)
2889
UINT_32 numMipLevels; ///< Depth surface total mipmap levels
2890
UINT_32 numSamples; ///< Depth surface number of samples
2891
UINT_32 pipeXor; ///< Pipe xor setting
2892
} ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT;
2893
2894
/**
2895
****************************************************************************************************
2896
* ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
2897
*
2898
* @brief
2899
* Output structure for Addr2ComputeHtileCoordFromAddr
2900
****************************************************************************************************
2901
*/
2902
typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
2903
{
2904
UINT_32 size; ///< Size of this structure in bytes
2905
2906
UINT_32 x; ///< X coordinate
2907
UINT_32 y; ///< Y coordinate
2908
UINT_32 slice; ///< Index of slices
2909
UINT_32 mipId; ///< mipmap level id
2910
} ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT;
2911
2912
/**
2913
****************************************************************************************************
2914
* Addr2ComputeHtileCoordFromAddr
2915
*
2916
* @brief
2917
* Compute coordinates within depth buffer (1st pixel of a micro tile) according to
2918
* Htile address
2919
****************************************************************************************************
2920
*/
2921
ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr(
2922
ADDR_HANDLE hLib,
2923
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
2924
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
2925
2926
2927
2928
////////////////////////////////////////////////////////////////////////////////////////////////////
2929
// C-mask functions for Gfx9
2930
////////////////////////////////////////////////////////////////////////////////////////////////////
2931
2932
/**
2933
****************************************************************************************************
2934
* ADDR2_COMPUTE_CMASK_INFO_INPUT
2935
*
2936
* @brief
2937
* Input structure of Addr2ComputeCmaskInfo
2938
****************************************************************************************************
2939
*/
2940
typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT
2941
{
2942
UINT_32 size; ///< Size of this structure in bytes
2943
2944
ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
2945
ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
2946
AddrResourceType resourceType; ///< Color surface type
2947
AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
2948
UINT_32 unalignedWidth; ///< Color surface original width
2949
UINT_32 unalignedHeight; ///< Color surface original height
2950
UINT_32 numSlices; ///< Number of slices of color buffer
2951
UINT_32 numMipLevels; ///< Number of mip levels
2952
UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,
2953
/// it should be number of mip levels
2954
/// Only for GFX10
2955
} ADDR2_COMPUTE_CMASK_INFO_INPUT;
2956
2957
/**
2958
****************************************************************************************************
2959
* ADDR2_COMPUTE_CMASK_INFO_OUTPUT
2960
*
2961
* @brief
2962
* Output structure of Addr2ComputeCmaskInfo
2963
****************************************************************************************************
2964
*/
2965
typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT
2966
{
2967
UINT_32 size; ///< Size of this structure in bytes
2968
2969
UINT_32 pitch; ///< Pitch in pixels of color buffer which
2970
/// this Cmask matches. The size might be larger than
2971
/// original color buffer pitch when called with
2972
/// an unaligned pitch.
2973
UINT_32 height; ///< Height in pixels, as above
2974
UINT_32 baseAlign; ///< Base alignment
2975
UINT_32 sliceSize; ///< Slice size, in bytes.
2976
UINT_32 cmaskBytes; ///< Size in bytes of CMask buffer
2977
UINT_32 metaBlkWidth; ///< Meta block width
2978
UINT_32 metaBlkHeight; ///< Meta block height
2979
2980
UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
2981
2982
ADDR2_META_MIP_INFO* pMipInfo; ///< CMASK mip information
2983
} ADDR2_COMPUTE_CMASK_INFO_OUTPUT;
2984
2985
/**
2986
****************************************************************************************************
2987
* Addr2ComputeCmaskInfo
2988
*
2989
* @brief
2990
* Compute Cmask pitch, height, base alignment and size in bytes from color buffer
2991
* info
2992
****************************************************************************************************
2993
*/
2994
ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo(
2995
ADDR_HANDLE hLib,
2996
const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
2997
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut);
2998
2999
3000
3001
/**
3002
****************************************************************************************************
3003
* ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
3004
*
3005
* @brief
3006
* Input structure for Addr2ComputeCmaskAddrFromCoord
3007
*
3008
****************************************************************************************************
3009
*/
3010
typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
3011
{
3012
UINT_32 size; ///< Size of this structure in bytes
3013
3014
UINT_32 x; ///< X coordinate
3015
UINT_32 y; ///< Y coordinate
3016
UINT_32 slice; ///< Index of slices
3017
3018
ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
3019
ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
3020
AddrResourceType resourceType; ///< Color surface type
3021
AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3022
3023
UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
3024
UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
3025
UINT_32 numSlices; ///< Color surface original slices (of mip0)
3026
3027
UINT_32 numSamples; ///< Color surfae sample number
3028
UINT_32 numFrags; ///< Color surface fragment number
3029
3030
UINT_32 pipeXor; ///< pipe Xor setting
3031
} ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT;
3032
3033
/**
3034
****************************************************************************************************
3035
* ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
3036
*
3037
* @brief
3038
* Output structure for Addr2ComputeCmaskAddrFromCoord
3039
****************************************************************************************************
3040
*/
3041
typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
3042
{
3043
UINT_32 size; ///< Size of this structure in bytes
3044
3045
UINT_64 addr; ///< CMASK address in bytes
3046
UINT_32 bitPosition; ///< Bit position within addr, 0 or 4
3047
} ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT;
3048
3049
/**
3050
****************************************************************************************************
3051
* Addr2ComputeCmaskAddrFromCoord
3052
*
3053
* @brief
3054
* Compute Cmask address according to coordinates (of MSAA color buffer)
3055
****************************************************************************************************
3056
*/
3057
ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord(
3058
ADDR_HANDLE hLib,
3059
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
3060
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
3061
3062
3063
3064
/**
3065
****************************************************************************************************
3066
* ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
3067
*
3068
* @brief
3069
* Input structure for Addr2ComputeCmaskCoordFromAddr
3070
****************************************************************************************************
3071
*/
3072
typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
3073
{
3074
UINT_32 size; ///< Size of this structure in bytes
3075
3076
UINT_64 addr; ///< CMASK address in bytes
3077
UINT_32 bitPosition; ///< Bit position within addr, 0 or 4
3078
3079
ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
3080
ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
3081
AddrResourceType resourceType; ///< Color surface type
3082
AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3083
3084
UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
3085
UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
3086
UINT_32 numSlices; ///< Color surface original slices (of mip0)
3087
UINT_32 numMipLevels; ///< Color surface total mipmap levels.
3088
} ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT;
3089
3090
/**
3091
****************************************************************************************************
3092
* ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
3093
*
3094
* @brief
3095
* Output structure for Addr2ComputeCmaskCoordFromAddr
3096
****************************************************************************************************
3097
*/
3098
typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
3099
{
3100
UINT_32 size; ///< Size of this structure in bytes
3101
3102
UINT_32 x; ///< X coordinate
3103
UINT_32 y; ///< Y coordinate
3104
UINT_32 slice; ///< Index of slices
3105
UINT_32 mipId; ///< mipmap level id
3106
} ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT;
3107
3108
/**
3109
****************************************************************************************************
3110
* Addr2ComputeCmaskCoordFromAddr
3111
*
3112
* @brief
3113
* Compute coordinates within color buffer (1st pixel of a micro tile) according to
3114
* Cmask address
3115
****************************************************************************************************
3116
*/
3117
ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr(
3118
ADDR_HANDLE hLib,
3119
const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
3120
ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);
3121
3122
3123
3124
////////////////////////////////////////////////////////////////////////////////////////////////////
3125
// F-mask functions for Gfx9
3126
////////////////////////////////////////////////////////////////////////////////////////////////////
3127
3128
/**
3129
****************************************************************************************************
3130
* ADDR2_FMASK_FLAGS
3131
*
3132
* @brief
3133
* FMASK flags
3134
****************************************************************************************************
3135
*/
3136
typedef union _ADDR2_FMASK_FLAGS
3137
{
3138
struct
3139
{
3140
UINT_32 resolved : 1; ///< TRUE if this is a resolved fmask, used by H/W clients
3141
/// by H/W clients. S/W should always set it to FALSE.
3142
UINT_32 reserved : 31; ///< Reserved for future use.
3143
};
3144
3145
UINT_32 value;
3146
} ADDR2_FMASK_FLAGS;
3147
3148
/**
3149
****************************************************************************************************
3150
* ADDR2_COMPUTE_FMASK_INFO_INPUT
3151
*
3152
* @brief
3153
* Input structure for Addr2ComputeFmaskInfo
3154
****************************************************************************************************
3155
*/
3156
typedef struct _ADDR2_COMPUTE_FMASK_INFO_INPUT
3157
{
3158
UINT_32 size; ///< Size of this structure in bytes
3159
3160
AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3161
UINT_32 unalignedWidth; ///< Color surface original width
3162
UINT_32 unalignedHeight; ///< Color surface original height
3163
UINT_32 numSlices; ///< Number of slices/depth
3164
UINT_32 numSamples; ///< Number of samples
3165
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3166
/// number of samples for normal AA; Set it to the
3167
/// number of fragments for EQAA
3168
ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
3169
} ADDR2_COMPUTE_FMASK_INFO_INPUT;
3170
3171
/**
3172
****************************************************************************************************
3173
* ADDR2_COMPUTE_FMASK_INFO_OUTPUT
3174
*
3175
* @brief
3176
* Output structure for Addr2ComputeFmaskInfo
3177
****************************************************************************************************
3178
*/
3179
typedef struct _ADDR2_COMPUTE_FMASK_INFO_OUTPUT
3180
{
3181
UINT_32 size; ///< Size of this structure in bytes
3182
3183
UINT_32 pitch; ///< Pitch of fmask in pixels
3184
UINT_32 height; ///< Height of fmask in pixels
3185
UINT_32 baseAlign; ///< Base alignment
3186
UINT_32 numSlices; ///< Slices of fmask
3187
UINT_32 fmaskBytes; ///< Size of fmask in bytes
3188
UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes
3189
UINT_32 numSamples; ///< Number of samples
3190
UINT_32 sliceSize; ///< Size of slice in bytes
3191
} ADDR2_COMPUTE_FMASK_INFO_OUTPUT;
3192
3193
/**
3194
****************************************************************************************************
3195
* Addr2ComputeFmaskInfo
3196
*
3197
* @brief
3198
* Compute Fmask pitch/height/slices/alignments and size in bytes
3199
****************************************************************************************************
3200
*/
3201
ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo(
3202
ADDR_HANDLE hLib,
3203
const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn,
3204
ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut);
3205
3206
3207
3208
/**
3209
****************************************************************************************************
3210
* ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
3211
*
3212
* @brief
3213
* Input structure for Addr2ComputeFmaskAddrFromCoord
3214
****************************************************************************************************
3215
*/
3216
typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
3217
{
3218
UINT_32 size; ///< Size of this structure in bytes
3219
3220
AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3221
UINT_32 x; ///< X coordinate
3222
UINT_32 y; ///< Y coordinate
3223
UINT_32 slice; ///< Slice index
3224
UINT_32 sample; ///< Sample index (fragment index for EQAA)
3225
UINT_32 plane; ///< Plane number
3226
3227
UINT_32 unalignedWidth; ///< Color surface original width
3228
UINT_32 unalignedHeight; ///< Color surface original height
3229
UINT_32 numSamples; ///< Number of samples
3230
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3231
/// number of samples for normal AA; Set it to the
3232
/// number of fragments for EQAA
3233
UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation
3234
3235
ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
3236
} ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT;
3237
3238
/**
3239
****************************************************************************************************
3240
* ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
3241
*
3242
* @brief
3243
* Output structure for Addr2ComputeFmaskAddrFromCoord
3244
****************************************************************************************************
3245
*/
3246
typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
3247
{
3248
UINT_32 size; ///< Size of this structure in bytes
3249
3250
UINT_64 addr; ///< Fmask address
3251
UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7.
3252
} ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT;
3253
3254
/**
3255
****************************************************************************************************
3256
* Addr2ComputeFmaskAddrFromCoord
3257
*
3258
* @brief
3259
* Compute Fmask address according to coordinates (x,y,slice,sample,plane)
3260
****************************************************************************************************
3261
*/
3262
ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord(
3263
ADDR_HANDLE hLib,
3264
const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
3265
ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);
3266
3267
3268
3269
/**
3270
****************************************************************************************************
3271
* ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
3272
*
3273
* @brief
3274
* Input structure for Addr2ComputeFmaskCoordFromAddr
3275
****************************************************************************************************
3276
*/
3277
typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
3278
{
3279
UINT_32 size; ///< Size of this structure in bytes
3280
3281
UINT_64 addr; ///< Address
3282
UINT_32 bitPosition; ///< Bit position within addr, 0-7.
3283
AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3284
3285
UINT_32 unalignedWidth; ///< Color surface original width
3286
UINT_32 unalignedHeight; ///< Color surface original height
3287
UINT_32 numSamples; ///< Number of samples
3288
UINT_32 numFrags; ///< Number of fragments
3289
3290
UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation
3291
3292
ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
3293
} ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT;
3294
3295
/**
3296
****************************************************************************************************
3297
* ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
3298
*
3299
* @brief
3300
* Output structure for Addr2ComputeFmaskCoordFromAddr
3301
****************************************************************************************************
3302
*/
3303
typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
3304
{
3305
UINT_32 size; ///< Size of this structure in bytes
3306
3307
UINT_32 x; ///< X coordinate
3308
UINT_32 y; ///< Y coordinate
3309
UINT_32 slice; ///< Slice index
3310
UINT_32 sample; ///< Sample index (fragment index for EQAA)
3311
UINT_32 plane; ///< Plane number
3312
} ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT;
3313
3314
/**
3315
****************************************************************************************************
3316
* Addr2ComputeFmaskCoordFromAddr
3317
*
3318
* @brief
3319
* Compute FMASK coordinate from an given address
3320
****************************************************************************************************
3321
*/
3322
ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr(
3323
ADDR_HANDLE hLib,
3324
const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
3325
ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);
3326
3327
3328
3329
////////////////////////////////////////////////////////////////////////////////////////////////////
3330
// DCC key functions for Gfx9
3331
////////////////////////////////////////////////////////////////////////////////////////////////////
3332
3333
/**
3334
****************************************************************************************************
3335
* _ADDR2_COMPUTE_DCCINFO_INPUT
3336
*
3337
* @brief
3338
* Input structure of Addr2ComputeDccInfo
3339
****************************************************************************************************
3340
*/
3341
typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT
3342
{
3343
UINT_32 size; ///< Size of this structure in bytes
3344
3345
ADDR2_META_FLAGS dccKeyFlags; ///< DCC key flags
3346
ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
3347
AddrResourceType resourceType; ///< Color surface type
3348
AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode
3349
UINT_32 bpp; ///< bits per pixel
3350
UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
3351
UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
3352
UINT_32 numSlices; ///< Number of slices, of color surface (of mip0)
3353
UINT_32 numFrags; ///< Fragment number of color surface
3354
UINT_32 numMipLevels; ///< Total mipmap levels of color surface
3355
UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels
3356
///< useful in meta linear case
3357
UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,
3358
/// it should be number of mip levels
3359
/// Only for GFX10
3360
} ADDR2_COMPUTE_DCCINFO_INPUT;
3361
3362
/**
3363
****************************************************************************************************
3364
* ADDR2_COMPUTE_DCCINFO_OUTPUT
3365
*
3366
* @brief
3367
* Output structure of Addr2ComputeDccInfo
3368
****************************************************************************************************
3369
*/
3370
typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT
3371
{
3372
UINT_32 size; ///< Size of this structure in bytes
3373
3374
UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key
3375
UINT_32 dccRamSize; ///< Size of dcc key
3376
3377
UINT_32 pitch; ///< DCC surface mip chain pitch
3378
UINT_32 height; ///< DCC surface mip chain height
3379
UINT_32 depth; ///< DCC surface mip chain depth
3380
3381
UINT_32 compressBlkWidth; ///< DCC compress block width
3382
UINT_32 compressBlkHeight; ///< DCC compress block height
3383
UINT_32 compressBlkDepth; ///< DCC compress block depth
3384
3385
UINT_32 metaBlkWidth; ///< DCC meta block width
3386
UINT_32 metaBlkHeight; ///< DCC meta block height
3387
UINT_32 metaBlkDepth; ///< DCC meta block depth
3388
UINT_32 metaBlkSize; ///< DCC meta block size in bytes
3389
UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
3390
3391
union
3392
{
3393
UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared
3394
UINT_32 dccRamSliceSize; ///< DCC ram size per slice. For mipmap, it's
3395
/// the slize size of a mip chain, the thickness of a
3396
/// a slice is meta block depth
3397
/// Only for GFX10
3398
};
3399
3400
ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information
3401
3402
/* The equation for doing DCC address computations in shaders. */
3403
union {
3404
/* This is chip-specific, and it varies with:
3405
* - resource type
3406
* - swizzle_mode
3407
* - bpp
3408
* - number of fragments
3409
* - pipe_aligned
3410
* - rb_aligned
3411
*/
3412
struct {
3413
UINT_8 num_bits;
3414
3415
struct {
3416
struct {
3417
UINT_8 dim; /* 0..4 as index, 5 means invalid */
3418
UINT_8 ord; /* 0..31 */
3419
} coord[8]; /* 0..num_coords */
3420
} bit[32]; /* 0..num_bits */
3421
UINT_8 numPipeBits;
3422
} gfx9;
3423
3424
/* This is chip-specific, it requires 64KB_R_X, and it varies with:
3425
* - bpp
3426
* - pipe_aligned
3427
*/
3428
UINT_16 *gfx10_bits; /* 68 2-byte elements */
3429
} equation;
3430
} ADDR2_COMPUTE_DCCINFO_OUTPUT;
3431
3432
/**
3433
****************************************************************************************************
3434
* Addr2ComputeDccInfo
3435
*
3436
* @brief
3437
* Compute DCC key size, base alignment
3438
* info
3439
****************************************************************************************************
3440
*/
3441
ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo(
3442
ADDR_HANDLE hLib,
3443
const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
3444
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut);
3445
3446
3447
/**
3448
****************************************************************************************************
3449
* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
3450
*
3451
* @brief
3452
* Input structure for Addr2ComputeDccAddrFromCoord
3453
*
3454
****************************************************************************************************
3455
*/
3456
typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
3457
{
3458
UINT_32 size; ///< Size of this structure in bytes
3459
3460
UINT_32 x; ///< X coordinate
3461
UINT_32 y; ///< Y coordinate
3462
UINT_32 slice; ///< Index of slices
3463
UINT_32 sample; ///< Index of samples, means fragment index for EQAA
3464
UINT_32 mipId; ///< mipmap level id
3465
3466
ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags
3467
ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
3468
AddrResourceType resourceType; ///< Color surface type
3469
AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode
3470
UINT_32 bpp; ///< Color surface bits per pixel
3471
UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
3472
UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
3473
UINT_32 numSlices; ///< Color surface original slices (of mip0)
3474
UINT_32 numMipLevels; ///< Color surface mipmap levels
3475
UINT_32 numFrags; ///< Color surface fragment number
3476
3477
UINT_32 pipeXor; ///< pipe Xor setting
3478
UINT_32 pitch; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::pitch
3479
UINT_32 height; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::height
3480
UINT_32 compressBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkWidth
3481
UINT_32 compressBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkHeight
3482
UINT_32 compressBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkDepth
3483
UINT_32 metaBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkWidth
3484
UINT_32 metaBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkHeight
3485
UINT_32 metaBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkDepth
3486
UINT_32 dccRamSliceSize; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::dccRamSliceSize
3487
} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT;
3488
3489
/**
3490
****************************************************************************************************
3491
* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
3492
*
3493
* @brief
3494
* Output structure for Addr2ComputeDccAddrFromCoord
3495
****************************************************************************************************
3496
*/
3497
typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
3498
{
3499
UINT_32 size; ///< Size of this structure in bytes
3500
3501
UINT_64 addr; ///< DCC address in bytes
3502
} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT;
3503
3504
/**
3505
****************************************************************************************************
3506
* Addr2ComputeDccAddrFromCoord
3507
*
3508
* @brief
3509
* Compute DCC address according to coordinates (of MSAA color buffer)
3510
****************************************************************************************************
3511
*/
3512
ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord(
3513
ADDR_HANDLE hLib,
3514
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
3515
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
3516
3517
////////////////////////////////////////////////////////////////////////////////////////////////////
3518
// Misc functions for Gfx9
3519
////////////////////////////////////////////////////////////////////////////////////////////////////
3520
3521
/**
3522
****************************************************************************************************
3523
* ADDR2_COMPUTE_PIPEBANKXOR_INPUT
3524
*
3525
* @brief
3526
* Input structure of Addr2ComputePipebankXor
3527
****************************************************************************************************
3528
*/
3529
typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT
3530
{
3531
UINT_32 size; ///< Size of this structure in bytes
3532
UINT_32 surfIndex; ///< Input surface index
3533
ADDR2_SURFACE_FLAGS flags; ///< Surface flag
3534
AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
3535
AddrResourceType resourceType; ///< Surface resource type
3536
AddrFormat format; ///< Surface format
3537
UINT_32 numSamples; ///< Number of samples
3538
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3539
/// number of samples for normal AA; Set it to the
3540
/// number of fragments for EQAA
3541
} ADDR2_COMPUTE_PIPEBANKXOR_INPUT;
3542
3543
/**
3544
****************************************************************************************************
3545
* ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
3546
*
3547
* @brief
3548
* Output structure of Addr2ComputePipebankXor
3549
****************************************************************************************************
3550
*/
3551
typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
3552
{
3553
UINT_32 size; ///< Size of this structure in bytes
3554
UINT_32 pipeBankXor; ///< Pipe bank xor
3555
} ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT;
3556
3557
/**
3558
****************************************************************************************************
3559
* Addr2ComputePipeBankXor
3560
*
3561
* @brief
3562
* Calculate a valid bank pipe xor value for client to use.
3563
****************************************************************************************************
3564
*/
3565
ADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor(
3566
ADDR_HANDLE hLib,
3567
const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
3568
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut);
3569
3570
/**
3571
****************************************************************************************************
3572
* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
3573
*
3574
* @brief
3575
* Input structure of Addr2ComputeSlicePipeBankXor
3576
****************************************************************************************************
3577
*/
3578
typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
3579
{
3580
UINT_32 size; ///< Size of this structure in bytes
3581
AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
3582
AddrResourceType resourceType; ///< Surface resource type
3583
UINT_32 bpe; ///< bits per element (e.g. block size for BCn format)
3584
UINT_32 basePipeBankXor; ///< Base pipe bank xor
3585
UINT_32 slice; ///< Slice id
3586
UINT_32 numSamples; ///< Number of samples
3587
} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT;
3588
3589
/**
3590
****************************************************************************************************
3591
* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
3592
*
3593
* @brief
3594
* Output structure of Addr2ComputeSlicePipeBankXor
3595
****************************************************************************************************
3596
*/
3597
typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
3598
{
3599
UINT_32 size; ///< Size of this structure in bytes
3600
UINT_32 pipeBankXor; ///< Pipe bank xor
3601
} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT;
3602
3603
/**
3604
****************************************************************************************************
3605
* Addr2ComputeSlicePipeBankXor
3606
*
3607
* @brief
3608
* Calculate slice pipe bank xor value based on base pipe bank xor and slice id.
3609
****************************************************************************************************
3610
*/
3611
ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor(
3612
ADDR_HANDLE hLib,
3613
const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
3614
ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut);
3615
3616
/**
3617
****************************************************************************************************
3618
* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
3619
*
3620
* @brief
3621
* Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
3622
****************************************************************************************************
3623
*/
3624
typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
3625
{
3626
UINT_32 size; ///< Size of this structure in bytes
3627
AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
3628
AddrResourceType resourceType; ///< Surface resource type
3629
UINT_32 pipeBankXor; ///< Per resource xor
3630
UINT_32 slice; ///< Slice id
3631
UINT_64 sliceSize; ///< Slice size of a mip chain
3632
UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO
3633
UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO
3634
} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT;
3635
3636
/**
3637
****************************************************************************************************
3638
* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
3639
*
3640
* @brief
3641
* Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
3642
****************************************************************************************************
3643
*/
3644
typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
3645
{
3646
UINT_32 size; ///< Size of this structure in bytes
3647
UINT_64 offset; ///< offset
3648
} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT;
3649
3650
/**
3651
****************************************************************************************************
3652
* Addr2ComputeSubResourceOffsetForSwizzlePattern
3653
*
3654
* @brief
3655
* Calculate sub resource offset to support swizzle pattern.
3656
****************************************************************************************************
3657
*/
3658
ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern(
3659
ADDR_HANDLE hLib,
3660
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
3661
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut);
3662
3663
/**
3664
****************************************************************************************************
3665
* ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT
3666
*
3667
* @brief
3668
* Input structure of Addr2ComputeNonBlockCompressedView
3669
****************************************************************************************************
3670
*/
3671
typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT
3672
{
3673
UINT_32 size; ///< Size of this structure in bytes
3674
ADDR2_SURFACE_FLAGS flags; ///< Surface flags
3675
AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9
3676
AddrResourceType resourceType; ///< Surface type
3677
AddrFormat format; ///< Surface format
3678
UINT_32 width; ///< Width of mip0 in texels (not in compressed block)
3679
UINT_32 height; ///< Height of mip0 in texels (not in compressed block)
3680
UINT_32 numSlices; ///< Number surface slice/depth of mip0
3681
UINT_32 numMipLevels; ///< Total mipmap levels.
3682
UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation
3683
UINT_32 slice; ///< Index of slice to view
3684
UINT_32 mipId; ///< Id of mip to view
3685
} ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT;
3686
3687
/**
3688
****************************************************************************************************
3689
* ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT
3690
*
3691
* @brief
3692
* Output structure of Addr2ComputeNonBlockCompressedView
3693
****************************************************************************************************
3694
*/
3695
typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT
3696
{
3697
UINT_32 size; ///< Size of this structure in bytes
3698
UINT_64 offset; ///< Offset shifted from resource base for the view
3699
UINT_32 pipeBankXor; ///< Pipe bank xor for the view
3700
UINT_32 unalignedWidth; ///< Mip0 width (in element) for the view
3701
UINT_32 unalignedHeight; ///< Mip0 height (in element) for the view
3702
UINT_32 numMipLevels; ///< Total mipmap levels for the view
3703
UINT_32 mipId; ///< Mip ID for the view
3704
} ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT;
3705
3706
/**
3707
****************************************************************************************************
3708
* Addr2ComputeNonBlockCompressedView
3709
*
3710
* @brief
3711
* Compute non-block-compressed view for a given mipmap level/slice
3712
****************************************************************************************************
3713
*/
3714
ADDR_E_RETURNCODE ADDR_API Addr2ComputeNonBlockCompressedView(
3715
ADDR_HANDLE hLib,
3716
const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn,
3717
ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut);
3718
3719
/**
3720
****************************************************************************************************
3721
* ADDR2_BLOCK_SET
3722
*
3723
* @brief
3724
* Bit field that defines block type
3725
****************************************************************************************************
3726
*/
3727
typedef union _ADDR2_BLOCK_SET
3728
{
3729
struct
3730
{
3731
UINT_32 micro : 1; // 256B block for 2D resource
3732
UINT_32 macroThin4KB : 1; // Thin 4KB for 2D/3D resource
3733
UINT_32 macroThick4KB : 1; // Thick 4KB for 3D resource
3734
UINT_32 macroThin64KB : 1; // Thin 64KB for 2D/3D resource
3735
UINT_32 macroThick64KB : 1; // Thick 64KB for 3D resource
3736
UINT_32 var : 1; // VAR block
3737
UINT_32 : 1;
3738
UINT_32 linear : 1; // Linear block
3739
UINT_32 reserved : 24;
3740
};
3741
3742
UINT_32 value;
3743
} ADDR2_BLOCK_SET;
3744
3745
/**
3746
****************************************************************************************************
3747
* ADDR2_SWTYPE_SET
3748
*
3749
* @brief
3750
* Bit field that defines swizzle type
3751
****************************************************************************************************
3752
*/
3753
typedef union _ADDR2_SWTYPE_SET
3754
{
3755
struct
3756
{
3757
UINT_32 sw_Z : 1; // SW_*_Z_*
3758
UINT_32 sw_S : 1; // SW_*_S_*
3759
UINT_32 sw_D : 1; // SW_*_D_*
3760
UINT_32 sw_R : 1; // SW_*_R_*
3761
UINT_32 reserved : 28;
3762
};
3763
3764
UINT_32 value;
3765
} ADDR2_SWTYPE_SET;
3766
3767
/**
3768
****************************************************************************************************
3769
* ADDR2_SWMODE_SET
3770
*
3771
* @brief
3772
* Bit field that defines swizzle type
3773
****************************************************************************************************
3774
*/
3775
typedef union _ADDR2_SWMODE_SET
3776
{
3777
struct
3778
{
3779
UINT_32 swLinear : 1;
3780
UINT_32 sw256B_S : 1;
3781
UINT_32 sw256B_D : 1;
3782
UINT_32 sw256B_R : 1;
3783
UINT_32 sw4KB_Z : 1;
3784
UINT_32 sw4KB_S : 1;
3785
UINT_32 sw4KB_D : 1;
3786
UINT_32 sw4KB_R : 1;
3787
UINT_32 sw64KB_Z : 1;
3788
UINT_32 sw64KB_S : 1;
3789
UINT_32 sw64KB_D : 1;
3790
UINT_32 sw64KB_R : 1;
3791
UINT_32 swMiscDef12 : 1;
3792
UINT_32 swMiscDef13 : 1;
3793
UINT_32 swMiscDef14 : 1;
3794
UINT_32 swMiscDef15 : 1;
3795
UINT_32 sw64KB_Z_T : 1;
3796
UINT_32 sw64KB_S_T : 1;
3797
UINT_32 sw64KB_D_T : 1;
3798
UINT_32 sw64KB_R_T : 1;
3799
UINT_32 sw4KB_Z_X : 1;
3800
UINT_32 sw4KB_S_X : 1;
3801
UINT_32 sw4KB_D_X : 1;
3802
UINT_32 sw4KB_R_X : 1;
3803
UINT_32 sw64KB_Z_X : 1;
3804
UINT_32 sw64KB_S_X : 1;
3805
UINT_32 sw64KB_D_X : 1;
3806
UINT_32 sw64KB_R_X : 1;
3807
UINT_32 swMiscDef28 : 1;
3808
UINT_32 swMiscDef29 : 1;
3809
UINT_32 swMiscDef30 : 1;
3810
UINT_32 swMiscDef31 : 1;
3811
};
3812
3813
struct
3814
{
3815
UINT_32 : 28;
3816
UINT_32 swVar_Z_X : 1;
3817
UINT_32 : 2;
3818
UINT_32 swVar_R_X : 1;
3819
} gfx10;
3820
3821
UINT_32 value;
3822
} ADDR2_SWMODE_SET;
3823
3824
/**
3825
****************************************************************************************************
3826
* ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
3827
*
3828
* @brief
3829
* Input structure of Addr2GetPreferredSurfaceSetting
3830
****************************************************************************************************
3831
*/
3832
typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
3833
{
3834
UINT_32 size; ///< Size of this structure in bytes
3835
3836
ADDR2_SURFACE_FLAGS flags; ///< Surface flags
3837
AddrResourceType resourceType; ///< Surface type
3838
AddrFormat format; ///< Surface format
3839
AddrResrouceLocation resourceLoction; ///< Surface heap choice
3840
ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting
3841
///< such as linear for DXTn, tiled for YUV
3842
ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted
3843
BOOL_32 noXor; ///< Do not use xor mode for this resource
3844
UINT_32 bpp; ///< bits per pixel
3845
UINT_32 width; ///< Width (of mip0), in pixels
3846
UINT_32 height; ///< Height (of mip0), in pixels
3847
UINT_32 numSlices; ///< Number surface slice/depth (of mip0),
3848
UINT_32 numMipLevels; ///< Total mipmap levels.
3849
UINT_32 numSamples; ///< Number of samples
3850
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3851
/// number of samples for normal AA; Set it to the
3852
/// number of fragments for EQAA
3853
UINT_32 maxAlign; ///< maximum base/size alignment requested by client
3854
UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will
3855
/// be padded to multiple of this value (in bytes)
3856
DOUBLE memoryBudget; ///< Memory consumption ratio based on minimum possible
3857
/// size.
3858
} ADDR2_GET_PREFERRED_SURF_SETTING_INPUT;
3859
3860
/**
3861
****************************************************************************************************
3862
* ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
3863
*
3864
* @brief
3865
* Output structure of Addr2GetPreferredSurfaceSetting
3866
****************************************************************************************************
3867
*/
3868
typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
3869
{
3870
UINT_32 size; ///< Size of this structure in bytes
3871
3872
AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used
3873
AddrResourceType resourceType; ///< Suggested resource type to program HW
3874
ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination
3875
BOOL_32 canXor; ///< If client can use xor on a valid macro block
3876
/// type
3877
ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination
3878
ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination
3879
ADDR2_SWMODE_SET validSwModeSet; ///< Valid swizzle mode bit combination
3880
} ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT;
3881
3882
/**
3883
****************************************************************************************************
3884
* Addr2GetPreferredSurfaceSetting
3885
*
3886
* @brief
3887
* Suggest a preferred setting for client driver to program HW register
3888
****************************************************************************************************
3889
*/
3890
ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting(
3891
ADDR_HANDLE hLib,
3892
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
3893
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut);
3894
3895
/**
3896
****************************************************************************************************
3897
* Addr2IsValidDisplaySwizzleMode
3898
*
3899
* @brief
3900
* Return whether the swizzle mode is supported by display engine
3901
****************************************************************************************************
3902
*/
3903
ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode(
3904
ADDR_HANDLE hLib,
3905
AddrSwizzleMode swizzleMode,
3906
UINT_32 bpp,
3907
BOOL_32 *pResult);
3908
3909
#if defined(__cplusplus)
3910
}
3911
#endif
3912
3913
#endif // __ADDR_INTERFACE_H__
3914
3915