CoCalc -- test

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/amd/compiler/tests/test_sdwa.cpp
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/*
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 * Copyright © 2020 Valve Corporation
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the next
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 * paragraph) shall be included in all copies or substantial portions of the
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 * Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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 * IN THE SOFTWARE.
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 *
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 */
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#include "helpers.h"
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#include <stdarg.h>
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using namespace aco;
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BEGIN_TEST(validate.sdwa.allow)
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   for (unsigned i = GFX8; i <= GFX10; i++) {
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      //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm
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      if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
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         continue;
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      //>> Validation results:
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      //! Validation passed
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      SDWA_instruction *sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]).instr->sdwa();
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      sdwa->neg[0] = sdwa->neg[1] = sdwa->abs[0] = sdwa->abs[1] = true;
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      sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]).instr->sdwa();
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      sdwa->dst_preserve = true;
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      sdwa->dst_sel = sdwa_ubyte0;
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      sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]).instr->sdwa();
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      sdwa->sel[0] = sdwa_sbyte2;
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      sdwa->sel[1] = sdwa_uword1;
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      finish_validator_test();
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   }
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END_TEST
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BEGIN_TEST(validate.sdwa.support)
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   for (unsigned i = GFX7; i <= GFX10; i++) {
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      //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm
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      if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
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         continue;
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      //>> Validation results:
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      //~gfx7! SDWA is GFX8+ only: v1: %t0 = v_mul_f32 %a, %b
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      //~gfx7! Validation failed
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      //~gfx([89]|10)! Validation passed
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      bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
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      finish_validator_test();
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   }
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END_TEST
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BEGIN_TEST(validate.sdwa.operands)
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   for (unsigned i = GFX8; i <= GFX10; i++) {
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      //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm
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      if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
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         continue;
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      //>> Validation results:
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      //~gfx8! Wrong source position for SGPR argument: v1: %_ = v_mul_f32 %sgpr0, %vgpr1
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      //~gfx8! Wrong source position for SGPR argument: v1: %_ = v_mul_f32 %vgpr0, %sgpr1
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      bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], inputs[1]);
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      bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[3]);
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      //~gfx8! Wrong source position for constant argument: v1: %_ = v_mul_f32 4, %vgpr1
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      //~gfx8! Wrong source position for constant argument: v1: %_ = v_mul_f32 %vgpr0, 4
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      bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(4u), inputs[1]);
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      bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(4u));
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      //! Literal applied on wrong instruction format: v1: %_ = v_mul_f32 0x1234, %vgpr1
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      //! Literal applied on wrong instruction format: v1: %_ = v_mul_f32 %vgpr0, 0x1234
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      //! Wrong source position for Literal argument: v1: %_ = v_mul_f32 %vgpr0, 0x1234
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      bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x1234u), inputs[1]);
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      bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(0x1234u));
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      //! Validation failed
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      finish_validator_test();
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   }
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END_TEST
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BEGIN_TEST(validate.sdwa.vopc)
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   for (unsigned i = GFX8; i <= GFX10; i++) {
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      //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm
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      if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
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         continue;
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      //>> Validation results:
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      bld.vopc_sdwa(aco_opcode::v_cmp_gt_f32, bld.def(bld.lm, vcc), inputs[0], inputs[1]);
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      //~gfx8! SDWA+VOPC definition must be fixed to vcc on GFX8: s2: %_ = v_cmp_lt_f32 %vgpr0, %vgpr1
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      bld.vopc_sdwa(aco_opcode::v_cmp_lt_f32, bld.def(bld.lm), inputs[0], inputs[1]);
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      //~gfx(9|10)! SDWA VOPC clamp only supported on GFX8: s2: %_:vcc = v_cmp_eq_f32 %vgpr0, %vgpr1 clamp
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      bld.vopc_sdwa(aco_opcode::v_cmp_eq_f32, bld.def(bld.lm, vcc), inputs[0], inputs[1]).instr->sdwa().clamp = true;
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      //! Validation failed
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      finish_validator_test();
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   }
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END_TEST
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BEGIN_TEST(validate.sdwa.omod)
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   for (unsigned i = GFX8; i <= GFX10; i++) {
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      //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm
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      if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
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         continue;
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      //>> Validation results:
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      //~gfx8! SDWA omod only supported on GFX9+: v1: %_ = v_mul_f32 %vgpr0, %vgpr1 *2
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      //~gfx8! Validation failed
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      //~gfx(9|10)! Validation passed
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      bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]).instr->sdwa().omod = 1;
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      finish_validator_test();
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   }
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END_TEST
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BEGIN_TEST(validate.sdwa.vcc)
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   for (unsigned i = GFX8; i <= GFX10; i++) {
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      //>> v1: %vgpr0, v1: %vgpr1, s2: %sgpr0 = p_startpgm
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      if (!setup_cs("v1 v1 s2", (chip_class)i))
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         continue;
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      //>> Validation results:
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      //! 3rd operand must be fixed to vcc with SDWA: v1: %_ = v_cndmask_b32 %vgpr0, %vgpr1, %_
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      bld.vop2_sdwa(aco_opcode::v_cndmask_b32, bld.def(v1), inputs[0], inputs[1], inputs[2]);
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      bld.vop2_sdwa(aco_opcode::v_cndmask_b32, bld.def(v1), inputs[0], inputs[1], bld.vcc(inputs[2]));
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      //! 2nd definition must be fixed to vcc with SDWA: v1: %_, s2: %_ = v_add_co_u32 %vgpr0, %vgpr1
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      bld.vop2_sdwa(aco_opcode::v_add_co_u32, bld.def(v1), bld.def(bld.lm), inputs[0], inputs[1]);
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      bld.vop2_sdwa(aco_opcode::v_add_co_u32, bld.def(v1), bld.def(bld.lm, vcc), inputs[0], inputs[1]);
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      //! Validation failed
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      finish_validator_test();
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   }
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END_TEST
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BEGIN_TEST(optimize.sdwa.extract)
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   for (unsigned i = GFX7; i <= GFX10; i++) {
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   for (unsigned is_signed = 0; is_signed <= 1; is_signed++) {
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      //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm
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      if (!setup_cs("v1 v1 s1 s1", (chip_class)i, CHIP_UNKNOWN, is_signed ? "_signed" : "_unsigned"))
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         continue;
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      //; funcs['b'] = lambda bits: ('sext(%%b)[%s]' if variant.endswith('_signed') else '%%b[%s]') % bits
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      //; def standard_test(index, offset, size):
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      //;    res = 'v1: %%res%d = v_mul_f32 %%a, @b(%d:%d)\n' % (index, offset % 32, offset % 32 + size % 32 - 1)
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      //;    res += 'p_unit_test %d, %%res%d' % (index, index)
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      //;    return res
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      //; funcs['standard_test'] = lambda a: standard_test(*(int(v) for v in a.split(',')))
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      aco_opcode ext = aco_opcode::p_extract;
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      aco_opcode ins = aco_opcode::p_insert;
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      {
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      //~gfx[^7].*! @standard_test(0, 0, 8)
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      Temp bfe_byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u),
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                                    Operand::c32(is_signed));
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      writeout(0, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte0_b));
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      //~gfx[^7].*! @standard_test(1, 8, 8)
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      Temp bfe_byte1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), Operand::c32(8u),
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                                    Operand::c32(is_signed));
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      writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte1_b));
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      //~gfx[^7].*! @standard_test(2, 16, 8)
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      Temp bfe_byte2_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(2u), Operand::c32(8u),
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                                    Operand::c32(is_signed));
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      writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte2_b));
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      //~gfx[^7].*! @standard_test(3, 24, 8)
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      Temp bfe_byte3_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(3u), Operand::c32(8u),
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                                    Operand::c32(is_signed));
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      writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte3_b));
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      //~gfx[^7].*! @standard_test(4, 0, 16)
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      Temp bfe_word0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(16u),
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                                    Operand::c32(is_signed));
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      writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_word0_b));
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      //~gfx[^7].*! @standard_test(5, 16, 16)
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      Temp bfe_word1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u),
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                                    Operand::c32(16u), Operand::c32(is_signed));
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      writeout(5, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_word1_b));
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      //~gfx[^7]_unsigned! @standard_test(6, 0, 8)
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      Temp bfi_byte0_b = bld.pseudo(ins, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u));
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      writeout(6, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_byte0_b));
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      //~gfx[^7]_unsigned! @standard_test(7, 0, 16)
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      Temp bfi_word0_b =
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         bld.pseudo(ins, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(16u));
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      writeout(7, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_word0_b));
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      }
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      //>> p_unit_test 63
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      writeout(63);
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      {
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      //! v1: %tmp8 = p_insert %b, 1, 8
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      //! v1: %res8 = v_mul_f32 %a, %tmp8
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      //! p_unit_test 8, %res8
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      Temp bfi_byte1_b =
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         bld.pseudo(ins, bld.def(v1), inputs[1], Operand::c32(1u), Operand::c32(8u));
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      writeout(8, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_byte1_b));
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      /* v_cvt_f32_ubyte[0-3] can be used instead of v_cvt_f32_u32+sdwa */
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      //~gfx7_signed! v1: %bfe_byte0_b = p_extract %b, 0, 8, 1
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      //~gfx7_signed! v1: %res9 = v_cvt_f32_u32 %bfe_byte0_b
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      //~gfx[^7]+_signed! v1: %res9 = v_cvt_f32_u32 @b(0:7)
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      //~gfx\d+_unsigned! v1: %res9 = v_cvt_f32_ubyte0 %b
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      //! p_unit_test 9, %res9
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      Temp bfe_byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u),
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                                    Operand::c32(is_signed));
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      writeout(9, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte0_b));
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      //~gfx7_signed! v1: %bfe_byte1_b = p_extract %b, 1, 8, 1
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      //~gfx7_signed! v1: %res10 = v_cvt_f32_u32 %bfe_byte1_b
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      //~gfx[^7]+_signed! v1: %res10 = v_cvt_f32_u32 @b(8:15)
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      //~gfx\d+_unsigned! v1: %res10 = v_cvt_f32_ubyte1 %b
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      //! p_unit_test 10, %res10
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      Temp bfe_byte1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), Operand::c32(8u),
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                                    Operand::c32(is_signed));
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      writeout(10, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte1_b));
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      //~gfx7_signed! v1: %bfe_byte2_b = p_extract %b, 2, 8, 1
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      //~gfx7_signed! v1: %res11 = v_cvt_f32_u32 %bfe_byte2_b
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      //~gfx[^7]+_signed! v1: %res11 = v_cvt_f32_u32 @b(16:23)
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      //~gfx\d+_unsigned! v1: %res11 = v_cvt_f32_ubyte2 %b
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      //! p_unit_test 11, %res11
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      Temp bfe_byte2_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(2u), Operand::c32(8u),
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                                    Operand::c32(is_signed));
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      writeout(11, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte2_b));
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      //~gfx7_signed! v1: %bfe_byte3_b = p_extract %b, 3, 8, 1
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      //~gfx7_signed! v1: %res12 = v_cvt_f32_u32 %bfe_byte3_b
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      //~gfx[^7]+_signed! v1: %res12 = v_cvt_f32_u32 @b(24:31)
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      //~gfx\d+_unsigned! v1: %res12 = v_cvt_f32_ubyte3 %b
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      //! p_unit_test 12, %res12
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      Temp bfe_byte3_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(3u), Operand::c32(8u),
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                                    Operand::c32(is_signed));
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      writeout(12, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte3_b));
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      //! v1: %res13 = v_add_i16 %a, %b
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      //! p_unit_test 13, %res13
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      Temp bfe_word0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(16u),
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                                    Operand::c32(is_signed));
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      writeout(13, bld.vop3(aco_opcode::v_add_i16, bld.def(v1), inputs[0], bfe_word0_b));
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      /* VOP3-only instructions can't use SDWA but they can use opsel instead */
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      //~gfx(9|10).*! v1: %res14 = v_add_i16 %a, hi(%b)
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      //~gfx(9|10).*! p_unit_test 14, %res14
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      Temp bfe_word1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u),
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                                    Operand::c32(16u), Operand::c32(is_signed));
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      writeout(14, bld.vop3(aco_opcode::v_add_i16, bld.def(v1), inputs[0], bfe_word1_b));
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      }
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      finish_opt_test();
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   }
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   }
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END_TEST
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BEGIN_TEST(optimize.sdwa.extract_modifiers)
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   for (unsigned i = GFX8; i <= GFX10; i++) {
283
      //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm
284
      if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
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         continue;
286

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      aco_opcode ext = aco_opcode::p_extract;
288

289
      //! v1: %res0 = v_mul_f32 %a, -%b[0:7]
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      //! p_unit_test 0, %res0
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      Temp byte0 = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u),
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                              Operand::zero());
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      Temp neg_byte0 = fneg(byte0);
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      writeout(0, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], neg_byte0));
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      //~gfx8! v1: %neg = v_mul_f32 -1.0, %b
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      //~gfx8! v1: %res1 = v_mul_f32 %a, %neg[0:7]
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      //~gfx(9|10)! v1: %neg_byte0 = v_mul_f32 -1.0, %b dst_sel:ubyte0
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      //~gfx(9|10)! v1: %res1 = v_mul_f32 %a, %neg_byte0
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      //! p_unit_test 1, %res1
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      Temp neg = fneg(inputs[1]);
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      Temp byte0_neg =
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         bld.pseudo(ext, bld.def(v1), neg, Operand::zero(), Operand::c32(8u), Operand::zero());
304
      writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_neg));
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306
      //! v1: %res2 = v_mul_f32 %a, |%b[0:7]|
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      //! p_unit_test 2, %res2
308
      Temp abs_byte0 = fabs(byte0);
309
      writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], abs_byte0));
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      //! v1: %abs = v_mul_f32 1.0, |%b|
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      //! v1: %res3 = v_mul_f32 %a, %abs[0:7]
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      //! p_unit_test 3, %res3
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      Temp abs = fabs(inputs[1]);
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      Temp byte0_abs =
316
         bld.pseudo(ext, bld.def(v1), abs, Operand::zero(), Operand::c32(8u), Operand::zero());
317
      writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_abs));
318

319
      //! v1: %res4 = v_mul_f32 %1, -|%2[0:7]|
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      //! p_unit_test 4, %res4
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      Temp neg_abs_byte0 = fneg(abs_byte0);
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      writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], neg_abs_byte0));
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      //~gfx8! v1: %neg_abs = v_mul_f32 -1.0, %abs
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      //~gfx8! v1: %res5 = v_mul_f32 %a, %neg_abs[0:7]
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      //~gfx(9|10)! v1: %neg_abs_byte0 = v_mul_f32 -1.0, %abs dst_sel:ubyte0
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      //~gfx(9|10)! v1: %res5 = v_mul_f32 %a, %neg_abs_byte0
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      //! p_unit_test 5, %res5
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      Temp neg_abs = fneg(abs);
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      Temp byte0_neg_abs =
331
         bld.pseudo(ext, bld.def(v1), neg_abs, Operand::zero(), Operand::c32(8u), Operand::zero());
332
      writeout(5, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_neg_abs));
333

334
      finish_opt_test();
335
   }
336
END_TEST
337

338
BEGIN_TEST(optimize.sdwa.extract.sgpr)
339
   for (unsigned i = GFX8; i <= GFX10; i++) {
340
      //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm
341
      if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
342
         continue;
343

344
      aco_opcode ext = aco_opcode::p_extract;
345

346
      //~gfx8! v1: %byte0_b = p_extract %b, 0, 8, 0
347
      //~gfx8! v1: %res1 = v_mul_f32 %c, %byte0_b
348
      //~gfx(9|10)! v1: %res1 = v_mul_f32 %c, %b[0:7]
349
      //! p_unit_test 1, %res1
350
      Temp byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u),
351
                                Operand::zero());
352
      writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], byte0_b));
353

354
      //~gfx8! v1: %byte0_c = p_extract %c, 0, 8, 0
355
      //~gfx8! v1: %res2 = v_mul_f32 %a, %byte0_c
356
      //~gfx(9|10)! v1: %res2 = v_mul_f32 %a, %c[0:7]
357
      //! p_unit_test 2, %res2
358
      Temp byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u),
359
                                Operand::zero());
360
      writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_c));
361

362
      //~gfx8! v1: %byte0_c_2 = p_extract %c, 0, 8, 0
363
      //~gfx8! v1: %res3 = v_mul_f32 %c, %byte0_c_2
364
      //~gfx(9|10)! v1: %res3 = v_mul_f32 %c, %c[0:7]
365
      //! p_unit_test 3, %res3
366
      byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u),
367
                           Operand::zero());
368
      writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], byte0_c));
369

370
      //~gfx(8|9)! v1: %byte0_c_3 = p_extract %c, 0, 8, 0
371
      //~gfx(8|9)! v1: %res4 = v_mul_f32 %d, %byte0_c_3
372
      //~gfx10! v1: %res4 = v_mul_f32 %d, %c[0:7]
373
      //! p_unit_test 4, %res4
374
      byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u),
375
                           Operand::zero());
376
      writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[3], byte0_c));
377

378
      finish_opt_test();
379
   }
380
END_TEST
381

382
BEGIN_TEST(optimize.sdwa.from_vop3)
383
   for (unsigned i = GFX8; i <= GFX10; i++) {
384
      //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm
385
      if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
386
         continue;
387

388
      //! v1: %res0 = v_mul_f32 -|%a|, %b[0:7]
389
      //! p_unit_test 0, %res0
390
      Temp byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(),
391
                                Operand::c32(8u), Operand::zero());
392
      VOP3_instruction *mul = &bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_b).instr->vop3();
393
      mul->neg[0] = true;
394
      mul->abs[0] = true;
395
      writeout(0, mul->definitions[0].getTemp());
396

397
      //~gfx8! v1: %byte0_b_0 = p_extract %b, 0, 8, 0
398
      //~gfx8! v1: %res1 = v_mul_f32 %a, %byte0_b_0 *4
399
      //~gfx(9|10)! v1: %res1 = v_mul_f32 %a, %b[0:7] *4
400
      //! p_unit_test 1, %res1
401
      byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(),
402
                           Operand::c32(8u), Operand::zero());
403
      mul = &bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_b).instr->vop3();
404
      mul->omod = 2;
405
      writeout(1, mul->definitions[0].getTemp());
406

407
      //~gfx8! v1: %byte0_b_1 = p_extract %b, 0, 8, 0
408
      //~gfx8! v1: %res2 = v_mul_f32 %byte0_b_1, %c
409
      //~gfx(9|10)! v1: %res2 = v_mul_f32 %b[0:7], %c
410
      //! p_unit_test 2, %res2
411
      byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(),
412
                           Operand::c32(8u), Operand::zero());
413
      writeout(2, bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), byte0_b, inputs[2]));
414

415
      if (i >= GFX10) {
416
         //~gfx10! v1: %byte0_b_2 = p_extract %b, 0, 8, 0
417
         //~gfx10! v1: %res3 = v_mul_f32 %byte0_b_2, 0x1234
418
         //~gfx10! p_unit_test 3, %res3
419
         byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(),
420
                              Operand::c32(8u), Operand::zero());
421
         writeout(3,
422
                  bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), byte0_b, Operand::c32(0x1234u)));
423
      }
424

425
      finish_opt_test();
426
   }
427
END_TEST
428

429
BEGIN_TEST(optimize.sdwa.insert)
430
   for (unsigned i = GFX7; i <= GFX10; i++) {
431
      //>> v1: %a, v1: %b = p_startpgm
432
      if (!setup_cs("v1 v1", (chip_class)i))
433
         continue;
434

435
      aco_opcode ext = aco_opcode::p_extract;
436
      aco_opcode ins = aco_opcode::p_insert;
437

438
      //~gfx[^7]! v1: %res0 = v_mul_f32 %a, %b dst_sel:ubyte0
439
      //~gfx[^7]! p_unit_test 0, %res0
440
      Temp val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
441
      writeout(0, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)));
442

443
      //~gfx[^7]! v1: %res1 = v_mul_f32 %a, %b dst_sel:ubyte1
444
      //~gfx[^7]! p_unit_test 1, %res1
445
      val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
446
      writeout(1, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(8u)));
447

448
      //~gfx[^7]! v1: %res2 = v_mul_f32 %a, %b dst_sel:ubyte2
449
      //~gfx[^7]! p_unit_test 2, %res2
450
      val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
451
      writeout(2, bld.pseudo(ins, bld.def(v1), val, Operand::c32(2u), Operand::c32(8u)));
452

453
      //~gfx[^7]! v1: %res3 = v_mul_f32 %a, %b dst_sel:ubyte3
454
      //~gfx[^7]! p_unit_test 3, %res3
455
      val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
456
      writeout(3, bld.pseudo(ins, bld.def(v1), val, Operand::c32(3u), Operand::c32(8u)));
457

458
      //~gfx[^7]! v1: %res4 = v_mul_f32 %a, %b dst_sel:uword0
459
      //~gfx[^7]! p_unit_test 4, %res4
460
      val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
461
      writeout(4, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(16u)));
462

463
      //~gfx[^7]! v1: %res5 = v_mul_f32 %a, %b dst_sel:uword1
464
      //~gfx[^7]! p_unit_test 5, %res5
465
      val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
466
      writeout(5, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u)));
467

468
      //~gfx[^7]! v1: %res6 = v_mul_f32 %a, %b dst_sel:ubyte0
469
      //~gfx[^7]! p_unit_test 6, %res6
470
      val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
471
      writeout(
472
         6, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(8u), Operand::zero()));
473

474
      //~gfx[^7]! v1: %res7 = v_mul_f32 %a, %b dst_sel:uword0
475
      //~gfx[^7]! p_unit_test 7, %res7
476
      val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
477
      writeout(
478
         7, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(16u), Operand::zero()));
479

480
      //~gfx[^7]! v1: %tmp8 = v_mul_f32 %a, %b
481
      //~gfx[^7]! v1: %res8 = p_extract %tmp8, 2, 8, 0
482
      //~gfx[^7]! p_unit_test 8, %res8
483
      val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
484
      writeout(
485
         8, bld.pseudo(ext, bld.def(v1), val, Operand::c32(2u), Operand::c32(8u), Operand::zero()));
486

487
      //~gfx[^7]! v1: %tmp9 = v_mul_f32 %a, %b
488
      //~gfx[^7]! v1: %res9 = p_extract %tmp9, 0, 8, 1
489
      //~gfx[^7]! p_unit_test 9, %res9
490
      val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
491
      writeout(
492
         9, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(8u), Operand::c32(1u)));
493

494
      //>> p_unit_test 63
495
      writeout(63);
496

497
      //! v1: %res10 = v_mul_f32 %a, %b
498
      //! p_unit_test 10, %res10
499
      val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]);
500
      bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u));
501
      writeout(10, val);
502

503
      //! v1: %res11 = v_sub_i16 %a, %b
504
      //! p_unit_test 11, %res11
505
      val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]);
506
      writeout(11, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(16u)));
507

508
      //~gfx[78]! v1: %tmp12 = v_sub_i16 %a, %b
509
      //~gfx[78]! v1: %res12 = p_insert %tmp11, 1, 16
510
      //~gfx(9|10)! v1: %res12 = v_sub_i16 %a, %b opsel_hi
511
      //! p_unit_test 12, %res12
512
      val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]);
513
      writeout(12, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u)));
514

515
      //! v1: %tmp13 = v_sub_i16 %a, %b
516
      //! v1: %res13 = p_insert %tmp13, 0, 8
517
      //! p_unit_test 13, %res13
518
      val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]);
519
      writeout(13, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)));
520

521
      finish_opt_test();
522
   }
523
END_TEST
524

525
BEGIN_TEST(optimize.sdwa.insert_modifiers)
526
   for (unsigned i = GFX8; i <= GFX9; i++) {
527
      //>> v1: %a = p_startpgm
528
      if (!setup_cs("v1", (chip_class)i))
529
         continue;
530

531
      aco_opcode ins = aco_opcode::p_insert;
532

533
      //~gfx8! v1: %tmp0 = v_rcp_f32 %a *2
534
      //~gfx8! v1: %res0 = p_insert %tmp0, 0, 8
535
      //~gfx9! v1: %res0 = v_rcp_f32 %a *2 dst_sel:ubyte0
536
      //! p_unit_test 0, %res0
537
      Temp val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
538
      val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u));
539
      writeout(0, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)));
540

541
      //! v1: %res1 = v_rcp_f32 %a clamp dst_sel:ubyte0
542
      //! p_unit_test 1, %res1
543
      val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
544
      val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(),
545
                     Operand::c32(0x3f800000u));
546
      writeout(1, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)));
547

548
      //! v1: %tmp2 = v_rcp_f32 %a dst_sel:ubyte0
549
      //! v1: %res2 = v_mul_f32 %tmp2, 2.0
550
      //! p_unit_test 2, %res2
551
      val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
552
      val = bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u));
553
      val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u));
554
      writeout(2, val);
555

556
      //! v1: %tmp3 = v_rcp_f32 %a dst_sel:ubyte0
557
      //! v1: %res3 = v_med3_f32 %tmp3, 0, 1.0
558
      //! p_unit_test 3, %res3
559
      val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
560
      val = bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u));
561
      val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(),
562
                     Operand::c32(0x3f800000u));
563
      writeout(3, val);
564

565
      //~gfx8! v1: %tmp4 = v_rcp_f32 %a *2 clamp
566
      //~gfx8! v1: %res4 = p_insert %tmp4, 0, 8
567
      //~gfx9! v1: %res4 = v_rcp_f32 %a *2 clamp dst_sel:ubyte0
568
      //! p_unit_test 4, %res4
569
      val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
570
      val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u));
571
      val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(),
572
                     Operand::c32(0x3f800000u));
573
      writeout(4, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)));
574

575
      finish_opt_test();
576
   }
577
END_TEST
578

579
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