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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
 Path: blob/21.2-virgl/src/amd/registers/gfx81.json
7354 views
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{

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 "enums": {

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  "ArrayMode": {

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   "entries": [

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    {"name": "ARRAY_LINEAR_GENERAL", "value": 0},

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    {"name": "ARRAY_LINEAR_ALIGNED", "value": 1},

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    {"name": "ARRAY_1D_TILED_THICK", "value": 3},

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    {"name": "ARRAY_3D_TILED_THICK", "value": 13},

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    {"name": "ARRAY_3D_TILED_XTHICK", "value": 14},

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    {"name": "BUF_DATA_FORMAT_32", "value": 4},

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    {"name": "BUF_DATA_FORMAT_16_16", "value": 5},

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    {"name": "BUF_DATA_FORMAT_10_11_11", "value": 6},

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    {"name": "BUF_DATA_FORMAT_11_11_10", "value": 7},

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    {"name": "BUF_DATA_FORMAT_10_10_10_2", "value": 8},

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    {"name": "BUF_DATA_FORMAT_32_32_32_32", "value": 14},

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    {"name": "BUF_DATA_FORMAT_RESERVED_15", "value": 15}

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   ]

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  "BUF_NUM_FORMAT": {

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   "entries": [

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    {"name": "BUF_NUM_FORMAT_SSCALED", "value": 3},

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    {"name": "BUF_NUM_FORMAT_UINT", "value": 4},

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    {"name": "BUF_NUM_FORMAT_SINT", "value": 5},

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    {"name": "BUF_NUM_FORMAT_RESERVED_6", "value": 6},

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    {"name": "BUF_NUM_FORMAT_FLOAT", "value": 7}

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   ]

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  },

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   "entries": [

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    {"name": "ADDR_SURF_BANK_HEIGHT_1", "value": 0},

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   ]

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  },

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    {"name": "ADDR_SURF_BANK_WIDTH_4", "value": 2},

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    {"name": "ADDR_SURF_BANK_WIDTH_8", "value": 3}

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   ]

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   "entries": [

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    {"name": "BLEND_ZERO", "value": 0},

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    {"name": "BLEND_ONE", "value": 1},

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    {"name": "BLEND_SRC_COLOR", "value": 2},

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    {"name": "BLEND_ONE_MINUS_SRC_COLOR", "value": 3},

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    {"name": "BLEND_SRC_ALPHA", "value": 4},

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    {"name": "BLEND_ONE_MINUS_SRC_ALPHA", "value": 5},

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    {"name": "BLEND_DST_ALPHA", "value": 6},

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    {"name": "BLEND_ONE_MINUS_DST_ALPHA", "value": 7},

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    {"name": "BLEND_DST_COLOR", "value": 8},

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    {"name": "BLEND_ONE_MINUS_DST_COLOR", "value": 9},

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    {"name": "BLEND_SRC_ALPHA_SATURATE", "value": 10},

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    {"name": "BLEND_BOTH_SRC_ALPHA", "value": 11},

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    {"name": "BLEND_BOTH_INV_SRC_ALPHA", "value": 12},

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    {"name": "BLEND_CONSTANT_COLOR", "value": 13},

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    {"name": "BLEND_ONE_MINUS_CONSTANT_COLOR", "value": 14},

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    {"name": "BLEND_SRC1_COLOR", "value": 15},

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    {"name": "BLEND_INV_SRC1_COLOR", "value": 16},

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    {"name": "BLEND_SRC1_ALPHA", "value": 17},

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    {"name": "BLEND_INV_SRC1_ALPHA", "value": 18},

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    {"name": "BLEND_CONSTANT_ALPHA", "value": 19},

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    {"name": "BLEND_ONE_MINUS_CONSTANT_ALPHA", "value": 20}

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   ]

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    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_0", "value": 3},

102
    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_0", "value": 4},

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    {"name": "FORCE_OPT_ENABLE_IF_SRC_A_1", "value": 5},

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    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_1", "value": 6},

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    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_1", "value": 7}

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   ]

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  },

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    {"name": "CB_DECOMPRESS", "value": 4},

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    {"name": "CB_DCC_DECOMPRESS", "value": 6}

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   ]

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  },

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   "entries": [

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    {"name": "CB_PERF_CLEAR_FILTER_SEL_NONCLEAR", "value": 0},

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    {"name": "CB_PERF_CLEAR_FILTER_SEL_CLEAR", "value": 1}

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   ]

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  },

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   "entries": [

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    {"name": "CB_PERF_OP_FILTER_SEL_WRITE_ONLY", "value": 0},

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    {"name": "CB_PERF_OP_FILTER_SEL_DECOMPRESS", "value": 3},

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    {"name": "CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS", "value": 4},

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    {"name": "CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR", "value": 5}

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   ]

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  },

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   "entries": [

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    {"name": "MIN_BLOCK_SIZE_64B", "value": 1}

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   ]

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  },

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   "entries": [

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    {"name": "OUT", "value": 1},

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    {"name": "IN_0", "value": 2},

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    {"name": "IN_1", "value": 4},

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    {"name": "IN_10", "value": 8},

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   ]

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    {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE", "value": 2},

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    {"name": "CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}

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   ]

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  },

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    {"name": "CMASK_ADDR_LINEAR", "value": 1},

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    {"name": "CMASK_ADDR_COMPATIBLE", "value": 2}

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   ]

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  },

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  "ColorFormat": {

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   "entries": [

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    {"name": "COLOR_INVALID", "value": 0},

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    {"name": "COLOR_32", "value": 4},

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    {"name": "COLOR_24_8", "value": 21},

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    {"name": "COLOR_X24_8_32_FLOAT", "value": 22},

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    {"name": "COLOR_RESERVED_23", "value": 23},

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    {"name": "COLOR_RESERVED_30", "value": 30}

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   ]

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  },

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  "CombFunc": {

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   "entries": [

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    {"name": "COMB_DST_PLUS_SRC", "value": 0},

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    {"name": "COMB_SRC_MINUS_DST", "value": 1},

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    {"name": "COMB_MIN_DST_SRC", "value": 2},

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    {"name": "COMB_MAX_DST_SRC", "value": 3},

234
    {"name": "COMB_DST_MINUS_SRC", "value": 4}

235
   ]

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  },

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   "entries": [

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    {"name": "FRAG_NEVER", "value": 0},

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    {"name": "FRAG_LESS", "value": 1},

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    {"name": "FRAG_EQUAL", "value": 2},

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    {"name": "FRAG_LEQUAL", "value": 3},

243
    {"name": "FRAG_GREATER", "value": 4},

244
    {"name": "FRAG_NOTEQUAL", "value": 5},

245
    {"name": "FRAG_GEQUAL", "value": 6},

246
    {"name": "FRAG_ALWAYS", "value": 7}

247
   ]

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  },

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  "ConservativeZExport": {

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   "entries": [

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    {"name": "EXPORT_LESS_THAN_Z", "value": 1},

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    {"name": "EXPORT_GREATER_THAN_Z", "value": 2},

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    {"name": "EXPORT_RESERVED", "value": 3}

255
   ]

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   "entries": [

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   ]

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   "entries": [

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270
    {"name": "OVERFLOW", "value": 8},

271
    {"name": "UNDERFLOW", "value": 16},

272
    {"name": "INEXACT", "value": 32},

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    {"name": "INT_DIVIDE_BY_ZERO", "value": 64},

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    {"name": "ADDRESS_WATCH", "value": 128},

275
    {"name": "MEMORY_VIOLATION", "value": 256}

276
   ]

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  },

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  "FLOAT_MODE": {

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   "entries": [

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    {"name": "FP_32_DENORMS", "value": 48},

281
    {"name": "FP_64_DENORMS", "value": 192},

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    {"name": "FP_ALL_DENORMS", "value": 240}

283
   ]

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  },

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286
   "entries": [

287
    {"name": "FORCE_OFF", "value": 0},

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    {"name": "FORCE_ENABLE", "value": 1},

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    {"name": "FORCE_DISABLE", "value": 2},

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    {"name": "FORCE_RESERVED", "value": 3}

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   ]

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  },

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   "entries": [

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    {"name": "IMG_DATA_FORMAT_32", "value": 4},

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310
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    {"name": "IMG_DATA_FORMAT_8_24", "value": 20},

316
    {"name": "IMG_DATA_FORMAT_24_8", "value": 21},

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319
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320
    {"name": "IMG_DATA_FORMAT_ETC2_RGBA", "value": 25},

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    {"name": "IMG_DATA_FORMAT_ETC2_R", "value": 26},

322
    {"name": "IMG_DATA_FORMAT_ETC2_RG", "value": 27},

323
    {"name": "IMG_DATA_FORMAT_ETC2_RGBA1", "value": 28},

324
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325
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326
    {"name": "IMG_DATA_FORMAT_RESERVED_31", "value": 31},

327
    {"name": "IMG_DATA_FORMAT_GB_GR", "value": 32},

328
    {"name": "IMG_DATA_FORMAT_BG_RG", "value": 33},

329
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330
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332
    {"name": "IMG_DATA_FORMAT_BC3", "value": 37},

333
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334
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335
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337
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338
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339
    {"name": "IMG_DATA_FORMAT_FMASK8_S2_F1", "value": 44},

340
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    {"name": "IMG_DATA_FORMAT_FMASK8_S8_F1", "value": 46},

342
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343
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344
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345
    {"name": "IMG_DATA_FORMAT_FMASK16_S16_F1", "value": 50},

346
    {"name": "IMG_DATA_FORMAT_FMASK16_S8_F2", "value": 51},

347
    {"name": "IMG_DATA_FORMAT_FMASK32_S16_F2", "value": 52},

348
    {"name": "IMG_DATA_FORMAT_FMASK32_S8_F4", "value": 53},

349
    {"name": "IMG_DATA_FORMAT_FMASK32_S8_F8", "value": 54},

350
    {"name": "IMG_DATA_FORMAT_FMASK64_S16_F4", "value": 55},

351
    {"name": "IMG_DATA_FORMAT_FMASK64_S16_F8", "value": 56},

352
    {"name": "IMG_DATA_FORMAT_4_4", "value": 57},

353
    {"name": "IMG_DATA_FORMAT_6_5_5", "value": 58},

354
    {"name": "IMG_DATA_FORMAT_1", "value": 59},

355
    {"name": "IMG_DATA_FORMAT_1_REVERSED", "value": 60},

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    {"name": "IMG_DATA_FORMAT_8_AS_32", "value": 61},

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    {"name": "IMG_DATA_FORMAT_32_AS_32_32_32_32", "value": 63}

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   ]

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  },

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  "IMG_NUM_FORMAT": {

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   "entries": [

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    {"name": "IMG_NUM_FORMAT_SNORM", "value": 1},

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    {"name": "IMG_NUM_FORMAT_USCALED", "value": 2},

366
    {"name": "IMG_NUM_FORMAT_SSCALED", "value": 3},

367
    {"name": "IMG_NUM_FORMAT_UINT", "value": 4},

368
    {"name": "IMG_NUM_FORMAT_SINT", "value": 5},

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    {"name": "IMG_NUM_FORMAT_RESERVED_6", "value": 6},

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    {"name": "IMG_NUM_FORMAT_FLOAT", "value": 7},

371
    {"name": "IMG_NUM_FORMAT_RESERVED_8", "value": 8},

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    {"name": "IMG_NUM_FORMAT_SRGB", "value": 9},

373
    {"name": "IMG_NUM_FORMAT_RESERVED_10", "value": 10},

374
    {"name": "IMG_NUM_FORMAT_RESERVED_11", "value": 11},

375
    {"name": "IMG_NUM_FORMAT_RESERVED_12", "value": 12},

376
    {"name": "IMG_NUM_FORMAT_RESERVED_13", "value": 13},

377
    {"name": "IMG_NUM_FORMAT_RESERVED_14", "value": 14},

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    {"name": "IMG_NUM_FORMAT_RESERVED_15", "value": 15}

379
   ]

380
  },

381
  "MacroTileAspect": {

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   "entries": [

383
    {"name": "ADDR_SURF_MACRO_ASPECT_1", "value": 0},

384
    {"name": "ADDR_SURF_MACRO_ASPECT_2", "value": 1},

385
    {"name": "ADDR_SURF_MACRO_ASPECT_4", "value": 2},

386
    {"name": "ADDR_SURF_MACRO_ASPECT_8", "value": 3}

387
   ]

388
  },

389
  "MicroTileMode": {

390
   "entries": [

391
    {"name": "ADDR_SURF_DISPLAY_MICRO_TILING", "value": 0},

392
    {"name": "ADDR_SURF_THIN_MICRO_TILING", "value": 1},

393
    {"name": "ADDR_SURF_DEPTH_MICRO_TILING", "value": 2},

394
    {"name": "ADDR_SURF_ROTATED_MICRO_TILING", "value": 3},

395
    {"name": "ADDR_SURF_THICK_MICRO_TILING", "value": 4}

396
   ]

397
  },

398
  "NumBanks": {

399
   "entries": [

400
    {"name": "ADDR_SURF_2_BANK", "value": 0},

401
    {"name": "ADDR_SURF_4_BANK", "value": 1},

402
    {"name": "ADDR_SURF_8_BANK", "value": 2},

403
    {"name": "ADDR_SURF_16_BANK", "value": 3}

404
   ]

405
  },

406
  "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE": {

407
   "entries": [

408
    {"name": "X_DRAW_POINTS", "value": 0},

409
    {"name": "X_DRAW_LINES", "value": 1},

410
    {"name": "X_DRAW_TRIANGLES", "value": 2}

411
   ]

412
  },

413
  "PA_SU_SC_MODE_CNTL__POLY_MODE": {

414
   "entries": [

415
    {"name": "X_DISABLE_POLY_MODE", "value": 0},

416
    {"name": "X_DUAL_MODE", "value": 1}

417
   ]

418
  },

419
  "PA_SU_VTX_CNTL__ROUND_MODE": {

420
   "entries": [

421
    {"name": "X_TRUNCATE", "value": 0},

422
    {"name": "X_ROUND", "value": 1},

423
    {"name": "X_ROUND_TO_EVEN", "value": 2},

424
    {"name": "X_ROUND_TO_ODD", "value": 3}

425
   ]

426
  },

427
  "PipeConfig": {

428
   "entries": [

429
    {"name": "ADDR_SURF_P2", "value": 0},

430
    {"name": "ADDR_SURF_P2_RESERVED0", "value": 1},

431
    {"name": "ADDR_SURF_P2_RESERVED1", "value": 2},

432
    {"name": "ADDR_SURF_P2_RESERVED2", "value": 3},

433
    {"name": "ADDR_SURF_P4_8x16", "value": 4},

434
    {"name": "ADDR_SURF_P4_16x16", "value": 5},

435
    {"name": "ADDR_SURF_P4_16x32", "value": 6},

436
    {"name": "ADDR_SURF_P4_32x32", "value": 7},

437
    {"name": "ADDR_SURF_P8_16x16_8x16", "value": 8},

438
    {"name": "ADDR_SURF_P8_16x32_8x16", "value": 9},

439
    {"name": "ADDR_SURF_P8_32x32_8x16", "value": 10},

440
    {"name": "ADDR_SURF_P8_16x32_16x16", "value": 11},

441
    {"name": "ADDR_SURF_P8_32x32_16x16", "value": 12},

442
    {"name": "ADDR_SURF_P8_32x32_16x32", "value": 13},

443
    {"name": "ADDR_SURF_P8_32x64_32x32", "value": 14},

444
    {"name": "ADDR_SURF_P8_RESERVED0", "value": 15},

445
    {"name": "ADDR_SURF_P16_32x32_8x16", "value": 16},

446
    {"name": "ADDR_SURF_P16_32x32_16x16", "value": 17}

447
   ]

448
  },

449
  "PkrMap": {

450
   "entries": [

451
    {"name": "RASTER_CONFIG_PKR_MAP_0", "value": 0},

452
    {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},

453
    {"name": "RASTER_CONFIG_PKR_MAP_2", "value": 2},

454
    {"name": "RASTER_CONFIG_PKR_MAP_3", "value": 3}

455
   ]

456
  },

457
  "PkrXsel": {

458
   "entries": [

459
    {"name": "RASTER_CONFIG_PKR_XSEL_0", "value": 0},

460
    {"name": "RASTER_CONFIG_PKR_XSEL_1", "value": 1},

461
    {"name": "RASTER_CONFIG_PKR_XSEL_2", "value": 2},

462
    {"name": "RASTER_CONFIG_PKR_XSEL_3", "value": 3}

463
   ]

464
  },

465
  "PkrXsel2": {

466
   "entries": [

467
    {"name": "RASTER_CONFIG_PKR_XSEL2_0", "value": 0},

468
    {"name": "RASTER_CONFIG_PKR_XSEL2_1", "value": 1},

469
    {"name": "RASTER_CONFIG_PKR_XSEL2_2", "value": 2},

470
    {"name": "RASTER_CONFIG_PKR_XSEL2_3", "value": 3}

471
   ]

472
  },

473
  "PkrYsel": {

474
   "entries": [

475
    {"name": "RASTER_CONFIG_PKR_YSEL_0", "value": 0},

476
    {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},

477
    {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},

478
    {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}

479
   ]

480
  },

481
  "QUANT_MODE": {

482
   "entries": [

483
    {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},

484
    {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},

485
    {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},

486
    {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},

487
    {"name": "X_16_8_FIXED_POINT_1", "value": 4},

488
    {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},

489
    {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},

490
    {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}

491
   ]

492
  },

493
  "ROP3": {

494
   "entries": [

495
    {"name": "ROP3_CLEAR", "value": 0},

496
    {"name": "X_0X05", "value": 5},

497
    {"name": "X_0X0A", "value": 10},

498
    {"name": "X_0X0F", "value": 15},

499
    {"name": "ROP3_NOR", "value": 17},

500
    {"name": "ROP3_AND_INVERTED", "value": 34},

501
    {"name": "ROP3_COPY_INVERTED", "value": 51},

502
    {"name": "ROP3_AND_REVERSE", "value": 68},

503
    {"name": "X_0X50", "value": 80},

504
    {"name": "ROP3_INVERT", "value": 85},

505
    {"name": "X_0X5A", "value": 90},

506
    {"name": "X_0X5F", "value": 95},

507
    {"name": "ROP3_XOR", "value": 102},

508
    {"name": "ROP3_NAND", "value": 119},

509
    {"name": "ROP3_AND", "value": 136},

510
    {"name": "ROP3_EQUIVALENT", "value": 153},

511
    {"name": "X_0XA0", "value": 160},

512
    {"name": "X_0XA5", "value": 165},

513
    {"name": "ROP3_NO_OP", "value": 170},

514
    {"name": "X_0XAF", "value": 175},

515
    {"name": "ROP3_OR_INVERTED", "value": 187},

516
    {"name": "ROP3_COPY", "value": 204},

517
    {"name": "ROP3_OR_REVERSE", "value": 221},

518
    {"name": "ROP3_OR", "value": 238},

519
    {"name": "X_0XF0", "value": 240},

520
    {"name": "X_0XF5", "value": 245},

521
    {"name": "X_0XFA", "value": 250},

522
    {"name": "ROP3_SET", "value": 255}

523
   ]

524
  },

525
  "RbMap": {

526
   "entries": [

527
    {"name": "RASTER_CONFIG_RB_MAP_0", "value": 0},

528
    {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},

529
    {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},

530
    {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}

531
   ]

532
  },

533
  "RbXsel": {

534
   "entries": [

535
    {"name": "RASTER_CONFIG_RB_XSEL_0", "value": 0},

536
    {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}

537
   ]

538
  },

539
  "RbXsel2": {

540
   "entries": [

541
    {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},

542
    {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},

543
    {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},

544
    {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}

545
   ]

546
  },

547
  "RbYsel": {

548
   "entries": [

549
    {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},

550
    {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}

551
   ]

552
  },

553
  "SPI_PNT_SPRITE_OVERRIDE": {

554
   "entries": [

555
    {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},

556
    {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},

557
    {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},

558
    {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},

559
    {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}

560
   ]

561
  },

562
  "SPI_SHADER_EX_FORMAT": {

563
   "entries": [

564
    {"name": "SPI_SHADER_ZERO", "value": 0},

565
    {"name": "SPI_SHADER_32_R", "value": 1},

566
    {"name": "SPI_SHADER_32_GR", "value": 2},

567
    {"name": "SPI_SHADER_32_AR", "value": 3},

568
    {"name": "SPI_SHADER_FP16_ABGR", "value": 4},

569
    {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},

570
    {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},

571
    {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},

572
    {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},

573
    {"name": "SPI_SHADER_32_ABGR", "value": 9}

574
   ]

575
  },

576
  "SPI_SHADER_FORMAT": {

577
   "entries": [

578
    {"name": "SPI_SHADER_NONE", "value": 0},

579
    {"name": "SPI_SHADER_1COMP", "value": 1},

580
    {"name": "SPI_SHADER_2COMP", "value": 2},

581
    {"name": "SPI_SHADER_4COMPRESS", "value": 3},

582
    {"name": "SPI_SHADER_4COMP", "value": 4}

583
   ]

584
  },

585
  "SPM_PERFMON_STATE": {

586
   "entries": [

587
    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},

588
    {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},

589
    {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},

590
    {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},

591
    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},

592
    {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}

593
   ]

594
  },

595
  "SQ_IMG_FILTER_TYPE": {

596
   "entries": [

597
    {"name": "SQ_IMG_FILTER_MODE_BLEND", "value": 0},

598
    {"name": "SQ_IMG_FILTER_MODE_MIN", "value": 1},

599
    {"name": "SQ_IMG_FILTER_MODE_MAX", "value": 2}

600
   ]

601
  },

602
  "SQ_RSRC_BUF_TYPE": {

603
   "entries": [

604
    {"name": "SQ_RSRC_BUF", "value": 0},

605
    {"name": "SQ_RSRC_BUF_RSVD_1", "value": 1},

606
    {"name": "SQ_RSRC_BUF_RSVD_2", "value": 2},

607
    {"name": "SQ_RSRC_BUF_RSVD_3", "value": 3}

608
   ]

609
  },

610
  "SQ_RSRC_IMG_TYPE": {

611
   "entries": [

612
    {"name": "SQ_RSRC_IMG_RSVD_0", "value": 0},

613
    {"name": "SQ_RSRC_IMG_RSVD_1", "value": 1},

614
    {"name": "SQ_RSRC_IMG_RSVD_2", "value": 2},

615
    {"name": "SQ_RSRC_IMG_RSVD_3", "value": 3},

616
    {"name": "SQ_RSRC_IMG_RSVD_4", "value": 4},

617
    {"name": "SQ_RSRC_IMG_RSVD_5", "value": 5},

618
    {"name": "SQ_RSRC_IMG_RSVD_6", "value": 6},

619
    {"name": "SQ_RSRC_IMG_RSVD_7", "value": 7},

620
    {"name": "SQ_RSRC_IMG_1D", "value": 8},

621
    {"name": "SQ_RSRC_IMG_2D", "value": 9},

622
    {"name": "SQ_RSRC_IMG_3D", "value": 10},

623
    {"name": "SQ_RSRC_IMG_CUBE", "value": 11},

624
    {"name": "SQ_RSRC_IMG_1D_ARRAY", "value": 12},

625
    {"name": "SQ_RSRC_IMG_2D_ARRAY", "value": 13},

626
    {"name": "SQ_RSRC_IMG_2D_MSAA", "value": 14},

627
    {"name": "SQ_RSRC_IMG_2D_MSAA_ARRAY", "value": 15}

628
   ]

629
  },

630
  "SQ_SEL_XYZW01": {

631
   "entries": [

632
    {"name": "SQ_SEL_0", "value": 0},

633
    {"name": "SQ_SEL_1", "value": 1},

634
    {"name": "SQ_SEL_RESERVED_0", "value": 2},

635
    {"name": "SQ_SEL_RESERVED_1", "value": 3},

636
    {"name": "SQ_SEL_X", "value": 4},

637
    {"name": "SQ_SEL_Y", "value": 5},

638
    {"name": "SQ_SEL_Z", "value": 6},

639
    {"name": "SQ_SEL_W", "value": 7}

640
   ]

641
  },

642
  "SQ_TEX_BORDER_COLOR": {

643
   "entries": [

644
    {"name": "SQ_TEX_BORDER_COLOR_TRANS_BLACK", "value": 0},

645
    {"name": "SQ_TEX_BORDER_COLOR_OPAQUE_BLACK", "value": 1},

646
    {"name": "SQ_TEX_BORDER_COLOR_OPAQUE_WHITE", "value": 2},

647
    {"name": "SQ_TEX_BORDER_COLOR_REGISTER", "value": 3}

648
   ]

649
  },

650
  "SQ_TEX_CLAMP": {

651
   "entries": [

652
    {"name": "SQ_TEX_WRAP", "value": 0},

653
    {"name": "SQ_TEX_MIRROR", "value": 1},

654
    {"name": "SQ_TEX_CLAMP_LAST_TEXEL", "value": 2},

655
    {"name": "SQ_TEX_MIRROR_ONCE_LAST_TEXEL", "value": 3},

656
    {"name": "SQ_TEX_CLAMP_HALF_BORDER", "value": 4},

657
    {"name": "SQ_TEX_MIRROR_ONCE_HALF_BORDER", "value": 5},

658
    {"name": "SQ_TEX_CLAMP_BORDER", "value": 6},

659
    {"name": "SQ_TEX_MIRROR_ONCE_BORDER", "value": 7}

660
   ]

661
  },

662
  "SQ_TEX_DEPTH_COMPARE": {

663
   "entries": [

664
    {"name": "SQ_TEX_DEPTH_COMPARE_NEVER", "value": 0},

665
    {"name": "SQ_TEX_DEPTH_COMPARE_LESS", "value": 1},

666
    {"name": "SQ_TEX_DEPTH_COMPARE_EQUAL", "value": 2},

667
    {"name": "SQ_TEX_DEPTH_COMPARE_LESSEQUAL", "value": 3},

668
    {"name": "SQ_TEX_DEPTH_COMPARE_GREATER", "value": 4},

669
    {"name": "SQ_TEX_DEPTH_COMPARE_NOTEQUAL", "value": 5},

670
    {"name": "SQ_TEX_DEPTH_COMPARE_GREATEREQUAL", "value": 6},

671
    {"name": "SQ_TEX_DEPTH_COMPARE_ALWAYS", "value": 7}

672
   ]

673
  },

674
  "SQ_TEX_MIP_FILTER": {

675
   "entries": [

676
    {"name": "SQ_TEX_MIP_FILTER_NONE", "value": 0},

677
    {"name": "SQ_TEX_MIP_FILTER_POINT", "value": 1},

678
    {"name": "SQ_TEX_MIP_FILTER_LINEAR", "value": 2},

679
    {"name": "SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ", "value": 3}

680
   ]

681
  },

682
  "SQ_TEX_XY_FILTER": {

683
   "entries": [

684
    {"name": "SQ_TEX_XY_FILTER_POINT", "value": 0},

685
    {"name": "SQ_TEX_XY_FILTER_BILINEAR", "value": 1},

686
    {"name": "SQ_TEX_XY_FILTER_ANISO_POINT", "value": 2},

687
    {"name": "SQ_TEX_XY_FILTER_ANISO_BILINEAR", "value": 3}

688
   ]

689
  },

690
  "SQ_TEX_Z_FILTER": {

691
   "entries": [

692
    {"name": "SQ_TEX_Z_FILTER_NONE", "value": 0},

693
    {"name": "SQ_TEX_Z_FILTER_POINT", "value": 1},

694
    {"name": "SQ_TEX_Z_FILTER_LINEAR", "value": 2}

695
   ]

696
  },

697
  "SX_BLEND_OPT": {

698
   "entries": [

699
    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_ALL", "value": 0},

700
    {"name": "BLEND_OPT_PRESERVE_ALL_IGNORE_NONE", "value": 1},

701
    {"name": "BLEND_OPT_PRESERVE_C1_IGNORE_C0", "value": 2},

702
    {"name": "BLEND_OPT_PRESERVE_C0_IGNORE_C1", "value": 3},

703
    {"name": "BLEND_OPT_PRESERVE_A1_IGNORE_A0", "value": 4},

704
    {"name": "BLEND_OPT_PRESERVE_A0_IGNORE_A1", "value": 5},

705
    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_A0", "value": 6},

706
    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_NONE", "value": 7}

707
   ]

708
  },

709
  "SX_BLEND_OPT_EPSILON__MRT0_EPSILON": {

710
   "entries": [

711
    {"name": "EXACT", "value": 0},

712
    {"name": "11BIT_FORMAT", "value": 1},

713
    {"name": "10BIT_FORMAT", "value": 3},

714
    {"name": "8BIT_FORMAT", "value": 6},

715
    {"name": "6BIT_FORMAT", "value": 11},

716
    {"name": "5BIT_FORMAT", "value": 13},

717
    {"name": "4BIT_FORMAT", "value": 15}

718
   ]

719
  },

720
  "SX_DOWNCONVERT_FORMAT": {

721
   "entries": [

722
    {"name": "SX_RT_EXPORT_NO_CONVERSION", "value": 0},

723
    {"name": "SX_RT_EXPORT_32_R", "value": 1},

724
    {"name": "SX_RT_EXPORT_32_A", "value": 2},

725
    {"name": "SX_RT_EXPORT_10_11_11", "value": 3},

726
    {"name": "SX_RT_EXPORT_2_10_10_10", "value": 4},

727
    {"name": "SX_RT_EXPORT_8_8_8_8", "value": 5},

728
    {"name": "SX_RT_EXPORT_5_6_5", "value": 6},

729
    {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7},

730
    {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8},

731
    {"name": "SX_RT_EXPORT_16_16_GR", "value": 9},

732
    {"name": "SX_RT_EXPORT_16_16_AR", "value": 10}

733
   ]

734
  },

735
  "SX_OPT_COMB_FCN": {

736
   "entries": [

737
    {"name": "OPT_COMB_NONE", "value": 0},

738
    {"name": "OPT_COMB_ADD", "value": 1},

739
    {"name": "OPT_COMB_SUBTRACT", "value": 2},

740
    {"name": "OPT_COMB_MIN", "value": 3},

741
    {"name": "OPT_COMB_MAX", "value": 4},

742
    {"name": "OPT_COMB_REVSUBTRACT", "value": 5},

743
    {"name": "OPT_COMB_BLEND_DISABLED", "value": 6},

744
    {"name": "OPT_COMB_SAFE_ADD", "value": 7}

745
   ]

746
  },

747
  "ScMap": {

748
   "entries": [

749
    {"name": "RASTER_CONFIG_SC_MAP_0", "value": 0},

750
    {"name": "RASTER_CONFIG_SC_MAP_1", "value": 1},

751
    {"name": "RASTER_CONFIG_SC_MAP_2", "value": 2},

752
    {"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}

753
   ]

754
  },

755
  "ScXsel": {

756
   "entries": [

757
    {"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},

758
    {"name": "RASTER_CONFIG_SC_XSEL_16_WIDE_TILE", "value": 1},

759
    {"name": "RASTER_CONFIG_SC_XSEL_32_WIDE_TILE", "value": 2},

760
    {"name": "RASTER_CONFIG_SC_XSEL_64_WIDE_TILE", "value": 3}

761
   ]

762
  },

763
  "ScYsel": {

764
   "entries": [

765
    {"name": "RASTER_CONFIG_SC_YSEL_8_WIDE_TILE", "value": 0},

766
    {"name": "RASTER_CONFIG_SC_YSEL_16_WIDE_TILE", "value": 1},

767
    {"name": "RASTER_CONFIG_SC_YSEL_32_WIDE_TILE", "value": 2},

768
    {"name": "RASTER_CONFIG_SC_YSEL_64_WIDE_TILE", "value": 3}

769
   ]

770
  },

771
  "SeMap": {

772
   "entries": [

773
    {"name": "RASTER_CONFIG_SE_MAP_0", "value": 0},

774
    {"name": "RASTER_CONFIG_SE_MAP_1", "value": 1},

775
    {"name": "RASTER_CONFIG_SE_MAP_2", "value": 2},

776
    {"name": "RASTER_CONFIG_SE_MAP_3", "value": 3}

777
   ]

778
  },

779
  "SePairMap": {

780
   "entries": [

781
    {"name": "RASTER_CONFIG_SE_PAIR_MAP_0", "value": 0},

782
    {"name": "RASTER_CONFIG_SE_PAIR_MAP_1", "value": 1},

783
    {"name": "RASTER_CONFIG_SE_PAIR_MAP_2", "value": 2},

784
    {"name": "RASTER_CONFIG_SE_PAIR_MAP_3", "value": 3}

785
   ]

786
  },

787
  "SePairXsel": {

788
   "entries": [

789
    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE", "value": 0},

790
    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE", "value": 1},

791
    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE", "value": 2},

792
    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE", "value": 3}

793
   ]

794
  },

795
  "SePairYsel": {

796
   "entries": [

797
    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE", "value": 0},

798
    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE", "value": 1},

799
    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE", "value": 2},

800
    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE", "value": 3}

801
   ]

802
  },

803
  "SeXsel": {

804
   "entries": [

805
    {"name": "RASTER_CONFIG_SE_XSEL_8_WIDE_TILE", "value": 0},

806
    {"name": "RASTER_CONFIG_SE_XSEL_16_WIDE_TILE", "value": 1},

807
    {"name": "RASTER_CONFIG_SE_XSEL_32_WIDE_TILE", "value": 2},

808
    {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3}

809
   ]

810
  },

811
  "SeYsel": {

812
   "entries": [

813
    {"name": "RASTER_CONFIG_SE_YSEL_8_WIDE_TILE", "value": 0},

814
    {"name": "RASTER_CONFIG_SE_YSEL_16_WIDE_TILE", "value": 1},

815
    {"name": "RASTER_CONFIG_SE_YSEL_32_WIDE_TILE", "value": 2},

816
    {"name": "RASTER_CONFIG_SE_YSEL_64_WIDE_TILE", "value": 3}

817
   ]

818
  },

819
  "StencilFormat": {

820
   "entries": [

821
    {"name": "STENCIL_INVALID", "value": 0},

822
    {"name": "STENCIL_8", "value": 1}

823
   ]

824
  },

825
  "StencilOp": {

826
   "entries": [

827
    {"name": "STENCIL_KEEP", "value": 0},

828
    {"name": "STENCIL_ZERO", "value": 1},

829
    {"name": "STENCIL_ONES", "value": 2},

830
    {"name": "STENCIL_REPLACE_TEST", "value": 3},

831
    {"name": "STENCIL_REPLACE_OP", "value": 4},

832
    {"name": "STENCIL_ADD_CLAMP", "value": 5},

833
    {"name": "STENCIL_SUB_CLAMP", "value": 6},

834
    {"name": "STENCIL_INVERT", "value": 7},

835
    {"name": "STENCIL_ADD_WRAP", "value": 8},

836
    {"name": "STENCIL_SUB_WRAP", "value": 9},

837
    {"name": "STENCIL_AND", "value": 10},

838
    {"name": "STENCIL_OR", "value": 11},

839
    {"name": "STENCIL_XOR", "value": 12},

840
    {"name": "STENCIL_NAND", "value": 13},

841
    {"name": "STENCIL_NOR", "value": 14},

842
    {"name": "STENCIL_XNOR", "value": 15}

843
   ]

844
  },

845
  "SurfaceEndian": {

846
   "entries": [

847
    {"name": "ENDIAN_NONE", "value": 0},

848
    {"name": "ENDIAN_8IN16", "value": 1},

849
    {"name": "ENDIAN_8IN32", "value": 2},

850
    {"name": "ENDIAN_8IN64", "value": 3}

851
   ]

852
  },

853
  "SurfaceNumber": {

854
   "entries": [

855
    {"name": "NUMBER_UNORM", "value": 0},

856
    {"name": "NUMBER_SNORM", "value": 1},

857
    {"name": "NUMBER_USCALED", "value": 2},

858
    {"name": "NUMBER_SSCALED", "value": 3},

859
    {"name": "NUMBER_UINT", "value": 4},

860
    {"name": "NUMBER_SINT", "value": 5},

861
    {"name": "NUMBER_SRGB", "value": 6},

862
    {"name": "NUMBER_FLOAT", "value": 7}

863
   ]

864
  },

865
  "SurfaceSwap": {

866
   "entries": [

867
    {"name": "SWAP_STD", "value": 0},

868
    {"name": "SWAP_ALT", "value": 1},

869
    {"name": "SWAP_STD_REV", "value": 2},

870
    {"name": "SWAP_ALT_REV", "value": 3}

871
   ]

872
  },

873
  "TileSplit": {

874
   "entries": [

875
    {"name": "ADDR_SURF_TILE_SPLIT_64B", "value": 0},

876
    {"name": "ADDR_SURF_TILE_SPLIT_128B", "value": 1},

877
    {"name": "ADDR_SURF_TILE_SPLIT_256B", "value": 2},

878
    {"name": "ADDR_SURF_TILE_SPLIT_512B", "value": 3},

879
    {"name": "ADDR_SURF_TILE_SPLIT_1KB", "value": 4},

880
    {"name": "ADDR_SURF_TILE_SPLIT_2KB", "value": 5},

881
    {"name": "ADDR_SURF_TILE_SPLIT_4KB", "value": 6}

882
   ]

883
  },

884
  "VGT_DIST_MODE": {

885
   "entries": [

886
    {"name": "NO_DIST", "value": 0},

887
    {"name": "PATCHES", "value": 1},

888
    {"name": "DONUTS", "value": 2}

889
   ]

890
  },

891
  "VGT_DI_MAJOR_MODE_SELECT": {

892
   "entries": [

893
    {"name": "DI_MAJOR_MODE_0", "value": 0},

894
    {"name": "DI_MAJOR_MODE_1", "value": 1}

895
   ]

896
  },

897
  "VGT_DI_PRIM_TYPE": {

898
   "entries": [

899
    {"name": "DI_PT_NONE", "value": 0},

900
    {"name": "DI_PT_POINTLIST", "value": 1},

901
    {"name": "DI_PT_LINELIST", "value": 2},

902
    {"name": "DI_PT_LINESTRIP", "value": 3},

903
    {"name": "DI_PT_TRILIST", "value": 4},

904
    {"name": "DI_PT_TRIFAN", "value": 5},

905
    {"name": "DI_PT_TRISTRIP", "value": 6},

906
    {"name": "DI_PT_UNUSED_0", "value": 7},

907
    {"name": "DI_PT_UNUSED_1", "value": 8},

908
    {"name": "DI_PT_PATCH", "value": 9},

909
    {"name": "DI_PT_LINELIST_ADJ", "value": 10},

910
    {"name": "DI_PT_LINESTRIP_ADJ", "value": 11},

911
    {"name": "DI_PT_TRILIST_ADJ", "value": 12},

912
    {"name": "DI_PT_TRISTRIP_ADJ", "value": 13},

913
    {"name": "DI_PT_UNUSED_3", "value": 14},

914
    {"name": "DI_PT_UNUSED_4", "value": 15},

915
    {"name": "DI_PT_TRI_WITH_WFLAGS", "value": 16},

916
    {"name": "DI_PT_RECTLIST", "value": 17},

917
    {"name": "DI_PT_LINELOOP", "value": 18},

918
    {"name": "DI_PT_QUADLIST", "value": 19},

919
    {"name": "DI_PT_QUADSTRIP", "value": 20},

920
    {"name": "DI_PT_POLYGON", "value": 21},

921
    {"name": "DI_PT_2D_COPY_RECT_LIST_V0", "value": 22},

922
    {"name": "DI_PT_2D_COPY_RECT_LIST_V1", "value": 23},

923
    {"name": "DI_PT_2D_COPY_RECT_LIST_V2", "value": 24},

924
    {"name": "DI_PT_2D_COPY_RECT_LIST_V3", "value": 25},

925
    {"name": "DI_PT_2D_FILL_RECT_LIST", "value": 26},

926
    {"name": "DI_PT_2D_LINE_STRIP", "value": 27},

927
    {"name": "DI_PT_2D_TRI_STRIP", "value": 28}

928
   ]

929
  },

930
  "VGT_DI_SOURCE_SELECT": {

931
   "entries": [

932
    {"name": "DI_SRC_SEL_DMA", "value": 0},

933
    {"name": "DI_SRC_SEL_IMMEDIATE", "value": 1},

934
    {"name": "DI_SRC_SEL_AUTO_INDEX", "value": 2},

935
    {"name": "DI_SRC_SEL_RESERVED", "value": 3}

936
   ]

937
  },

938
  "VGT_DMA_BUF_TYPE": {

939
   "entries": [

940
    {"name": "VGT_DMA_BUF_MEM", "value": 0},

941
    {"name": "VGT_DMA_BUF_RING", "value": 1},

942
    {"name": "VGT_DMA_BUF_SETUP", "value": 2},

943
    {"name": "VGT_DMA_PTR_UPDATE", "value": 3}

944
   ]

945
  },

946
  "VGT_DMA_SWAP_MODE": {

947
   "entries": [

948
    {"name": "VGT_DMA_SWAP_NONE", "value": 0},

949
    {"name": "VGT_DMA_SWAP_16_BIT", "value": 1},

950
    {"name": "VGT_DMA_SWAP_32_BIT", "value": 2},

951
    {"name": "VGT_DMA_SWAP_WORD", "value": 3}

952
   ]

953
  },

954
  "VGT_EVENT_TYPE": {

955
   "entries": [

956
    {"name": "Reserved_0x00", "value": 0},

957
    {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},

958
    {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},

959
    {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},

960
    {"name": "CACHE_FLUSH_TS", "value": 4},

961
    {"name": "CONTEXT_DONE", "value": 5},

962
    {"name": "CACHE_FLUSH", "value": 6},

963
    {"name": "CS_PARTIAL_FLUSH", "value": 7},

964
    {"name": "VGT_STREAMOUT_SYNC", "value": 8},

965
    {"name": "Reserved_0x09", "value": 9},

966
    {"name": "VGT_STREAMOUT_RESET", "value": 10},

967
    {"name": "END_OF_PIPE_INCR_DE", "value": 11},

968
    {"name": "END_OF_PIPE_IB_END", "value": 12},

969
    {"name": "RST_PIX_CNT", "value": 13},

970
    {"name": "Reserved_0x0E", "value": 14},

971
    {"name": "VS_PARTIAL_FLUSH", "value": 15},

972
    {"name": "PS_PARTIAL_FLUSH", "value": 16},

973
    {"name": "FLUSH_HS_OUTPUT", "value": 17},

974
    {"name": "FLUSH_LS_OUTPUT", "value": 18},

975
    {"name": "Reserved_0x13", "value": 19},

976
    {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},

977
    {"name": "ZPASS_DONE", "value": 21},

978
    {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},

979
    {"name": "PERFCOUNTER_START", "value": 23},

980
    {"name": "PERFCOUNTER_STOP", "value": 24},

981
    {"name": "PIPELINESTAT_START", "value": 25},

982
    {"name": "PIPELINESTAT_STOP", "value": 26},

983
    {"name": "PERFCOUNTER_SAMPLE", "value": 27},

984
    {"name": "FLUSH_ES_OUTPUT", "value": 28},

985
    {"name": "FLUSH_GS_OUTPUT", "value": 29},

986
    {"name": "SAMPLE_PIPELINESTAT", "value": 30},

987
    {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},

988
    {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},

989
    {"name": "RESET_VTX_CNT", "value": 33},

990
    {"name": "BLOCK_CONTEXT_DONE", "value": 34},

991
    {"name": "CS_CONTEXT_DONE", "value": 35},

992
    {"name": "VGT_FLUSH", "value": 36},

993
    {"name": "TGID_ROLLOVER", "value": 37},

994
    {"name": "SQ_NON_EVENT", "value": 38},

995
    {"name": "SC_SEND_DB_VPZ", "value": 39},

996
    {"name": "BOTTOM_OF_PIPE_TS", "value": 40},

997
    {"name": "FLUSH_SX_TS", "value": 41},

998
    {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},

999
    {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},

1000
    {"name": "FLUSH_AND_INV_DB_META", "value": 44},

1001
    {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},

1002
    {"name": "FLUSH_AND_INV_CB_META", "value": 46},

1003
    {"name": "CS_DONE", "value": 47},

1004
    {"name": "PS_DONE", "value": 48},

1005
    {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},

1006
    {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},

1007
    {"name": "THREAD_TRACE_START", "value": 51},

1008
    {"name": "THREAD_TRACE_STOP", "value": 52},

1009
    {"name": "THREAD_TRACE_MARKER", "value": 53},

1010
    {"name": "THREAD_TRACE_FLUSH", "value": 54},

1011
    {"name": "THREAD_TRACE_FINISH", "value": 55},

1012
    {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},

1013
    {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},

1014
    {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},

1015
    {"name": "CONTEXT_SUSPEND", "value": 59},

1016
    {"name": "OFFCHIP_HS_DEALLOC", "value": 60}

1017
   ]

1018
  },

1019
  "VGT_GS_CUT_MODE": {

1020
   "entries": [

1021
    {"name": "GS_CUT_1024", "value": 0},

1022
    {"name": "GS_CUT_512", "value": 1},

1023
    {"name": "GS_CUT_256", "value": 2},

1024
    {"name": "GS_CUT_128", "value": 3}

1025
   ]

1026
  },

1027
  "VGT_GS_MODE_TYPE": {

1028
   "entries": [

1029
    {"name": "GS_OFF", "value": 0},

1030
    {"name": "GS_SCENARIO_A", "value": 1},

1031
    {"name": "GS_SCENARIO_B", "value": 2},

1032
    {"name": "GS_SCENARIO_G", "value": 3},

1033
    {"name": "GS_SCENARIO_C", "value": 4},

1034
    {"name": "SPRITE_EN", "value": 5}

1035
   ]

1036
  },

1037
  "VGT_GS_OUTPRIM_TYPE": {

1038
   "entries": [

1039
    {"name": "POINTLIST", "value": 0},

1040
    {"name": "LINESTRIP", "value": 1},

1041
    {"name": "TRISTRIP", "value": 2}

1042
   ]

1043
  },

1044
  "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY": {

1045
   "entries": [

1046
    {"name": "X_8K_DWORDS", "value": 0},

1047
    {"name": "X_4K_DWORDS", "value": 1},

1048
    {"name": "X_2K_DWORDS", "value": 2},

1049
    {"name": "X_1K_DWORDS", "value": 3}

1050
   ]

1051
  },

1052
  "VGT_INDEX_TYPE_MODE": {

1053
   "entries": [

1054
    {"name": "VGT_INDEX_16", "value": 0},

1055
    {"name": "VGT_INDEX_32", "value": 1},

1056
    {"name": "VGT_INDEX_8", "value": 2}

1057
   ]

1058
  },

1059
  "VGT_RDREQ_POLICY": {

1060
   "entries": [

1061
    {"name": "VGT_POLICY_LRU", "value": 0},

1062
    {"name": "VGT_POLICY_STREAM", "value": 1}

1063
   ]

1064
  },

1065
  "VGT_STAGES_ES_EN": {

1066
   "entries": [

1067
    {"name": "ES_STAGE_OFF", "value": 0},

1068
    {"name": "ES_STAGE_DS", "value": 1},

1069
    {"name": "ES_STAGE_REAL", "value": 2},

1070
    {"name": "RESERVED_ES", "value": 3}

1071
   ]

1072
  },

1073
  "VGT_STAGES_GS_EN": {

1074
   "entries": [

1075
    {"name": "GS_STAGE_OFF", "value": 0},

1076
    {"name": "GS_STAGE_ON", "value": 1}

1077
   ]

1078
  },

1079
  "VGT_STAGES_HS_EN": {

1080
   "entries": [

1081
    {"name": "HS_STAGE_OFF", "value": 0},

1082
    {"name": "HS_STAGE_ON", "value": 1}

1083
   ]

1084
  },

1085
  "VGT_STAGES_LS_EN": {

1086
   "entries": [

1087
    {"name": "LS_STAGE_OFF", "value": 0},

1088
    {"name": "LS_STAGE_ON", "value": 1},

1089
    {"name": "CS_STAGE_ON", "value": 2},

1090
    {"name": "RESERVED_LS", "value": 3}

1091
   ]

1092
  },

1093
  "VGT_STAGES_VS_EN": {

1094
   "entries": [

1095
    {"name": "VS_STAGE_REAL", "value": 0},

1096
    {"name": "VS_STAGE_DS", "value": 1},

1097
    {"name": "VS_STAGE_COPY_SHADER", "value": 2},

1098
    {"name": "RESERVED_VS", "value": 3}

1099
   ]

1100
  },

1101
  "VGT_TESS_PARTITION": {

1102
   "entries": [

1103
    {"name": "PART_INTEGER", "value": 0},

1104
    {"name": "PART_POW2", "value": 1},

1105
    {"name": "PART_FRAC_ODD", "value": 2},

1106
    {"name": "PART_FRAC_EVEN", "value": 3}

1107
   ]

1108
  },

1109
  "VGT_TESS_TOPOLOGY": {

1110
   "entries": [

1111
    {"name": "OUTPUT_POINT", "value": 0},

1112
    {"name": "OUTPUT_LINE", "value": 1},

1113
    {"name": "OUTPUT_TRIANGLE_CW", "value": 2},

1114
    {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}

1115
   ]

1116
  },

1117
  "VGT_TESS_TYPE": {

1118
   "entries": [

1119
    {"name": "TESS_ISOLINE", "value": 0},

1120
    {"name": "TESS_TRIANGLE", "value": 1},

1121
    {"name": "TESS_QUAD", "value": 2}

1122
   ]

1123
  },

1124
  "ZFormat": {

1125
   "entries": [

1126
    {"name": "Z_INVALID", "value": 0},

1127
    {"name": "Z_16", "value": 1},

1128
    {"name": "Z_24", "value": 2},

1129
    {"name": "Z_32_FLOAT", "value": 3}

1130
   ]

1131
  },

1132
  "ZLimitSumm": {

1133
   "entries": [

1134
    {"name": "FORCE_SUMM_OFF", "value": 0},

1135
    {"name": "FORCE_SUMM_MINZ", "value": 1},

1136
    {"name": "FORCE_SUMM_MAXZ", "value": 2},

1137
    {"name": "FORCE_SUMM_BOTH", "value": 3}

1138
   ]

1139
  },

1140
  "ZOrder": {

1141
   "entries": [

1142
    {"name": "LATE_Z", "value": 0},

1143
    {"name": "EARLY_Z_THEN_LATE_Z", "value": 1},

1144
    {"name": "RE_Z", "value": 2},

1145
    {"name": "EARLY_Z_THEN_RE_Z", "value": 3}

1146
   ]

1147
  }

1148
 },

1149
 "register_mappings": [

1150
  {

1151
   "chips": ["gfx81"],

1152
   "map": {"at": 68, "to": "mm"},

1153
   "name": "SQ_WAVE_MODE",

1154
   "type_ref": "SQ_WAVE_MODE"

1155
  },

1156
  {

1157
   "chips": ["gfx81"],

1158
   "map": {"at": 72, "to": "mm"},

1159
   "name": "SQ_WAVE_STATUS",

1160
   "type_ref": "SQ_WAVE_STATUS"

1161
  },

1162
  {

1163
   "chips": ["gfx81"],

1164
   "map": {"at": 76, "to": "mm"},

1165
   "name": "SQ_WAVE_TRAPSTS",

1166
   "type_ref": "SQ_WAVE_TRAPSTS"

1167
  },

1168
  {

1169
   "chips": ["gfx81"],

1170
   "map": {"at": 80, "to": "mm"},

1171
   "name": "SQ_WAVE_HW_ID",

1172
   "type_ref": "SQ_WAVE_HW_ID"

1173
  },

1174
  {

1175
   "chips": ["gfx81"],

1176
   "map": {"at": 84, "to": "mm"},

1177
   "name": "SQ_WAVE_GPR_ALLOC",

1178
   "type_ref": "SQ_WAVE_GPR_ALLOC"

1179
  },

1180
  {

1181
   "chips": ["gfx81"],

1182
   "map": {"at": 88, "to": "mm"},

1183
   "name": "SQ_WAVE_LDS_ALLOC",

1184
   "type_ref": "SQ_WAVE_LDS_ALLOC"

1185
  },

1186
  {

1187
   "chips": ["gfx81"],

1188
   "map": {"at": 92, "to": "mm"},

1189
   "name": "SQ_WAVE_IB_STS",

1190
   "type_ref": "SQ_WAVE_IB_STS"

1191
  },

1192
  {

1193
   "chips": ["gfx81"],

1194
   "map": {"at": 96, "to": "mm"},

1195
   "name": "SQ_WAVE_PC_LO"

1196
  },

1197
  {

1198
   "chips": ["gfx81"],

1199
   "map": {"at": 100, "to": "mm"},

1200
   "name": "SQ_WAVE_PC_HI",

1201
   "type_ref": "SQ_WAVE_PC_HI"

1202
  },

1203
  {

1204
   "chips": ["gfx81"],

1205
   "map": {"at": 104, "to": "mm"},

1206
   "name": "SQ_WAVE_INST_DW0"

1207
  },

1208
  {

1209
   "chips": ["gfx81"],

1210
   "map": {"at": 108, "to": "mm"},

1211
   "name": "SQ_WAVE_INST_DW1"

1212
  },

1213
  {

1214
   "chips": ["gfx81"],

1215
   "map": {"at": 112, "to": "mm"},

1216
   "name": "SQ_WAVE_IB_DBG0",

1217
   "type_ref": "SQ_WAVE_IB_DBG0"

1218
  },

1219
  {

1220
   "chips": ["gfx81"],

1221
   "map": {"at": 116, "to": "mm"},

1222
   "name": "SQ_WAVE_IB_DBG1",

1223
   "type_ref": "SQ_WAVE_IB_DBG1"

1224
  },

1225
  {

1226
   "chips": ["gfx81"],

1227
   "map": {"at": 2480, "to": "mm"},

1228
   "name": "SQ_WAVE_TBA_LO"

1229
  },

1230
  {

1231
   "chips": ["gfx81"],

1232
   "map": {"at": 2484, "to": "mm"},

1233
   "name": "SQ_WAVE_TBA_HI",

1234
   "type_ref": "SQ_WAVE_TBA_HI"

1235
  },

1236
  {

1237
   "chips": ["gfx81"],

1238
   "map": {"at": 2488, "to": "mm"},

1239
   "name": "SQ_WAVE_TMA_LO"

1240
  },

1241
  {

1242
   "chips": ["gfx81"],

1243
   "map": {"at": 2492, "to": "mm"},

1244
   "name": "SQ_WAVE_TMA_HI",

1245
   "type_ref": "SQ_WAVE_TBA_HI"

1246
  },

1247
  {

1248
   "chips": ["gfx81"],

1249
   "map": {"at": 2496, "to": "mm"},

1250
   "name": "SQ_WAVE_TTMP0"

1251
  },

1252
  {

1253
   "chips": ["gfx81"],

1254
   "map": {"at": 2500, "to": "mm"},

1255
   "name": "SQ_WAVE_TTMP1"

1256
  },

1257
  {

1258
   "chips": ["gfx81"],

1259
   "map": {"at": 2504, "to": "mm"},

1260
   "name": "SQ_WAVE_TTMP2"

1261
  },

1262
  {

1263
   "chips": ["gfx81"],

1264
   "map": {"at": 2508, "to": "mm"},

1265
   "name": "SQ_WAVE_TTMP3"

1266
  },

1267
  {

1268
   "chips": ["gfx81"],

1269
   "map": {"at": 2512, "to": "mm"},

1270
   "name": "SQ_WAVE_TTMP4"

1271
  },

1272
  {

1273
   "chips": ["gfx81"],

1274
   "map": {"at": 2516, "to": "mm"},

1275
   "name": "SQ_WAVE_TTMP5"

1276
  },

1277
  {

1278
   "chips": ["gfx81"],

1279
   "map": {"at": 2520, "to": "mm"},

1280
   "name": "SQ_WAVE_TTMP6"

1281
  },

1282
  {

1283
   "chips": ["gfx81"],

1284
   "map": {"at": 2524, "to": "mm"},

1285
   "name": "SQ_WAVE_TTMP7"

1286
  },

1287
  {

1288
   "chips": ["gfx81"],

1289
   "map": {"at": 2528, "to": "mm"},

1290
   "name": "SQ_WAVE_TTMP8"

1291
  },

1292
  {

1293
   "chips": ["gfx81"],

1294
   "map": {"at": 2532, "to": "mm"},

1295
   "name": "SQ_WAVE_TTMP9"

1296
  },

1297
  {

1298
   "chips": ["gfx81"],

1299
   "map": {"at": 2536, "to": "mm"},

1300
   "name": "SQ_WAVE_TTMP10"

1301
  },

1302
  {

1303
   "chips": ["gfx81"],

1304
   "map": {"at": 2540, "to": "mm"},

1305
   "name": "SQ_WAVE_TTMP11"

1306
  },

1307
  {

1308
   "chips": ["gfx81"],

1309
   "map": {"at": 2544, "to": "mm"},

1310
   "name": "SQ_WAVE_M0"

1311
  },

1312
  {

1313
   "chips": ["gfx81"],

1314
   "map": {"at": 2552, "to": "mm"},

1315
   "name": "SQ_WAVE_EXEC_LO"

1316
  },

1317
  {

1318
   "chips": ["gfx81"],

1319
   "map": {"at": 2556, "to": "mm"},

1320
   "name": "SQ_WAVE_EXEC_HI"

1321
  },

1322
  {

1323
   "chips": ["gfx81"],

1324
   "map": {"at": 32776, "to": "mm"},

1325
   "name": "GRBM_STATUS2",

1326
   "type_ref": "GRBM_STATUS2"

1327
  },

1328
  {

1329
   "chips": ["gfx81"],

1330
   "map": {"at": 32784, "to": "mm"},

1331
   "name": "GRBM_STATUS",

1332
   "type_ref": "GRBM_STATUS"

1333
  },

1334
  {

1335
   "chips": ["gfx81"],

1336
   "map": {"at": 32788, "to": "mm"},

1337
   "name": "GRBM_STATUS_SE0",

1338
   "type_ref": "GRBM_STATUS_SE0"

1339
  },

1340
  {

1341
   "chips": ["gfx81"],

1342
   "map": {"at": 32792, "to": "mm"},

1343
   "name": "GRBM_STATUS_SE1",

1344
   "type_ref": "GRBM_STATUS_SE0"

1345
  },

1346
  {

1347
   "chips": ["gfx81"],

1348
   "map": {"at": 32824, "to": "mm"},

1349
   "name": "GRBM_STATUS_SE2",

1350
   "type_ref": "GRBM_STATUS_SE0"

1351
  },

1352
  {

1353
   "chips": ["gfx81"],

1354
   "map": {"at": 32828, "to": "mm"},

1355
   "name": "GRBM_STATUS_SE3",

1356
   "type_ref": "GRBM_STATUS_SE0"

1357
  },

1358
  {

1359
   "chips": ["gfx81"],

1360
   "map": {"at": 33296, "to": "mm"},

1361
   "name": "CP_CPC_STATUS",

1362
   "type_ref": "CP_CPC_STATUS"

1363
  },

1364
  {

1365
   "chips": ["gfx81"],

1366
   "map": {"at": 33300, "to": "mm"},

1367
   "name": "CP_CPC_BUSY_STAT",

1368
   "type_ref": "CP_CPC_BUSY_STAT"

1369
  },

1370
  {

1371
   "chips": ["gfx81"],

1372
   "map": {"at": 33304, "to": "mm"},

1373
   "name": "CP_CPC_STALLED_STAT1",

1374
   "type_ref": "CP_CPC_STALLED_STAT1"

1375
  },

1376
  {

1377
   "chips": ["gfx81"],

1378
   "map": {"at": 33308, "to": "mm"},

1379
   "name": "CP_CPF_STATUS",

1380
   "type_ref": "CP_CPF_STATUS"

1381
  },

1382
  {

1383
   "chips": ["gfx81"],

1384
   "map": {"at": 33312, "to": "mm"},

1385
   "name": "CP_CPF_BUSY_STAT",

1386
   "type_ref": "CP_CPF_BUSY_STAT"

1387
  },

1388
  {

1389
   "chips": ["gfx81"],

1390
   "map": {"at": 33316, "to": "mm"},

1391
   "name": "CP_CPF_STALLED_STAT1",

1392
   "type_ref": "CP_CPF_STALLED_STAT1"

1393
  },

1394
  {

1395
   "chips": ["gfx81"],

1396
   "map": {"at": 33324, "to": "mm"},

1397
   "name": "CP_CPC_GRBM_FREE_COUNT",

1398
   "type_ref": "CP_CPC_GRBM_FREE_COUNT"

1399
  },

1400
  {

1401
   "chips": ["gfx81"],

1402
   "map": {"at": 33344, "to": "mm"},

1403
   "name": "CP_CPC_SCRATCH_INDEX",

1404
   "type_ref": "CP_CPC_SCRATCH_INDEX"

1405
  },

1406
  {

1407
   "chips": ["gfx81"],

1408
   "map": {"at": 33348, "to": "mm"},

1409
   "name": "CP_CPC_SCRATCH_DATA"

1410
  },

1411
  {

1412
   "chips": ["gfx81"],

1413
   "map": {"at": 33436, "to": "mm"},

1414
   "name": "CP_CPC_HALT_HYST_COUNT",

1415
   "type_ref": "CP_CPC_HALT_HYST_COUNT"

1416
  },

1417
  {

1418
   "chips": ["gfx81"],

1419
   "map": {"at": 36416, "to": "mm"},

1420
   "name": "SQ_THREAD_TRACE_CNTR"

1421
  },

1422
  {

1423
   "chips": ["gfx81"],

1424
   "map": {"at": 36608, "to": "mm"},

1425
   "name": "SQ_BUF_RSRC_WORD0"

1426
  },

1427
  {

1428
   "chips": ["gfx81"],

1429
   "map": {"at": 36612, "to": "mm"},

1430
   "name": "SQ_BUF_RSRC_WORD1",

1431
   "type_ref": "SQ_BUF_RSRC_WORD1"

1432
  },

1433
  {

1434
   "chips": ["gfx81"],

1435
   "map": {"at": 36616, "to": "mm"},

1436
   "name": "SQ_BUF_RSRC_WORD2"

1437
  },

1438
  {

1439
   "chips": ["gfx81"],

1440
   "map": {"at": 36620, "to": "mm"},

1441
   "name": "SQ_BUF_RSRC_WORD3",

1442
   "type_ref": "SQ_BUF_RSRC_WORD3"

1443
  },

1444
  {

1445
   "chips": ["gfx81"],

1446
   "map": {"at": 36624, "to": "mm"},

1447
   "name": "SQ_IMG_RSRC_WORD0"

1448
  },

1449
  {

1450
   "chips": ["gfx81"],

1451
   "map": {"at": 36628, "to": "mm"},

1452
   "name": "SQ_IMG_RSRC_WORD1",

1453
   "type_ref": "SQ_IMG_RSRC_WORD1"

1454
  },

1455
  {

1456
   "chips": ["gfx81"],

1457
   "map": {"at": 36632, "to": "mm"},

1458
   "name": "SQ_IMG_RSRC_WORD2",

1459
   "type_ref": "SQ_IMG_RSRC_WORD2"

1460
  },

1461
  {

1462
   "chips": ["gfx81"],

1463
   "map": {"at": 36636, "to": "mm"},

1464
   "name": "SQ_IMG_RSRC_WORD3",

1465
   "type_ref": "SQ_IMG_RSRC_WORD3"

1466
  },

1467
  {

1468
   "chips": ["gfx81"],

1469
   "map": {"at": 36640, "to": "mm"},

1470
   "name": "SQ_IMG_RSRC_WORD4",

1471
   "type_ref": "SQ_IMG_RSRC_WORD4"

1472
  },

1473
  {

1474
   "chips": ["gfx81"],

1475
   "map": {"at": 36644, "to": "mm"},

1476
   "name": "SQ_IMG_RSRC_WORD5",

1477
   "type_ref": "SQ_IMG_RSRC_WORD5"

1478
  },

1479
  {

1480
   "chips": ["gfx81"],

1481
   "map": {"at": 36648, "to": "mm"},

1482
   "name": "SQ_IMG_RSRC_WORD6",

1483
   "type_ref": "SQ_IMG_RSRC_WORD6"

1484
  },

1485
  {

1486
   "chips": ["gfx81"],

1487
   "map": {"at": 36652, "to": "mm"},

1488
   "name": "SQ_IMG_RSRC_WORD7"

1489
  },

1490
  {

1491
   "chips": ["gfx81"],

1492
   "map": {"at": 36656, "to": "mm"},

1493
   "name": "SQ_IMG_SAMP_WORD0",

1494
   "type_ref": "SQ_IMG_SAMP_WORD0"

1495
  },

1496
  {

1497
   "chips": ["gfx81"],

1498
   "map": {"at": 36660, "to": "mm"},

1499
   "name": "SQ_IMG_SAMP_WORD1",

1500
   "type_ref": "SQ_IMG_SAMP_WORD1"

1501
  },

1502
  {

1503
   "chips": ["gfx81"],

1504
   "map": {"at": 36664, "to": "mm"},

1505
   "name": "SQ_IMG_SAMP_WORD2",

1506
   "type_ref": "SQ_IMG_SAMP_WORD2"

1507
  },

1508
  {

1509
   "chips": ["gfx81"],

1510
   "map": {"at": 36668, "to": "mm"},

1511
   "name": "SQ_IMG_SAMP_WORD3",

1512
   "type_ref": "SQ_IMG_SAMP_WORD3"

1513
  },

1514
  {

1515
   "chips": ["gfx81"],

1516
   "map": {"at": 37120, "to": "mm"},

1517
   "name": "SPI_CONFIG_CNTL",

1518
   "type_ref": "SPI_CONFIG_CNTL"

1519
  },

1520
  {

1521
   "chips": ["gfx81"],

1522
   "map": {"at": 39160, "to": "mm"},

1523
   "name": "GB_ADDR_CONFIG",

1524
   "type_ref": "GB_ADDR_CONFIG"

1525
  },

1526
  {

1527
   "chips": ["gfx81"],

1528
   "map": {"at": 39184, "to": "mm"},

1529
   "name": "GB_TILE_MODE0",

1530
   "type_ref": "GB_TILE_MODE0"

1531
  },

1532
  {

1533
   "chips": ["gfx81"],

1534
   "map": {"at": 39188, "to": "mm"},

1535
   "name": "GB_TILE_MODE1",

1536
   "type_ref": "GB_TILE_MODE0"

1537
  },

1538
  {

1539
   "chips": ["gfx81"],

1540
   "map": {"at": 39192, "to": "mm"},

1541
   "name": "GB_TILE_MODE2",

1542
   "type_ref": "GB_TILE_MODE0"

1543
  },

1544
  {

1545
   "chips": ["gfx81"],

1546
   "map": {"at": 39196, "to": "mm"},

1547
   "name": "GB_TILE_MODE3",

1548
   "type_ref": "GB_TILE_MODE0"

1549
  },

1550
  {

1551
   "chips": ["gfx81"],

1552
   "map": {"at": 39200, "to": "mm"},

1553
   "name": "GB_TILE_MODE4",

1554
   "type_ref": "GB_TILE_MODE0"

1555
  },

1556
  {

1557
   "chips": ["gfx81"],

1558
   "map": {"at": 39204, "to": "mm"},

1559
   "name": "GB_TILE_MODE5",

1560
   "type_ref": "GB_TILE_MODE0"

1561
  },

1562
  {

1563
   "chips": ["gfx81"],

1564
   "map": {"at": 39208, "to": "mm"},

1565
   "name": "GB_TILE_MODE6",

1566
   "type_ref": "GB_TILE_MODE0"

1567
  },

1568
  {

1569
   "chips": ["gfx81"],

1570
   "map": {"at": 39212, "to": "mm"},

1571
   "name": "GB_TILE_MODE7",

1572
   "type_ref": "GB_TILE_MODE0"

1573
  },

1574
  {

1575
   "chips": ["gfx81"],

1576
   "map": {"at": 39216, "to": "mm"},

1577
   "name": "GB_TILE_MODE8",

1578
   "type_ref": "GB_TILE_MODE0"

1579
  },

1580
  {

1581
   "chips": ["gfx81"],

1582
   "map": {"at": 39220, "to": "mm"},

1583
   "name": "GB_TILE_MODE9",

1584
   "type_ref": "GB_TILE_MODE0"

1585
  },

1586
  {

1587
   "chips": ["gfx81"],

1588
   "map": {"at": 39224, "to": "mm"},

1589
   "name": "GB_TILE_MODE10",

1590
   "type_ref": "GB_TILE_MODE0"

1591
  },

1592
  {

1593
   "chips": ["gfx81"],

1594
   "map": {"at": 39228, "to": "mm"},

1595
   "name": "GB_TILE_MODE11",

1596
   "type_ref": "GB_TILE_MODE0"

1597
  },

1598
  {

1599
   "chips": ["gfx81"],

1600
   "map": {"at": 39232, "to": "mm"},

1601
   "name": "GB_TILE_MODE12",

1602
   "type_ref": "GB_TILE_MODE0"

1603
  },

1604
  {

1605
   "chips": ["gfx81"],

1606
   "map": {"at": 39236, "to": "mm"},

1607
   "name": "GB_TILE_MODE13",

1608
   "type_ref": "GB_TILE_MODE0"

1609
  },

1610
  {

1611
   "chips": ["gfx81"],

1612
   "map": {"at": 39240, "to": "mm"},

1613
   "name": "GB_TILE_MODE14",

1614
   "type_ref": "GB_TILE_MODE0"

1615
  },

1616
  {

1617
   "chips": ["gfx81"],

1618
   "map": {"at": 39244, "to": "mm"},

1619
   "name": "GB_TILE_MODE15",

1620
   "type_ref": "GB_TILE_MODE0"

1621
  },

1622
  {

1623
   "chips": ["gfx81"],

1624
   "map": {"at": 39248, "to": "mm"},

1625
   "name": "GB_TILE_MODE16",

1626
   "type_ref": "GB_TILE_MODE0"

1627
  },

1628
  {

1629
   "chips": ["gfx81"],

1630
   "map": {"at": 39252, "to": "mm"},

1631
   "name": "GB_TILE_MODE17",

1632
   "type_ref": "GB_TILE_MODE0"

1633
  },

1634
  {

1635
   "chips": ["gfx81"],

1636
   "map": {"at": 39256, "to": "mm"},

1637
   "name": "GB_TILE_MODE18",

1638
   "type_ref": "GB_TILE_MODE0"

1639
  },

1640
  {

1641
   "chips": ["gfx81"],

1642
   "map": {"at": 39260, "to": "mm"},

1643
   "name": "GB_TILE_MODE19",

1644
   "type_ref": "GB_TILE_MODE0"

1645
  },

1646
  {

1647
   "chips": ["gfx81"],

1648
   "map": {"at": 39264, "to": "mm"},

1649
   "name": "GB_TILE_MODE20",

1650
   "type_ref": "GB_TILE_MODE0"

1651
  },

1652
  {

1653
   "chips": ["gfx81"],

1654
   "map": {"at": 39268, "to": "mm"},

1655
   "name": "GB_TILE_MODE21",

1656
   "type_ref": "GB_TILE_MODE0"

1657
  },

1658
  {

1659
   "chips": ["gfx81"],

1660
   "map": {"at": 39272, "to": "mm"},

1661
   "name": "GB_TILE_MODE22",

1662
   "type_ref": "GB_TILE_MODE0"

1663
  },

1664
  {

1665
   "chips": ["gfx81"],

1666
   "map": {"at": 39276, "to": "mm"},

1667
   "name": "GB_TILE_MODE23",

1668
   "type_ref": "GB_TILE_MODE0"

1669
  },

1670
  {

1671
   "chips": ["gfx81"],

1672
   "map": {"at": 39280, "to": "mm"},

1673
   "name": "GB_TILE_MODE24",

1674
   "type_ref": "GB_TILE_MODE0"

1675
  },

1676
  {

1677
   "chips": ["gfx81"],

1678
   "map": {"at": 39284, "to": "mm"},

1679
   "name": "GB_TILE_MODE25",

1680
   "type_ref": "GB_TILE_MODE0"

1681
  },

1682
  {

1683
   "chips": ["gfx81"],

1684
   "map": {"at": 39288, "to": "mm"},

1685
   "name": "GB_TILE_MODE26",

1686
   "type_ref": "GB_TILE_MODE0"

1687
  },

1688
  {

1689
   "chips": ["gfx81"],

1690
   "map": {"at": 39292, "to": "mm"},

1691
   "name": "GB_TILE_MODE27",

1692
   "type_ref": "GB_TILE_MODE0"

1693
  },

1694
  {

1695
   "chips": ["gfx81"],

1696
   "map": {"at": 39296, "to": "mm"},

1697
   "name": "GB_TILE_MODE28",

1698
   "type_ref": "GB_TILE_MODE0"

1699
  },

1700
  {

1701
   "chips": ["gfx81"],

1702
   "map": {"at": 39300, "to": "mm"},

1703
   "name": "GB_TILE_MODE29",

1704
   "type_ref": "GB_TILE_MODE0"

1705
  },

1706
  {

1707
   "chips": ["gfx81"],

1708
   "map": {"at": 39304, "to": "mm"},

1709
   "name": "GB_TILE_MODE30",

1710
   "type_ref": "GB_TILE_MODE0"

1711
  },

1712
  {

1713
   "chips": ["gfx81"],

1714
   "map": {"at": 39308, "to": "mm"},

1715
   "name": "GB_TILE_MODE31",

1716
   "type_ref": "GB_TILE_MODE0"

1717
  },

1718
  {

1719
   "chips": ["gfx81"],

1720
   "map": {"at": 39312, "to": "mm"},

1721
   "name": "GB_MACROTILE_MODE0",

1722
   "type_ref": "GB_MACROTILE_MODE0"

1723
  },

1724
  {

1725
   "chips": ["gfx81"],

1726
   "map": {"at": 39316, "to": "mm"},

1727
   "name": "GB_MACROTILE_MODE1",

1728
   "type_ref": "GB_MACROTILE_MODE0"

1729
  },

1730
  {

1731
   "chips": ["gfx81"],

1732
   "map": {"at": 39320, "to": "mm"},

1733
   "name": "GB_MACROTILE_MODE2",

1734
   "type_ref": "GB_MACROTILE_MODE0"

1735
  },

1736
  {

1737
   "chips": ["gfx81"],

1738
   "map": {"at": 39324, "to": "mm"},

1739
   "name": "GB_MACROTILE_MODE3",

1740
   "type_ref": "GB_MACROTILE_MODE0"

1741
  },

1742
  {

1743
   "chips": ["gfx81"],

1744
   "map": {"at": 39328, "to": "mm"},

1745
   "name": "GB_MACROTILE_MODE4",

1746
   "type_ref": "GB_MACROTILE_MODE0"

1747
  },

1748
  {

1749
   "chips": ["gfx81"],

1750
   "map": {"at": 39332, "to": "mm"},

1751
   "name": "GB_MACROTILE_MODE5",

1752
   "type_ref": "GB_MACROTILE_MODE0"

1753
  },

1754
  {

1755
   "chips": ["gfx81"],

1756
   "map": {"at": 39336, "to": "mm"},

1757
   "name": "GB_MACROTILE_MODE6",

1758
   "type_ref": "GB_MACROTILE_MODE0"

1759
  },

1760
  {

1761
   "chips": ["gfx81"],

1762
   "map": {"at": 39340, "to": "mm"},

1763
   "name": "GB_MACROTILE_MODE7",

1764
   "type_ref": "GB_MACROTILE_MODE0"

1765
  },

1766
  {

1767
   "chips": ["gfx81"],

1768
   "map": {"at": 39344, "to": "mm"},

1769
   "name": "GB_MACROTILE_MODE8",

1770
   "type_ref": "GB_MACROTILE_MODE0"

1771
  },

1772
  {

1773
   "chips": ["gfx81"],

1774
   "map": {"at": 39348, "to": "mm"},

1775
   "name": "GB_MACROTILE_MODE9",

1776
   "type_ref": "GB_MACROTILE_MODE0"

1777
  },

1778
  {

1779
   "chips": ["gfx81"],

1780
   "map": {"at": 39352, "to": "mm"},

1781
   "name": "GB_MACROTILE_MODE10",

1782
   "type_ref": "GB_MACROTILE_MODE0"

1783
  },

1784
  {

1785
   "chips": ["gfx81"],

1786
   "map": {"at": 39356, "to": "mm"},

1787
   "name": "GB_MACROTILE_MODE11",

1788
   "type_ref": "GB_MACROTILE_MODE0"

1789
  },

1790
  {

1791
   "chips": ["gfx81"],

1792
   "map": {"at": 39360, "to": "mm"},

1793
   "name": "GB_MACROTILE_MODE12",

1794
   "type_ref": "GB_MACROTILE_MODE0"

1795
  },

1796
  {

1797
   "chips": ["gfx81"],

1798
   "map": {"at": 39364, "to": "mm"},

1799
   "name": "GB_MACROTILE_MODE13",

1800
   "type_ref": "GB_MACROTILE_MODE0"

1801
  },

1802
  {

1803
   "chips": ["gfx81"],

1804
   "map": {"at": 39368, "to": "mm"},

1805
   "name": "GB_MACROTILE_MODE14",

1806
   "type_ref": "GB_MACROTILE_MODE0"

1807
  },

1808
  {

1809
   "chips": ["gfx81"],

1810
   "map": {"at": 39372, "to": "mm"},

1811
   "name": "GB_MACROTILE_MODE15",

1812
   "type_ref": "GB_MACROTILE_MODE0"

1813
  },

1814
  {

1815
   "chips": ["gfx81"],

1816
   "map": {"at": 45056, "to": "mm"},

1817
   "name": "SPI_SHADER_TBA_LO_PS"

1818
  },

1819
  {

1820
   "chips": ["gfx81"],

1821
   "map": {"at": 45060, "to": "mm"},

1822
   "name": "SPI_SHADER_TBA_HI_PS",

1823
   "type_ref": "SPI_SHADER_TBA_HI_PS"

1824
  },

1825
  {

1826
   "chips": ["gfx81"],

1827
   "map": {"at": 45064, "to": "mm"},

1828
   "name": "SPI_SHADER_TMA_LO_PS"

1829
  },

1830
  {

1831
   "chips": ["gfx81"],

1832
   "map": {"at": 45068, "to": "mm"},

1833
   "name": "SPI_SHADER_TMA_HI_PS",

1834
   "type_ref": "SPI_SHADER_TBA_HI_PS"

1835
  },

1836
  {

1837
   "chips": ["gfx81"],

1838
   "map": {"at": 45084, "to": "mm"},

1839
   "name": "SPI_SHADER_PGM_RSRC3_PS",

1840
   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"

1841
  },

1842
  {

1843
   "chips": ["gfx81"],

1844
   "map": {"at": 45088, "to": "mm"},

1845
   "name": "SPI_SHADER_PGM_LO_PS"

1846
  },

1847
  {

1848
   "chips": ["gfx81"],

1849
   "map": {"at": 45092, "to": "mm"},

1850
   "name": "SPI_SHADER_PGM_HI_PS",

1851
   "type_ref": "SPI_SHADER_TBA_HI_PS"

1852
  },

1853
  {

1854
   "chips": ["gfx81"],

1855
   "map": {"at": 45096, "to": "mm"},

1856
   "name": "SPI_SHADER_PGM_RSRC1_PS",

1857
   "type_ref": "SPI_SHADER_PGM_RSRC1_PS"

1858
  },

1859
  {

1860
   "chips": ["gfx81"],

1861
   "map": {"at": 45100, "to": "mm"},

1862
   "name": "SPI_SHADER_PGM_RSRC2_PS",

1863
   "type_ref": "SPI_SHADER_PGM_RSRC2_PS"

1864
  },

1865
  {

1866
   "chips": ["gfx81"],

1867
   "map": {"at": 45104, "to": "mm"},

1868
   "name": "SPI_SHADER_USER_DATA_PS_0"

1869
  },

1870
  {

1871
   "chips": ["gfx81"],

1872
   "map": {"at": 45108, "to": "mm"},

1873
   "name": "SPI_SHADER_USER_DATA_PS_1"

1874
  },

1875
  {

1876
   "chips": ["gfx81"],

1877
   "map": {"at": 45112, "to": "mm"},

1878
   "name": "SPI_SHADER_USER_DATA_PS_2"

1879
  },

1880
  {

1881
   "chips": ["gfx81"],

1882
   "map": {"at": 45116, "to": "mm"},

1883
   "name": "SPI_SHADER_USER_DATA_PS_3"

1884
  },

1885
  {

1886
   "chips": ["gfx81"],

1887
   "map": {"at": 45120, "to": "mm"},

1888
   "name": "SPI_SHADER_USER_DATA_PS_4"

1889
  },

1890
  {

1891
   "chips": ["gfx81"],

1892
   "map": {"at": 45124, "to": "mm"},

1893
   "name": "SPI_SHADER_USER_DATA_PS_5"

1894
  },

1895
  {

1896
   "chips": ["gfx81"],

1897
   "map": {"at": 45128, "to": "mm"},

1898
   "name": "SPI_SHADER_USER_DATA_PS_6"

1899
  },

1900
  {

1901
   "chips": ["gfx81"],

1902
   "map": {"at": 45132, "to": "mm"},

1903
   "name": "SPI_SHADER_USER_DATA_PS_7"

1904
  },

1905
  {

1906
   "chips": ["gfx81"],

1907
   "map": {"at": 45136, "to": "mm"},

1908
   "name": "SPI_SHADER_USER_DATA_PS_8"

1909
  },

1910
  {

1911
   "chips": ["gfx81"],

1912
   "map": {"at": 45140, "to": "mm"},

1913
   "name": "SPI_SHADER_USER_DATA_PS_9"

1914
  },

1915
  {

1916
   "chips": ["gfx81"],

1917
   "map": {"at": 45144, "to": "mm"},

1918
   "name": "SPI_SHADER_USER_DATA_PS_10"

1919
  },

1920
  {

1921
   "chips": ["gfx81"],

1922
   "map": {"at": 45148, "to": "mm"},

1923
   "name": "SPI_SHADER_USER_DATA_PS_11"

1924
  },

1925
  {

1926
   "chips": ["gfx81"],

1927
   "map": {"at": 45152, "to": "mm"},

1928
   "name": "SPI_SHADER_USER_DATA_PS_12"

1929
  },

1930
  {

1931
   "chips": ["gfx81"],

1932
   "map": {"at": 45156, "to": "mm"},

1933
   "name": "SPI_SHADER_USER_DATA_PS_13"

1934
  },

1935
  {

1936
   "chips": ["gfx81"],

1937
   "map": {"at": 45160, "to": "mm"},

1938
   "name": "SPI_SHADER_USER_DATA_PS_14"

1939
  },

1940
  {

1941
   "chips": ["gfx81"],

1942
   "map": {"at": 45164, "to": "mm"},

1943
   "name": "SPI_SHADER_USER_DATA_PS_15"

1944
  },

1945
  {

1946
   "chips": ["gfx81"],

1947
   "map": {"at": 45312, "to": "mm"},

1948
   "name": "SPI_SHADER_TBA_LO_VS"

1949
  },

1950
  {

1951
   "chips": ["gfx81"],

1952
   "map": {"at": 45316, "to": "mm"},

1953
   "name": "SPI_SHADER_TBA_HI_VS",

1954
   "type_ref": "SPI_SHADER_TBA_HI_PS"

1955
  },

1956
  {

1957
   "chips": ["gfx81"],

1958
   "map": {"at": 45320, "to": "mm"},

1959
   "name": "SPI_SHADER_TMA_LO_VS"

1960
  },

1961
  {

1962
   "chips": ["gfx81"],

1963
   "map": {"at": 45324, "to": "mm"},

1964
   "name": "SPI_SHADER_TMA_HI_VS",

1965
   "type_ref": "SPI_SHADER_TBA_HI_PS"

1966
  },

1967
  {

1968
   "chips": ["gfx81"],

1969
   "map": {"at": 45336, "to": "mm"},

1970
   "name": "SPI_SHADER_PGM_RSRC3_VS",

1971
   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"

1972
  },

1973
  {

1974
   "chips": ["gfx81"],

1975
   "map": {"at": 45340, "to": "mm"},

1976
   "name": "SPI_SHADER_LATE_ALLOC_VS",

1977
   "type_ref": "SPI_SHADER_LATE_ALLOC_VS"

1978
  },

1979
  {

1980
   "chips": ["gfx81"],

1981
   "map": {"at": 45344, "to": "mm"},

1982
   "name": "SPI_SHADER_PGM_LO_VS"

1983
  },

1984
  {

1985
   "chips": ["gfx81"],

1986
   "map": {"at": 45348, "to": "mm"},

1987
   "name": "SPI_SHADER_PGM_HI_VS",

1988
   "type_ref": "SPI_SHADER_TBA_HI_PS"

1989
  },

1990
  {

1991
   "chips": ["gfx81"],

1992
   "map": {"at": 45352, "to": "mm"},

1993
   "name": "SPI_SHADER_PGM_RSRC1_VS",

1994
   "type_ref": "SPI_SHADER_PGM_RSRC1_VS"

1995
  },

1996
  {

1997
   "chips": ["gfx81"],

1998
   "map": {"at": 45356, "to": "mm"},

1999
   "name": "SPI_SHADER_PGM_RSRC2_VS",

2000
   "type_ref": "SPI_SHADER_PGM_RSRC2_VS"

2001
  },

2002
  {

2003
   "chips": ["gfx81"],

2004
   "map": {"at": 45360, "to": "mm"},

2005
   "name": "SPI_SHADER_USER_DATA_VS_0"

2006
  },

2007
  {

2008
   "chips": ["gfx81"],

2009
   "map": {"at": 45364, "to": "mm"},

2010
   "name": "SPI_SHADER_USER_DATA_VS_1"

2011
  },

2012
  {

2013
   "chips": ["gfx81"],

2014
   "map": {"at": 45368, "to": "mm"},

2015
   "name": "SPI_SHADER_USER_DATA_VS_2"

2016
  },

2017
  {

2018
   "chips": ["gfx81"],

2019
   "map": {"at": 45372, "to": "mm"},

2020
   "name": "SPI_SHADER_USER_DATA_VS_3"

2021
  },

2022
  {

2023
   "chips": ["gfx81"],

2024
   "map": {"at": 45376, "to": "mm"},

2025
   "name": "SPI_SHADER_USER_DATA_VS_4"

2026
  },

2027
  {

2028
   "chips": ["gfx81"],

2029
   "map": {"at": 45380, "to": "mm"},

2030
   "name": "SPI_SHADER_USER_DATA_VS_5"

2031
  },

2032
  {

2033
   "chips": ["gfx81"],

2034
   "map": {"at": 45384, "to": "mm"},

2035
   "name": "SPI_SHADER_USER_DATA_VS_6"

2036
  },

2037
  {

2038
   "chips": ["gfx81"],

2039
   "map": {"at": 45388, "to": "mm"},

2040
   "name": "SPI_SHADER_USER_DATA_VS_7"

2041
  },

2042
  {

2043
   "chips": ["gfx81"],

2044
   "map": {"at": 45392, "to": "mm"},

2045
   "name": "SPI_SHADER_USER_DATA_VS_8"

2046
  },

2047
  {

2048
   "chips": ["gfx81"],

2049
   "map": {"at": 45396, "to": "mm"},

2050
   "name": "SPI_SHADER_USER_DATA_VS_9"

2051
  },

2052
  {

2053
   "chips": ["gfx81"],

2054
   "map": {"at": 45400, "to": "mm"},

2055
   "name": "SPI_SHADER_USER_DATA_VS_10"

2056
  },

2057
  {

2058
   "chips": ["gfx81"],

2059
   "map": {"at": 45404, "to": "mm"},

2060
   "name": "SPI_SHADER_USER_DATA_VS_11"

2061
  },

2062
  {

2063
   "chips": ["gfx81"],

2064
   "map": {"at": 45408, "to": "mm"},

2065
   "name": "SPI_SHADER_USER_DATA_VS_12"

2066
  },

2067
  {

2068
   "chips": ["gfx81"],

2069
   "map": {"at": 45412, "to": "mm"},

2070
   "name": "SPI_SHADER_USER_DATA_VS_13"

2071
  },

2072
  {

2073
   "chips": ["gfx81"],

2074
   "map": {"at": 45416, "to": "mm"},

2075
   "name": "SPI_SHADER_USER_DATA_VS_14"

2076
  },

2077
  {

2078
   "chips": ["gfx81"],

2079
   "map": {"at": 45420, "to": "mm"},

2080
   "name": "SPI_SHADER_USER_DATA_VS_15"

2081
  },

2082
  {

2083
   "chips": ["gfx81"],

2084
   "map": {"at": 45552, "to": "mm"},

2085
   "name": "SPI_SHADER_PGM_RSRC2_ES_VS",

2086
   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"

2087
  },

2088
  {

2089
   "chips": ["gfx81"],

2090
   "map": {"at": 45556, "to": "mm"},

2091
   "name": "SPI_SHADER_PGM_RSRC2_LS_VS",

2092
   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"

2093
  },

2094
  {

2095
   "chips": ["gfx81"],

2096
   "map": {"at": 45568, "to": "mm"},

2097
   "name": "SPI_SHADER_TBA_LO_GS"

2098
  },

2099
  {

2100
   "chips": ["gfx81"],

2101
   "map": {"at": 45572, "to": "mm"},

2102
   "name": "SPI_SHADER_TBA_HI_GS",

2103
   "type_ref": "SPI_SHADER_TBA_HI_PS"

2104
  },

2105
  {

2106
   "chips": ["gfx81"],

2107
   "map": {"at": 45576, "to": "mm"},

2108
   "name": "SPI_SHADER_TMA_LO_GS"

2109
  },

2110
  {

2111
   "chips": ["gfx81"],

2112
   "map": {"at": 45580, "to": "mm"},

2113
   "name": "SPI_SHADER_TMA_HI_GS",

2114
   "type_ref": "SPI_SHADER_TBA_HI_PS"

2115
  },

2116
  {

2117
   "chips": ["gfx81"],

2118
   "map": {"at": 45596, "to": "mm"},

2119
   "name": "SPI_SHADER_PGM_RSRC3_GS",

2120
   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"

2121
  },

2122
  {

2123
   "chips": ["gfx81"],

2124
   "map": {"at": 45600, "to": "mm"},

2125
   "name": "SPI_SHADER_PGM_LO_GS"

2126
  },

2127
  {

2128
   "chips": ["gfx81"],

2129
   "map": {"at": 45604, "to": "mm"},

2130
   "name": "SPI_SHADER_PGM_HI_GS",

2131
   "type_ref": "SPI_SHADER_TBA_HI_PS"

2132
  },

2133
  {

2134
   "chips": ["gfx81"],

2135
   "map": {"at": 45608, "to": "mm"},

2136
   "name": "SPI_SHADER_PGM_RSRC1_GS",

2137
   "type_ref": "SPI_SHADER_PGM_RSRC1_GS"

2138
  },

2139
  {

2140
   "chips": ["gfx81"],

2141
   "map": {"at": 45612, "to": "mm"},

2142
   "name": "SPI_SHADER_PGM_RSRC2_GS",

2143
   "type_ref": "SPI_SHADER_PGM_RSRC2_GS"

2144
  },

2145
  {

2146
   "chips": ["gfx81"],

2147
   "map": {"at": 45616, "to": "mm"},

2148
   "name": "SPI_SHADER_USER_DATA_GS_0"

2149
  },

2150
  {

2151
   "chips": ["gfx81"],

2152
   "map": {"at": 45620, "to": "mm"},

2153
   "name": "SPI_SHADER_USER_DATA_GS_1"

2154
  },

2155
  {

2156
   "chips": ["gfx81"],

2157
   "map": {"at": 45624, "to": "mm"},

2158
   "name": "SPI_SHADER_USER_DATA_GS_2"

2159
  },

2160
  {

2161
   "chips": ["gfx81"],

2162
   "map": {"at": 45628, "to": "mm"},

2163
   "name": "SPI_SHADER_USER_DATA_GS_3"

2164
  },

2165
  {

2166
   "chips": ["gfx81"],

2167
   "map": {"at": 45632, "to": "mm"},

2168
   "name": "SPI_SHADER_USER_DATA_GS_4"

2169
  },

2170
  {

2171
   "chips": ["gfx81"],

2172
   "map": {"at": 45636, "to": "mm"},

2173
   "name": "SPI_SHADER_USER_DATA_GS_5"

2174
  },

2175
  {

2176
   "chips": ["gfx81"],

2177
   "map": {"at": 45640, "to": "mm"},

2178
   "name": "SPI_SHADER_USER_DATA_GS_6"

2179
  },

2180
  {

2181
   "chips": ["gfx81"],

2182
   "map": {"at": 45644, "to": "mm"},

2183
   "name": "SPI_SHADER_USER_DATA_GS_7"

2184
  },

2185
  {

2186
   "chips": ["gfx81"],

2187
   "map": {"at": 45648, "to": "mm"},

2188
   "name": "SPI_SHADER_USER_DATA_GS_8"

2189
  },

2190
  {

2191
   "chips": ["gfx81"],

2192
   "map": {"at": 45652, "to": "mm"},

2193
   "name": "SPI_SHADER_USER_DATA_GS_9"

2194
  },

2195
  {

2196
   "chips": ["gfx81"],

2197
   "map": {"at": 45656, "to": "mm"},

2198
   "name": "SPI_SHADER_USER_DATA_GS_10"

2199
  },

2200
  {

2201
   "chips": ["gfx81"],

2202
   "map": {"at": 45660, "to": "mm"},

2203
   "name": "SPI_SHADER_USER_DATA_GS_11"

2204
  },

2205
  {

2206
   "chips": ["gfx81"],

2207
   "map": {"at": 45664, "to": "mm"},

2208
   "name": "SPI_SHADER_USER_DATA_GS_12"

2209
  },

2210
  {

2211
   "chips": ["gfx81"],

2212
   "map": {"at": 45668, "to": "mm"},

2213
   "name": "SPI_SHADER_USER_DATA_GS_13"

2214
  },

2215
  {

2216
   "chips": ["gfx81"],

2217
   "map": {"at": 45672, "to": "mm"},

2218
   "name": "SPI_SHADER_USER_DATA_GS_14"

2219
  },

2220
  {

2221
   "chips": ["gfx81"],

2222
   "map": {"at": 45676, "to": "mm"},

2223
   "name": "SPI_SHADER_USER_DATA_GS_15"

2224
  },

2225
  {

2226
   "chips": ["gfx81"],

2227
   "map": {"at": 45808, "to": "mm"},

2228
   "name": "SPI_SHADER_PGM_RSRC2_ES_GS",

2229
   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"

2230
  },

2231
  {

2232
   "chips": ["gfx81"],

2233
   "map": {"at": 45824, "to": "mm"},

2234
   "name": "SPI_SHADER_TBA_LO_ES"

2235
  },

2236
  {

2237
   "chips": ["gfx81"],

2238
   "map": {"at": 45828, "to": "mm"},

2239
   "name": "SPI_SHADER_TBA_HI_ES",

2240
   "type_ref": "SPI_SHADER_TBA_HI_PS"

2241
  },

2242
  {

2243
   "chips": ["gfx81"],

2244
   "map": {"at": 45832, "to": "mm"},

2245
   "name": "SPI_SHADER_TMA_LO_ES"

2246
  },

2247
  {

2248
   "chips": ["gfx81"],

2249
   "map": {"at": 45836, "to": "mm"},

2250
   "name": "SPI_SHADER_TMA_HI_ES",

2251
   "type_ref": "SPI_SHADER_TBA_HI_PS"

2252
  },

2253
  {

2254
   "chips": ["gfx81"],

2255
   "map": {"at": 45852, "to": "mm"},

2256
   "name": "SPI_SHADER_PGM_RSRC3_ES",

2257
   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"

2258
  },

2259
  {

2260
   "chips": ["gfx81"],

2261
   "map": {"at": 45856, "to": "mm"},

2262
   "name": "SPI_SHADER_PGM_LO_ES"

2263
  },

2264
  {

2265
   "chips": ["gfx81"],

2266
   "map": {"at": 45860, "to": "mm"},

2267
   "name": "SPI_SHADER_PGM_HI_ES",

2268
   "type_ref": "SPI_SHADER_TBA_HI_PS"

2269
  },

2270
  {

2271
   "chips": ["gfx81"],

2272
   "map": {"at": 45864, "to": "mm"},

2273
   "name": "SPI_SHADER_PGM_RSRC1_ES",

2274
   "type_ref": "SPI_SHADER_PGM_RSRC1_VS"

2275
  },

2276
  {

2277
   "chips": ["gfx81"],

2278
   "map": {"at": 45868, "to": "mm"},

2279
   "name": "SPI_SHADER_PGM_RSRC2_ES",

2280
   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"

2281
  },

2282
  {

2283
   "chips": ["gfx81"],

2284
   "map": {"at": 45872, "to": "mm"},

2285
   "name": "SPI_SHADER_USER_DATA_ES_0"

2286
  },

2287
  {

2288
   "chips": ["gfx81"],

2289
   "map": {"at": 45876, "to": "mm"},

2290
   "name": "SPI_SHADER_USER_DATA_ES_1"

2291
  },

2292
  {

2293
   "chips": ["gfx81"],

2294
   "map": {"at": 45880, "to": "mm"},

2295
   "name": "SPI_SHADER_USER_DATA_ES_2"

2296
  },

2297
  {

2298
   "chips": ["gfx81"],

2299
   "map": {"at": 45884, "to": "mm"},

2300
   "name": "SPI_SHADER_USER_DATA_ES_3"

2301
  },

2302
  {

2303
   "chips": ["gfx81"],

2304
   "map": {"at": 45888, "to": "mm"},

2305
   "name": "SPI_SHADER_USER_DATA_ES_4"

2306
  },

2307
  {

2308
   "chips": ["gfx81"],

2309
   "map": {"at": 45892, "to": "mm"},

2310
   "name": "SPI_SHADER_USER_DATA_ES_5"

2311
  },

2312
  {

2313
   "chips": ["gfx81"],

2314
   "map": {"at": 45896, "to": "mm"},

2315
   "name": "SPI_SHADER_USER_DATA_ES_6"

2316
  },

2317
  {

2318
   "chips": ["gfx81"],

2319
   "map": {"at": 45900, "to": "mm"},

2320
   "name": "SPI_SHADER_USER_DATA_ES_7"

2321
  },

2322
  {

2323
   "chips": ["gfx81"],

2324
   "map": {"at": 45904, "to": "mm"},

2325
   "name": "SPI_SHADER_USER_DATA_ES_8"

2326
  },

2327
  {

2328
   "chips": ["gfx81"],

2329
   "map": {"at": 45908, "to": "mm"},

2330
   "name": "SPI_SHADER_USER_DATA_ES_9"

2331
  },

2332
  {

2333
   "chips": ["gfx81"],

2334
   "map": {"at": 45912, "to": "mm"},

2335
   "name": "SPI_SHADER_USER_DATA_ES_10"

2336
  },

2337
  {

2338
   "chips": ["gfx81"],

2339
   "map": {"at": 45916, "to": "mm"},

2340
   "name": "SPI_SHADER_USER_DATA_ES_11"

2341
  },

2342
  {

2343
   "chips": ["gfx81"],

2344
   "map": {"at": 45920, "to": "mm"},

2345
   "name": "SPI_SHADER_USER_DATA_ES_12"

2346
  },

2347
  {

2348
   "chips": ["gfx81"],

2349
   "map": {"at": 45924, "to": "mm"},

2350
   "name": "SPI_SHADER_USER_DATA_ES_13"

2351
  },

2352
  {

2353
   "chips": ["gfx81"],

2354
   "map": {"at": 45928, "to": "mm"},

2355
   "name": "SPI_SHADER_USER_DATA_ES_14"

2356
  },

2357
  {

2358
   "chips": ["gfx81"],

2359
   "map": {"at": 45932, "to": "mm"},

2360
   "name": "SPI_SHADER_USER_DATA_ES_15"

2361
  },

2362
  {

2363
   "chips": ["gfx81"],

2364
   "map": {"at": 46068, "to": "mm"},

2365
   "name": "SPI_SHADER_PGM_RSRC2_LS_ES",

2366
   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"

2367
  },

2368
  {

2369
   "chips": ["gfx81"],

2370
   "map": {"at": 46080, "to": "mm"},

2371
   "name": "SPI_SHADER_TBA_LO_HS"

2372
  },

2373
  {

2374
   "chips": ["gfx81"],

2375
   "map": {"at": 46084, "to": "mm"},

2376
   "name": "SPI_SHADER_TBA_HI_HS",

2377
   "type_ref": "SPI_SHADER_TBA_HI_PS"

2378
  },

2379
  {

2380
   "chips": ["gfx81"],

2381
   "map": {"at": 46088, "to": "mm"},

2382
   "name": "SPI_SHADER_TMA_LO_HS"

2383
  },

2384
  {

2385
   "chips": ["gfx81"],

2386
   "map": {"at": 46092, "to": "mm"},

2387
   "name": "SPI_SHADER_TMA_HI_HS",

2388
   "type_ref": "SPI_SHADER_TBA_HI_PS"

2389
  },

2390
  {

2391
   "chips": ["gfx81"],

2392
   "map": {"at": 46108, "to": "mm"},

2393
   "name": "SPI_SHADER_PGM_RSRC3_HS",

2394
   "type_ref": "SPI_SHADER_PGM_RSRC3_HS"

2395
  },

2396
  {

2397
   "chips": ["gfx81"],

2398
   "map": {"at": 46112, "to": "mm"},

2399
   "name": "SPI_SHADER_PGM_LO_HS"

2400
  },

2401
  {

2402
   "chips": ["gfx81"],

2403
   "map": {"at": 46116, "to": "mm"},

2404
   "name": "SPI_SHADER_PGM_HI_HS",

2405
   "type_ref": "SPI_SHADER_TBA_HI_PS"

2406
  },

2407
  {

2408
   "chips": ["gfx81"],

2409
   "map": {"at": 46120, "to": "mm"},

2410
   "name": "SPI_SHADER_PGM_RSRC1_HS",

2411
   "type_ref": "SPI_SHADER_PGM_RSRC1_HS"

2412
  },

2413
  {

2414
   "chips": ["gfx81"],

2415
   "map": {"at": 46124, "to": "mm"},

2416
   "name": "SPI_SHADER_PGM_RSRC2_HS",

2417
   "type_ref": "SPI_SHADER_PGM_RSRC2_HS"

2418
  },

2419
  {

2420
   "chips": ["gfx81"],

2421
   "map": {"at": 46128, "to": "mm"},

2422
   "name": "SPI_SHADER_USER_DATA_HS_0"

2423
  },

2424
  {

2425
   "chips": ["gfx81"],

2426
   "map": {"at": 46132, "to": "mm"},

2427
   "name": "SPI_SHADER_USER_DATA_HS_1"

2428
  },

2429
  {

2430
   "chips": ["gfx81"],

2431
   "map": {"at": 46136, "to": "mm"},

2432
   "name": "SPI_SHADER_USER_DATA_HS_2"

2433
  },

2434
  {

2435
   "chips": ["gfx81"],

2436
   "map": {"at": 46140, "to": "mm"},

2437
   "name": "SPI_SHADER_USER_DATA_HS_3"

2438
  },

2439
  {

2440
   "chips": ["gfx81"],

2441
   "map": {"at": 46144, "to": "mm"},

2442
   "name": "SPI_SHADER_USER_DATA_HS_4"

2443
  },

2444
  {

2445
   "chips": ["gfx81"],

2446
   "map": {"at": 46148, "to": "mm"},

2447
   "name": "SPI_SHADER_USER_DATA_HS_5"

2448
  },

2449
  {

2450
   "chips": ["gfx81"],

2451
   "map": {"at": 46152, "to": "mm"},

2452
   "name": "SPI_SHADER_USER_DATA_HS_6"

2453
  },

2454
  {

2455
   "chips": ["gfx81"],

2456
   "map": {"at": 46156, "to": "mm"},

2457
   "name": "SPI_SHADER_USER_DATA_HS_7"

2458
  },

2459
  {

2460
   "chips": ["gfx81"],

2461
   "map": {"at": 46160, "to": "mm"},

2462
   "name": "SPI_SHADER_USER_DATA_HS_8"

2463
  },

2464
  {

2465
   "chips": ["gfx81"],

2466
   "map": {"at": 46164, "to": "mm"},

2467
   "name": "SPI_SHADER_USER_DATA_HS_9"

2468
  },

2469
  {

2470
   "chips": ["gfx81"],

2471
   "map": {"at": 46168, "to": "mm"},

2472
   "name": "SPI_SHADER_USER_DATA_HS_10"

2473
  },

2474
  {

2475
   "chips": ["gfx81"],

2476
   "map": {"at": 46172, "to": "mm"},

2477
   "name": "SPI_SHADER_USER_DATA_HS_11"

2478
  },

2479
  {

2480
   "chips": ["gfx81"],

2481
   "map": {"at": 46176, "to": "mm"},

2482
   "name": "SPI_SHADER_USER_DATA_HS_12"

2483
  },

2484
  {

2485
   "chips": ["gfx81"],

2486
   "map": {"at": 46180, "to": "mm"},

2487
   "name": "SPI_SHADER_USER_DATA_HS_13"

2488
  },

2489
  {

2490
   "chips": ["gfx81"],

2491
   "map": {"at": 46184, "to": "mm"},

2492
   "name": "SPI_SHADER_USER_DATA_HS_14"

2493
  },

2494
  {

2495
   "chips": ["gfx81"],

2496
   "map": {"at": 46188, "to": "mm"},

2497
   "name": "SPI_SHADER_USER_DATA_HS_15"

2498
  },

2499
  {

2500
   "chips": ["gfx81"],

2501
   "map": {"at": 46324, "to": "mm"},

2502
   "name": "SPI_SHADER_PGM_RSRC2_LS_HS",

2503
   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"

2504
  },

2505
  {

2506
   "chips": ["gfx81"],

2507
   "map": {"at": 46336, "to": "mm"},

2508
   "name": "SPI_SHADER_TBA_LO_LS"

2509
  },

2510
  {

2511
   "chips": ["gfx81"],

2512
   "map": {"at": 46340, "to": "mm"},

2513
   "name": "SPI_SHADER_TBA_HI_LS",

2514
   "type_ref": "SPI_SHADER_TBA_HI_PS"

2515
  },

2516
  {

2517
   "chips": ["gfx81"],

2518
   "map": {"at": 46344, "to": "mm"},

2519
   "name": "SPI_SHADER_TMA_LO_LS"

2520
  },

2521
  {

2522
   "chips": ["gfx81"],

2523
   "map": {"at": 46348, "to": "mm"},

2524
   "name": "SPI_SHADER_TMA_HI_LS",

2525
   "type_ref": "SPI_SHADER_TBA_HI_PS"

2526
  },

2527
  {

2528
   "chips": ["gfx81"],

2529
   "map": {"at": 46364, "to": "mm"},

2530
   "name": "SPI_SHADER_PGM_RSRC3_LS",

2531
   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"

2532
  },

2533
  {

2534
   "chips": ["gfx81"],

2535
   "map": {"at": 46368, "to": "mm"},

2536
   "name": "SPI_SHADER_PGM_LO_LS"

2537
  },

2538
  {

2539
   "chips": ["gfx81"],

2540
   "map": {"at": 46372, "to": "mm"},

2541
   "name": "SPI_SHADER_PGM_HI_LS",

2542
   "type_ref": "SPI_SHADER_TBA_HI_PS"

2543
  },

2544
  {

2545
   "chips": ["gfx81"],

2546
   "map": {"at": 46376, "to": "mm"},

2547
   "name": "SPI_SHADER_PGM_RSRC1_LS",

2548
   "type_ref": "SPI_SHADER_PGM_RSRC1_LS"

2549
  },

2550
  {

2551
   "chips": ["gfx81"],

2552
   "map": {"at": 46380, "to": "mm"},

2553
   "name": "SPI_SHADER_PGM_RSRC2_LS",

2554
   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"

2555
  },

2556
  {

2557
   "chips": ["gfx81"],

2558
   "map": {"at": 46384, "to": "mm"},

2559
   "name": "SPI_SHADER_USER_DATA_LS_0"

2560
  },

2561
  {

2562
   "chips": ["gfx81"],

2563
   "map": {"at": 46388, "to": "mm"},

2564
   "name": "SPI_SHADER_USER_DATA_LS_1"

2565
  },

2566
  {

2567
   "chips": ["gfx81"],

2568
   "map": {"at": 46392, "to": "mm"},

2569
   "name": "SPI_SHADER_USER_DATA_LS_2"

2570
  },

2571
  {

2572
   "chips": ["gfx81"],

2573
   "map": {"at": 46396, "to": "mm"},

2574
   "name": "SPI_SHADER_USER_DATA_LS_3"

2575
  },

2576
  {

2577
   "chips": ["gfx81"],

2578
   "map": {"at": 46400, "to": "mm"},

2579
   "name": "SPI_SHADER_USER_DATA_LS_4"

2580
  },

2581
  {

2582
   "chips": ["gfx81"],

2583
   "map": {"at": 46404, "to": "mm"},

2584
   "name": "SPI_SHADER_USER_DATA_LS_5"

2585
  },

2586
  {

2587
   "chips": ["gfx81"],

2588
   "map": {"at": 46408, "to": "mm"},

2589
   "name": "SPI_SHADER_USER_DATA_LS_6"

2590
  },

2591
  {

2592
   "chips": ["gfx81"],

2593
   "map": {"at": 46412, "to": "mm"},

2594
   "name": "SPI_SHADER_USER_DATA_LS_7"

2595
  },

2596
  {

2597
   "chips": ["gfx81"],

2598
   "map": {"at": 46416, "to": "mm"},

2599
   "name": "SPI_SHADER_USER_DATA_LS_8"

2600
  },

2601
  {

2602
   "chips": ["gfx81"],

2603
   "map": {"at": 46420, "to": "mm"},

2604
   "name": "SPI_SHADER_USER_DATA_LS_9"

2605
  },

2606
  {

2607
   "chips": ["gfx81"],

2608
   "map": {"at": 46424, "to": "mm"},

2609
   "name": "SPI_SHADER_USER_DATA_LS_10"

2610
  },

2611
  {

2612
   "chips": ["gfx81"],

2613
   "map": {"at": 46428, "to": "mm"},

2614
   "name": "SPI_SHADER_USER_DATA_LS_11"

2615
  },

2616
  {

2617
   "chips": ["gfx81"],

2618
   "map": {"at": 46432, "to": "mm"},

2619
   "name": "SPI_SHADER_USER_DATA_LS_12"

2620
  },

2621
  {

2622
   "chips": ["gfx81"],

2623
   "map": {"at": 46436, "to": "mm"},

2624
   "name": "SPI_SHADER_USER_DATA_LS_13"

2625
  },

2626
  {

2627
   "chips": ["gfx81"],

2628
   "map": {"at": 46440, "to": "mm"},

2629
   "name": "SPI_SHADER_USER_DATA_LS_14"

2630
  },

2631
  {

2632
   "chips": ["gfx81"],

2633
   "map": {"at": 46444, "to": "mm"},

2634
   "name": "SPI_SHADER_USER_DATA_LS_15"

2635
  },

2636
  {

2637
   "chips": ["gfx81"],

2638
   "map": {"at": 47104, "to": "mm"},

2639
   "name": "COMPUTE_DISPATCH_INITIATOR",

2640
   "type_ref": "COMPUTE_DISPATCH_INITIATOR"

2641
  },

2642
  {

2643
   "chips": ["gfx81"],

2644
   "map": {"at": 47108, "to": "mm"},

2645
   "name": "COMPUTE_DIM_X"

2646
  },

2647
  {

2648
   "chips": ["gfx81"],

2649
   "map": {"at": 47112, "to": "mm"},

2650
   "name": "COMPUTE_DIM_Y"

2651
  },

2652
  {

2653
   "chips": ["gfx81"],

2654
   "map": {"at": 47116, "to": "mm"},

2655
   "name": "COMPUTE_DIM_Z"

2656
  },

2657
  {

2658
   "chips": ["gfx81"],

2659
   "map": {"at": 47120, "to": "mm"},

2660
   "name": "COMPUTE_START_X"

2661
  },

2662
  {

2663
   "chips": ["gfx81"],

2664
   "map": {"at": 47124, "to": "mm"},

2665
   "name": "COMPUTE_START_Y"

2666
  },

2667
  {

2668
   "chips": ["gfx81"],

2669
   "map": {"at": 47128, "to": "mm"},

2670
   "name": "COMPUTE_START_Z"

2671
  },

2672
  {

2673
   "chips": ["gfx81"],

2674
   "map": {"at": 47132, "to": "mm"},

2675
   "name": "COMPUTE_NUM_THREAD_X",

2676
   "type_ref": "COMPUTE_NUM_THREAD_X"

2677
  },

2678
  {

2679
   "chips": ["gfx81"],

2680
   "map": {"at": 47136, "to": "mm"},

2681
   "name": "COMPUTE_NUM_THREAD_Y",

2682
   "type_ref": "COMPUTE_NUM_THREAD_X"

2683
  },

2684
  {

2685
   "chips": ["gfx81"],

2686
   "map": {"at": 47140, "to": "mm"},

2687
   "name": "COMPUTE_NUM_THREAD_Z",

2688
   "type_ref": "COMPUTE_NUM_THREAD_X"

2689
  },

2690
  {

2691
   "chips": ["gfx81"],

2692
   "map": {"at": 47144, "to": "mm"},

2693
   "name": "COMPUTE_PIPELINESTAT_ENABLE",

2694
   "type_ref": "COMPUTE_PIPELINESTAT_ENABLE"

2695
  },

2696
  {

2697
   "chips": ["gfx81"],

2698
   "map": {"at": 47148, "to": "mm"},

2699
   "name": "COMPUTE_PERFCOUNT_ENABLE",

2700
   "type_ref": "COMPUTE_PERFCOUNT_ENABLE"

2701
  },

2702
  {

2703
   "chips": ["gfx81"],

2704
   "map": {"at": 47152, "to": "mm"},

2705
   "name": "COMPUTE_PGM_LO"

2706
  },

2707
  {

2708
   "chips": ["gfx81"],

2709
   "map": {"at": 47156, "to": "mm"},

2710
   "name": "COMPUTE_PGM_HI",

2711
   "type_ref": "COMPUTE_PGM_HI"

2712
  },

2713
  {

2714
   "chips": ["gfx81"],

2715
   "map": {"at": 47160, "to": "mm"},

2716
   "name": "COMPUTE_TBA_LO"

2717
  },

2718
  {

2719
   "chips": ["gfx81"],

2720
   "map": {"at": 47164, "to": "mm"},

2721
   "name": "COMPUTE_TBA_HI",

2722
   "type_ref": "COMPUTE_TBA_HI"

2723
  },

2724
  {

2725
   "chips": ["gfx81"],

2726
   "map": {"at": 47168, "to": "mm"},

2727
   "name": "COMPUTE_TMA_LO"

2728
  },

2729
  {

2730
   "chips": ["gfx81"],

2731
   "map": {"at": 47172, "to": "mm"},

2732
   "name": "COMPUTE_TMA_HI",

2733
   "type_ref": "COMPUTE_TBA_HI"

2734
  },

2735
  {

2736
   "chips": ["gfx81"],

2737
   "map": {"at": 47176, "to": "mm"},

2738
   "name": "COMPUTE_PGM_RSRC1",

2739
   "type_ref": "COMPUTE_PGM_RSRC1"

2740
  },

2741
  {

2742
   "chips": ["gfx81"],

2743
   "map": {"at": 47180, "to": "mm"},

2744
   "name": "COMPUTE_PGM_RSRC2",

2745
   "type_ref": "COMPUTE_PGM_RSRC2"

2746
  },

2747
  {

2748
   "chips": ["gfx81"],

2749
   "map": {"at": 47184, "to": "mm"},

2750
   "name": "COMPUTE_VMID",

2751
   "type_ref": "COMPUTE_VMID"

2752
  },

2753
  {

2754
   "chips": ["gfx81"],

2755
   "map": {"at": 47188, "to": "mm"},

2756
   "name": "COMPUTE_RESOURCE_LIMITS",

2757
   "type_ref": "COMPUTE_RESOURCE_LIMITS"

2758
  },

2759
  {

2760
   "chips": ["gfx81"],

2761
   "map": {"at": 47192, "to": "mm"},

2762
   "name": "COMPUTE_STATIC_THREAD_MGMT_SE0",

2763
   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"

2764
  },

2765
  {

2766
   "chips": ["gfx81"],

2767
   "map": {"at": 47196, "to": "mm"},

2768
   "name": "COMPUTE_STATIC_THREAD_MGMT_SE1",

2769
   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"

2770
  },

2771
  {

2772
   "chips": ["gfx81"],

2773
   "map": {"at": 47200, "to": "mm"},

2774
   "name": "COMPUTE_TMPRING_SIZE",

2775
   "type_ref": "COMPUTE_TMPRING_SIZE"

2776
  },

2777
  {

2778
   "chips": ["gfx81"],

2779
   "map": {"at": 47204, "to": "mm"},

2780
   "name": "COMPUTE_STATIC_THREAD_MGMT_SE2",

2781
   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"

2782
  },

2783
  {

2784
   "chips": ["gfx81"],

2785
   "map": {"at": 47208, "to": "mm"},

2786
   "name": "COMPUTE_STATIC_THREAD_MGMT_SE3",

2787
   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"

2788
  },

2789
  {

2790
   "chips": ["gfx81"],

2791
   "map": {"at": 47212, "to": "mm"},

2792
   "name": "COMPUTE_RESTART_X"

2793
  },

2794
  {

2795
   "chips": ["gfx81"],

2796
   "map": {"at": 47216, "to": "mm"},

2797
   "name": "COMPUTE_RESTART_Y"

2798
  },

2799
  {

2800
   "chips": ["gfx81"],

2801
   "map": {"at": 47220, "to": "mm"},

2802
   "name": "COMPUTE_RESTART_Z"

2803
  },

2804
  {

2805
   "chips": ["gfx81"],

2806
   "map": {"at": 47224, "to": "mm"},

2807
   "name": "COMPUTE_THREAD_TRACE_ENABLE",

2808
   "type_ref": "COMPUTE_THREAD_TRACE_ENABLE"

2809
  },

2810
  {

2811
   "chips": ["gfx81"],

2812
   "map": {"at": 47228, "to": "mm"},

2813
   "name": "COMPUTE_MISC_RESERVED",

2814
   "type_ref": "COMPUTE_MISC_RESERVED"

2815
  },

2816
  {

2817
   "chips": ["gfx81"],

2818
   "map": {"at": 47232, "to": "mm"},

2819
   "name": "COMPUTE_DISPATCH_ID"

2820
  },

2821
  {

2822
   "chips": ["gfx81"],

2823
   "map": {"at": 47236, "to": "mm"},

2824
   "name": "COMPUTE_THREADGROUP_ID"

2825
  },

2826
  {

2827
   "chips": ["gfx81"],

2828
   "map": {"at": 47240, "to": "mm"},

2829
   "name": "COMPUTE_RELAUNCH",

2830
   "type_ref": "COMPUTE_RELAUNCH"

2831
  },

2832
  {

2833
   "chips": ["gfx81"],

2834
   "map": {"at": 47244, "to": "mm"},

2835
   "name": "COMPUTE_WAVE_RESTORE_ADDR_LO"

2836
  },

2837
  {

2838
   "chips": ["gfx81"],

2839
   "map": {"at": 47248, "to": "mm"},

2840
   "name": "COMPUTE_WAVE_RESTORE_ADDR_HI",

2841
   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_HI"

2842
  },

2843
  {

2844
   "chips": ["gfx81"],

2845
   "map": {"at": 47252, "to": "mm"},

2846
   "name": "COMPUTE_WAVE_RESTORE_CONTROL",

2847
   "type_ref": "COMPUTE_WAVE_RESTORE_CONTROL"

2848
  },

2849
  {

2850
   "chips": ["gfx81"],

2851
   "map": {"at": 47360, "to": "mm"},

2852
   "name": "COMPUTE_USER_DATA_0"

2853
  },

2854
  {

2855
   "chips": ["gfx81"],

2856
   "map": {"at": 47364, "to": "mm"},

2857
   "name": "COMPUTE_USER_DATA_1"

2858
  },

2859
  {

2860
   "chips": ["gfx81"],

2861
   "map": {"at": 47368, "to": "mm"},

2862
   "name": "COMPUTE_USER_DATA_2"

2863
  },

2864
  {

2865
   "chips": ["gfx81"],

2866
   "map": {"at": 47372, "to": "mm"},

2867
   "name": "COMPUTE_USER_DATA_3"

2868
  },

2869
  {

2870
   "chips": ["gfx81"],

2871
   "map": {"at": 47376, "to": "mm"},

2872
   "name": "COMPUTE_USER_DATA_4"

2873
  },

2874
  {

2875
   "chips": ["gfx81"],

2876
   "map": {"at": 47380, "to": "mm"},

2877
   "name": "COMPUTE_USER_DATA_5"

2878
  },

2879
  {

2880
   "chips": ["gfx81"],

2881
   "map": {"at": 47384, "to": "mm"},

2882
   "name": "COMPUTE_USER_DATA_6"

2883
  },

2884
  {

2885
   "chips": ["gfx81"],

2886
   "map": {"at": 47388, "to": "mm"},

2887
   "name": "COMPUTE_USER_DATA_7"

2888
  },

2889
  {

2890
   "chips": ["gfx81"],

2891
   "map": {"at": 47392, "to": "mm"},

2892
   "name": "COMPUTE_USER_DATA_8"

2893
  },

2894
  {

2895
   "chips": ["gfx81"],

2896
   "map": {"at": 47396, "to": "mm"},

2897
   "name": "COMPUTE_USER_DATA_9"

2898
  },

2899
  {

2900
   "chips": ["gfx81"],

2901
   "map": {"at": 47400, "to": "mm"},

2902
   "name": "COMPUTE_USER_DATA_10"

2903
  },

2904
  {

2905
   "chips": ["gfx81"],

2906
   "map": {"at": 47404, "to": "mm"},

2907
   "name": "COMPUTE_USER_DATA_11"

2908
  },

2909
  {

2910
   "chips": ["gfx81"],

2911
   "map": {"at": 47408, "to": "mm"},

2912
   "name": "COMPUTE_USER_DATA_12"

2913
  },

2914
  {

2915
   "chips": ["gfx81"],

2916
   "map": {"at": 47412, "to": "mm"},

2917
   "name": "COMPUTE_USER_DATA_13"

2918
  },

2919
  {

2920
   "chips": ["gfx81"],

2921
   "map": {"at": 47416, "to": "mm"},

2922
   "name": "COMPUTE_USER_DATA_14"

2923
  },

2924
  {

2925
   "chips": ["gfx81"],

2926
   "map": {"at": 47420, "to": "mm"},

2927
   "name": "COMPUTE_USER_DATA_15"

2928
  },

2929
  {

2930
   "chips": ["gfx81"],

2931
   "map": {"at": 47612, "to": "mm"},

2932
   "name": "COMPUTE_NOWHERE"

2933
  },

2934
  {

2935
   "chips": ["gfx81"],

2936
   "map": {"at": 163840, "to": "mm"},

2937
   "name": "DB_RENDER_CONTROL",

2938
   "type_ref": "DB_RENDER_CONTROL"

2939
  },

2940
  {

2941
   "chips": ["gfx81"],

2942
   "map": {"at": 163844, "to": "mm"},

2943
   "name": "DB_COUNT_CONTROL",

2944
   "type_ref": "DB_COUNT_CONTROL"

2945
  },

2946
  {

2947
   "chips": ["gfx81"],

2948
   "map": {"at": 163848, "to": "mm"},

2949
   "name": "DB_DEPTH_VIEW",

2950
   "type_ref": "DB_DEPTH_VIEW"

2951
  },

2952
  {

2953
   "chips": ["gfx81"],

2954
   "map": {"at": 163852, "to": "mm"},

2955
   "name": "DB_RENDER_OVERRIDE",

2956
   "type_ref": "DB_RENDER_OVERRIDE"

2957
  },

2958
  {

2959
   "chips": ["gfx81"],

2960
   "map": {"at": 163856, "to": "mm"},

2961
   "name": "DB_RENDER_OVERRIDE2",

2962
   "type_ref": "DB_RENDER_OVERRIDE2"

2963
  },

2964
  {

2965
   "chips": ["gfx81"],

2966
   "map": {"at": 163860, "to": "mm"},

2967
   "name": "DB_HTILE_DATA_BASE"

2968
  },

2969
  {

2970
   "chips": ["gfx81"],

2971
   "map": {"at": 163872, "to": "mm"},

2972
   "name": "DB_DEPTH_BOUNDS_MIN"

2973
  },

2974
  {

2975
   "chips": ["gfx81"],

2976
   "map": {"at": 163876, "to": "mm"},

2977
   "name": "DB_DEPTH_BOUNDS_MAX"

2978
  },

2979
  {

2980
   "chips": ["gfx81"],

2981
   "map": {"at": 163880, "to": "mm"},

2982
   "name": "DB_STENCIL_CLEAR",

2983
   "type_ref": "DB_STENCIL_CLEAR"

2984
  },

2985
  {

2986
   "chips": ["gfx81"],

2987
   "map": {"at": 163884, "to": "mm"},

2988
   "name": "DB_DEPTH_CLEAR"

2989
  },

2990
  {

2991
   "chips": ["gfx81"],

2992
   "map": {"at": 163888, "to": "mm"},

2993
   "name": "PA_SC_SCREEN_SCISSOR_TL",

2994
   "type_ref": "PA_SC_SCREEN_SCISSOR_TL"

2995
  },

2996
  {

2997
   "chips": ["gfx81"],

2998
   "map": {"at": 163892, "to": "mm"},

2999
   "name": "PA_SC_SCREEN_SCISSOR_BR",

3000
   "type_ref": "PA_SC_SCREEN_SCISSOR_BR"

3001
  },

3002
  {

3003
   "chips": ["gfx81"],

3004
   "map": {"at": 163900, "to": "mm"},

3005
   "name": "DB_DEPTH_INFO",

3006
   "type_ref": "DB_DEPTH_INFO"

3007
  },

3008
  {

3009
   "chips": ["gfx81"],

3010
   "map": {"at": 163904, "to": "mm"},

3011
   "name": "DB_Z_INFO",

3012
   "type_ref": "DB_Z_INFO"

3013
  },

3014
  {

3015
   "chips": ["gfx81"],

3016
   "map": {"at": 163908, "to": "mm"},

3017
   "name": "DB_STENCIL_INFO",

3018
   "type_ref": "DB_STENCIL_INFO"

3019
  },

3020
  {

3021
   "chips": ["gfx81"],

3022
   "map": {"at": 163912, "to": "mm"},

3023
   "name": "DB_Z_READ_BASE"

3024
  },

3025
  {

3026
   "chips": ["gfx81"],

3027
   "map": {"at": 163916, "to": "mm"},

3028
   "name": "DB_STENCIL_READ_BASE"

3029
  },

3030
  {

3031
   "chips": ["gfx81"],

3032
   "map": {"at": 163920, "to": "mm"},

3033
   "name": "DB_Z_WRITE_BASE"

3034
  },

3035
  {

3036
   "chips": ["gfx81"],

3037
   "map": {"at": 163924, "to": "mm"},

3038
   "name": "DB_STENCIL_WRITE_BASE"

3039
  },

3040
  {

3041
   "chips": ["gfx81"],

3042
   "map": {"at": 163928, "to": "mm"},

3043
   "name": "DB_DEPTH_SIZE",

3044
   "type_ref": "DB_DEPTH_SIZE"

3045
  },

3046
  {

3047
   "chips": ["gfx81"],

3048
   "map": {"at": 163932, "to": "mm"},

3049
   "name": "DB_DEPTH_SLICE",

3050
   "type_ref": "DB_DEPTH_SLICE"

3051
  },

3052
  {

3053
   "chips": ["gfx81"],

3054
   "map": {"at": 163968, "to": "mm"},

3055
   "name": "TA_BC_BASE_ADDR"

3056
  },

3057
  {

3058
   "chips": ["gfx81"],

3059
   "map": {"at": 163972, "to": "mm"},

3060
   "name": "TA_BC_BASE_ADDR_HI",

3061
   "type_ref": "TA_BC_BASE_ADDR_HI"

3062
  },

3063
  {

3064
   "chips": ["gfx81"],

3065
   "map": {"at": 164328, "to": "mm"},

3066
   "name": "COHER_DEST_BASE_HI_0"

3067
  },

3068
  {

3069
   "chips": ["gfx81"],

3070
   "map": {"at": 164332, "to": "mm"},

3071
   "name": "COHER_DEST_BASE_HI_1"

3072
  },

3073
  {

3074
   "chips": ["gfx81"],

3075
   "map": {"at": 164336, "to": "mm"},

3076
   "name": "COHER_DEST_BASE_HI_2"

3077
  },

3078
  {

3079
   "chips": ["gfx81"],

3080
   "map": {"at": 164340, "to": "mm"},

3081
   "name": "COHER_DEST_BASE_HI_3"

3082
  },

3083
  {

3084
   "chips": ["gfx81"],

3085
   "map": {"at": 164344, "to": "mm"},

3086
   "name": "COHER_DEST_BASE_2"

3087
  },

3088
  {

3089
   "chips": ["gfx81"],

3090
   "map": {"at": 164348, "to": "mm"},

3091
   "name": "COHER_DEST_BASE_3"

3092
  },

3093
  {

3094
   "chips": ["gfx81"],

3095
   "map": {"at": 164352, "to": "mm"},

3096
   "name": "PA_SC_WINDOW_OFFSET",

3097
   "type_ref": "PA_SC_WINDOW_OFFSET"

3098
  },

3099
  {

3100
   "chips": ["gfx81"],

3101
   "map": {"at": 164356, "to": "mm"},

3102
   "name": "PA_SC_WINDOW_SCISSOR_TL",

3103
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3104
  },

3105
  {

3106
   "chips": ["gfx81"],

3107
   "map": {"at": 164360, "to": "mm"},

3108
   "name": "PA_SC_WINDOW_SCISSOR_BR",

3109
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3110
  },

3111
  {

3112
   "chips": ["gfx81"],

3113
   "map": {"at": 164364, "to": "mm"},

3114
   "name": "PA_SC_CLIPRECT_RULE",

3115
   "type_ref": "PA_SC_CLIPRECT_RULE"

3116
  },

3117
  {

3118
   "chips": ["gfx81"],

3119
   "map": {"at": 164368, "to": "mm"},

3120
   "name": "PA_SC_CLIPRECT_0_TL",

3121
   "type_ref": "PA_SC_CLIPRECT_0_TL"

3122
  },

3123
  {

3124
   "chips": ["gfx81"],

3125
   "map": {"at": 164372, "to": "mm"},

3126
   "name": "PA_SC_CLIPRECT_0_BR",

3127
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3128
  },

3129
  {

3130
   "chips": ["gfx81"],

3131
   "map": {"at": 164376, "to": "mm"},

3132
   "name": "PA_SC_CLIPRECT_1_TL",

3133
   "type_ref": "PA_SC_CLIPRECT_0_TL"

3134
  },

3135
  {

3136
   "chips": ["gfx81"],

3137
   "map": {"at": 164380, "to": "mm"},

3138
   "name": "PA_SC_CLIPRECT_1_BR",

3139
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3140
  },

3141
  {

3142
   "chips": ["gfx81"],

3143
   "map": {"at": 164384, "to": "mm"},

3144
   "name": "PA_SC_CLIPRECT_2_TL",

3145
   "type_ref": "PA_SC_CLIPRECT_0_TL"

3146
  },

3147
  {

3148
   "chips": ["gfx81"],

3149
   "map": {"at": 164388, "to": "mm"},

3150
   "name": "PA_SC_CLIPRECT_2_BR",

3151
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3152
  },

3153
  {

3154
   "chips": ["gfx81"],

3155
   "map": {"at": 164392, "to": "mm"},

3156
   "name": "PA_SC_CLIPRECT_3_TL",

3157
   "type_ref": "PA_SC_CLIPRECT_0_TL"

3158
  },

3159
  {

3160
   "chips": ["gfx81"],

3161
   "map": {"at": 164396, "to": "mm"},

3162
   "name": "PA_SC_CLIPRECT_3_BR",

3163
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3164
  },

3165
  {

3166
   "chips": ["gfx81"],

3167
   "map": {"at": 164400, "to": "mm"},

3168
   "name": "PA_SC_EDGERULE",

3169
   "type_ref": "PA_SC_EDGERULE"

3170
  },

3171
  {

3172
   "chips": ["gfx81"],

3173
   "map": {"at": 164404, "to": "mm"},

3174
   "name": "PA_SU_HARDWARE_SCREEN_OFFSET",

3175
   "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET"

3176
  },

3177
  {

3178
   "chips": ["gfx81"],

3179
   "map": {"at": 164408, "to": "mm"},

3180
   "name": "CB_TARGET_MASK",

3181
   "type_ref": "CB_TARGET_MASK"

3182
  },

3183
  {

3184
   "chips": ["gfx81"],

3185
   "map": {"at": 164412, "to": "mm"},

3186
   "name": "CB_SHADER_MASK",

3187
   "type_ref": "CB_SHADER_MASK"

3188
  },

3189
  {

3190
   "chips": ["gfx81"],

3191
   "map": {"at": 164416, "to": "mm"},

3192
   "name": "PA_SC_GENERIC_SCISSOR_TL",

3193
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3194
  },

3195
  {

3196
   "chips": ["gfx81"],

3197
   "map": {"at": 164420, "to": "mm"},

3198
   "name": "PA_SC_GENERIC_SCISSOR_BR",

3199
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3200
  },

3201
  {

3202
   "chips": ["gfx81"],

3203
   "map": {"at": 164424, "to": "mm"},

3204
   "name": "COHER_DEST_BASE_0"

3205
  },

3206
  {

3207
   "chips": ["gfx81"],

3208
   "map": {"at": 164428, "to": "mm"},

3209
   "name": "COHER_DEST_BASE_1"

3210
  },

3211
  {

3212
   "chips": ["gfx81"],

3213
   "map": {"at": 164432, "to": "mm"},

3214
   "name": "PA_SC_VPORT_SCISSOR_0_TL",

3215
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3216
  },

3217
  {

3218
   "chips": ["gfx81"],

3219
   "map": {"at": 164436, "to": "mm"},

3220
   "name": "PA_SC_VPORT_SCISSOR_0_BR",

3221
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3222
  },

3223
  {

3224
   "chips": ["gfx81"],

3225
   "map": {"at": 164440, "to": "mm"},

3226
   "name": "PA_SC_VPORT_SCISSOR_1_TL",

3227
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3228
  },

3229
  {

3230
   "chips": ["gfx81"],

3231
   "map": {"at": 164444, "to": "mm"},

3232
   "name": "PA_SC_VPORT_SCISSOR_1_BR",

3233
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3234
  },

3235
  {

3236
   "chips": ["gfx81"],

3237
   "map": {"at": 164448, "to": "mm"},

3238
   "name": "PA_SC_VPORT_SCISSOR_2_TL",

3239
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3240
  },

3241
  {

3242
   "chips": ["gfx81"],

3243
   "map": {"at": 164452, "to": "mm"},

3244
   "name": "PA_SC_VPORT_SCISSOR_2_BR",

3245
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3246
  },

3247
  {

3248
   "chips": ["gfx81"],

3249
   "map": {"at": 164456, "to": "mm"},

3250
   "name": "PA_SC_VPORT_SCISSOR_3_TL",

3251
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3252
  },

3253
  {

3254
   "chips": ["gfx81"],

3255
   "map": {"at": 164460, "to": "mm"},

3256
   "name": "PA_SC_VPORT_SCISSOR_3_BR",

3257
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3258
  },

3259
  {

3260
   "chips": ["gfx81"],

3261
   "map": {"at": 164464, "to": "mm"},

3262
   "name": "PA_SC_VPORT_SCISSOR_4_TL",

3263
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3264
  },

3265
  {

3266
   "chips": ["gfx81"],

3267
   "map": {"at": 164468, "to": "mm"},

3268
   "name": "PA_SC_VPORT_SCISSOR_4_BR",

3269
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3270
  },

3271
  {

3272
   "chips": ["gfx81"],

3273
   "map": {"at": 164472, "to": "mm"},

3274
   "name": "PA_SC_VPORT_SCISSOR_5_TL",

3275
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3276
  },

3277
  {

3278
   "chips": ["gfx81"],

3279
   "map": {"at": 164476, "to": "mm"},

3280
   "name": "PA_SC_VPORT_SCISSOR_5_BR",

3281
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3282
  },

3283
  {

3284
   "chips": ["gfx81"],

3285
   "map": {"at": 164480, "to": "mm"},

3286
   "name": "PA_SC_VPORT_SCISSOR_6_TL",

3287
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3288
  },

3289
  {

3290
   "chips": ["gfx81"],

3291
   "map": {"at": 164484, "to": "mm"},

3292
   "name": "PA_SC_VPORT_SCISSOR_6_BR",

3293
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3294
  },

3295
  {

3296
   "chips": ["gfx81"],

3297
   "map": {"at": 164488, "to": "mm"},

3298
   "name": "PA_SC_VPORT_SCISSOR_7_TL",

3299
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3300
  },

3301
  {

3302
   "chips": ["gfx81"],

3303
   "map": {"at": 164492, "to": "mm"},

3304
   "name": "PA_SC_VPORT_SCISSOR_7_BR",

3305
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3306
  },

3307
  {

3308
   "chips": ["gfx81"],

3309
   "map": {"at": 164496, "to": "mm"},

3310
   "name": "PA_SC_VPORT_SCISSOR_8_TL",

3311
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3312
  },

3313
  {

3314
   "chips": ["gfx81"],

3315
   "map": {"at": 164500, "to": "mm"},

3316
   "name": "PA_SC_VPORT_SCISSOR_8_BR",

3317
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3318
  },

3319
  {

3320
   "chips": ["gfx81"],

3321
   "map": {"at": 164504, "to": "mm"},

3322
   "name": "PA_SC_VPORT_SCISSOR_9_TL",

3323
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3324
  },

3325
  {

3326
   "chips": ["gfx81"],

3327
   "map": {"at": 164508, "to": "mm"},

3328
   "name": "PA_SC_VPORT_SCISSOR_9_BR",

3329
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3330
  },

3331
  {

3332
   "chips": ["gfx81"],

3333
   "map": {"at": 164512, "to": "mm"},

3334
   "name": "PA_SC_VPORT_SCISSOR_10_TL",

3335
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3336
  },

3337
  {

3338
   "chips": ["gfx81"],

3339
   "map": {"at": 164516, "to": "mm"},

3340
   "name": "PA_SC_VPORT_SCISSOR_10_BR",

3341
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3342
  },

3343
  {

3344
   "chips": ["gfx81"],

3345
   "map": {"at": 164520, "to": "mm"},

3346
   "name": "PA_SC_VPORT_SCISSOR_11_TL",

3347
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3348
  },

3349
  {

3350
   "chips": ["gfx81"],

3351
   "map": {"at": 164524, "to": "mm"},

3352
   "name": "PA_SC_VPORT_SCISSOR_11_BR",

3353
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3354
  },

3355
  {

3356
   "chips": ["gfx81"],

3357
   "map": {"at": 164528, "to": "mm"},

3358
   "name": "PA_SC_VPORT_SCISSOR_12_TL",

3359
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3360
  },

3361
  {

3362
   "chips": ["gfx81"],

3363
   "map": {"at": 164532, "to": "mm"},

3364
   "name": "PA_SC_VPORT_SCISSOR_12_BR",

3365
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3366
  },

3367
  {

3368
   "chips": ["gfx81"],

3369
   "map": {"at": 164536, "to": "mm"},

3370
   "name": "PA_SC_VPORT_SCISSOR_13_TL",

3371
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3372
  },

3373
  {

3374
   "chips": ["gfx81"],

3375
   "map": {"at": 164540, "to": "mm"},

3376
   "name": "PA_SC_VPORT_SCISSOR_13_BR",

3377
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3378
  },

3379
  {

3380
   "chips": ["gfx81"],

3381
   "map": {"at": 164544, "to": "mm"},

3382
   "name": "PA_SC_VPORT_SCISSOR_14_TL",

3383
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3384
  },

3385
  {

3386
   "chips": ["gfx81"],

3387
   "map": {"at": 164548, "to": "mm"},

3388
   "name": "PA_SC_VPORT_SCISSOR_14_BR",

3389
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3390
  },

3391
  {

3392
   "chips": ["gfx81"],

3393
   "map": {"at": 164552, "to": "mm"},

3394
   "name": "PA_SC_VPORT_SCISSOR_15_TL",

3395
   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"

3396
  },

3397
  {

3398
   "chips": ["gfx81"],

3399
   "map": {"at": 164556, "to": "mm"},

3400
   "name": "PA_SC_VPORT_SCISSOR_15_BR",

3401
   "type_ref": "PA_SC_CLIPRECT_0_BR"

3402
  },

3403
  {

3404
   "chips": ["gfx81"],

3405
   "map": {"at": 164560, "to": "mm"},

3406
   "name": "PA_SC_VPORT_ZMIN_0"

3407
  },

3408
  {

3409
   "chips": ["gfx81"],

3410
   "map": {"at": 164564, "to": "mm"},

3411
   "name": "PA_SC_VPORT_ZMAX_0"

3412
  },

3413
  {

3414
   "chips": ["gfx81"],

3415
   "map": {"at": 164568, "to": "mm"},

3416
   "name": "PA_SC_VPORT_ZMIN_1"

3417
  },

3418
  {

3419
   "chips": ["gfx81"],

3420
   "map": {"at": 164572, "to": "mm"},

3421
   "name": "PA_SC_VPORT_ZMAX_1"

3422
  },

3423
  {

3424
   "chips": ["gfx81"],

3425
   "map": {"at": 164576, "to": "mm"},

3426
   "name": "PA_SC_VPORT_ZMIN_2"

3427
  },

3428
  {

3429
   "chips": ["gfx81"],

3430
   "map": {"at": 164580, "to": "mm"},

3431
   "name": "PA_SC_VPORT_ZMAX_2"

3432
  },

3433
  {

3434
   "chips": ["gfx81"],

3435
   "map": {"at": 164584, "to": "mm"},

3436
   "name": "PA_SC_VPORT_ZMIN_3"

3437
  },

3438
  {

3439
   "chips": ["gfx81"],

3440
   "map": {"at": 164588, "to": "mm"},

3441
   "name": "PA_SC_VPORT_ZMAX_3"

3442
  },

3443
  {

3444
   "chips": ["gfx81"],

3445
   "map": {"at": 164592, "to": "mm"},

3446
   "name": "PA_SC_VPORT_ZMIN_4"

3447
  },

3448
  {

3449
   "chips": ["gfx81"],

3450
   "map": {"at": 164596, "to": "mm"},

3451
   "name": "PA_SC_VPORT_ZMAX_4"

3452
  },

3453
  {

3454
   "chips": ["gfx81"],

3455
   "map": {"at": 164600, "to": "mm"},

3456
   "name": "PA_SC_VPORT_ZMIN_5"

3457
  },

3458
  {

3459
   "chips": ["gfx81"],

3460
   "map": {"at": 164604, "to": "mm"},

3461
   "name": "PA_SC_VPORT_ZMAX_5"

3462
  },

3463
  {

3464
   "chips": ["gfx81"],

3465
   "map": {"at": 164608, "to": "mm"},

3466
   "name": "PA_SC_VPORT_ZMIN_6"

3467
  },

3468
  {

3469
   "chips": ["gfx81"],

3470
   "map": {"at": 164612, "to": "mm"},

3471
   "name": "PA_SC_VPORT_ZMAX_6"

3472
  },

3473
  {

3474
   "chips": ["gfx81"],

3475
   "map": {"at": 164616, "to": "mm"},

3476
   "name": "PA_SC_VPORT_ZMIN_7"

3477
  },

3478
  {

3479
   "chips": ["gfx81"],

3480
   "map": {"at": 164620, "to": "mm"},

3481
   "name": "PA_SC_VPORT_ZMAX_7"

3482
  },

3483
  {

3484
   "chips": ["gfx81"],

3485
   "map": {"at": 164624, "to": "mm"},

3486
   "name": "PA_SC_VPORT_ZMIN_8"

3487
  },

3488
  {

3489
   "chips": ["gfx81"],

3490
   "map": {"at": 164628, "to": "mm"},

3491
   "name": "PA_SC_VPORT_ZMAX_8"

3492
  },

3493
  {

3494
   "chips": ["gfx81"],

3495
   "map": {"at": 164632, "to": "mm"},

3496
   "name": "PA_SC_VPORT_ZMIN_9"

3497
  },

3498
  {

3499
   "chips": ["gfx81"],

3500
   "map": {"at": 164636, "to": "mm"},

3501
   "name": "PA_SC_VPORT_ZMAX_9"

3502
  },

3503
  {

3504
   "chips": ["gfx81"],

3505
   "map": {"at": 164640, "to": "mm"},

3506
   "name": "PA_SC_VPORT_ZMIN_10"

3507
  },

3508
  {

3509
   "chips": ["gfx81"],

3510
   "map": {"at": 164644, "to": "mm"},

3511
   "name": "PA_SC_VPORT_ZMAX_10"

3512
  },

3513
  {

3514
   "chips": ["gfx81"],

3515
   "map": {"at": 164648, "to": "mm"},

3516
   "name": "PA_SC_VPORT_ZMIN_11"

3517
  },

3518
  {

3519
   "chips": ["gfx81"],

3520
   "map": {"at": 164652, "to": "mm"},

3521
   "name": "PA_SC_VPORT_ZMAX_11"

3522
  },

3523
  {

3524
   "chips": ["gfx81"],

3525
   "map": {"at": 164656, "to": "mm"},

3526
   "name": "PA_SC_VPORT_ZMIN_12"

3527
  },

3528
  {

3529
   "chips": ["gfx81"],

3530
   "map": {"at": 164660, "to": "mm"},

3531
   "name": "PA_SC_VPORT_ZMAX_12"

3532
  },

3533
  {

3534
   "chips": ["gfx81"],

3535
   "map": {"at": 164664, "to": "mm"},

3536
   "name": "PA_SC_VPORT_ZMIN_13"

3537
  },

3538
  {

3539
   "chips": ["gfx81"],

3540
   "map": {"at": 164668, "to": "mm"},

3541
   "name": "PA_SC_VPORT_ZMAX_13"

3542
  },

3543
  {

3544
   "chips": ["gfx81"],

3545
   "map": {"at": 164672, "to": "mm"},

3546
   "name": "PA_SC_VPORT_ZMIN_14"

3547
  },

3548
  {

3549
   "chips": ["gfx81"],

3550
   "map": {"at": 164676, "to": "mm"},

3551
   "name": "PA_SC_VPORT_ZMAX_14"

3552
  },

3553
  {

3554
   "chips": ["gfx81"],

3555
   "map": {"at": 164680, "to": "mm"},

3556
   "name": "PA_SC_VPORT_ZMIN_15"

3557
  },

3558
  {

3559
   "chips": ["gfx81"],

3560
   "map": {"at": 164684, "to": "mm"},

3561
   "name": "PA_SC_VPORT_ZMAX_15"

3562
  },

3563
  {

3564
   "chips": ["gfx81"],

3565
   "map": {"at": 164688, "to": "mm"},

3566
   "name": "PA_SC_RASTER_CONFIG",

3567
   "type_ref": "PA_SC_RASTER_CONFIG"

3568
  },

3569
  {

3570
   "chips": ["gfx81"],

3571
   "map": {"at": 164692, "to": "mm"},

3572
   "name": "PA_SC_RASTER_CONFIG_1",

3573
   "type_ref": "PA_SC_RASTER_CONFIG_1"

3574
  },

3575
  {

3576
   "chips": ["gfx81"],

3577
   "map": {"at": 164696, "to": "mm"},

3578
   "name": "PA_SC_SCREEN_EXTENT_CONTROL",

3579
   "type_ref": "PA_SC_SCREEN_EXTENT_CONTROL"

3580
  },

3581
  {

3582
   "chips": ["gfx81"],

3583
   "map": {"at": 164704, "to": "mm"},

3584
   "name": "CP_PERFMON_CNTX_CNTL",

3585
   "type_ref": "CP_PERFMON_CNTX_CNTL"

3586
  },

3587
  {

3588
   "chips": ["gfx81"],

3589
   "map": {"at": 164708, "to": "mm"},

3590
   "name": "CP_RINGID",

3591
   "type_ref": "CP_RINGID"

3592
  },

3593
  {

3594
   "chips": ["gfx81"],

3595
   "map": {"at": 164712, "to": "mm"},

3596
   "name": "CP_VMID",

3597
   "type_ref": "CP_VMID"

3598
  },

3599
  {

3600
   "chips": ["gfx81"],

3601
   "map": {"at": 164864, "to": "mm"},

3602
   "name": "VGT_MAX_VTX_INDX"

3603
  },

3604
  {

3605
   "chips": ["gfx81"],

3606
   "map": {"at": 164868, "to": "mm"},

3607
   "name": "VGT_MIN_VTX_INDX"

3608
  },

3609
  {

3610
   "chips": ["gfx81"],

3611
   "map": {"at": 164872, "to": "mm"},

3612
   "name": "VGT_INDX_OFFSET"

3613
  },

3614
  {

3615
   "chips": ["gfx81"],

3616
   "map": {"at": 164876, "to": "mm"},

3617
   "name": "VGT_MULTI_PRIM_IB_RESET_INDX"

3618
  },

3619
  {

3620
   "chips": ["gfx81"],

3621
   "map": {"at": 164884, "to": "mm"},

3622
   "name": "CB_BLEND_RED"

3623
  },

3624
  {

3625
   "chips": ["gfx81"],

3626
   "map": {"at": 164888, "to": "mm"},

3627
   "name": "CB_BLEND_GREEN"

3628
  },

3629
  {

3630
   "chips": ["gfx81"],

3631
   "map": {"at": 164892, "to": "mm"},

3632
   "name": "CB_BLEND_BLUE"

3633
  },

3634
  {

3635
   "chips": ["gfx81"],

3636
   "map": {"at": 164896, "to": "mm"},

3637
   "name": "CB_BLEND_ALPHA"

3638
  },

3639
  {

3640
   "chips": ["gfx81"],

3641
   "map": {"at": 164900, "to": "mm"},

3642
   "name": "CB_DCC_CONTROL",

3643
   "type_ref": "CB_DCC_CONTROL"

3644
  },

3645
  {

3646
   "chips": ["gfx81"],

3647
   "map": {"at": 164908, "to": "mm"},

3648
   "name": "DB_STENCIL_CONTROL",

3649
   "type_ref": "DB_STENCIL_CONTROL"

3650
  },

3651
  {

3652
   "chips": ["gfx81"],

3653
   "map": {"at": 164912, "to": "mm"},

3654
   "name": "DB_STENCILREFMASK",

3655
   "type_ref": "DB_STENCILREFMASK"

3656
  },

3657
  {

3658
   "chips": ["gfx81"],

3659
   "map": {"at": 164916, "to": "mm"},

3660
   "name": "DB_STENCILREFMASK_BF",

3661
   "type_ref": "DB_STENCILREFMASK_BF"

3662
  },

3663
  {

3664
   "chips": ["gfx81"],

3665
   "map": {"at": 164924, "to": "mm"},

3666
   "name": "PA_CL_VPORT_XSCALE"

3667
  },

3668
  {

3669
   "chips": ["gfx81"],

3670
   "map": {"at": 164928, "to": "mm"},

3671
   "name": "PA_CL_VPORT_XOFFSET"

3672
  },

3673
  {

3674
   "chips": ["gfx81"],

3675
   "map": {"at": 164932, "to": "mm"},

3676
   "name": "PA_CL_VPORT_YSCALE"

3677
  },

3678
  {

3679
   "chips": ["gfx81"],

3680
   "map": {"at": 164936, "to": "mm"},

3681
   "name": "PA_CL_VPORT_YOFFSET"

3682
  },

3683
  {

3684
   "chips": ["gfx81"],

3685
   "map": {"at": 164940, "to": "mm"},

3686
   "name": "PA_CL_VPORT_ZSCALE"

3687
  },

3688
  {

3689
   "chips": ["gfx81"],

3690
   "map": {"at": 164944, "to": "mm"},

3691
   "name": "PA_CL_VPORT_ZOFFSET"

3692
  },

3693
  {

3694
   "chips": ["gfx81"],

3695
   "map": {"at": 164948, "to": "mm"},

3696
   "name": "PA_CL_VPORT_XSCALE_1"

3697
  },

3698
  {

3699
   "chips": ["gfx81"],

3700
   "map": {"at": 164952, "to": "mm"},

3701
   "name": "PA_CL_VPORT_XOFFSET_1"

3702
  },

3703
  {

3704
   "chips": ["gfx81"],

3705
   "map": {"at": 164956, "to": "mm"},

3706
   "name": "PA_CL_VPORT_YSCALE_1"

3707
  },

3708
  {

3709
   "chips": ["gfx81"],

3710
   "map": {"at": 164960, "to": "mm"},

3711
   "name": "PA_CL_VPORT_YOFFSET_1"

3712
  },

3713
  {

3714
   "chips": ["gfx81"],

3715
   "map": {"at": 164964, "to": "mm"},

3716
   "name": "PA_CL_VPORT_ZSCALE_1"

3717
  },

3718
  {

3719
   "chips": ["gfx81"],

3720
   "map": {"at": 164968, "to": "mm"},

3721
   "name": "PA_CL_VPORT_ZOFFSET_1"

3722
  },

3723
  {

3724
   "chips": ["gfx81"],

3725
   "map": {"at": 164972, "to": "mm"},

3726
   "name": "PA_CL_VPORT_XSCALE_2"

3727
  },

3728
  {

3729
   "chips": ["gfx81"],

3730
   "map": {"at": 164976, "to": "mm"},

3731
   "name": "PA_CL_VPORT_XOFFSET_2"

3732
  },

3733
  {

3734
   "chips": ["gfx81"],

3735
   "map": {"at": 164980, "to": "mm"},

3736
   "name": "PA_CL_VPORT_YSCALE_2"

3737
  },

3738
  {

3739
   "chips": ["gfx81"],

3740
   "map": {"at": 164984, "to": "mm"},

3741
   "name": "PA_CL_VPORT_YOFFSET_2"

3742
  },

3743
  {

3744
   "chips": ["gfx81"],

3745
   "map": {"at": 164988, "to": "mm"},

3746
   "name": "PA_CL_VPORT_ZSCALE_2"

3747
  },

3748
  {

3749
   "chips": ["gfx81"],

3750
   "map": {"at": 164992, "to": "mm"},

3751
   "name": "PA_CL_VPORT_ZOFFSET_2"

3752
  },

3753
  {

3754
   "chips": ["gfx81"],

3755
   "map": {"at": 164996, "to": "mm"},

3756
   "name": "PA_CL_VPORT_XSCALE_3"

3757
  },

3758
  {

3759
   "chips": ["gfx81"],

3760
   "map": {"at": 165000, "to": "mm"},

3761
   "name": "PA_CL_VPORT_XOFFSET_3"

3762
  },

3763
  {

3764
   "chips": ["gfx81"],

3765
   "map": {"at": 165004, "to": "mm"},

3766
   "name": "PA_CL_VPORT_YSCALE_3"

3767
  },

3768
  {

3769
   "chips": ["gfx81"],

3770
   "map": {"at": 165008, "to": "mm"},

3771
   "name": "PA_CL_VPORT_YOFFSET_3"

3772
  },

3773
  {

3774
   "chips": ["gfx81"],

3775
   "map": {"at": 165012, "to": "mm"},

3776
   "name": "PA_CL_VPORT_ZSCALE_3"

3777
  },

3778
  {

3779
   "chips": ["gfx81"],

3780
   "map": {"at": 165016, "to": "mm"},

3781
   "name": "PA_CL_VPORT_ZOFFSET_3"

3782
  },

3783
  {

3784
   "chips": ["gfx81"],

3785
   "map": {"at": 165020, "to": "mm"},

3786
   "name": "PA_CL_VPORT_XSCALE_4"

3787
  },

3788
  {

3789
   "chips": ["gfx81"],

3790
   "map": {"at": 165024, "to": "mm"},

3791
   "name": "PA_CL_VPORT_XOFFSET_4"

3792
  },

3793
  {

3794
   "chips": ["gfx81"],

3795
   "map": {"at": 165028, "to": "mm"},

3796
   "name": "PA_CL_VPORT_YSCALE_4"

3797
  },

3798
  {

3799
   "chips": ["gfx81"],

3800
   "map": {"at": 165032, "to": "mm"},

3801
   "name": "PA_CL_VPORT_YOFFSET_4"

3802
  },

3803
  {

3804
   "chips": ["gfx81"],

3805
   "map": {"at": 165036, "to": "mm"},

3806
   "name": "PA_CL_VPORT_ZSCALE_4"

3807
  },

3808
  {

3809
   "chips": ["gfx81"],

3810
   "map": {"at": 165040, "to": "mm"},

3811
   "name": "PA_CL_VPORT_ZOFFSET_4"

3812
  },

3813
  {

3814
   "chips": ["gfx81"],

3815
   "map": {"at": 165044, "to": "mm"},

3816
   "name": "PA_CL_VPORT_XSCALE_5"

3817
  },

3818
  {

3819
   "chips": ["gfx81"],

3820
   "map": {"at": 165048, "to": "mm"},

3821
   "name": "PA_CL_VPORT_XOFFSET_5"

3822
  },

3823
  {

3824
   "chips": ["gfx81"],

3825
   "map": {"at": 165052, "to": "mm"},

3826
   "name": "PA_CL_VPORT_YSCALE_5"

3827
  },

3828
  {

3829
   "chips": ["gfx81"],

3830
   "map": {"at": 165056, "to": "mm"},

3831
   "name": "PA_CL_VPORT_YOFFSET_5"

3832
  },

3833
  {

3834
   "chips": ["gfx81"],

3835
   "map": {"at": 165060, "to": "mm"},

3836
   "name": "PA_CL_VPORT_ZSCALE_5"

3837
  },

3838
  {

3839
   "chips": ["gfx81"],

3840
   "map": {"at": 165064, "to": "mm"},

3841
   "name": "PA_CL_VPORT_ZOFFSET_5"

3842
  },

3843
  {

3844
   "chips": ["gfx81"],

3845
   "map": {"at": 165068, "to": "mm"},

3846
   "name": "PA_CL_VPORT_XSCALE_6"

3847
  },

3848
  {

3849
   "chips": ["gfx81"],

3850
   "map": {"at": 165072, "to": "mm"},

3851
   "name": "PA_CL_VPORT_XOFFSET_6"

3852
  },

3853
  {

3854
   "chips": ["gfx81"],

3855
   "map": {"at": 165076, "to": "mm"},

3856
   "name": "PA_CL_VPORT_YSCALE_6"

3857
  },

3858
  {

3859
   "chips": ["gfx81"],

3860
   "map": {"at": 165080, "to": "mm"},

3861
   "name": "PA_CL_VPORT_YOFFSET_6"

3862
  },

3863
  {

3864
   "chips": ["gfx81"],

3865
   "map": {"at": 165084, "to": "mm"},

3866
   "name": "PA_CL_VPORT_ZSCALE_6"

3867
  },

3868
  {

3869
   "chips": ["gfx81"],

3870
   "map": {"at": 165088, "to": "mm"},

3871
   "name": "PA_CL_VPORT_ZOFFSET_6"

3872
  },

3873
  {

3874
   "chips": ["gfx81"],

3875
   "map": {"at": 165092, "to": "mm"},

3876
   "name": "PA_CL_VPORT_XSCALE_7"

3877
  },

3878
  {

3879
   "chips": ["gfx81"],

3880
   "map": {"at": 165096, "to": "mm"},

3881
   "name": "PA_CL_VPORT_XOFFSET_7"

3882
  },

3883
  {

3884
   "chips": ["gfx81"],

3885
   "map": {"at": 165100, "to": "mm"},

3886
   "name": "PA_CL_VPORT_YSCALE_7"

3887
  },

3888
  {

3889
   "chips": ["gfx81"],

3890
   "map": {"at": 165104, "to": "mm"},

3891
   "name": "PA_CL_VPORT_YOFFSET_7"

3892
  },

3893
  {

3894
   "chips": ["gfx81"],

3895
   "map": {"at": 165108, "to": "mm"},

3896
   "name": "PA_CL_VPORT_ZSCALE_7"

3897
  },

3898
  {

3899
   "chips": ["gfx81"],

3900
   "map": {"at": 165112, "to": "mm"},

3901
   "name": "PA_CL_VPORT_ZOFFSET_7"

3902
  },

3903
  {

3904
   "chips": ["gfx81"],

3905
   "map": {"at": 165116, "to": "mm"},

3906
   "name": "PA_CL_VPORT_XSCALE_8"

3907
  },

3908
  {

3909
   "chips": ["gfx81"],

3910
   "map": {"at": 165120, "to": "mm"},

3911
   "name": "PA_CL_VPORT_XOFFSET_8"

3912
  },

3913
  {

3914
   "chips": ["gfx81"],

3915
   "map": {"at": 165124, "to": "mm"},

3916
   "name": "PA_CL_VPORT_YSCALE_8"

3917
  },

3918
  {

3919
   "chips": ["gfx81"],

3920
   "map": {"at": 165128, "to": "mm"},

3921
   "name": "PA_CL_VPORT_YOFFSET_8"

3922
  },

3923
  {

3924
   "chips": ["gfx81"],

3925
   "map": {"at": 165132, "to": "mm"},

3926
   "name": "PA_CL_VPORT_ZSCALE_8"

3927
  },

3928
  {

3929
   "chips": ["gfx81"],

3930
   "map": {"at": 165136, "to": "mm"},

3931
   "name": "PA_CL_VPORT_ZOFFSET_8"

3932
  },

3933
  {

3934
   "chips": ["gfx81"],

3935
   "map": {"at": 165140, "to": "mm"},

3936
   "name": "PA_CL_VPORT_XSCALE_9"

3937
  },

3938
  {

3939
   "chips": ["gfx81"],

3940
   "map": {"at": 165144, "to": "mm"},

3941
   "name": "PA_CL_VPORT_XOFFSET_9"

3942
  },

3943
  {

3944
   "chips": ["gfx81"],

3945
   "map": {"at": 165148, "to": "mm"},

3946
   "name": "PA_CL_VPORT_YSCALE_9"

3947
  },

3948
  {

3949
   "chips": ["gfx81"],

3950
   "map": {"at": 165152, "to": "mm"},

3951
   "name": "PA_CL_VPORT_YOFFSET_9"

3952
  },

3953
  {

3954
   "chips": ["gfx81"],

3955
   "map": {"at": 165156, "to": "mm"},

3956
   "name": "PA_CL_VPORT_ZSCALE_9"

3957
  },

3958
  {

3959
   "chips": ["gfx81"],

3960
   "map": {"at": 165160, "to": "mm"},

3961
   "name": "PA_CL_VPORT_ZOFFSET_9"

3962
  },

3963
  {

3964
   "chips": ["gfx81"],

3965
   "map": {"at": 165164, "to": "mm"},

3966
   "name": "PA_CL_VPORT_XSCALE_10"

3967
  },

3968
  {

3969
   "chips": ["gfx81"],

3970
   "map": {"at": 165168, "to": "mm"},

3971
   "name": "PA_CL_VPORT_XOFFSET_10"

3972
  },

3973
  {

3974
   "chips": ["gfx81"],

3975
   "map": {"at": 165172, "to": "mm"},

3976
   "name": "PA_CL_VPORT_YSCALE_10"

3977
  },

3978
  {

3979
   "chips": ["gfx81"],

3980
   "map": {"at": 165176, "to": "mm"},

3981
   "name": "PA_CL_VPORT_YOFFSET_10"

3982
  },

3983
  {

3984
   "chips": ["gfx81"],

3985
   "map": {"at": 165180, "to": "mm"},

3986
   "name": "PA_CL_VPORT_ZSCALE_10"

3987
  },

3988
  {

3989
   "chips": ["gfx81"],

3990
   "map": {"at": 165184, "to": "mm"},

3991
   "name": "PA_CL_VPORT_ZOFFSET_10"

3992
  },

3993
  {

3994
   "chips": ["gfx81"],

3995
   "map": {"at": 165188, "to": "mm"},

3996
   "name": "PA_CL_VPORT_XSCALE_11"

3997
  },

3998
  {

3999
   "chips": ["gfx81"],

4000
   "map": {"at": 165192, "to": "mm"},

4001
   "name": "PA_CL_VPORT_XOFFSET_11"

4002
  },

4003
  {

4004
   "chips": ["gfx81"],

4005
   "map": {"at": 165196, "to": "mm"},

4006
   "name": "PA_CL_VPORT_YSCALE_11"

4007
  },

4008
  {

4009
   "chips": ["gfx81"],

4010
   "map": {"at": 165200, "to": "mm"},

4011
   "name": "PA_CL_VPORT_YOFFSET_11"

4012
  },

4013
  {

4014
   "chips": ["gfx81"],

4015
   "map": {"at": 165204, "to": "mm"},

4016
   "name": "PA_CL_VPORT_ZSCALE_11"

4017
  },

4018
  {

4019
   "chips": ["gfx81"],

4020
   "map": {"at": 165208, "to": "mm"},

4021
   "name": "PA_CL_VPORT_ZOFFSET_11"

4022
  },

4023
  {

4024
   "chips": ["gfx81"],

4025
   "map": {"at": 165212, "to": "mm"},

4026
   "name": "PA_CL_VPORT_XSCALE_12"

4027
  },

4028
  {

4029
   "chips": ["gfx81"],

4030
   "map": {"at": 165216, "to": "mm"},

4031
   "name": "PA_CL_VPORT_XOFFSET_12"

4032
  },

4033
  {

4034
   "chips": ["gfx81"],

4035
   "map": {"at": 165220, "to": "mm"},

4036
   "name": "PA_CL_VPORT_YSCALE_12"

4037
  },

4038
  {

4039
   "chips": ["gfx81"],

4040
   "map": {"at": 165224, "to": "mm"},

4041
   "name": "PA_CL_VPORT_YOFFSET_12"

4042
  },

4043
  {

4044
   "chips": ["gfx81"],

4045
   "map": {"at": 165228, "to": "mm"},

4046
   "name": "PA_CL_VPORT_ZSCALE_12"

4047
  },

4048
  {

4049
   "chips": ["gfx81"],

4050
   "map": {"at": 165232, "to": "mm"},

4051
   "name": "PA_CL_VPORT_ZOFFSET_12"

4052
  },

4053
  {

4054
   "chips": ["gfx81"],

4055
   "map": {"at": 165236, "to": "mm"},

4056
   "name": "PA_CL_VPORT_XSCALE_13"

4057
  },

4058
  {

4059
   "chips": ["gfx81"],

4060
   "map": {"at": 165240, "to": "mm"},

4061
   "name": "PA_CL_VPORT_XOFFSET_13"

4062
  },

4063
  {

4064
   "chips": ["gfx81"],

4065
   "map": {"at": 165244, "to": "mm"},

4066
   "name": "PA_CL_VPORT_YSCALE_13"

4067
  },

4068
  {

4069
   "chips": ["gfx81"],

4070
   "map": {"at": 165248, "to": "mm"},

4071
   "name": "PA_CL_VPORT_YOFFSET_13"

4072
  },

4073
  {

4074
   "chips": ["gfx81"],

4075
   "map": {"at": 165252, "to": "mm"},

4076
   "name": "PA_CL_VPORT_ZSCALE_13"

4077
  },

4078
  {

4079
   "chips": ["gfx81"],

4080
   "map": {"at": 165256, "to": "mm"},

4081
   "name": "PA_CL_VPORT_ZOFFSET_13"

4082
  },

4083
  {

4084
   "chips": ["gfx81"],

4085
   "map": {"at": 165260, "to": "mm"},

4086
   "name": "PA_CL_VPORT_XSCALE_14"

4087
  },

4088
  {

4089
   "chips": ["gfx81"],

4090
   "map": {"at": 165264, "to": "mm"},

4091
   "name": "PA_CL_VPORT_XOFFSET_14"

4092
  },

4093
  {

4094
   "chips": ["gfx81"],

4095
   "map": {"at": 165268, "to": "mm"},

4096
   "name": "PA_CL_VPORT_YSCALE_14"

4097
  },

4098
  {

4099
   "chips": ["gfx81"],

4100
   "map": {"at": 165272, "to": "mm"},

4101
   "name": "PA_CL_VPORT_YOFFSET_14"

4102
  },

4103
  {

4104
   "chips": ["gfx81"],

4105
   "map": {"at": 165276, "to": "mm"},

4106
   "name": "PA_CL_VPORT_ZSCALE_14"

4107
  },

4108
  {

4109
   "chips": ["gfx81"],

4110
   "map": {"at": 165280, "to": "mm"},

4111
   "name": "PA_CL_VPORT_ZOFFSET_14"

4112
  },

4113
  {

4114
   "chips": ["gfx81"],

4115
   "map": {"at": 165284, "to": "mm"},

4116
   "name": "PA_CL_VPORT_XSCALE_15"

4117
  },

4118
  {

4119
   "chips": ["gfx81"],

4120
   "map": {"at": 165288, "to": "mm"},

4121
   "name": "PA_CL_VPORT_XOFFSET_15"

4122
  },

4123
  {

4124
   "chips": ["gfx81"],

4125
   "map": {"at": 165292, "to": "mm"},

4126
   "name": "PA_CL_VPORT_YSCALE_15"

4127
  },

4128
  {

4129
   "chips": ["gfx81"],

4130
   "map": {"at": 165296, "to": "mm"},

4131
   "name": "PA_CL_VPORT_YOFFSET_15"

4132
  },

4133
  {

4134
   "chips": ["gfx81"],

4135
   "map": {"at": 165300, "to": "mm"},

4136
   "name": "PA_CL_VPORT_ZSCALE_15"

4137
  },

4138
  {

4139
   "chips": ["gfx81"],

4140
   "map": {"at": 165304, "to": "mm"},

4141
   "name": "PA_CL_VPORT_ZOFFSET_15"

4142
  },

4143
  {

4144
   "chips": ["gfx81"],

4145
   "map": {"at": 165308, "to": "mm"},

4146
   "name": "PA_CL_UCP_0_X"

4147
  },

4148
  {

4149
   "chips": ["gfx81"],

4150
   "map": {"at": 165312, "to": "mm"},

4151
   "name": "PA_CL_UCP_0_Y"

4152
  },

4153
  {

4154
   "chips": ["gfx81"],

4155
   "map": {"at": 165316, "to": "mm"},

4156
   "name": "PA_CL_UCP_0_Z"

4157
  },

4158
  {

4159
   "chips": ["gfx81"],

4160
   "map": {"at": 165320, "to": "mm"},

4161
   "name": "PA_CL_UCP_0_W"

4162
  },

4163
  {

4164
   "chips": ["gfx81"],

4165
   "map": {"at": 165324, "to": "mm"},

4166
   "name": "PA_CL_UCP_1_X"

4167
  },

4168
  {

4169
   "chips": ["gfx81"],

4170
   "map": {"at": 165328, "to": "mm"},

4171
   "name": "PA_CL_UCP_1_Y"

4172
  },

4173
  {

4174
   "chips": ["gfx81"],

4175
   "map": {"at": 165332, "to": "mm"},

4176
   "name": "PA_CL_UCP_1_Z"

4177
  },

4178
  {

4179
   "chips": ["gfx81"],

4180
   "map": {"at": 165336, "to": "mm"},

4181
   "name": "PA_CL_UCP_1_W"

4182
  },

4183
  {

4184
   "chips": ["gfx81"],

4185
   "map": {"at": 165340, "to": "mm"},

4186
   "name": "PA_CL_UCP_2_X"

4187
  },

4188
  {

4189
   "chips": ["gfx81"],

4190
   "map": {"at": 165344, "to": "mm"},

4191
   "name": "PA_CL_UCP_2_Y"

4192
  },

4193
  {

4194
   "chips": ["gfx81"],

4195
   "map": {"at": 165348, "to": "mm"},

4196
   "name": "PA_CL_UCP_2_Z"

4197
  },

4198
  {

4199
   "chips": ["gfx81"],

4200
   "map": {"at": 165352, "to": "mm"},

4201
   "name": "PA_CL_UCP_2_W"

4202
  },

4203
  {

4204
   "chips": ["gfx81"],

4205
   "map": {"at": 165356, "to": "mm"},

4206
   "name": "PA_CL_UCP_3_X"

4207
  },

4208
  {

4209
   "chips": ["gfx81"],

4210
   "map": {"at": 165360, "to": "mm"},

4211
   "name": "PA_CL_UCP_3_Y"

4212
  },

4213
  {

4214
   "chips": ["gfx81"],

4215
   "map": {"at": 165364, "to": "mm"},

4216
   "name": "PA_CL_UCP_3_Z"

4217
  },

4218
  {

4219
   "chips": ["gfx81"],

4220
   "map": {"at": 165368, "to": "mm"},

4221
   "name": "PA_CL_UCP_3_W"

4222
  },

4223
  {

4224
   "chips": ["gfx81"],

4225
   "map": {"at": 165372, "to": "mm"},

4226
   "name": "PA_CL_UCP_4_X"

4227
  },

4228
  {

4229
   "chips": ["gfx81"],

4230
   "map": {"at": 165376, "to": "mm"},

4231
   "name": "PA_CL_UCP_4_Y"

4232
  },

4233
  {

4234
   "chips": ["gfx81"],

4235
   "map": {"at": 165380, "to": "mm"},

4236
   "name": "PA_CL_UCP_4_Z"

4237
  },

4238
  {

4239
   "chips": ["gfx81"],

4240
   "map": {"at": 165384, "to": "mm"},

4241
   "name": "PA_CL_UCP_4_W"

4242
  },

4243
  {

4244
   "chips": ["gfx81"],

4245
   "map": {"at": 165388, "to": "mm"},

4246
   "name": "PA_CL_UCP_5_X"

4247
  },

4248
  {

4249
   "chips": ["gfx81"],

4250
   "map": {"at": 165392, "to": "mm"},

4251
   "name": "PA_CL_UCP_5_Y"

4252
  },

4253
  {

4254
   "chips": ["gfx81"],

4255
   "map": {"at": 165396, "to": "mm"},

4256
   "name": "PA_CL_UCP_5_Z"

4257
  },

4258
  {

4259
   "chips": ["gfx81"],

4260
   "map": {"at": 165400, "to": "mm"},

4261
   "name": "PA_CL_UCP_5_W"

4262
  },

4263
  {

4264
   "chips": ["gfx81"],

4265
   "map": {"at": 165444, "to": "mm"},

4266
   "name": "SPI_PS_INPUT_CNTL_0",

4267
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4268
  },

4269
  {

4270
   "chips": ["gfx81"],

4271
   "map": {"at": 165448, "to": "mm"},

4272
   "name": "SPI_PS_INPUT_CNTL_1",

4273
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4274
  },

4275
  {

4276
   "chips": ["gfx81"],

4277
   "map": {"at": 165452, "to": "mm"},

4278
   "name": "SPI_PS_INPUT_CNTL_2",

4279
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4280
  },

4281
  {

4282
   "chips": ["gfx81"],

4283
   "map": {"at": 165456, "to": "mm"},

4284
   "name": "SPI_PS_INPUT_CNTL_3",

4285
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4286
  },

4287
  {

4288
   "chips": ["gfx81"],

4289
   "map": {"at": 165460, "to": "mm"},

4290
   "name": "SPI_PS_INPUT_CNTL_4",

4291
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4292
  },

4293
  {

4294
   "chips": ["gfx81"],

4295
   "map": {"at": 165464, "to": "mm"},

4296
   "name": "SPI_PS_INPUT_CNTL_5",

4297
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4298
  },

4299
  {

4300
   "chips": ["gfx81"],

4301
   "map": {"at": 165468, "to": "mm"},

4302
   "name": "SPI_PS_INPUT_CNTL_6",

4303
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4304
  },

4305
  {

4306
   "chips": ["gfx81"],

4307
   "map": {"at": 165472, "to": "mm"},

4308
   "name": "SPI_PS_INPUT_CNTL_7",

4309
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4310
  },

4311
  {

4312
   "chips": ["gfx81"],

4313
   "map": {"at": 165476, "to": "mm"},

4314
   "name": "SPI_PS_INPUT_CNTL_8",

4315
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4316
  },

4317
  {

4318
   "chips": ["gfx81"],

4319
   "map": {"at": 165480, "to": "mm"},

4320
   "name": "SPI_PS_INPUT_CNTL_9",

4321
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4322
  },

4323
  {

4324
   "chips": ["gfx81"],

4325
   "map": {"at": 165484, "to": "mm"},

4326
   "name": "SPI_PS_INPUT_CNTL_10",

4327
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4328
  },

4329
  {

4330
   "chips": ["gfx81"],

4331
   "map": {"at": 165488, "to": "mm"},

4332
   "name": "SPI_PS_INPUT_CNTL_11",

4333
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4334
  },

4335
  {

4336
   "chips": ["gfx81"],

4337
   "map": {"at": 165492, "to": "mm"},

4338
   "name": "SPI_PS_INPUT_CNTL_12",

4339
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4340
  },

4341
  {

4342
   "chips": ["gfx81"],

4343
   "map": {"at": 165496, "to": "mm"},

4344
   "name": "SPI_PS_INPUT_CNTL_13",

4345
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4346
  },

4347
  {

4348
   "chips": ["gfx81"],

4349
   "map": {"at": 165500, "to": "mm"},

4350
   "name": "SPI_PS_INPUT_CNTL_14",

4351
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4352
  },

4353
  {

4354
   "chips": ["gfx81"],

4355
   "map": {"at": 165504, "to": "mm"},

4356
   "name": "SPI_PS_INPUT_CNTL_15",

4357
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4358
  },

4359
  {

4360
   "chips": ["gfx81"],

4361
   "map": {"at": 165508, "to": "mm"},

4362
   "name": "SPI_PS_INPUT_CNTL_16",

4363
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4364
  },

4365
  {

4366
   "chips": ["gfx81"],

4367
   "map": {"at": 165512, "to": "mm"},

4368
   "name": "SPI_PS_INPUT_CNTL_17",

4369
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4370
  },

4371
  {

4372
   "chips": ["gfx81"],

4373
   "map": {"at": 165516, "to": "mm"},

4374
   "name": "SPI_PS_INPUT_CNTL_18",

4375
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4376
  },

4377
  {

4378
   "chips": ["gfx81"],

4379
   "map": {"at": 165520, "to": "mm"},

4380
   "name": "SPI_PS_INPUT_CNTL_19",

4381
   "type_ref": "SPI_PS_INPUT_CNTL_0"

4382
  },

4383
  {

4384
   "chips": ["gfx81"],

4385
   "map": {"at": 165524, "to": "mm"},

4386
   "name": "SPI_PS_INPUT_CNTL_20",

4387
   "type_ref": "SPI_PS_INPUT_CNTL_20"

4388
  },

4389
  {

4390
   "chips": ["gfx81"],

4391
   "map": {"at": 165528, "to": "mm"},

4392
   "name": "SPI_PS_INPUT_CNTL_21",

4393
   "type_ref": "SPI_PS_INPUT_CNTL_20"

4394
  },

4395
  {

4396
   "chips": ["gfx81"],

4397
   "map": {"at": 165532, "to": "mm"},

4398
   "name": "SPI_PS_INPUT_CNTL_22",

4399
   "type_ref": "SPI_PS_INPUT_CNTL_20"

4400
  },

4401
  {

4402
   "chips": ["gfx81"],

4403
   "map": {"at": 165536, "to": "mm"},

4404
   "name": "SPI_PS_INPUT_CNTL_23",

4405
   "type_ref": "SPI_PS_INPUT_CNTL_20"

4406
  },

4407
  {

4408
   "chips": ["gfx81"],

4409
   "map": {"at": 165540, "to": "mm"},

4410
   "name": "SPI_PS_INPUT_CNTL_24",

4411
   "type_ref": "SPI_PS_INPUT_CNTL_20"

4412
  },

4413
  {

4414
   "chips": ["gfx81"],

4415
   "map": {"at": 165544, "to": "mm"},

4416
   "name": "SPI_PS_INPUT_CNTL_25",

4417
   "type_ref": "SPI_PS_INPUT_CNTL_20"

4418
  },

4419
  {

4420
   "chips": ["gfx81"],

4421
   "map": {"at": 165548, "to": "mm"},

4422
   "name": "SPI_PS_INPUT_CNTL_26",

4423
   "type_ref": "SPI_PS_INPUT_CNTL_20"

4424
  },

4425
  {

4426
   "chips": ["gfx81"],

4427
   "map": {"at": 165552, "to": "mm"},

4428
   "name": "SPI_PS_INPUT_CNTL_27",

4429
   "type_ref": "SPI_PS_INPUT_CNTL_20"

4430
  },

4431
  {

4432
   "chips": ["gfx81"],

4433
   "map": {"at": 165556, "to": "mm"},

4434
   "name": "SPI_PS_INPUT_CNTL_28",

4435
   "type_ref": "SPI_PS_INPUT_CNTL_20"

4436
  },

4437
  {

4438
   "chips": ["gfx81"],

4439
   "map": {"at": 165560, "to": "mm"},

4440
   "name": "SPI_PS_INPUT_CNTL_29",

4441
   "type_ref": "SPI_PS_INPUT_CNTL_20"

4442
  },

4443
  {

4444
   "chips": ["gfx81"],

4445
   "map": {"at": 165564, "to": "mm"},

4446
   "name": "SPI_PS_INPUT_CNTL_30",

4447
   "type_ref": "SPI_PS_INPUT_CNTL_20"

4448
  },

4449
  {

4450
   "chips": ["gfx81"],

4451
   "map": {"at": 165568, "to": "mm"},

4452
   "name": "SPI_PS_INPUT_CNTL_31",

4453
   "type_ref": "SPI_PS_INPUT_CNTL_20"

4454
  },

4455
  {

4456
   "chips": ["gfx81"],

4457
   "map": {"at": 165572, "to": "mm"},

4458
   "name": "SPI_VS_OUT_CONFIG",

4459
   "type_ref": "SPI_VS_OUT_CONFIG"

4460
  },

4461
  {

4462
   "chips": ["gfx81"],

4463
   "map": {"at": 165580, "to": "mm"},

4464
   "name": "SPI_PS_INPUT_ENA",

4465
   "type_ref": "SPI_PS_INPUT_ENA"

4466
  },

4467
  {

4468
   "chips": ["gfx81"],

4469
   "map": {"at": 165584, "to": "mm"},

4470
   "name": "SPI_PS_INPUT_ADDR",

4471
   "type_ref": "SPI_PS_INPUT_ENA"

4472
  },

4473
  {

4474
   "chips": ["gfx81"],

4475
   "map": {"at": 165588, "to": "mm"},

4476
   "name": "SPI_INTERP_CONTROL_0",

4477
   "type_ref": "SPI_INTERP_CONTROL_0"

4478
  },

4479
  {

4480
   "chips": ["gfx81"],

4481
   "map": {"at": 165592, "to": "mm"},

4482
   "name": "SPI_PS_IN_CONTROL",

4483
   "type_ref": "SPI_PS_IN_CONTROL"

4484
  },

4485
  {

4486
   "chips": ["gfx81"],

4487
   "map": {"at": 165600, "to": "mm"},

4488
   "name": "SPI_BARYC_CNTL",

4489
   "type_ref": "SPI_BARYC_CNTL"

4490
  },

4491
  {

4492
   "chips": ["gfx81"],

4493
   "map": {"at": 165608, "to": "mm"},

4494
   "name": "SPI_TMPRING_SIZE",

4495
   "type_ref": "COMPUTE_TMPRING_SIZE"

4496
  },

4497
  {

4498
   "chips": ["gfx81"],

4499
   "map": {"at": 165644, "to": "mm"},

4500
   "name": "SPI_SHADER_POS_FORMAT",

4501
   "type_ref": "SPI_SHADER_POS_FORMAT"

4502
  },

4503
  {

4504
   "chips": ["gfx81"],

4505
   "map": {"at": 165648, "to": "mm"},

4506
   "name": "SPI_SHADER_Z_FORMAT",

4507
   "type_ref": "SPI_SHADER_Z_FORMAT"

4508
  },

4509
  {

4510
   "chips": ["gfx81"],

4511
   "map": {"at": 165652, "to": "mm"},

4512
   "name": "SPI_SHADER_COL_FORMAT",

4513
   "type_ref": "SPI_SHADER_COL_FORMAT"

4514
  },

4515
  {

4516
   "chips": ["gfx81"],

4517
   "map": {"at": 165716, "to": "mm"},

4518
   "name": "SX_PS_DOWNCONVERT",

4519
   "type_ref": "SX_PS_DOWNCONVERT"

4520
  },

4521
  {

4522
   "chips": ["gfx81"],

4523
   "map": {"at": 165720, "to": "mm"},

4524
   "name": "SX_BLEND_OPT_EPSILON",

4525
   "type_ref": "SX_BLEND_OPT_EPSILON"

4526
  },

4527
  {

4528
   "chips": ["gfx81"],

4529
   "map": {"at": 165724, "to": "mm"},

4530
   "name": "SX_BLEND_OPT_CONTROL",

4531
   "type_ref": "SX_BLEND_OPT_CONTROL"

4532
  },

4533
  {

4534
   "chips": ["gfx81"],

4535
   "map": {"at": 165728, "to": "mm"},

4536
   "name": "SX_MRT0_BLEND_OPT",

4537
   "type_ref": "SX_MRT0_BLEND_OPT"

4538
  },

4539
  {

4540
   "chips": ["gfx81"],

4541
   "map": {"at": 165732, "to": "mm"},

4542
   "name": "SX_MRT1_BLEND_OPT",

4543
   "type_ref": "SX_MRT0_BLEND_OPT"

4544
  },

4545
  {

4546
   "chips": ["gfx81"],

4547
   "map": {"at": 165736, "to": "mm"},

4548
   "name": "SX_MRT2_BLEND_OPT",

4549
   "type_ref": "SX_MRT0_BLEND_OPT"

4550
  },

4551
  {

4552
   "chips": ["gfx81"],

4553
   "map": {"at": 165740, "to": "mm"},

4554
   "name": "SX_MRT3_BLEND_OPT",

4555
   "type_ref": "SX_MRT0_BLEND_OPT"

4556
  },

4557
  {

4558
   "chips": ["gfx81"],

4559
   "map": {"at": 165744, "to": "mm"},

4560
   "name": "SX_MRT4_BLEND_OPT",

4561
   "type_ref": "SX_MRT0_BLEND_OPT"

4562
  },

4563
  {

4564
   "chips": ["gfx81"],

4565
   "map": {"at": 165748, "to": "mm"},

4566
   "name": "SX_MRT5_BLEND_OPT",

4567
   "type_ref": "SX_MRT0_BLEND_OPT"

4568
  },

4569
  {

4570
   "chips": ["gfx81"],

4571
   "map": {"at": 165752, "to": "mm"},

4572
   "name": "SX_MRT6_BLEND_OPT",

4573
   "type_ref": "SX_MRT0_BLEND_OPT"

4574
  },

4575
  {

4576
   "chips": ["gfx81"],

4577
   "map": {"at": 165756, "to": "mm"},

4578
   "name": "SX_MRT7_BLEND_OPT",

4579
   "type_ref": "SX_MRT0_BLEND_OPT"

4580
  },

4581
  {

4582
   "chips": ["gfx81"],

4583
   "map": {"at": 165760, "to": "mm"},

4584
   "name": "CB_BLEND0_CONTROL",

4585
   "type_ref": "CB_BLEND0_CONTROL"

4586
  },

4587
  {

4588
   "chips": ["gfx81"],

4589
   "map": {"at": 165764, "to": "mm"},

4590
   "name": "CB_BLEND1_CONTROL",

4591
   "type_ref": "CB_BLEND0_CONTROL"

4592
  },

4593
  {

4594
   "chips": ["gfx81"],

4595
   "map": {"at": 165768, "to": "mm"},

4596
   "name": "CB_BLEND2_CONTROL",

4597
   "type_ref": "CB_BLEND0_CONTROL"

4598
  },

4599
  {

4600
   "chips": ["gfx81"],

4601
   "map": {"at": 165772, "to": "mm"},

4602
   "name": "CB_BLEND3_CONTROL",

4603
   "type_ref": "CB_BLEND0_CONTROL"

4604
  },

4605
  {

4606
   "chips": ["gfx81"],

4607
   "map": {"at": 165776, "to": "mm"},

4608
   "name": "CB_BLEND4_CONTROL",

4609
   "type_ref": "CB_BLEND0_CONTROL"

4610
  },

4611
  {

4612
   "chips": ["gfx81"],

4613
   "map": {"at": 165780, "to": "mm"},

4614
   "name": "CB_BLEND5_CONTROL",

4615
   "type_ref": "CB_BLEND0_CONTROL"

4616
  },

4617
  {

4618
   "chips": ["gfx81"],

4619
   "map": {"at": 165784, "to": "mm"},

4620
   "name": "CB_BLEND6_CONTROL",

4621
   "type_ref": "CB_BLEND0_CONTROL"

4622
  },

4623
  {

4624
   "chips": ["gfx81"],

4625
   "map": {"at": 165788, "to": "mm"},

4626
   "name": "CB_BLEND7_CONTROL",

4627
   "type_ref": "CB_BLEND0_CONTROL"

4628
  },

4629
  {

4630
   "chips": ["gfx81"],

4631
   "map": {"at": 165836, "to": "mm"},

4632
   "name": "CS_COPY_STATE",

4633
   "type_ref": "CS_COPY_STATE"

4634
  },

4635
  {

4636
   "chips": ["gfx81"],

4637
   "map": {"at": 165840, "to": "mm"},

4638
   "name": "GFX_COPY_STATE",

4639
   "type_ref": "CS_COPY_STATE"

4640
  },

4641
  {

4642
   "chips": ["gfx81"],

4643
   "map": {"at": 165844, "to": "mm"},

4644
   "name": "PA_CL_POINT_X_RAD"

4645
  },

4646
  {

4647
   "chips": ["gfx81"],

4648
   "map": {"at": 165848, "to": "mm"},

4649
   "name": "PA_CL_POINT_Y_RAD"

4650
  },

4651
  {

4652
   "chips": ["gfx81"],

4653
   "map": {"at": 165852, "to": "mm"},

4654
   "name": "PA_CL_POINT_SIZE"

4655
  },

4656
  {

4657
   "chips": ["gfx81"],

4658
   "map": {"at": 165856, "to": "mm"},

4659
   "name": "PA_CL_POINT_CULL_RAD"

4660
  },

4661
  {

4662
   "chips": ["gfx81"],

4663
   "map": {"at": 165860, "to": "mm"},

4664
   "name": "VGT_DMA_BASE_HI",

4665
   "type_ref": "VGT_DMA_BASE_HI"

4666
  },

4667
  {

4668
   "chips": ["gfx81"],

4669
   "map": {"at": 165864, "to": "mm"},

4670
   "name": "VGT_DMA_BASE"

4671
  },

4672
  {

4673
   "chips": ["gfx81"],

4674
   "map": {"at": 165872, "to": "mm"},

4675
   "name": "VGT_DRAW_INITIATOR",

4676
   "type_ref": "VGT_DRAW_INITIATOR"

4677
  },

4678
  {

4679
   "chips": ["gfx81"],

4680
   "map": {"at": 165876, "to": "mm"},

4681
   "name": "VGT_IMMED_DATA"

4682
  },

4683
  {

4684
   "chips": ["gfx81"],

4685
   "map": {"at": 165880, "to": "mm"},

4686
   "name": "VGT_EVENT_ADDRESS_REG",

4687
   "type_ref": "VGT_EVENT_ADDRESS_REG"

4688
  },

4689
  {

4690
   "chips": ["gfx81"],

4691
   "map": {"at": 165888, "to": "mm"},

4692
   "name": "DB_DEPTH_CONTROL",

4693
   "type_ref": "DB_DEPTH_CONTROL"

4694
  },

4695
  {

4696
   "chips": ["gfx81"],

4697
   "map": {"at": 165892, "to": "mm"},

4698
   "name": "DB_EQAA",

4699
   "type_ref": "DB_EQAA"

4700
  },

4701
  {

4702
   "chips": ["gfx81"],

4703
   "map": {"at": 165896, "to": "mm"},

4704
   "name": "CB_COLOR_CONTROL",

4705
   "type_ref": "CB_COLOR_CONTROL"

4706
  },

4707
  {

4708
   "chips": ["gfx81"],

4709
   "map": {"at": 165900, "to": "mm"},

4710
   "name": "DB_SHADER_CONTROL",

4711
   "type_ref": "DB_SHADER_CONTROL"

4712
  },

4713
  {

4714
   "chips": ["gfx81"],

4715
   "map": {"at": 165904, "to": "mm"},

4716
   "name": "PA_CL_CLIP_CNTL",

4717
   "type_ref": "PA_CL_CLIP_CNTL"

4718
  },

4719
  {

4720
   "chips": ["gfx81"],

4721
   "map": {"at": 165908, "to": "mm"},

4722
   "name": "PA_SU_SC_MODE_CNTL",

4723
   "type_ref": "PA_SU_SC_MODE_CNTL"

4724
  },

4725
  {

4726
   "chips": ["gfx81"],

4727
   "map": {"at": 165912, "to": "mm"},

4728
   "name": "PA_CL_VTE_CNTL",

4729
   "type_ref": "PA_CL_VTE_CNTL"

4730
  },

4731
  {

4732
   "chips": ["gfx81"],

4733
   "map": {"at": 165916, "to": "mm"},

4734
   "name": "PA_CL_VS_OUT_CNTL",

4735
   "type_ref": "PA_CL_VS_OUT_CNTL"

4736
  },

4737
  {

4738
   "chips": ["gfx81"],

4739
   "map": {"at": 165920, "to": "mm"},

4740
   "name": "PA_CL_NANINF_CNTL",

4741
   "type_ref": "PA_CL_NANINF_CNTL"

4742
  },

4743
  {

4744
   "chips": ["gfx81"],

4745
   "map": {"at": 165924, "to": "mm"},

4746
   "name": "PA_SU_LINE_STIPPLE_CNTL",

4747
   "type_ref": "PA_SU_LINE_STIPPLE_CNTL"

4748
  },

4749
  {

4750
   "chips": ["gfx81"],

4751
   "map": {"at": 165928, "to": "mm"},

4752
   "name": "PA_SU_LINE_STIPPLE_SCALE"

4753
  },

4754
  {

4755
   "chips": ["gfx81"],

4756
   "map": {"at": 165932, "to": "mm"},

4757
   "name": "PA_SU_PRIM_FILTER_CNTL",

4758
   "type_ref": "PA_SU_PRIM_FILTER_CNTL"

4759
  },

4760
  {

4761
   "chips": ["gfx81"],

4762
   "map": {"at": 166400, "to": "mm"},

4763
   "name": "PA_SU_POINT_SIZE",

4764
   "type_ref": "PA_SU_POINT_SIZE"

4765
  },

4766
  {

4767
   "chips": ["gfx81"],

4768
   "map": {"at": 166404, "to": "mm"},

4769
   "name": "PA_SU_POINT_MINMAX",

4770
   "type_ref": "PA_SU_POINT_MINMAX"

4771
  },

4772
  {

4773
   "chips": ["gfx81"],

4774
   "map": {"at": 166408, "to": "mm"},

4775
   "name": "PA_SU_LINE_CNTL",

4776
   "type_ref": "PA_SU_LINE_CNTL"

4777
  },

4778
  {

4779
   "chips": ["gfx81"],

4780
   "map": {"at": 166412, "to": "mm"},

4781
   "name": "PA_SC_LINE_STIPPLE",

4782
   "type_ref": "PA_SC_LINE_STIPPLE"

4783
  },

4784
  {

4785
   "chips": ["gfx81"],

4786
   "map": {"at": 166416, "to": "mm"},

4787
   "name": "VGT_OUTPUT_PATH_CNTL",

4788
   "type_ref": "VGT_OUTPUT_PATH_CNTL"

4789
  },

4790
  {

4791
   "chips": ["gfx81"],

4792
   "map": {"at": 166420, "to": "mm"},

4793
   "name": "VGT_HOS_CNTL",

4794
   "type_ref": "VGT_HOS_CNTL"

4795
  },

4796
  {

4797
   "chips": ["gfx81"],

4798
   "map": {"at": 166424, "to": "mm"},

4799
   "name": "VGT_HOS_MAX_TESS_LEVEL"

4800
  },

4801
  {

4802
   "chips": ["gfx81"],

4803
   "map": {"at": 166428, "to": "mm"},

4804
   "name": "VGT_HOS_MIN_TESS_LEVEL"

4805
  },

4806
  {

4807
   "chips": ["gfx81"],

4808
   "map": {"at": 166432, "to": "mm"},

4809
   "name": "VGT_HOS_REUSE_DEPTH",

4810
   "type_ref": "VGT_HOS_REUSE_DEPTH"

4811
  },

4812
  {

4813
   "chips": ["gfx81"],

4814
   "map": {"at": 166436, "to": "mm"},

4815
   "name": "VGT_GROUP_PRIM_TYPE",

4816
   "type_ref": "VGT_GROUP_PRIM_TYPE"

4817
  },

4818
  {

4819
   "chips": ["gfx81"],

4820
   "map": {"at": 166440, "to": "mm"},

4821
   "name": "VGT_GROUP_FIRST_DECR",

4822
   "type_ref": "VGT_GROUP_FIRST_DECR"

4823
  },

4824
  {

4825
   "chips": ["gfx81"],

4826
   "map": {"at": 166444, "to": "mm"},

4827
   "name": "VGT_GROUP_DECR",

4828
   "type_ref": "VGT_GROUP_DECR"

4829
  },

4830
  {

4831
   "chips": ["gfx81"],

4832
   "map": {"at": 166448, "to": "mm"},

4833
   "name": "VGT_GROUP_VECT_0_CNTL",

4834
   "type_ref": "VGT_GROUP_VECT_0_CNTL"

4835
  },

4836
  {

4837
   "chips": ["gfx81"],

4838
   "map": {"at": 166452, "to": "mm"},

4839
   "name": "VGT_GROUP_VECT_1_CNTL",

4840
   "type_ref": "VGT_GROUP_VECT_0_CNTL"

4841
  },

4842
  {

4843
   "chips": ["gfx81"],

4844
   "map": {"at": 166456, "to": "mm"},

4845
   "name": "VGT_GROUP_VECT_0_FMT_CNTL",

4846
   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"

4847
  },

4848
  {

4849
   "chips": ["gfx81"],

4850
   "map": {"at": 166460, "to": "mm"},

4851
   "name": "VGT_GROUP_VECT_1_FMT_CNTL",

4852
   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"

4853
  },

4854
  {

4855
   "chips": ["gfx81"],

4856
   "map": {"at": 166464, "to": "mm"},

4857
   "name": "VGT_GS_MODE",

4858
   "type_ref": "VGT_GS_MODE"

4859
  },

4860
  {

4861
   "chips": ["gfx81"],

4862
   "map": {"at": 166468, "to": "mm"},

4863
   "name": "VGT_GS_ONCHIP_CNTL",

4864
   "type_ref": "VGT_GS_ONCHIP_CNTL"

4865
  },

4866
  {

4867
   "chips": ["gfx81"],

4868
   "map": {"at": 166472, "to": "mm"},

4869
   "name": "PA_SC_MODE_CNTL_0",

4870
   "type_ref": "PA_SC_MODE_CNTL_0"

4871
  },

4872
  {

4873
   "chips": ["gfx81"],

4874
   "map": {"at": 166476, "to": "mm"},

4875
   "name": "PA_SC_MODE_CNTL_1",

4876
   "type_ref": "PA_SC_MODE_CNTL_1"

4877
  },

4878
  {

4879
   "chips": ["gfx81"],

4880
   "map": {"at": 166480, "to": "mm"},

4881
   "name": "VGT_ENHANCE"

4882
  },

4883
  {

4884
   "chips": ["gfx81"],

4885
   "map": {"at": 166484, "to": "mm"},

4886
   "name": "VGT_GS_PER_ES",

4887
   "type_ref": "VGT_GS_PER_ES"

4888
  },

4889
  {

4890
   "chips": ["gfx81"],

4891
   "map": {"at": 166488, "to": "mm"},

4892
   "name": "VGT_ES_PER_GS",

4893
   "type_ref": "VGT_ES_PER_GS"

4894
  },

4895
  {

4896
   "chips": ["gfx81"],

4897
   "map": {"at": 166492, "to": "mm"},

4898
   "name": "VGT_GS_PER_VS",

4899
   "type_ref": "VGT_GS_PER_VS"

4900
  },

4901
  {

4902
   "chips": ["gfx81"],

4903
   "map": {"at": 166496, "to": "mm"},

4904
   "name": "VGT_GSVS_RING_OFFSET_1",

4905
   "type_ref": "VGT_GSVS_RING_OFFSET_1"

4906
  },

4907
  {

4908
   "chips": ["gfx81"],

4909
   "map": {"at": 166500, "to": "mm"},

4910
   "name": "VGT_GSVS_RING_OFFSET_2",

4911
   "type_ref": "VGT_GSVS_RING_OFFSET_1"

4912
  },

4913
  {

4914
   "chips": ["gfx81"],

4915
   "map": {"at": 166504, "to": "mm"},

4916
   "name": "VGT_GSVS_RING_OFFSET_3",

4917
   "type_ref": "VGT_GSVS_RING_OFFSET_1"

4918
  },

4919
  {

4920
   "chips": ["gfx81"],

4921
   "map": {"at": 166508, "to": "mm"},

4922
   "name": "VGT_GS_OUT_PRIM_TYPE",

4923
   "type_ref": "VGT_GS_OUT_PRIM_TYPE"

4924
  },

4925
  {

4926
   "chips": ["gfx81"],

4927
   "map": {"at": 166512, "to": "mm"},

4928
   "name": "IA_ENHANCE"

4929
  },

4930
  {

4931
   "chips": ["gfx81"],

4932
   "map": {"at": 166516, "to": "mm"},

4933
   "name": "VGT_DMA_SIZE"

4934
  },

4935
  {

4936
   "chips": ["gfx81"],

4937
   "map": {"at": 166520, "to": "mm"},

4938
   "name": "VGT_DMA_MAX_SIZE"

4939
  },

4940
  {

4941
   "chips": ["gfx81"],

4942
   "map": {"at": 166524, "to": "mm"},

4943
   "name": "VGT_DMA_INDEX_TYPE",

4944
   "type_ref": "VGT_DMA_INDEX_TYPE"

4945
  },

4946
  {

4947
   "chips": ["gfx81"],

4948
   "map": {"at": 166528, "to": "mm"},

4949
   "name": "WD_ENHANCE"

4950
  },

4951
  {

4952
   "chips": ["gfx81"],

4953
   "map": {"at": 166532, "to": "mm"},

4954
   "name": "VGT_PRIMITIVEID_EN",

4955
   "type_ref": "VGT_PRIMITIVEID_EN"

4956
  },

4957
  {

4958
   "chips": ["gfx81"],

4959
   "map": {"at": 166536, "to": "mm"},

4960
   "name": "VGT_DMA_NUM_INSTANCES"

4961
  },

4962
  {

4963
   "chips": ["gfx81"],

4964
   "map": {"at": 166540, "to": "mm"},

4965
   "name": "VGT_PRIMITIVEID_RESET"

4966
  },

4967
  {

4968
   "chips": ["gfx81"],

4969
   "map": {"at": 166544, "to": "mm"},

4970
   "name": "VGT_EVENT_INITIATOR",

4971
   "type_ref": "VGT_EVENT_INITIATOR"

4972
  },

4973
  {

4974
   "chips": ["gfx81"],

4975
   "map": {"at": 166548, "to": "mm"},

4976
   "name": "VGT_MULTI_PRIM_IB_RESET_EN",

4977
   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"

4978
  },

4979
  {

4980
   "chips": ["gfx81"],

4981
   "map": {"at": 166560, "to": "mm"},

4982
   "name": "VGT_INSTANCE_STEP_RATE_0"

4983
  },

4984
  {

4985
   "chips": ["gfx81"],

4986
   "map": {"at": 166564, "to": "mm"},

4987
   "name": "VGT_INSTANCE_STEP_RATE_1"

4988
  },

4989
  {

4990
   "chips": ["gfx81"],

4991
   "map": {"at": 166568, "to": "mm"},

4992
   "name": "IA_MULTI_VGT_PARAM",

4993
   "type_ref": "IA_MULTI_VGT_PARAM"

4994
  },

4995
  {

4996
   "chips": ["gfx81"],

4997
   "map": {"at": 166572, "to": "mm"},

4998
   "name": "VGT_ESGS_RING_ITEMSIZE",

4999
   "type_ref": "VGT_ESGS_RING_ITEMSIZE"

5000
  },

5001
  {

5002
   "chips": ["gfx81"],

5003
   "map": {"at": 166576, "to": "mm"},

5004
   "name": "VGT_GSVS_RING_ITEMSIZE",

5005
   "type_ref": "VGT_ESGS_RING_ITEMSIZE"

5006
  },

5007
  {

5008
   "chips": ["gfx81"],

5009
   "map": {"at": 166580, "to": "mm"},

5010
   "name": "VGT_REUSE_OFF",

5011
   "type_ref": "VGT_REUSE_OFF"

5012
  },

5013
  {

5014
   "chips": ["gfx81"],

5015
   "map": {"at": 166584, "to": "mm"},

5016
   "name": "VGT_VTX_CNT_EN",

5017
   "type_ref": "VGT_VTX_CNT_EN"

5018
  },

5019
  {

5020
   "chips": ["gfx81"],

5021
   "map": {"at": 166588, "to": "mm"},

5022
   "name": "DB_HTILE_SURFACE",

5023
   "type_ref": "DB_HTILE_SURFACE"

5024
  },

5025
  {

5026
   "chips": ["gfx81"],

5027
   "map": {"at": 166592, "to": "mm"},

5028
   "name": "DB_SRESULTS_COMPARE_STATE0",

5029
   "type_ref": "DB_SRESULTS_COMPARE_STATE0"

5030
  },

5031
  {

5032
   "chips": ["gfx81"],

5033
   "map": {"at": 166596, "to": "mm"},

5034
   "name": "DB_SRESULTS_COMPARE_STATE1",

5035
   "type_ref": "DB_SRESULTS_COMPARE_STATE1"

5036
  },

5037
  {

5038
   "chips": ["gfx81"],

5039
   "map": {"at": 166600, "to": "mm"},

5040
   "name": "DB_PRELOAD_CONTROL",

5041
   "type_ref": "DB_PRELOAD_CONTROL"

5042
  },

5043
  {

5044
   "chips": ["gfx81"],

5045
   "map": {"at": 166608, "to": "mm"},

5046
   "name": "VGT_STRMOUT_BUFFER_SIZE_0"

5047
  },

5048
  {

5049
   "chips": ["gfx81"],

5050
   "map": {"at": 166612, "to": "mm"},

5051
   "name": "VGT_STRMOUT_VTX_STRIDE_0",

5052
   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"

5053
  },

5054
  {

5055
   "chips": ["gfx81"],

5056
   "map": {"at": 166620, "to": "mm"},

5057
   "name": "VGT_STRMOUT_BUFFER_OFFSET_0"

5058
  },

5059
  {

5060
   "chips": ["gfx81"],

5061
   "map": {"at": 166624, "to": "mm"},

5062
   "name": "VGT_STRMOUT_BUFFER_SIZE_1"

5063
  },

5064
  {

5065
   "chips": ["gfx81"],

5066
   "map": {"at": 166628, "to": "mm"},

5067
   "name": "VGT_STRMOUT_VTX_STRIDE_1",

5068
   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"

5069
  },

5070
  {

5071
   "chips": ["gfx81"],

5072
   "map": {"at": 166636, "to": "mm"},

5073
   "name": "VGT_STRMOUT_BUFFER_OFFSET_1"

5074
  },

5075
  {

5076
   "chips": ["gfx81"],

5077
   "map": {"at": 166640, "to": "mm"},

5078
   "name": "VGT_STRMOUT_BUFFER_SIZE_2"

5079
  },

5080
  {

5081
   "chips": ["gfx81"],

5082
   "map": {"at": 166644, "to": "mm"},

5083
   "name": "VGT_STRMOUT_VTX_STRIDE_2",

5084
   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"

5085
  },

5086
  {

5087
   "chips": ["gfx81"],

5088
   "map": {"at": 166652, "to": "mm"},

5089
   "name": "VGT_STRMOUT_BUFFER_OFFSET_2"

5090
  },

5091
  {

5092
   "chips": ["gfx81"],

5093
   "map": {"at": 166656, "to": "mm"},

5094
   "name": "VGT_STRMOUT_BUFFER_SIZE_3"

5095
  },

5096
  {

5097
   "chips": ["gfx81"],

5098
   "map": {"at": 166660, "to": "mm"},

5099
   "name": "VGT_STRMOUT_VTX_STRIDE_3",

5100
   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"

5101
  },

5102
  {

5103
   "chips": ["gfx81"],

5104
   "map": {"at": 166668, "to": "mm"},

5105
   "name": "VGT_STRMOUT_BUFFER_OFFSET_3"

5106
  },

5107
  {

5108
   "chips": ["gfx81"],

5109
   "map": {"at": 166696, "to": "mm"},

5110
   "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET"

5111
  },

5112
  {

5113
   "chips": ["gfx81"],

5114
   "map": {"at": 166700, "to": "mm"},

5115
   "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE"

5116
  },

5117
  {

5118
   "chips": ["gfx81"],

5119
   "map": {"at": 166704, "to": "mm"},

5120
   "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",

5121
   "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE"

5122
  },

5123
  {

5124
   "chips": ["gfx81"],

5125
   "map": {"at": 166712, "to": "mm"},

5126
   "name": "VGT_GS_MAX_VERT_OUT",

5127
   "type_ref": "VGT_GS_MAX_VERT_OUT"

5128
  },

5129
  {

5130
   "chips": ["gfx81"],

5131
   "map": {"at": 166736, "to": "mm"},

5132
   "name": "VGT_TESS_DISTRIBUTION",

5133
   "type_ref": "VGT_TESS_DISTRIBUTION"

5134
  },

5135
  {

5136
   "chips": ["gfx81"],

5137
   "map": {"at": 166740, "to": "mm"},

5138
   "name": "VGT_SHADER_STAGES_EN",

5139
   "type_ref": "VGT_SHADER_STAGES_EN"

5140
  },

5141
  {

5142
   "chips": ["gfx81"],

5143
   "map": {"at": 166744, "to": "mm"},

5144
   "name": "VGT_LS_HS_CONFIG",

5145
   "type_ref": "VGT_LS_HS_CONFIG"

5146
  },

5147
  {

5148
   "chips": ["gfx81"],

5149
   "map": {"at": 166748, "to": "mm"},

5150
   "name": "VGT_GS_VERT_ITEMSIZE",

5151
   "type_ref": "VGT_ESGS_RING_ITEMSIZE"

5152
  },

5153
  {

5154
   "chips": ["gfx81"],

5155
   "map": {"at": 166752, "to": "mm"},

5156
   "name": "VGT_GS_VERT_ITEMSIZE_1",

5157
   "type_ref": "VGT_ESGS_RING_ITEMSIZE"

5158
  },

5159
  {

5160
   "chips": ["gfx81"],

5161
   "map": {"at": 166756, "to": "mm"},

5162
   "name": "VGT_GS_VERT_ITEMSIZE_2",

5163
   "type_ref": "VGT_ESGS_RING_ITEMSIZE"

5164
  },

5165
  {

5166
   "chips": ["gfx81"],

5167
   "map": {"at": 166760, "to": "mm"},

5168
   "name": "VGT_GS_VERT_ITEMSIZE_3",

5169
   "type_ref": "VGT_ESGS_RING_ITEMSIZE"

5170
  },

5171
  {

5172
   "chips": ["gfx81"],

5173
   "map": {"at": 166764, "to": "mm"},

5174
   "name": "VGT_TF_PARAM",

5175
   "type_ref": "VGT_TF_PARAM"

5176
  },

5177
  {

5178
   "chips": ["gfx81"],

5179
   "map": {"at": 166768, "to": "mm"},

5180
   "name": "DB_ALPHA_TO_MASK",

5181
   "type_ref": "DB_ALPHA_TO_MASK"

5182
  },

5183
  {

5184
   "chips": ["gfx81"],

5185
   "map": {"at": 166772, "to": "mm"},

5186
   "name": "VGT_DISPATCH_DRAW_INDEX"

5187
  },

5188
  {

5189
   "chips": ["gfx81"],

5190
   "map": {"at": 166776, "to": "mm"},

5191
   "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",

5192
   "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL"

5193
  },

5194
  {

5195
   "chips": ["gfx81"],

5196
   "map": {"at": 166780, "to": "mm"},

5197
   "name": "PA_SU_POLY_OFFSET_CLAMP"

5198
  },

5199
  {

5200
   "chips": ["gfx81"],

5201
   "map": {"at": 166784, "to": "mm"},

5202
   "name": "PA_SU_POLY_OFFSET_FRONT_SCALE"

5203
  },

5204
  {

5205
   "chips": ["gfx81"],

5206
   "map": {"at": 166788, "to": "mm"},

5207
   "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET"

5208
  },

5209
  {

5210
   "chips": ["gfx81"],

5211
   "map": {"at": 166792, "to": "mm"},

5212
   "name": "PA_SU_POLY_OFFSET_BACK_SCALE"

5213
  },

5214
  {

5215
   "chips": ["gfx81"],

5216
   "map": {"at": 166796, "to": "mm"},

5217
   "name": "PA_SU_POLY_OFFSET_BACK_OFFSET"

5218
  },

5219
  {

5220
   "chips": ["gfx81"],

5221
   "map": {"at": 166800, "to": "mm"},

5222
   "name": "VGT_GS_INSTANCE_CNT",

5223
   "type_ref": "VGT_GS_INSTANCE_CNT"

5224
  },

5225
  {

5226
   "chips": ["gfx81"],

5227
   "map": {"at": 166804, "to": "mm"},

5228
   "name": "VGT_STRMOUT_CONFIG",

5229
   "type_ref": "VGT_STRMOUT_CONFIG"

5230
  },

5231
  {

5232
   "chips": ["gfx81"],

5233
   "map": {"at": 166808, "to": "mm"},

5234
   "name": "VGT_STRMOUT_BUFFER_CONFIG",

5235
   "type_ref": "VGT_STRMOUT_BUFFER_CONFIG"

5236
  },

5237
  {

5238
   "chips": ["gfx81"],

5239
   "map": {"at": 166868, "to": "mm"},

5240
   "name": "PA_SC_CENTROID_PRIORITY_0",

5241
   "type_ref": "PA_SC_CENTROID_PRIORITY_0"

5242
  },

5243
  {

5244
   "chips": ["gfx81"],

5245
   "map": {"at": 166872, "to": "mm"},

5246
   "name": "PA_SC_CENTROID_PRIORITY_1",

5247
   "type_ref": "PA_SC_CENTROID_PRIORITY_1"

5248
  },

5249
  {

5250
   "chips": ["gfx81"],

5251
   "map": {"at": 166876, "to": "mm"},

5252
   "name": "PA_SC_LINE_CNTL",

5253
   "type_ref": "PA_SC_LINE_CNTL"

5254
  },

5255
  {

5256
   "chips": ["gfx81"],

5257
   "map": {"at": 166880, "to": "mm"},

5258
   "name": "PA_SC_AA_CONFIG",

5259
   "type_ref": "PA_SC_AA_CONFIG"

5260
  },

5261
  {

5262
   "chips": ["gfx81"],

5263
   "map": {"at": 166884, "to": "mm"},

5264
   "name": "PA_SU_VTX_CNTL",

5265
   "type_ref": "PA_SU_VTX_CNTL"

5266
  },

5267
  {

5268
   "chips": ["gfx81"],

5269
   "map": {"at": 166888, "to": "mm"},

5270
   "name": "PA_CL_GB_VERT_CLIP_ADJ"

5271
  },

5272
  {

5273
   "chips": ["gfx81"],

5274
   "map": {"at": 166892, "to": "mm"},

5275
   "name": "PA_CL_GB_VERT_DISC_ADJ"

5276
  },

5277
  {

5278
   "chips": ["gfx81"],

5279
   "map": {"at": 166896, "to": "mm"},

5280
   "name": "PA_CL_GB_HORZ_CLIP_ADJ"

5281
  },

5282
  {

5283
   "chips": ["gfx81"],

5284
   "map": {"at": 166900, "to": "mm"},

5285
   "name": "PA_CL_GB_HORZ_DISC_ADJ"

5286
  },

5287
  {

5288
   "chips": ["gfx81"],

5289
   "map": {"at": 166904, "to": "mm"},

5290
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",

5291
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"

5292
  },

5293
  {

5294
   "chips": ["gfx81"],

5295
   "map": {"at": 166908, "to": "mm"},

5296
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",

5297
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"

5298
  },

5299
  {

5300
   "chips": ["gfx81"],

5301
   "map": {"at": 166912, "to": "mm"},

5302
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",

5303
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"

5304
  },

5305
  {

5306
   "chips": ["gfx81"],

5307
   "map": {"at": 166916, "to": "mm"},

5308
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",

5309
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"

5310
  },

5311
  {

5312
   "chips": ["gfx81"],

5313
   "map": {"at": 166920, "to": "mm"},

5314
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",

5315
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"

5316
  },

5317
  {

5318
   "chips": ["gfx81"],

5319
   "map": {"at": 166924, "to": "mm"},

5320
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",

5321
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"

5322
  },

5323
  {

5324
   "chips": ["gfx81"],

5325
   "map": {"at": 166928, "to": "mm"},

5326
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",

5327
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"

5328
  },

5329
  {

5330
   "chips": ["gfx81"],

5331
   "map": {"at": 166932, "to": "mm"},

5332
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",

5333
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"

5334
  },

5335
  {

5336
   "chips": ["gfx81"],

5337
   "map": {"at": 166936, "to": "mm"},

5338
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",

5339
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"

5340
  },

5341
  {

5342
   "chips": ["gfx81"],

5343
   "map": {"at": 166940, "to": "mm"},

5344
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",

5345
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"

5346
  },

5347
  {

5348
   "chips": ["gfx81"],

5349
   "map": {"at": 166944, "to": "mm"},

5350
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",

5351
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"

5352
  },

5353
  {

5354
   "chips": ["gfx81"],

5355
   "map": {"at": 166948, "to": "mm"},

5356
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",

5357
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"

5358
  },

5359
  {

5360
   "chips": ["gfx81"],

5361
   "map": {"at": 166952, "to": "mm"},

5362
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",

5363
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"

5364
  },

5365
  {

5366
   "chips": ["gfx81"],

5367
   "map": {"at": 166956, "to": "mm"},

5368
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",

5369
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"

5370
  },

5371
  {

5372
   "chips": ["gfx81"],

5373
   "map": {"at": 166960, "to": "mm"},

5374
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",

5375
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"

5376
  },

5377
  {

5378
   "chips": ["gfx81"],

5379
   "map": {"at": 166964, "to": "mm"},

5380
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",

5381
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"

5382
  },

5383
  {

5384
   "chips": ["gfx81"],

5385
   "map": {"at": 166968, "to": "mm"},

5386
   "name": "PA_SC_AA_MASK_X0Y0_X1Y0",

5387
   "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0"

5388
  },

5389
  {

5390
   "chips": ["gfx81"],

5391
   "map": {"at": 166972, "to": "mm"},

5392
   "name": "PA_SC_AA_MASK_X0Y1_X1Y1",

5393
   "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1"

5394
  },

5395
  {

5396
   "chips": ["gfx81"],

5397
   "map": {"at": 166976, "to": "mm"},

5398
   "name": "PA_SC_SHADER_CONTROL",

5399
   "type_ref": "PA_SC_SHADER_CONTROL"

5400
  },

5401
  {

5402
   "chips": ["gfx81"],

5403
   "map": {"at": 167000, "to": "mm"},

5404
   "name": "VGT_VERTEX_REUSE_BLOCK_CNTL",

5405
   "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL"

5406
  },

5407
  {

5408
   "chips": ["gfx81"],

5409
   "map": {"at": 167004, "to": "mm"},

5410
   "name": "VGT_OUT_DEALLOC_CNTL",

5411
   "type_ref": "VGT_OUT_DEALLOC_CNTL"

5412
  },

5413
  {

5414
   "chips": ["gfx81"],

5415
   "map": {"at": 167008, "to": "mm"},

5416
   "name": "CB_COLOR0_BASE"

5417
  },

5418
  {

5419
   "chips": ["gfx81"],

5420
   "map": {"at": 167012, "to": "mm"},

5421
   "name": "CB_COLOR0_PITCH",

5422
   "type_ref": "CB_COLOR0_PITCH"

5423
  },

5424
  {

5425
   "chips": ["gfx81"],

5426
   "map": {"at": 167016, "to": "mm"},

5427
   "name": "CB_COLOR0_SLICE",

5428
   "type_ref": "CB_COLOR0_SLICE"

5429
  },

5430
  {

5431
   "chips": ["gfx81"],

5432
   "map": {"at": 167020, "to": "mm"},

5433
   "name": "CB_COLOR0_VIEW",

5434
   "type_ref": "CB_COLOR0_VIEW"

5435
  },

5436
  {

5437
   "chips": ["gfx81"],

5438
   "map": {"at": 167024, "to": "mm"},

5439
   "name": "CB_COLOR0_INFO",

5440
   "type_ref": "CB_COLOR0_INFO"

5441
  },

5442
  {

5443
   "chips": ["gfx81"],

5444
   "map": {"at": 167028, "to": "mm"},

5445
   "name": "CB_COLOR0_ATTRIB",

5446
   "type_ref": "CB_COLOR0_ATTRIB"

5447
  },

5448
  {

5449
   "chips": ["gfx81"],

5450
   "map": {"at": 167032, "to": "mm"},

5451
   "name": "CB_COLOR0_DCC_CONTROL",

5452
   "type_ref": "CB_COLOR0_DCC_CONTROL"

5453
  },

5454
  {

5455
   "chips": ["gfx81"],

5456
   "map": {"at": 167036, "to": "mm"},

5457
   "name": "CB_COLOR0_CMASK"

5458
  },

5459
  {

5460
   "chips": ["gfx81"],

5461
   "map": {"at": 167040, "to": "mm"},

5462
   "name": "CB_COLOR0_CMASK_SLICE",

5463
   "type_ref": "CB_COLOR0_CMASK_SLICE"

5464
  },

5465
  {

5466
   "chips": ["gfx81"],

5467
   "map": {"at": 167044, "to": "mm"},

5468
   "name": "CB_COLOR0_FMASK"

5469
  },

5470
  {

5471
   "chips": ["gfx81"],

5472
   "map": {"at": 167048, "to": "mm"},

5473
   "name": "CB_COLOR0_FMASK_SLICE",

5474
   "type_ref": "CB_COLOR0_SLICE"

5475
  },

5476
  {

5477
   "chips": ["gfx81"],

5478
   "map": {"at": 167052, "to": "mm"},

5479
   "name": "CB_COLOR0_CLEAR_WORD0"

5480
  },

5481
  {

5482
   "chips": ["gfx81"],

5483
   "map": {"at": 167056, "to": "mm"},

5484
   "name": "CB_COLOR0_CLEAR_WORD1"

5485
  },

5486
  {

5487
   "chips": ["gfx81"],

5488
   "map": {"at": 167060, "to": "mm"},

5489
   "name": "CB_COLOR0_DCC_BASE"

5490
  },

5491
  {

5492
   "chips": ["gfx81"],

5493
   "map": {"at": 167068, "to": "mm"},

5494
   "name": "CB_COLOR1_BASE"

5495
  },

5496
  {

5497
   "chips": ["gfx81"],

5498
   "map": {"at": 167072, "to": "mm"},

5499
   "name": "CB_COLOR1_PITCH",

5500
   "type_ref": "CB_COLOR0_PITCH"

5501
  },

5502
  {

5503
   "chips": ["gfx81"],

5504
   "map": {"at": 167076, "to": "mm"},

5505
   "name": "CB_COLOR1_SLICE",

5506
   "type_ref": "CB_COLOR0_SLICE"

5507
  },

5508
  {

5509
   "chips": ["gfx81"],

5510
   "map": {"at": 167080, "to": "mm"},

5511
   "name": "CB_COLOR1_VIEW",

5512
   "type_ref": "CB_COLOR0_VIEW"

5513
  },

5514
  {

5515
   "chips": ["gfx81"],

5516
   "map": {"at": 167084, "to": "mm"},

5517
   "name": "CB_COLOR1_INFO",

5518
   "type_ref": "CB_COLOR0_INFO"

5519
  },

5520
  {

5521
   "chips": ["gfx81"],

5522
   "map": {"at": 167088, "to": "mm"},

5523
   "name": "CB_COLOR1_ATTRIB",

5524
   "type_ref": "CB_COLOR0_ATTRIB"

5525
  },

5526
  {

5527
   "chips": ["gfx81"],

5528
   "map": {"at": 167092, "to": "mm"},

5529
   "name": "CB_COLOR1_DCC_CONTROL",

5530
   "type_ref": "CB_COLOR0_DCC_CONTROL"

5531
  },

5532
  {

5533
   "chips": ["gfx81"],

5534
   "map": {"at": 167096, "to": "mm"},

5535
   "name": "CB_COLOR1_CMASK"

5536
  },

5537
  {

5538
   "chips": ["gfx81"],

5539
   "map": {"at": 167100, "to": "mm"},

5540
   "name": "CB_COLOR1_CMASK_SLICE",

5541
   "type_ref": "CB_COLOR0_CMASK_SLICE"

5542
  },

5543
  {

5544
   "chips": ["gfx81"],

5545
   "map": {"at": 167104, "to": "mm"},

5546
   "name": "CB_COLOR1_FMASK"

5547
  },

5548
  {

5549
   "chips": ["gfx81"],

5550
   "map": {"at": 167108, "to": "mm"},

5551
   "name": "CB_COLOR1_FMASK_SLICE",

5552
   "type_ref": "CB_COLOR0_SLICE"

5553
  },

5554
  {

5555
   "chips": ["gfx81"],

5556
   "map": {"at": 167112, "to": "mm"},

5557
   "name": "CB_COLOR1_CLEAR_WORD0"

5558
  },

5559
  {

5560
   "chips": ["gfx81"],

5561
   "map": {"at": 167116, "to": "mm"},

5562
   "name": "CB_COLOR1_CLEAR_WORD1"

5563
  },

5564
  {

5565
   "chips": ["gfx81"],

5566
   "map": {"at": 167120, "to": "mm"},

5567
   "name": "CB_COLOR1_DCC_BASE"

5568
  },

5569
  {

5570
   "chips": ["gfx81"],

5571
   "map": {"at": 167128, "to": "mm"},

5572
   "name": "CB_COLOR2_BASE"

5573
  },

5574
  {

5575
   "chips": ["gfx81"],

5576
   "map": {"at": 167132, "to": "mm"},

5577
   "name": "CB_COLOR2_PITCH",

5578
   "type_ref": "CB_COLOR0_PITCH"

5579
  },

5580
  {

5581
   "chips": ["gfx81"],

5582
   "map": {"at": 167136, "to": "mm"},

5583
   "name": "CB_COLOR2_SLICE",

5584
   "type_ref": "CB_COLOR0_SLICE"

5585
  },

5586
  {

5587
   "chips": ["gfx81"],

5588
   "map": {"at": 167140, "to": "mm"},

5589
   "name": "CB_COLOR2_VIEW",

5590
   "type_ref": "CB_COLOR0_VIEW"

5591
  },

5592
  {

5593
   "chips": ["gfx81"],

5594
   "map": {"at": 167144, "to": "mm"},

5595
   "name": "CB_COLOR2_INFO",

5596
   "type_ref": "CB_COLOR0_INFO"

5597
  },

5598
  {

5599
   "chips": ["gfx81"],

5600
   "map": {"at": 167148, "to": "mm"},

5601
   "name": "CB_COLOR2_ATTRIB",

5602
   "type_ref": "CB_COLOR0_ATTRIB"

5603
  },

5604
  {

5605
   "chips": ["gfx81"],

5606
   "map": {"at": 167152, "to": "mm"},

5607
   "name": "CB_COLOR2_DCC_CONTROL",

5608
   "type_ref": "CB_COLOR0_DCC_CONTROL"

5609
  },

5610
  {

5611
   "chips": ["gfx81"],

5612
   "map": {"at": 167156, "to": "mm"},

5613
   "name": "CB_COLOR2_CMASK"

5614
  },

5615
  {

5616
   "chips": ["gfx81"],

5617
   "map": {"at": 167160, "to": "mm"},

5618
   "name": "CB_COLOR2_CMASK_SLICE",

5619
   "type_ref": "CB_COLOR0_CMASK_SLICE"

5620
  },

5621
  {

5622
   "chips": ["gfx81"],

5623
   "map": {"at": 167164, "to": "mm"},

5624
   "name": "CB_COLOR2_FMASK"

5625
  },

5626
  {

5627
   "chips": ["gfx81"],

5628
   "map": {"at": 167168, "to": "mm"},

5629
   "name": "CB_COLOR2_FMASK_SLICE",

5630
   "type_ref": "CB_COLOR0_SLICE"

5631
  },

5632
  {

5633
   "chips": ["gfx81"],

5634
   "map": {"at": 167172, "to": "mm"},

5635
   "name": "CB_COLOR2_CLEAR_WORD0"

5636
  },

5637
  {

5638
   "chips": ["gfx81"],

5639
   "map": {"at": 167176, "to": "mm"},

5640
   "name": "CB_COLOR2_CLEAR_WORD1"

5641
  },

5642
  {

5643
   "chips": ["gfx81"],

5644
   "map": {"at": 167180, "to": "mm"},

5645
   "name": "CB_COLOR2_DCC_BASE"

5646
  },

5647
  {

5648
   "chips": ["gfx81"],

5649
   "map": {"at": 167188, "to": "mm"},

5650
   "name": "CB_COLOR3_BASE"

5651
  },

5652
  {

5653
   "chips": ["gfx81"],

5654
   "map": {"at": 167192, "to": "mm"},

5655
   "name": "CB_COLOR3_PITCH",

5656
   "type_ref": "CB_COLOR0_PITCH"

5657
  },

5658
  {

5659
   "chips": ["gfx81"],

5660
   "map": {"at": 167196, "to": "mm"},

5661
   "name": "CB_COLOR3_SLICE",

5662
   "type_ref": "CB_COLOR0_SLICE"

5663
  },

5664
  {

5665
   "chips": ["gfx81"],

5666
   "map": {"at": 167200, "to": "mm"},

5667
   "name": "CB_COLOR3_VIEW",

5668
   "type_ref": "CB_COLOR0_VIEW"

5669
  },

5670
  {

5671
   "chips": ["gfx81"],

5672
   "map": {"at": 167204, "to": "mm"},

5673
   "name": "CB_COLOR3_INFO",

5674
   "type_ref": "CB_COLOR0_INFO"

5675
  },

5676
  {

5677
   "chips": ["gfx81"],

5678
   "map": {"at": 167208, "to": "mm"},

5679
   "name": "CB_COLOR3_ATTRIB",

5680
   "type_ref": "CB_COLOR0_ATTRIB"

5681
  },

5682
  {

5683
   "chips": ["gfx81"],

5684
   "map": {"at": 167212, "to": "mm"},

5685
   "name": "CB_COLOR3_DCC_CONTROL",

5686
   "type_ref": "CB_COLOR0_DCC_CONTROL"

5687
  },

5688
  {

5689
   "chips": ["gfx81"],

5690
   "map": {"at": 167216, "to": "mm"},

5691
   "name": "CB_COLOR3_CMASK"

5692
  },

5693
  {

5694
   "chips": ["gfx81"],

5695
   "map": {"at": 167220, "to": "mm"},

5696
   "name": "CB_COLOR3_CMASK_SLICE",

5697
   "type_ref": "CB_COLOR0_CMASK_SLICE"

5698
  },

5699
  {

5700
   "chips": ["gfx81"],

5701
   "map": {"at": 167224, "to": "mm"},

5702
   "name": "CB_COLOR3_FMASK"

5703
  },

5704
  {

5705
   "chips": ["gfx81"],

5706
   "map": {"at": 167228, "to": "mm"},

5707
   "name": "CB_COLOR3_FMASK_SLICE",

5708
   "type_ref": "CB_COLOR0_SLICE"

5709
  },

5710
  {

5711
   "chips": ["gfx81"],

5712
   "map": {"at": 167232, "to": "mm"},

5713
   "name": "CB_COLOR3_CLEAR_WORD0"

5714
  },

5715
  {

5716
   "chips": ["gfx81"],

5717
   "map": {"at": 167236, "to": "mm"},

5718
   "name": "CB_COLOR3_CLEAR_WORD1"

5719
  },

5720
  {

5721
   "chips": ["gfx81"],

5722
   "map": {"at": 167240, "to": "mm"},

5723
   "name": "CB_COLOR3_DCC_BASE"

5724
  },

5725
  {

5726
   "chips": ["gfx81"],

5727
   "map": {"at": 167248, "to": "mm"},

5728
   "name": "CB_COLOR4_BASE"

5729
  },

5730
  {

5731
   "chips": ["gfx81"],

5732
   "map": {"at": 167252, "to": "mm"},

5733
   "name": "CB_COLOR4_PITCH",

5734
   "type_ref": "CB_COLOR0_PITCH"

5735
  },

5736
  {

5737
   "chips": ["gfx81"],

5738
   "map": {"at": 167256, "to": "mm"},

5739
   "name": "CB_COLOR4_SLICE",

5740
   "type_ref": "CB_COLOR0_SLICE"

5741
  },

5742
  {

5743
   "chips": ["gfx81"],

5744
   "map": {"at": 167260, "to": "mm"},

5745
   "name": "CB_COLOR4_VIEW",

5746
   "type_ref": "CB_COLOR0_VIEW"

5747
  },

5748
  {

5749
   "chips": ["gfx81"],

5750
   "map": {"at": 167264, "to": "mm"},

5751
   "name": "CB_COLOR4_INFO",

5752
   "type_ref": "CB_COLOR0_INFO"

5753
  },

5754
  {

5755
   "chips": ["gfx81"],

5756
   "map": {"at": 167268, "to": "mm"},

5757
   "name": "CB_COLOR4_ATTRIB",

5758
   "type_ref": "CB_COLOR0_ATTRIB"

5759
  },

5760
  {

5761
   "chips": ["gfx81"],

5762
   "map": {"at": 167272, "to": "mm"},

5763
   "name": "CB_COLOR4_DCC_CONTROL",

5764
   "type_ref": "CB_COLOR0_DCC_CONTROL"

5765
  },

5766
  {

5767
   "chips": ["gfx81"],

5768
   "map": {"at": 167276, "to": "mm"},

5769
   "name": "CB_COLOR4_CMASK"

5770
  },

5771
  {

5772
   "chips": ["gfx81"],

5773
   "map": {"at": 167280, "to": "mm"},

5774
   "name": "CB_COLOR4_CMASK_SLICE",

5775
   "type_ref": "CB_COLOR0_CMASK_SLICE"

5776
  },

5777
  {

5778
   "chips": ["gfx81"],

5779
   "map": {"at": 167284, "to": "mm"},

5780
   "name": "CB_COLOR4_FMASK"

5781
  },

5782
  {

5783
   "chips": ["gfx81"],

5784
   "map": {"at": 167288, "to": "mm"},

5785
   "name": "CB_COLOR4_FMASK_SLICE",

5786
   "type_ref": "CB_COLOR0_SLICE"

5787
  },

5788
  {

5789
   "chips": ["gfx81"],

5790
   "map": {"at": 167292, "to": "mm"},

5791
   "name": "CB_COLOR4_CLEAR_WORD0"

5792
  },

5793
  {

5794
   "chips": ["gfx81"],

5795
   "map": {"at": 167296, "to": "mm"},

5796
   "name": "CB_COLOR4_CLEAR_WORD1"

5797
  },

5798
  {

5799
   "chips": ["gfx81"],

5800
   "map": {"at": 167300, "to": "mm"},

5801
   "name": "CB_COLOR4_DCC_BASE"

5802
  },

5803
  {

5804
   "chips": ["gfx81"],

5805
   "map": {"at": 167308, "to": "mm"},

5806
   "name": "CB_COLOR5_BASE"

5807
  },

5808
  {

5809
   "chips": ["gfx81"],

5810
   "map": {"at": 167312, "to": "mm"},

5811
   "name": "CB_COLOR5_PITCH",

5812
   "type_ref": "CB_COLOR0_PITCH"

5813
  },

5814
  {

5815
   "chips": ["gfx81"],

5816
   "map": {"at": 167316, "to": "mm"},

5817
   "name": "CB_COLOR5_SLICE",

5818
   "type_ref": "CB_COLOR0_SLICE"

5819
  },

5820
  {

5821
   "chips": ["gfx81"],

5822
   "map": {"at": 167320, "to": "mm"},

5823
   "name": "CB_COLOR5_VIEW",

5824
   "type_ref": "CB_COLOR0_VIEW"

5825
  },

5826
  {

5827
   "chips": ["gfx81"],

5828
   "map": {"at": 167324, "to": "mm"},

5829
   "name": "CB_COLOR5_INFO",

5830
   "type_ref": "CB_COLOR0_INFO"

5831
  },

5832
  {

5833
   "chips": ["gfx81"],

5834
   "map": {"at": 167328, "to": "mm"},

5835
   "name": "CB_COLOR5_ATTRIB",

5836
   "type_ref": "CB_COLOR0_ATTRIB"

5837
  },

5838
  {

5839
   "chips": ["gfx81"],

5840
   "map": {"at": 167332, "to": "mm"},

5841
   "name": "CB_COLOR5_DCC_CONTROL",

5842
   "type_ref": "CB_COLOR0_DCC_CONTROL"

5843
  },

5844
  {

5845
   "chips": ["gfx81"],

5846
   "map": {"at": 167336, "to": "mm"},

5847
   "name": "CB_COLOR5_CMASK"

5848
  },

5849
  {

5850
   "chips": ["gfx81"],

5851
   "map": {"at": 167340, "to": "mm"},

5852
   "name": "CB_COLOR5_CMASK_SLICE",

5853
   "type_ref": "CB_COLOR0_CMASK_SLICE"

5854
  },

5855
  {

5856
   "chips": ["gfx81"],

5857
   "map": {"at": 167344, "to": "mm"},

5858
   "name": "CB_COLOR5_FMASK"

5859
  },

5860
  {

5861
   "chips": ["gfx81"],

5862
   "map": {"at": 167348, "to": "mm"},

5863
   "name": "CB_COLOR5_FMASK_SLICE",

5864
   "type_ref": "CB_COLOR0_SLICE"

5865
  },

5866
  {

5867
   "chips": ["gfx81"],

5868
   "map": {"at": 167352, "to": "mm"},

5869
   "name": "CB_COLOR5_CLEAR_WORD0"

5870
  },

5871
  {

5872
   "chips": ["gfx81"],

5873
   "map": {"at": 167356, "to": "mm"},

5874
   "name": "CB_COLOR5_CLEAR_WORD1"

5875
  },

5876
  {

5877
   "chips": ["gfx81"],

5878
   "map": {"at": 167360, "to": "mm"},

5879
   "name": "CB_COLOR5_DCC_BASE"

5880
  },

5881
  {

5882
   "chips": ["gfx81"],

5883
   "map": {"at": 167368, "to": "mm"},

5884
   "name": "CB_COLOR6_BASE"

5885
  },

5886
  {

5887
   "chips": ["gfx81"],

5888
   "map": {"at": 167372, "to": "mm"},

5889
   "name": "CB_COLOR6_PITCH",

5890
   "type_ref": "CB_COLOR0_PITCH"

5891
  },

5892
  {

5893
   "chips": ["gfx81"],

5894
   "map": {"at": 167376, "to": "mm"},

5895
   "name": "CB_COLOR6_SLICE",

5896
   "type_ref": "CB_COLOR0_SLICE"

5897
  },

5898
  {

5899
   "chips": ["gfx81"],

5900
   "map": {"at": 167380, "to": "mm"},

5901
   "name": "CB_COLOR6_VIEW",

5902
   "type_ref": "CB_COLOR0_VIEW"

5903
  },

5904
  {

5905
   "chips": ["gfx81"],

5906
   "map": {"at": 167384, "to": "mm"},

5907
   "name": "CB_COLOR6_INFO",

5908
   "type_ref": "CB_COLOR0_INFO"

5909
  },

5910
  {

5911
   "chips": ["gfx81"],

5912
   "map": {"at": 167388, "to": "mm"},

5913
   "name": "CB_COLOR6_ATTRIB",

5914
   "type_ref": "CB_COLOR0_ATTRIB"

5915
  },

5916
  {

5917
   "chips": ["gfx81"],

5918
   "map": {"at": 167392, "to": "mm"},

5919
   "name": "CB_COLOR6_DCC_CONTROL",

5920
   "type_ref": "CB_COLOR0_DCC_CONTROL"

5921
  },

5922
  {

5923
   "chips": ["gfx81"],

5924
   "map": {"at": 167396, "to": "mm"},

5925
   "name": "CB_COLOR6_CMASK"

5926
  },

5927
  {

5928
   "chips": ["gfx81"],

5929
   "map": {"at": 167400, "to": "mm"},

5930
   "name": "CB_COLOR6_CMASK_SLICE",

5931
   "type_ref": "CB_COLOR0_CMASK_SLICE"

5932
  },

5933
  {

5934
   "chips": ["gfx81"],

5935
   "map": {"at": 167404, "to": "mm"},

5936
   "name": "CB_COLOR6_FMASK"

5937
  },

5938
  {

5939
   "chips": ["gfx81"],

5940
   "map": {"at": 167408, "to": "mm"},

5941
   "name": "CB_COLOR6_FMASK_SLICE",

5942
   "type_ref": "CB_COLOR0_SLICE"

5943
  },

5944
  {

5945
   "chips": ["gfx81"],

5946
   "map": {"at": 167412, "to": "mm"},

5947
   "name": "CB_COLOR6_CLEAR_WORD0"

5948
  },

5949
  {

5950
   "chips": ["gfx81"],

5951
   "map": {"at": 167416, "to": "mm"},

5952
   "name": "CB_COLOR6_CLEAR_WORD1"

5953
  },

5954
  {

5955
   "chips": ["gfx81"],

5956
   "map": {"at": 167420, "to": "mm"},

5957
   "name": "CB_COLOR6_DCC_BASE"

5958
  },

5959
  {

5960
   "chips": ["gfx81"],

5961
   "map": {"at": 167428, "to": "mm"},

5962
   "name": "CB_COLOR7_BASE"

5963
  },

5964
  {

5965
   "chips": ["gfx81"],

5966
   "map": {"at": 167432, "to": "mm"},

5967
   "name": "CB_COLOR7_PITCH",

5968
   "type_ref": "CB_COLOR0_PITCH"

5969
  },

5970
  {

5971
   "chips": ["gfx81"],

5972
   "map": {"at": 167436, "to": "mm"},

5973
   "name": "CB_COLOR7_SLICE",

5974
   "type_ref": "CB_COLOR0_SLICE"

5975
  },

5976
  {

5977
   "chips": ["gfx81"],

5978
   "map": {"at": 167440, "to": "mm"},

5979
   "name": "CB_COLOR7_VIEW",

5980
   "type_ref": "CB_COLOR0_VIEW"

5981
  },

5982
  {

5983
   "chips": ["gfx81"],

5984
   "map": {"at": 167444, "to": "mm"},

5985
   "name": "CB_COLOR7_INFO",

5986
   "type_ref": "CB_COLOR0_INFO"

5987
  },

5988
  {

5989
   "chips": ["gfx81"],

5990
   "map": {"at": 167448, "to": "mm"},

5991
   "name": "CB_COLOR7_ATTRIB",

5992
   "type_ref": "CB_COLOR0_ATTRIB"

5993
  },

5994
  {

5995
   "chips": ["gfx81"],

5996
   "map": {"at": 167452, "to": "mm"},

5997
   "name": "CB_COLOR7_DCC_CONTROL",

5998
   "type_ref": "CB_COLOR0_DCC_CONTROL"

5999
  },

6000
  {

6001
   "chips": ["gfx81"],

6002
   "map": {"at": 167456, "to": "mm"},

6003
   "name": "CB_COLOR7_CMASK"

6004
  },

6005
  {

6006
   "chips": ["gfx81"],

6007
   "map": {"at": 167460, "to": "mm"},

6008
   "name": "CB_COLOR7_CMASK_SLICE",

6009
   "type_ref": "CB_COLOR0_CMASK_SLICE"

6010
  },

6011
  {

6012
   "chips": ["gfx81"],

6013
   "map": {"at": 167464, "to": "mm"},

6014
   "name": "CB_COLOR7_FMASK"

6015
  },

6016
  {

6017
   "chips": ["gfx81"],

6018
   "map": {"at": 167468, "to": "mm"},

6019
   "name": "CB_COLOR7_FMASK_SLICE",

6020
   "type_ref": "CB_COLOR0_SLICE"

6021
  },

6022
  {

6023
   "chips": ["gfx81"],

6024
   "map": {"at": 167472, "to": "mm"},

6025
   "name": "CB_COLOR7_CLEAR_WORD0"

6026
  },

6027
  {

6028
   "chips": ["gfx81"],

6029
   "map": {"at": 167476, "to": "mm"},

6030
   "name": "CB_COLOR7_CLEAR_WORD1"

6031
  },

6032
  {

6033
   "chips": ["gfx81"],

6034
   "map": {"at": 167480, "to": "mm"},

6035
   "name": "CB_COLOR7_DCC_BASE"

6036
  },

6037
  {

6038
   "chips": ["gfx81"],

6039
   "map": {"at": 196608, "to": "mm"},

6040
   "name": "CP_EOP_DONE_ADDR_LO",

6041
   "type_ref": "CP_EOP_DONE_ADDR_LO"

6042
  },

6043
  {

6044
   "chips": ["gfx81"],

6045
   "map": {"at": 196612, "to": "mm"},

6046
   "name": "CP_EOP_DONE_ADDR_HI",

6047
   "type_ref": "CP_EOP_DONE_ADDR_HI"

6048
  },

6049
  {

6050
   "chips": ["gfx81"],

6051
   "map": {"at": 196616, "to": "mm"},

6052
   "name": "CP_EOP_DONE_DATA_LO"

6053
  },

6054
  {

6055
   "chips": ["gfx81"],

6056
   "map": {"at": 196620, "to": "mm"},

6057
   "name": "CP_EOP_DONE_DATA_HI"

6058
  },

6059
  {

6060
   "chips": ["gfx81"],

6061
   "map": {"at": 196624, "to": "mm"},

6062
   "name": "CP_EOP_LAST_FENCE_LO"

6063
  },

6064
  {

6065
   "chips": ["gfx81"],

6066
   "map": {"at": 196628, "to": "mm"},

6067
   "name": "CP_EOP_LAST_FENCE_HI"

6068
  },

6069
  {

6070
   "chips": ["gfx81"],

6071
   "map": {"at": 196632, "to": "mm"},

6072
   "name": "CP_STREAM_OUT_ADDR_LO",

6073
   "type_ref": "CP_STREAM_OUT_ADDR_LO"

6074
  },

6075
  {

6076
   "chips": ["gfx81"],

6077
   "map": {"at": 196636, "to": "mm"},

6078
   "name": "CP_STREAM_OUT_ADDR_HI",

6079
   "type_ref": "CP_STREAM_OUT_ADDR_HI"

6080
  },

6081
  {

6082
   "chips": ["gfx81"],

6083
   "map": {"at": 196640, "to": "mm"},

6084
   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO"

6085
  },

6086
  {

6087
   "chips": ["gfx81"],

6088
   "map": {"at": 196644, "to": "mm"},

6089
   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI"

6090
  },

6091
  {

6092
   "chips": ["gfx81"],

6093
   "map": {"at": 196648, "to": "mm"},

6094
   "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO"

6095
  },

6096
  {

6097
   "chips": ["gfx81"],

6098
   "map": {"at": 196652, "to": "mm"},

6099
   "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI"

6100
  },

6101
  {

6102
   "chips": ["gfx81"],

6103
   "map": {"at": 196656, "to": "mm"},

6104
   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO"

6105
  },

6106
  {

6107
   "chips": ["gfx81"],

6108
   "map": {"at": 196660, "to": "mm"},

6109
   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI"

6110
  },

6111
  {

6112
   "chips": ["gfx81"],

6113
   "map": {"at": 196664, "to": "mm"},

6114
   "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO"

6115
  },

6116
  {

6117
   "chips": ["gfx81"],

6118
   "map": {"at": 196668, "to": "mm"},

6119
   "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI"

6120
  },

6121
  {

6122
   "chips": ["gfx81"],

6123
   "map": {"at": 196672, "to": "mm"},

6124
   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO"

6125
  },

6126
  {

6127
   "chips": ["gfx81"],

6128
   "map": {"at": 196676, "to": "mm"},

6129
   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI"

6130
  },

6131
  {

6132
   "chips": ["gfx81"],

6133
   "map": {"at": 196680, "to": "mm"},

6134
   "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO"

6135
  },

6136
  {

6137
   "chips": ["gfx81"],

6138
   "map": {"at": 196684, "to": "mm"},

6139
   "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI"

6140
  },

6141
  {

6142
   "chips": ["gfx81"],

6143
   "map": {"at": 196688, "to": "mm"},

6144
   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO"

6145
  },

6146
  {

6147
   "chips": ["gfx81"],

6148
   "map": {"at": 196692, "to": "mm"},

6149
   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI"

6150
  },

6151
  {

6152
   "chips": ["gfx81"],

6153
   "map": {"at": 196696, "to": "mm"},

6154
   "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO"

6155
  },

6156
  {

6157
   "chips": ["gfx81"],

6158
   "map": {"at": 196700, "to": "mm"},

6159
   "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI"

6160
  },

6161
  {

6162
   "chips": ["gfx81"],

6163
   "map": {"at": 196704, "to": "mm"},

6164
   "name": "CP_PIPE_STATS_ADDR_LO",

6165
   "type_ref": "CP_PIPE_STATS_ADDR_LO"

6166
  },

6167
  {

6168
   "chips": ["gfx81"],

6169
   "map": {"at": 196708, "to": "mm"},

6170
   "name": "CP_PIPE_STATS_ADDR_HI",

6171
   "type_ref": "CP_PIPE_STATS_ADDR_HI"

6172
  },

6173
  {

6174
   "chips": ["gfx81"],

6175
   "map": {"at": 196712, "to": "mm"},

6176
   "name": "CP_VGT_IAVERT_COUNT_LO"

6177
  },

6178
  {

6179
   "chips": ["gfx81"],

6180
   "map": {"at": 196716, "to": "mm"},

6181
   "name": "CP_VGT_IAVERT_COUNT_HI"

6182
  },

6183
  {

6184
   "chips": ["gfx81"],

6185
   "map": {"at": 196720, "to": "mm"},

6186
   "name": "CP_VGT_IAPRIM_COUNT_LO"

6187
  },

6188
  {

6189
   "chips": ["gfx81"],

6190
   "map": {"at": 196724, "to": "mm"},

6191
   "name": "CP_VGT_IAPRIM_COUNT_HI"

6192
  },

6193
  {

6194
   "chips": ["gfx81"],

6195
   "map": {"at": 196728, "to": "mm"},

6196
   "name": "CP_VGT_GSPRIM_COUNT_LO"

6197
  },

6198
  {

6199
   "chips": ["gfx81"],

6200
   "map": {"at": 196732, "to": "mm"},

6201
   "name": "CP_VGT_GSPRIM_COUNT_HI"

6202
  },

6203
  {

6204
   "chips": ["gfx81"],

6205
   "map": {"at": 196736, "to": "mm"},

6206
   "name": "CP_VGT_VSINVOC_COUNT_LO"

6207
  },

6208
  {

6209
   "chips": ["gfx81"],

6210
   "map": {"at": 196740, "to": "mm"},

6211
   "name": "CP_VGT_VSINVOC_COUNT_HI"

6212
  },

6213
  {

6214
   "chips": ["gfx81"],

6215
   "map": {"at": 196744, "to": "mm"},

6216
   "name": "CP_VGT_GSINVOC_COUNT_LO"

6217
  },

6218
  {

6219
   "chips": ["gfx81"],

6220
   "map": {"at": 196748, "to": "mm"},

6221
   "name": "CP_VGT_GSINVOC_COUNT_HI"

6222
  },

6223
  {

6224
   "chips": ["gfx81"],

6225
   "map": {"at": 196752, "to": "mm"},

6226
   "name": "CP_VGT_HSINVOC_COUNT_LO"

6227
  },

6228
  {

6229
   "chips": ["gfx81"],

6230
   "map": {"at": 196756, "to": "mm"},

6231
   "name": "CP_VGT_HSINVOC_COUNT_HI"

6232
  },

6233
  {

6234
   "chips": ["gfx81"],

6235
   "map": {"at": 196760, "to": "mm"},

6236
   "name": "CP_VGT_DSINVOC_COUNT_LO"

6237
  },

6238
  {

6239
   "chips": ["gfx81"],

6240
   "map": {"at": 196764, "to": "mm"},

6241
   "name": "CP_VGT_DSINVOC_COUNT_HI"

6242
  },

6243
  {

6244
   "chips": ["gfx81"],

6245
   "map": {"at": 196768, "to": "mm"},

6246
   "name": "CP_PA_CINVOC_COUNT_LO"

6247
  },

6248
  {

6249
   "chips": ["gfx81"],

6250
   "map": {"at": 196772, "to": "mm"},

6251
   "name": "CP_PA_CINVOC_COUNT_HI"

6252
  },

6253
  {

6254
   "chips": ["gfx81"],

6255
   "map": {"at": 196776, "to": "mm"},

6256
   "name": "CP_PA_CPRIM_COUNT_LO"

6257
  },

6258
  {

6259
   "chips": ["gfx81"],

6260
   "map": {"at": 196780, "to": "mm"},

6261
   "name": "CP_PA_CPRIM_COUNT_HI"

6262
  },

6263
  {

6264
   "chips": ["gfx81"],

6265
   "map": {"at": 196784, "to": "mm"},

6266
   "name": "CP_SC_PSINVOC_COUNT0_LO"

6267
  },

6268
  {

6269
   "chips": ["gfx81"],

6270
   "map": {"at": 196788, "to": "mm"},

6271
   "name": "CP_SC_PSINVOC_COUNT0_HI"

6272
  },

6273
  {

6274
   "chips": ["gfx81"],

6275
   "map": {"at": 196792, "to": "mm"},

6276
   "name": "CP_SC_PSINVOC_COUNT1_LO"

6277
  },

6278
  {

6279
   "chips": ["gfx81"],

6280
   "map": {"at": 196796, "to": "mm"},

6281
   "name": "CP_SC_PSINVOC_COUNT1_HI"

6282
  },

6283
  {

6284
   "chips": ["gfx81"],

6285
   "map": {"at": 196800, "to": "mm"},

6286
   "name": "CP_VGT_CSINVOC_COUNT_LO"

6287
  },

6288
  {

6289
   "chips": ["gfx81"],

6290
   "map": {"at": 196804, "to": "mm"},

6291
   "name": "CP_VGT_CSINVOC_COUNT_HI"

6292
  },

6293
  {

6294
   "chips": ["gfx81"],

6295
   "map": {"at": 196852, "to": "mm"},

6296
   "name": "CP_PIPE_STATS_CONTROL",

6297
   "type_ref": "CP_PIPE_STATS_CONTROL"

6298
  },

6299
  {

6300
   "chips": ["gfx81"],

6301
   "map": {"at": 196856, "to": "mm"},

6302
   "name": "CP_STREAM_OUT_CONTROL",

6303
   "type_ref": "CP_PIPE_STATS_CONTROL"

6304
  },

6305
  {

6306
   "chips": ["gfx81"],

6307
   "map": {"at": 196860, "to": "mm"},

6308
   "name": "CP_STRMOUT_CNTL",

6309
   "type_ref": "CP_STRMOUT_CNTL"

6310
  },

6311
  {

6312
   "chips": ["gfx81"],

6313
   "map": {"at": 196864, "to": "mm"},

6314
   "name": "SCRATCH_REG0"

6315
  },

6316
  {

6317
   "chips": ["gfx81"],

6318
   "map": {"at": 196868, "to": "mm"},

6319
   "name": "SCRATCH_REG1"

6320
  },

6321
  {

6322
   "chips": ["gfx81"],

6323
   "map": {"at": 196872, "to": "mm"},

6324
   "name": "SCRATCH_REG2"

6325
  },

6326
  {

6327
   "chips": ["gfx81"],

6328
   "map": {"at": 196876, "to": "mm"},

6329
   "name": "SCRATCH_REG3"

6330
  },

6331
  {

6332
   "chips": ["gfx81"],

6333
   "map": {"at": 196880, "to": "mm"},

6334
   "name": "SCRATCH_REG4"

6335
  },

6336
  {

6337
   "chips": ["gfx81"],

6338
   "map": {"at": 196884, "to": "mm"},

6339
   "name": "SCRATCH_REG5"

6340
  },

6341
  {

6342
   "chips": ["gfx81"],

6343
   "map": {"at": 196888, "to": "mm"},

6344
   "name": "SCRATCH_REG6"

6345
  },

6346
  {

6347
   "chips": ["gfx81"],

6348
   "map": {"at": 196892, "to": "mm"},

6349
   "name": "SCRATCH_REG7"

6350
  },

6351
  {

6352
   "chips": ["gfx81"],

6353
   "map": {"at": 196928, "to": "mm"},

6354
   "name": "SCRATCH_UMSK",

6355
   "type_ref": "SCRATCH_UMSK"

6356
  },

6357
  {

6358
   "chips": ["gfx81"],

6359
   "map": {"at": 196932, "to": "mm"},

6360
   "name": "SCRATCH_ADDR"

6361
  },

6362
  {

6363
   "chips": ["gfx81"],

6364
   "map": {"at": 196936, "to": "mm"},

6365
   "name": "CP_PFP_ATOMIC_PREOP_LO"

6366
  },

6367
  {

6368
   "chips": ["gfx81"],

6369
   "map": {"at": 196940, "to": "mm"},

6370
   "name": "CP_PFP_ATOMIC_PREOP_HI"

6371
  },

6372
  {

6373
   "chips": ["gfx81"],

6374
   "map": {"at": 196944, "to": "mm"},

6375
   "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO"

6376
  },

6377
  {

6378
   "chips": ["gfx81"],

6379
   "map": {"at": 196948, "to": "mm"},

6380
   "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI"

6381
  },

6382
  {

6383
   "chips": ["gfx81"],

6384
   "map": {"at": 196952, "to": "mm"},

6385
   "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO"

6386
  },

6387
  {

6388
   "chips": ["gfx81"],

6389
   "map": {"at": 196956, "to": "mm"},

6390
   "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI"

6391
  },

6392
  {

6393
   "chips": ["gfx81"],

6394
   "map": {"at": 196960, "to": "mm"},

6395
   "name": "CP_APPEND_ADDR_LO",

6396
   "type_ref": "CP_APPEND_ADDR_LO"

6397
  },

6398
  {

6399
   "chips": ["gfx81"],

6400
   "map": {"at": 196964, "to": "mm"},

6401
   "name": "CP_APPEND_ADDR_HI",

6402
   "type_ref": "CP_APPEND_ADDR_HI"

6403
  },

6404
  {

6405
   "chips": ["gfx81"],

6406
   "map": {"at": 196968, "to": "mm"},

6407
   "name": "CP_APPEND_DATA"

6408
  },

6409
  {

6410
   "chips": ["gfx81"],

6411
   "map": {"at": 196972, "to": "mm"},

6412
   "name": "CP_APPEND_LAST_CS_FENCE"

6413
  },

6414
  {

6415
   "chips": ["gfx81"],

6416
   "map": {"at": 196976, "to": "mm"},

6417
   "name": "CP_APPEND_LAST_PS_FENCE"

6418
  },

6419
  {

6420
   "chips": ["gfx81"],

6421
   "map": {"at": 196980, "to": "mm"},

6422
   "name": "CP_ATOMIC_PREOP_LO"

6423
  },

6424
  {

6425
   "chips": ["gfx81"],

6426
   "map": {"at": 196984, "to": "mm"},

6427
   "name": "CP_ATOMIC_PREOP_HI"

6428
  },

6429
  {

6430
   "chips": ["gfx81"],

6431
   "map": {"at": 196988, "to": "mm"},

6432
   "name": "CP_GDS_ATOMIC0_PREOP_LO"

6433
  },

6434
  {

6435
   "chips": ["gfx81"],

6436
   "map": {"at": 196992, "to": "mm"},

6437
   "name": "CP_GDS_ATOMIC0_PREOP_HI"

6438
  },

6439
  {

6440
   "chips": ["gfx81"],

6441
   "map": {"at": 196996, "to": "mm"},

6442
   "name": "CP_GDS_ATOMIC1_PREOP_LO"

6443
  },

6444
  {

6445
   "chips": ["gfx81"],

6446
   "map": {"at": 197000, "to": "mm"},

6447
   "name": "CP_GDS_ATOMIC1_PREOP_HI"

6448
  },

6449
  {

6450
   "chips": ["gfx81"],

6451
   "map": {"at": 197028, "to": "mm"},

6452
   "name": "CP_ME_MC_WADDR_LO",

6453
   "type_ref": "CP_ME_MC_WADDR_LO"

6454
  },

6455
  {

6456
   "chips": ["gfx81"],

6457
   "map": {"at": 197032, "to": "mm"},

6458
   "name": "CP_ME_MC_WADDR_HI",

6459
   "type_ref": "CP_ME_MC_WADDR_HI"

6460
  },

6461
  {

6462
   "chips": ["gfx81"],

6463
   "map": {"at": 197036, "to": "mm"},

6464
   "name": "CP_ME_MC_WDATA_LO"

6465
  },

6466
  {

6467
   "chips": ["gfx81"],

6468
   "map": {"at": 197040, "to": "mm"},

6469
   "name": "CP_ME_MC_WDATA_HI"

6470
  },

6471
  {

6472
   "chips": ["gfx81"],

6473
   "map": {"at": 197044, "to": "mm"},

6474
   "name": "CP_ME_MC_RADDR_LO",

6475
   "type_ref": "CP_ME_MC_RADDR_LO"

6476
  },

6477
  {

6478
   "chips": ["gfx81"],

6479
   "map": {"at": 197048, "to": "mm"},

6480
   "name": "CP_ME_MC_RADDR_HI",

6481
   "type_ref": "CP_ME_MC_RADDR_HI"

6482
  },

6483
  {

6484
   "chips": ["gfx81"],

6485
   "map": {"at": 197052, "to": "mm"},

6486
   "name": "CP_SEM_WAIT_TIMER"

6487
  },

6488
  {

6489
   "chips": ["gfx81"],

6490
   "map": {"at": 197056, "to": "mm"},

6491
   "name": "CP_SIG_SEM_ADDR_LO",

6492
   "type_ref": "CP_SIG_SEM_ADDR_LO"

6493
  },

6494
  {

6495
   "chips": ["gfx81"],

6496
   "map": {"at": 197060, "to": "mm"},

6497
   "name": "CP_SIG_SEM_ADDR_HI",

6498
   "type_ref": "CP_SIG_SEM_ADDR_HI"

6499
  },

6500
  {

6501
   "chips": ["gfx81"],

6502
   "map": {"at": 197072, "to": "mm"},

6503
   "name": "CP_WAIT_REG_MEM_TIMEOUT"

6504
  },

6505
  {

6506
   "chips": ["gfx81"],

6507
   "map": {"at": 197076, "to": "mm"},

6508
   "name": "CP_WAIT_SEM_ADDR_LO",

6509
   "type_ref": "CP_SIG_SEM_ADDR_LO"

6510
  },

6511
  {

6512
   "chips": ["gfx81"],

6513
   "map": {"at": 197080, "to": "mm"},

6514
   "name": "CP_WAIT_SEM_ADDR_HI",

6515
   "type_ref": "CP_SIG_SEM_ADDR_HI"

6516
  },

6517
  {

6518
   "chips": ["gfx81"],

6519
   "map": {"at": 197084, "to": "mm"},

6520
   "name": "CP_DMA_PFP_CONTROL",

6521
   "type_ref": "CP_DMA_ME_CONTROL"

6522
  },

6523
  {

6524
   "chips": ["gfx81"],

6525
   "map": {"at": 197088, "to": "mm"},

6526
   "name": "CP_DMA_ME_CONTROL",

6527
   "type_ref": "CP_DMA_ME_CONTROL"

6528
  },

6529
  {

6530
   "chips": ["gfx81"],

6531
   "map": {"at": 197092, "to": "mm"},

6532
   "name": "CP_COHER_BASE_HI",

6533
   "type_ref": "CP_COHER_BASE_HI"

6534
  },

6535
  {

6536
   "chips": ["gfx81"],

6537
   "map": {"at": 197100, "to": "mm"},

6538
   "name": "CP_COHER_START_DELAY",

6539
   "type_ref": "CP_COHER_START_DELAY"

6540
  },

6541
  {

6542
   "chips": ["gfx81"],

6543
   "map": {"at": 197104, "to": "mm"},

6544
   "name": "CP_COHER_CNTL",

6545
   "type_ref": "CP_COHER_CNTL"

6546
  },

6547
  {

6548
   "chips": ["gfx81"],

6549
   "map": {"at": 197108, "to": "mm"},

6550
   "name": "CP_COHER_SIZE"

6551
  },

6552
  {

6553
   "chips": ["gfx81"],

6554
   "map": {"at": 197112, "to": "mm"},

6555
   "name": "CP_COHER_BASE"

6556
  },

6557
  {

6558
   "chips": ["gfx81"],

6559
   "map": {"at": 197116, "to": "mm"},

6560
   "name": "CP_COHER_STATUS",

6561
   "type_ref": "CP_COHER_STATUS"

6562
  },

6563
  {

6564
   "chips": ["gfx81"],

6565
   "map": {"at": 197120, "to": "mm"},

6566
   "name": "CP_DMA_ME_SRC_ADDR"

6567
  },

6568
  {

6569
   "chips": ["gfx81"],

6570
   "map": {"at": 197124, "to": "mm"},

6571
   "name": "CP_DMA_ME_SRC_ADDR_HI",

6572
   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"

6573
  },

6574
  {

6575
   "chips": ["gfx81"],

6576
   "map": {"at": 197128, "to": "mm"},

6577
   "name": "CP_DMA_ME_DST_ADDR"

6578
  },

6579
  {

6580
   "chips": ["gfx81"],

6581
   "map": {"at": 197132, "to": "mm"},

6582
   "name": "CP_DMA_ME_DST_ADDR_HI",

6583
   "type_ref": "CP_DMA_ME_DST_ADDR_HI"

6584
  },

6585
  {

6586
   "chips": ["gfx81"],

6587
   "map": {"at": 197136, "to": "mm"},

6588
   "name": "CP_DMA_ME_COMMAND",

6589
   "type_ref": "CP_DMA_ME_COMMAND"

6590
  },

6591
  {

6592
   "chips": ["gfx81"],

6593
   "map": {"at": 197140, "to": "mm"},

6594
   "name": "CP_DMA_PFP_SRC_ADDR"

6595
  },

6596
  {

6597
   "chips": ["gfx81"],

6598
   "map": {"at": 197144, "to": "mm"},

6599
   "name": "CP_DMA_PFP_SRC_ADDR_HI",

6600
   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"

6601
  },

6602
  {

6603
   "chips": ["gfx81"],

6604
   "map": {"at": 197148, "to": "mm"},

6605
   "name": "CP_DMA_PFP_DST_ADDR"

6606
  },

6607
  {

6608
   "chips": ["gfx81"],

6609
   "map": {"at": 197152, "to": "mm"},

6610
   "name": "CP_DMA_PFP_DST_ADDR_HI",

6611
   "type_ref": "CP_DMA_ME_DST_ADDR_HI"

6612
  },

6613
  {

6614
   "chips": ["gfx81"],

6615
   "map": {"at": 197156, "to": "mm"},

6616
   "name": "CP_DMA_PFP_COMMAND",

6617
   "type_ref": "CP_DMA_ME_COMMAND"

6618
  },

6619
  {

6620
   "chips": ["gfx81"],

6621
   "map": {"at": 197160, "to": "mm"},

6622
   "name": "CP_DMA_CNTL",

6623
   "type_ref": "CP_DMA_CNTL"

6624
  },

6625
  {

6626
   "chips": ["gfx81"],

6627
   "map": {"at": 197164, "to": "mm"},

6628
   "name": "CP_DMA_READ_TAGS",

6629
   "type_ref": "CP_DMA_READ_TAGS"

6630
  },

6631
  {

6632
   "chips": ["gfx81"],

6633
   "map": {"at": 197168, "to": "mm"},

6634
   "name": "CP_COHER_SIZE_HI",

6635
   "type_ref": "CP_COHER_SIZE_HI"

6636
  },

6637
  {

6638
   "chips": ["gfx81"],

6639
   "map": {"at": 197172, "to": "mm"},

6640
   "name": "CP_PFP_IB_CONTROL",

6641
   "type_ref": "CP_PFP_IB_CONTROL"

6642
  },

6643
  {

6644
   "chips": ["gfx81"],

6645
   "map": {"at": 197176, "to": "mm"},

6646
   "name": "CP_PFP_LOAD_CONTROL",

6647
   "type_ref": "CP_PFP_LOAD_CONTROL"

6648
  },

6649
  {

6650
   "chips": ["gfx81"],

6651
   "map": {"at": 197180, "to": "mm"},

6652
   "name": "CP_SCRATCH_INDEX",

6653
   "type_ref": "CP_SCRATCH_INDEX"

6654
  },

6655
  {

6656
   "chips": ["gfx81"],

6657
   "map": {"at": 197184, "to": "mm"},

6658
   "name": "CP_SCRATCH_DATA"

6659
  },

6660
  {

6661
   "chips": ["gfx81"],

6662
   "map": {"at": 197188, "to": "mm"},

6663
   "name": "CP_RB_OFFSET",

6664
   "type_ref": "CP_RB_OFFSET"

6665
  },

6666
  {

6667
   "chips": ["gfx81"],

6668
   "map": {"at": 197192, "to": "mm"},

6669
   "name": "CP_IB1_OFFSET",

6670
   "type_ref": "CP_IB1_OFFSET"

6671
  },

6672
  {

6673
   "chips": ["gfx81"],

6674
   "map": {"at": 197196, "to": "mm"},

6675
   "name": "CP_IB2_OFFSET",

6676
   "type_ref": "CP_IB2_OFFSET"

6677
  },

6678
  {

6679
   "chips": ["gfx81"],

6680
   "map": {"at": 197200, "to": "mm"},

6681
   "name": "CP_IB1_PREAMBLE_BEGIN",

6682
   "type_ref": "CP_IB1_PREAMBLE_BEGIN"

6683
  },

6684
  {

6685
   "chips": ["gfx81"],

6686
   "map": {"at": 197204, "to": "mm"},

6687
   "name": "CP_IB1_PREAMBLE_END",

6688
   "type_ref": "CP_IB1_PREAMBLE_END"

6689
  },

6690
  {

6691
   "chips": ["gfx81"],

6692
   "map": {"at": 197208, "to": "mm"},

6693
   "name": "CP_IB2_PREAMBLE_BEGIN",

6694
   "type_ref": "CP_IB2_PREAMBLE_BEGIN"

6695
  },

6696
  {

6697
   "chips": ["gfx81"],

6698
   "map": {"at": 197212, "to": "mm"},

6699
   "name": "CP_IB2_PREAMBLE_END",

6700
   "type_ref": "CP_IB2_PREAMBLE_END"

6701
  },

6702
  {

6703
   "chips": ["gfx81"],

6704
   "map": {"at": 197216, "to": "mm"},

6705
   "name": "CP_CE_IB1_OFFSET",

6706
   "type_ref": "CP_IB1_OFFSET"

6707
  },

6708
  {

6709
   "chips": ["gfx81"],

6710
   "map": {"at": 197220, "to": "mm"},

6711
   "name": "CP_CE_IB2_OFFSET",

6712
   "type_ref": "CP_IB2_OFFSET"

6713
  },

6714
  {

6715
   "chips": ["gfx81"],

6716
   "map": {"at": 197224, "to": "mm"},

6717
   "name": "CP_CE_COUNTER"

6718
  },

6719
  {

6720
   "chips": ["gfx81"],

6721
   "map": {"at": 197228, "to": "mm"},

6722
   "name": "CP_CE_RB_OFFSET",

6723
   "type_ref": "CP_RB_OFFSET"

6724
  },

6725
  {

6726
   "chips": ["gfx81"],

6727
   "map": {"at": 197388, "to": "mm"},

6728
   "name": "CP_CE_INIT_BASE_LO",

6729
   "type_ref": "CP_CE_INIT_BASE_LO"

6730
  },

6731
  {

6732
   "chips": ["gfx81"],

6733
   "map": {"at": 197392, "to": "mm"},

6734
   "name": "CP_CE_INIT_BASE_HI",

6735
   "type_ref": "CP_CE_INIT_BASE_HI"

6736
  },

6737
  {

6738
   "chips": ["gfx81"],

6739
   "map": {"at": 197396, "to": "mm"},

6740
   "name": "CP_CE_INIT_BUFSZ",

6741
   "type_ref": "CP_CE_INIT_BUFSZ"

6742
  },

6743
  {

6744
   "chips": ["gfx81"],

6745
   "map": {"at": 197400, "to": "mm"},

6746
   "name": "CP_CE_IB1_BASE_LO",

6747
   "type_ref": "CP_CE_IB1_BASE_LO"

6748
  },

6749
  {

6750
   "chips": ["gfx81"],

6751
   "map": {"at": 197404, "to": "mm"},

6752
   "name": "CP_CE_IB1_BASE_HI",

6753
   "type_ref": "CP_CE_IB1_BASE_HI"

6754
  },

6755
  {

6756
   "chips": ["gfx81"],

6757
   "map": {"at": 197408, "to": "mm"},

6758
   "name": "CP_CE_IB1_BUFSZ",

6759
   "type_ref": "CP_CE_IB1_BUFSZ"

6760
  },

6761
  {

6762
   "chips": ["gfx81"],

6763
   "map": {"at": 197412, "to": "mm"},

6764
   "name": "CP_CE_IB2_BASE_LO",

6765
   "type_ref": "CP_CE_IB2_BASE_LO"

6766
  },

6767
  {

6768
   "chips": ["gfx81"],

6769
   "map": {"at": 197416, "to": "mm"},

6770
   "name": "CP_CE_IB2_BASE_HI",

6771
   "type_ref": "CP_CE_IB2_BASE_HI"

6772
  },

6773
  {

6774
   "chips": ["gfx81"],

6775
   "map": {"at": 197420, "to": "mm"},

6776
   "name": "CP_CE_IB2_BUFSZ",

6777
   "type_ref": "CP_CE_IB2_BUFSZ"

6778
  },

6779
  {

6780
   "chips": ["gfx81"],

6781
   "map": {"at": 197424, "to": "mm"},

6782
   "name": "CP_IB1_BASE_LO",

6783
   "type_ref": "CP_CE_IB1_BASE_LO"

6784
  },

6785
  {

6786
   "chips": ["gfx81"],

6787
   "map": {"at": 197428, "to": "mm"},

6788
   "name": "CP_IB1_BASE_HI",

6789
   "type_ref": "CP_CE_IB1_BASE_HI"

6790
  },

6791
  {

6792
   "chips": ["gfx81"],

6793
   "map": {"at": 197432, "to": "mm"},

6794
   "name": "CP_IB1_BUFSZ",

6795
   "type_ref": "CP_CE_IB1_BUFSZ"

6796
  },

6797
  {

6798
   "chips": ["gfx81"],

6799
   "map": {"at": 197436, "to": "mm"},

6800
   "name": "CP_IB2_BASE_LO",

6801
   "type_ref": "CP_CE_IB2_BASE_LO"

6802
  },

6803
  {

6804
   "chips": ["gfx81"],

6805
   "map": {"at": 197440, "to": "mm"},

6806
   "name": "CP_IB2_BASE_HI",

6807
   "type_ref": "CP_CE_IB2_BASE_HI"

6808
  },

6809
  {

6810
   "chips": ["gfx81"],

6811
   "map": {"at": 197444, "to": "mm"},

6812
   "name": "CP_IB2_BUFSZ",

6813
   "type_ref": "CP_CE_IB2_BUFSZ"

6814
  },

6815
  {

6816
   "chips": ["gfx81"],

6817
   "map": {"at": 197448, "to": "mm"},

6818
   "name": "CP_ST_BASE_LO",

6819
   "type_ref": "CP_ST_BASE_LO"

6820
  },

6821
  {

6822
   "chips": ["gfx81"],

6823
   "map": {"at": 197452, "to": "mm"},

6824
   "name": "CP_ST_BASE_HI",

6825
   "type_ref": "CP_ST_BASE_HI"

6826
  },

6827
  {

6828
   "chips": ["gfx81"],

6829
   "map": {"at": 197456, "to": "mm"},

6830
   "name": "CP_ST_BUFSZ",

6831
   "type_ref": "CP_ST_BUFSZ"

6832
  },

6833
  {

6834
   "chips": ["gfx81"],

6835
   "map": {"at": 197460, "to": "mm"},

6836
   "name": "CP_EOP_DONE_EVENT_CNTL",

6837
   "type_ref": "CP_EOP_DONE_EVENT_CNTL"

6838
  },

6839
  {

6840
   "chips": ["gfx81"],

6841
   "map": {"at": 197464, "to": "mm"},

6842
   "name": "CP_EOP_DONE_DATA_CNTL",

6843
   "type_ref": "CP_EOP_DONE_DATA_CNTL"

6844
  },

6845
  {

6846
   "chips": ["gfx81"],

6847
   "map": {"at": 197468, "to": "mm"},

6848
   "name": "CP_EOP_DONE_CNTX_ID",

6849
   "type_ref": "CP_EOP_DONE_CNTX_ID"

6850
  },

6851
  {

6852
   "chips": ["gfx81"],

6853
   "map": {"at": 197552, "to": "mm"},

6854
   "name": "CP_PFP_COMPLETION_STATUS",

6855
   "type_ref": "CP_PFP_COMPLETION_STATUS"

6856
  },

6857
  {

6858
   "chips": ["gfx81"],

6859
   "map": {"at": 197556, "to": "mm"},

6860
   "name": "CP_CE_COMPLETION_STATUS",

6861
   "type_ref": "CP_PFP_COMPLETION_STATUS"

6862
  },

6863
  {

6864
   "chips": ["gfx81"],

6865
   "map": {"at": 197560, "to": "mm"},

6866
   "name": "CP_PRED_NOT_VISIBLE",

6867
   "type_ref": "CP_PRED_NOT_VISIBLE"

6868
  },

6869
  {

6870
   "chips": ["gfx81"],

6871
   "map": {"at": 197568, "to": "mm"},

6872
   "name": "CP_PFP_METADATA_BASE_ADDR"

6873
  },

6874
  {

6875
   "chips": ["gfx81"],

6876
   "map": {"at": 197572, "to": "mm"},

6877
   "name": "CP_PFP_METADATA_BASE_ADDR_HI",

6878
   "type_ref": "CP_EOP_DONE_ADDR_HI"

6879
  },

6880
  {

6881
   "chips": ["gfx81"],

6882
   "map": {"at": 197576, "to": "mm"},

6883
   "name": "CP_CE_METADATA_BASE_ADDR"

6884
  },

6885
  {

6886
   "chips": ["gfx81"],

6887
   "map": {"at": 197580, "to": "mm"},

6888
   "name": "CP_CE_METADATA_BASE_ADDR_HI",

6889
   "type_ref": "CP_EOP_DONE_ADDR_HI"

6890
  },

6891
  {

6892
   "chips": ["gfx81"],

6893
   "map": {"at": 197584, "to": "mm"},

6894
   "name": "CP_DRAW_INDX_INDR_ADDR"

6895
  },

6896
  {

6897
   "chips": ["gfx81"],

6898
   "map": {"at": 197588, "to": "mm"},

6899
   "name": "CP_DRAW_INDX_INDR_ADDR_HI",

6900
   "type_ref": "CP_EOP_DONE_ADDR_HI"

6901
  },

6902
  {

6903
   "chips": ["gfx81"],

6904
   "map": {"at": 197592, "to": "mm"},

6905
   "name": "CP_DISPATCH_INDR_ADDR"

6906
  },

6907
  {

6908
   "chips": ["gfx81"],

6909
   "map": {"at": 197596, "to": "mm"},

6910
   "name": "CP_DISPATCH_INDR_ADDR_HI",

6911
   "type_ref": "CP_EOP_DONE_ADDR_HI"

6912
  },

6913
  {

6914
   "chips": ["gfx81"],

6915
   "map": {"at": 197600, "to": "mm"},

6916
   "name": "CP_INDEX_BASE_ADDR"

6917
  },

6918
  {

6919
   "chips": ["gfx81"],

6920
   "map": {"at": 197604, "to": "mm"},

6921
   "name": "CP_INDEX_BASE_ADDR_HI",

6922
   "type_ref": "CP_EOP_DONE_ADDR_HI"

6923
  },

6924
  {

6925
   "chips": ["gfx81"],

6926
   "map": {"at": 197608, "to": "mm"},

6927
   "name": "CP_INDEX_TYPE",

6928
   "type_ref": "CP_INDEX_TYPE"

6929
  },

6930
  {

6931
   "chips": ["gfx81"],

6932
   "map": {"at": 197612, "to": "mm"},

6933
   "name": "CP_GDS_BKUP_ADDR"

6934
  },

6935
  {

6936
   "chips": ["gfx81"],

6937
   "map": {"at": 197616, "to": "mm"},

6938
   "name": "CP_GDS_BKUP_ADDR_HI",

6939
   "type_ref": "CP_EOP_DONE_ADDR_HI"

6940
  },

6941
  {

6942
   "chips": ["gfx81"],

6943
   "map": {"at": 197620, "to": "mm"},

6944
   "name": "CP_SAMPLE_STATUS",

6945
   "type_ref": "CP_SAMPLE_STATUS"

6946
  },

6947
  {

6948
   "chips": ["gfx81"],

6949
   "map": {"at": 198656, "to": "mm"},

6950
   "name": "GRBM_GFX_INDEX",

6951
   "type_ref": "GRBM_GFX_INDEX"

6952
  },

6953
  {

6954
   "chips": ["gfx81"],

6955
   "map": {"at": 198912, "to": "mm"},

6956
   "name": "VGT_ESGS_RING_SIZE"

6957
  },

6958
  {

6959
   "chips": ["gfx81"],

6960
   "map": {"at": 198916, "to": "mm"},

6961
   "name": "VGT_GSVS_RING_SIZE"

6962
  },

6963
  {

6964
   "chips": ["gfx81"],

6965
   "map": {"at": 198920, "to": "mm"},

6966
   "name": "VGT_PRIMITIVE_TYPE",

6967
   "type_ref": "VGT_PRIMITIVE_TYPE"

6968
  },

6969
  {

6970
   "chips": ["gfx81"],

6971
   "map": {"at": 198924, "to": "mm"},

6972
   "name": "VGT_INDEX_TYPE",

6973
   "type_ref": "CP_INDEX_TYPE"

6974
  },

6975
  {

6976
   "chips": ["gfx81"],

6977
   "map": {"at": 198928, "to": "mm"},

6978
   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0"

6979
  },

6980
  {

6981
   "chips": ["gfx81"],

6982
   "map": {"at": 198932, "to": "mm"},

6983
   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1"

6984
  },

6985
  {

6986
   "chips": ["gfx81"],

6987
   "map": {"at": 198936, "to": "mm"},

6988
   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2"

6989
  },

6990
  {

6991
   "chips": ["gfx81"],

6992
   "map": {"at": 198940, "to": "mm"},

6993
   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3"

6994
  },

6995
  {

6996
   "chips": ["gfx81"],

6997
   "map": {"at": 198960, "to": "mm"},

6998
   "name": "VGT_NUM_INDICES"

6999
  },

7000
  {

7001
   "chips": ["gfx81"],

7002
   "map": {"at": 198964, "to": "mm"},

7003
   "name": "VGT_NUM_INSTANCES"

7004
  },

7005
  {

7006
   "chips": ["gfx81"],

7007
   "map": {"at": 198968, "to": "mm"},

7008
   "name": "VGT_TF_RING_SIZE",

7009
   "type_ref": "VGT_TF_RING_SIZE"

7010
  },

7011
  {

7012
   "chips": ["gfx81"],

7013
   "map": {"at": 198972, "to": "mm"},

7014
   "name": "VGT_HS_OFFCHIP_PARAM",

7015
   "type_ref": "VGT_HS_OFFCHIP_PARAM"

7016
  },

7017
  {

7018
   "chips": ["gfx81"],

7019
   "map": {"at": 198976, "to": "mm"},

7020
   "name": "VGT_TF_MEMORY_BASE"

7021
  },

7022
  {

7023
   "chips": ["gfx81"],

7024
   "map": {"at": 199168, "to": "mm"},

7025
   "name": "PA_SU_LINE_STIPPLE_VALUE",

7026
   "type_ref": "PA_SU_LINE_STIPPLE_VALUE"

7027
  },

7028
  {

7029
   "chips": ["gfx81"],

7030
   "map": {"at": 199172, "to": "mm"},

7031
   "name": "PA_SC_LINE_STIPPLE_STATE",

7032
   "type_ref": "PA_SC_LINE_STIPPLE_STATE"

7033
  },

7034
  {

7035
   "chips": ["gfx81"],

7036
   "map": {"at": 199184, "to": "mm"},

7037
   "name": "PA_SC_SCREEN_EXTENT_MIN_0",

7038
   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"

7039
  },

7040
  {

7041
   "chips": ["gfx81"],

7042
   "map": {"at": 199188, "to": "mm"},

7043
   "name": "PA_SC_SCREEN_EXTENT_MAX_0",

7044
   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"

7045
  },

7046
  {

7047
   "chips": ["gfx81"],

7048
   "map": {"at": 199192, "to": "mm"},

7049
   "name": "PA_SC_SCREEN_EXTENT_MIN_1",

7050
   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"

7051
  },

7052
  {

7053
   "chips": ["gfx81"],

7054
   "map": {"at": 199212, "to": "mm"},

7055
   "name": "PA_SC_SCREEN_EXTENT_MAX_1",

7056
   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"

7057
  },

7058
  {

7059
   "chips": ["gfx81"],

7060
   "map": {"at": 199296, "to": "mm"},

7061
   "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN",

7062
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"

7063
  },

7064
  {

7065
   "chips": ["gfx81"],

7066
   "map": {"at": 199300, "to": "mm"},

7067
   "name": "PA_SC_P3D_TRAP_SCREEN_H",

7068
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"

7069
  },

7070
  {

7071
   "chips": ["gfx81"],

7072
   "map": {"at": 199304, "to": "mm"},

7073
   "name": "PA_SC_P3D_TRAP_SCREEN_V",

7074
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"

7075
  },

7076
  {

7077
   "chips": ["gfx81"],

7078
   "map": {"at": 199308, "to": "mm"},

7079
   "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE",

7080
   "type_ref": "CP_DRAW_OBJECT_COUNTER"

7081
  },

7082
  {

7083
   "chips": ["gfx81"],

7084
   "map": {"at": 199312, "to": "mm"},

7085
   "name": "PA_SC_P3D_TRAP_SCREEN_COUNT",

7086
   "type_ref": "CP_DRAW_OBJECT_COUNTER"

7087
  },

7088
  {

7089
   "chips": ["gfx81"],

7090
   "map": {"at": 199328, "to": "mm"},

7091
   "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN",

7092
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"

7093
  },

7094
  {

7095
   "chips": ["gfx81"],

7096
   "map": {"at": 199332, "to": "mm"},

7097
   "name": "PA_SC_HP3D_TRAP_SCREEN_H",

7098
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"

7099
  },

7100
  {

7101
   "chips": ["gfx81"],

7102
   "map": {"at": 199336, "to": "mm"},

7103
   "name": "PA_SC_HP3D_TRAP_SCREEN_V",

7104
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"

7105
  },

7106
  {

7107
   "chips": ["gfx81"],

7108
   "map": {"at": 199340, "to": "mm"},

7109
   "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE",

7110
   "type_ref": "CP_DRAW_OBJECT_COUNTER"

7111
  },

7112
  {

7113
   "chips": ["gfx81"],

7114
   "map": {"at": 199344, "to": "mm"},

7115
   "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT",

7116
   "type_ref": "CP_DRAW_OBJECT_COUNTER"

7117
  },

7118
  {

7119
   "chips": ["gfx81"],

7120
   "map": {"at": 199360, "to": "mm"},

7121
   "name": "PA_SC_TRAP_SCREEN_HV_EN",

7122
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"

7123
  },

7124
  {

7125
   "chips": ["gfx81"],

7126
   "map": {"at": 199364, "to": "mm"},

7127
   "name": "PA_SC_TRAP_SCREEN_H",

7128
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"

7129
  },

7130
  {

7131
   "chips": ["gfx81"],

7132
   "map": {"at": 199368, "to": "mm"},

7133
   "name": "PA_SC_TRAP_SCREEN_V",

7134
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"

7135
  },

7136
  {

7137
   "chips": ["gfx81"],

7138
   "map": {"at": 199372, "to": "mm"},

7139
   "name": "PA_SC_TRAP_SCREEN_OCCURRENCE",

7140
   "type_ref": "CP_DRAW_OBJECT_COUNTER"

7141
  },

7142
  {

7143
   "chips": ["gfx81"],

7144
   "map": {"at": 199376, "to": "mm"},

7145
   "name": "PA_SC_TRAP_SCREEN_COUNT",

7146
   "type_ref": "CP_DRAW_OBJECT_COUNTER"

7147
  },

7148
  {

7149
   "chips": ["gfx81"],

7150
   "map": {"at": 199872, "to": "mm"},

7151
   "name": "SQ_THREAD_TRACE_BASE"

7152
  },

7153
  {

7154
   "chips": ["gfx81"],

7155
   "map": {"at": 199876, "to": "mm"},

7156
   "name": "SQ_THREAD_TRACE_SIZE",

7157
   "type_ref": "SQ_THREAD_TRACE_SIZE"

7158
  },

7159
  {

7160
   "chips": ["gfx81"],

7161
   "map": {"at": 199880, "to": "mm"},

7162
   "name": "SQ_THREAD_TRACE_MASK",

7163
   "type_ref": "SQ_THREAD_TRACE_MASK"

7164
  },

7165
  {

7166
   "chips": ["gfx81"],

7167
   "map": {"at": 199884, "to": "mm"},

7168
   "name": "SQ_THREAD_TRACE_TOKEN_MASK",

7169
   "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK"

7170
  },

7171
  {

7172
   "chips": ["gfx81"],

7173
   "map": {"at": 199888, "to": "mm"},

7174
   "name": "SQ_THREAD_TRACE_PERF_MASK",

7175
   "type_ref": "SQ_PERFCOUNTER_MASK"

7176
  },

7177
  {

7178
   "chips": ["gfx81"],

7179
   "map": {"at": 199892, "to": "mm"},

7180
   "name": "SQ_THREAD_TRACE_CTRL",

7181
   "type_ref": "SQ_THREAD_TRACE_CTRL"

7182
  },

7183
  {

7184
   "chips": ["gfx81"],

7185
   "map": {"at": 199896, "to": "mm"},

7186
   "name": "SQ_THREAD_TRACE_MODE",

7187
   "type_ref": "SQ_THREAD_TRACE_MODE"

7188
  },

7189
  {

7190
   "chips": ["gfx81"],

7191
   "map": {"at": 199900, "to": "mm"},

7192
   "name": "SQ_THREAD_TRACE_BASE2",

7193
   "type_ref": "SQ_THREAD_TRACE_BASE2"

7194
  },

7195
  {

7196
   "chips": ["gfx81"],

7197
   "map": {"at": 199904, "to": "mm"},

7198
   "name": "SQ_THREAD_TRACE_TOKEN_MASK2"

7199
  },

7200
  {

7201
   "chips": ["gfx81"],

7202
   "map": {"at": 199908, "to": "mm"},

7203
   "name": "SQ_THREAD_TRACE_WPTR",

7204
   "type_ref": "SQ_THREAD_TRACE_WPTR"

7205
  },

7206
  {

7207
   "chips": ["gfx81"],

7208
   "map": {"at": 199912, "to": "mm"},

7209
   "name": "SQ_THREAD_TRACE_STATUS",

7210
   "type_ref": "SQ_THREAD_TRACE_STATUS"

7211
  },

7212
  {

7213
   "chips": ["gfx81"],

7214
   "map": {"at": 199916, "to": "mm"},

7215
   "name": "SQ_THREAD_TRACE_HIWATER",

7216
   "type_ref": "SQ_THREAD_TRACE_HIWATER"

7217
  },

7218
  {

7219
   "chips": ["gfx81"],

7220
   "map": {"at": 199936, "to": "mm"},

7221
   "name": "SQ_THREAD_TRACE_USERDATA_0"

7222
  },

7223
  {

7224
   "chips": ["gfx81"],

7225
   "map": {"at": 199940, "to": "mm"},

7226
   "name": "SQ_THREAD_TRACE_USERDATA_1"

7227
  },

7228
  {

7229
   "chips": ["gfx81"],

7230
   "map": {"at": 199944, "to": "mm"},

7231
   "name": "SQ_THREAD_TRACE_USERDATA_2"

7232
  },

7233
  {

7234
   "chips": ["gfx81"],

7235
   "map": {"at": 199948, "to": "mm"},

7236
   "name": "SQ_THREAD_TRACE_USERDATA_3"

7237
  },

7238
  {

7239
   "chips": ["gfx81"],

7240
   "map": {"at": 199968, "to": "mm"},

7241
   "name": "SQC_CACHES",

7242
   "type_ref": "SQC_CACHES"

7243
  },

7244
  {

7245
   "chips": ["gfx81"],

7246
   "map": {"at": 199972, "to": "mm"},

7247
   "name": "SQC_WRITEBACK",

7248
   "type_ref": "SQC_WRITEBACK"

7249
  },

7250
  {

7251
   "chips": ["gfx81"],

7252
   "map": {"at": 200192, "to": "mm"},

7253
   "name": "TA_CS_BC_BASE_ADDR"

7254
  },

7255
  {

7256
   "chips": ["gfx81"],

7257
   "map": {"at": 200196, "to": "mm"},

7258
   "name": "TA_CS_BC_BASE_ADDR_HI",

7259
   "type_ref": "TA_BC_BASE_ADDR_HI"

7260
  },

7261
  {

7262
   "chips": ["gfx81"],

7263
   "map": {"at": 200448, "to": "mm"},

7264
   "name": "DB_OCCLUSION_COUNT0_LOW"

7265
  },

7266
  {

7267
   "chips": ["gfx81"],

7268
   "map": {"at": 200452, "to": "mm"},

7269
   "name": "DB_OCCLUSION_COUNT0_HI",

7270
   "type_ref": "DB_ZPASS_COUNT_HI"

7271
  },

7272
  {

7273
   "chips": ["gfx81"],

7274
   "map": {"at": 200456, "to": "mm"},

7275
   "name": "DB_OCCLUSION_COUNT1_LOW"

7276
  },

7277
  {

7278
   "chips": ["gfx81"],

7279
   "map": {"at": 200460, "to": "mm"},

7280
   "name": "DB_OCCLUSION_COUNT1_HI",

7281
   "type_ref": "DB_ZPASS_COUNT_HI"

7282
  },

7283
  {

7284
   "chips": ["gfx81"],

7285
   "map": {"at": 200464, "to": "mm"},

7286
   "name": "DB_OCCLUSION_COUNT2_LOW"

7287
  },

7288
  {

7289
   "chips": ["gfx81"],

7290
   "map": {"at": 200468, "to": "mm"},

7291
   "name": "DB_OCCLUSION_COUNT2_HI",

7292
   "type_ref": "DB_ZPASS_COUNT_HI"

7293
  },

7294
  {

7295
   "chips": ["gfx81"],

7296
   "map": {"at": 200472, "to": "mm"},

7297
   "name": "DB_OCCLUSION_COUNT3_LOW"

7298
  },

7299
  {

7300
   "chips": ["gfx81"],

7301
   "map": {"at": 200476, "to": "mm"},

7302
   "name": "DB_OCCLUSION_COUNT3_HI",

7303
   "type_ref": "DB_ZPASS_COUNT_HI"

7304
  },

7305
  {

7306
   "chips": ["gfx81"],

7307
   "map": {"at": 200696, "to": "mm"},

7308
   "name": "DB_ZPASS_COUNT_LOW"

7309
  },

7310
  {

7311
   "chips": ["gfx81"],

7312
   "map": {"at": 200700, "to": "mm"},

7313
   "name": "DB_ZPASS_COUNT_HI",

7314
   "type_ref": "DB_ZPASS_COUNT_HI"

7315
  },

7316
  {

7317
   "chips": ["gfx81"],

7318
   "map": {"at": 200704, "to": "mm"},

7319
   "name": "GDS_RD_ADDR"

7320
  },

7321
  {

7322
   "chips": ["gfx81"],

7323
   "map": {"at": 200708, "to": "mm"},

7324
   "name": "GDS_RD_DATA"

7325
  },

7326
  {

7327
   "chips": ["gfx81"],

7328
   "map": {"at": 200712, "to": "mm"},

7329
   "name": "GDS_RD_BURST_ADDR"

7330
  },

7331
  {

7332
   "chips": ["gfx81"],

7333
   "map": {"at": 200716, "to": "mm"},

7334
   "name": "GDS_RD_BURST_COUNT"

7335
  },

7336
  {

7337
   "chips": ["gfx81"],

7338
   "map": {"at": 200720, "to": "mm"},

7339
   "name": "GDS_RD_BURST_DATA"

7340
  },

7341
  {

7342
   "chips": ["gfx81"],

7343
   "map": {"at": 200724, "to": "mm"},

7344
   "name": "GDS_WR_ADDR"

7345
  },

7346
  {

7347
   "chips": ["gfx81"],

7348
   "map": {"at": 200728, "to": "mm"},

7349
   "name": "GDS_WR_DATA"

7350
  },

7351
  {

7352
   "chips": ["gfx81"],

7353
   "map": {"at": 200732, "to": "mm"},

7354
   "name": "GDS_WR_BURST_ADDR"

7355
  },

7356
  {

7357
   "chips": ["gfx81"],

7358
   "map": {"at": 200736, "to": "mm"},

7359
   "name": "GDS_WR_BURST_DATA"

7360
  },

7361
  {

7362
   "chips": ["gfx81"],

7363
   "map": {"at": 200740, "to": "mm"},

7364
   "name": "GDS_WRITE_COMPLETE"

7365
  },

7366
  {

7367
   "chips": ["gfx81"],

7368
   "map": {"at": 200744, "to": "mm"},

7369
   "name": "GDS_ATOM_CNTL",

7370
   "type_ref": "GDS_ATOM_CNTL"

7371
  },

7372
  {

7373
   "chips": ["gfx81"],

7374
   "map": {"at": 200748, "to": "mm"},

7375
   "name": "GDS_ATOM_COMPLETE",

7376
   "type_ref": "GDS_ATOM_COMPLETE"

7377
  },

7378
  {

7379
   "chips": ["gfx81"],

7380
   "map": {"at": 200752, "to": "mm"},

7381
   "name": "GDS_ATOM_BASE",

7382
   "type_ref": "GDS_ATOM_BASE"

7383
  },

7384
  {

7385
   "chips": ["gfx81"],

7386
   "map": {"at": 200756, "to": "mm"},

7387
   "name": "GDS_ATOM_SIZE",

7388
   "type_ref": "GDS_ATOM_SIZE"

7389
  },

7390
  {

7391
   "chips": ["gfx81"],

7392
   "map": {"at": 200760, "to": "mm"},

7393
   "name": "GDS_ATOM_OFFSET0",

7394
   "type_ref": "GDS_ATOM_OFFSET0"

7395
  },

7396
  {

7397
   "chips": ["gfx81"],

7398
   "map": {"at": 200764, "to": "mm"},

7399
   "name": "GDS_ATOM_OFFSET1",

7400
   "type_ref": "GDS_ATOM_OFFSET1"

7401
  },

7402
  {

7403
   "chips": ["gfx81"],

7404
   "map": {"at": 200768, "to": "mm"},

7405
   "name": "GDS_ATOM_DST"

7406
  },

7407
  {

7408
   "chips": ["gfx81"],

7409
   "map": {"at": 200772, "to": "mm"},

7410
   "name": "GDS_ATOM_OP",

7411
   "type_ref": "GDS_ATOM_OP"

7412
  },

7413
  {

7414
   "chips": ["gfx81"],

7415
   "map": {"at": 200776, "to": "mm"},

7416
   "name": "GDS_ATOM_SRC0"

7417
  },

7418
  {

7419
   "chips": ["gfx81"],

7420
   "map": {"at": 200780, "to": "mm"},

7421
   "name": "GDS_ATOM_SRC0_U"

7422
  },

7423
  {

7424
   "chips": ["gfx81"],

7425
   "map": {"at": 200784, "to": "mm"},

7426
   "name": "GDS_ATOM_SRC1"

7427
  },

7428
  {

7429
   "chips": ["gfx81"],

7430
   "map": {"at": 200788, "to": "mm"},

7431
   "name": "GDS_ATOM_SRC1_U"

7432
  },

7433
  {

7434
   "chips": ["gfx81"],

7435
   "map": {"at": 200792, "to": "mm"},

7436
   "name": "GDS_ATOM_READ0"

7437
  },

7438
  {

7439
   "chips": ["gfx81"],

7440
   "map": {"at": 200796, "to": "mm"},

7441
   "name": "GDS_ATOM_READ0_U"

7442
  },

7443
  {

7444
   "chips": ["gfx81"],

7445
   "map": {"at": 200800, "to": "mm"},

7446
   "name": "GDS_ATOM_READ1"

7447
  },

7448
  {

7449
   "chips": ["gfx81"],

7450
   "map": {"at": 200804, "to": "mm"},

7451
   "name": "GDS_ATOM_READ1_U"

7452
  },

7453
  {

7454
   "chips": ["gfx81"],

7455
   "map": {"at": 200808, "to": "mm"},

7456
   "name": "GDS_GWS_RESOURCE_CNTL",

7457
   "type_ref": "GDS_GWS_RESOURCE_CNTL"

7458
  },

7459
  {

7460
   "chips": ["gfx81"],

7461
   "map": {"at": 200812, "to": "mm"},

7462
   "name": "GDS_GWS_RESOURCE",

7463
   "type_ref": "GDS_GWS_RESOURCE"

7464
  },

7465
  {

7466
   "chips": ["gfx81"],

7467
   "map": {"at": 200816, "to": "mm"},

7468
   "name": "GDS_GWS_RESOURCE_CNT",

7469
   "type_ref": "GDS_GWS_RESOURCE_CNT"

7470
  },

7471
  {

7472
   "chips": ["gfx81"],

7473
   "map": {"at": 200820, "to": "mm"},

7474
   "name": "GDS_OA_CNTL",

7475
   "type_ref": "GDS_OA_CNTL"

7476
  },

7477
  {

7478
   "chips": ["gfx81"],

7479
   "map": {"at": 200824, "to": "mm"},

7480
   "name": "GDS_OA_COUNTER"

7481
  },

7482
  {

7483
   "chips": ["gfx81"],

7484
   "map": {"at": 200828, "to": "mm"},

7485
   "name": "GDS_OA_ADDRESS",

7486
   "type_ref": "GDS_OA_ADDRESS"

7487
  },

7488
  {

7489
   "chips": ["gfx81"],

7490
   "map": {"at": 200832, "to": "mm"},

7491
   "name": "GDS_OA_INCDEC",

7492
   "type_ref": "GDS_OA_INCDEC"

7493
  },

7494
  {

7495
   "chips": ["gfx81"],

7496
   "map": {"at": 200836, "to": "mm"},

7497
   "name": "GDS_OA_RING_SIZE"

7498
  },

7499
  {

7500
   "chips": ["gfx81"],

7501
   "map": {"at": 212992, "to": "mm"},

7502
   "name": "CPG_PERFCOUNTER1_LO"

7503
  },

7504
  {

7505
   "chips": ["gfx81"],

7506
   "map": {"at": 212996, "to": "mm"},

7507
   "name": "CPG_PERFCOUNTER1_HI"

7508
  },

7509
  {

7510
   "chips": ["gfx81"],

7511
   "map": {"at": 213000, "to": "mm"},

7512
   "name": "CPG_PERFCOUNTER0_LO"

7513
  },

7514
  {

7515
   "chips": ["gfx81"],

7516
   "map": {"at": 213004, "to": "mm"},

7517
   "name": "CPG_PERFCOUNTER0_HI"

7518
  },

7519
  {

7520
   "chips": ["gfx81"],

7521
   "map": {"at": 213008, "to": "mm"},

7522
   "name": "CPC_PERFCOUNTER1_LO"

7523
  },

7524
  {

7525
   "chips": ["gfx81"],

7526
   "map": {"at": 213012, "to": "mm"},

7527
   "name": "CPC_PERFCOUNTER1_HI"

7528
  },

7529
  {

7530
   "chips": ["gfx81"],

7531
   "map": {"at": 213016, "to": "mm"},

7532
   "name": "CPC_PERFCOUNTER0_LO"

7533
  },

7534
  {

7535
   "chips": ["gfx81"],

7536
   "map": {"at": 213020, "to": "mm"},

7537
   "name": "CPC_PERFCOUNTER0_HI"

7538
  },

7539
  {

7540
   "chips": ["gfx81"],

7541
   "map": {"at": 213024, "to": "mm"},

7542
   "name": "CPF_PERFCOUNTER1_LO"

7543
  },

7544
  {

7545
   "chips": ["gfx81"],

7546
   "map": {"at": 213028, "to": "mm"},

7547
   "name": "CPF_PERFCOUNTER1_HI"

7548
  },

7549
  {

7550
   "chips": ["gfx81"],

7551
   "map": {"at": 213032, "to": "mm"},

7552
   "name": "CPF_PERFCOUNTER0_LO"

7553
  },

7554
  {

7555
   "chips": ["gfx81"],

7556
   "map": {"at": 213036, "to": "mm"},

7557
   "name": "CPF_PERFCOUNTER0_HI"

7558
  },

7559
  {

7560
   "chips": ["gfx81"],

7561
   "map": {"at": 213248, "to": "mm"},

7562
   "name": "GRBM_PERFCOUNTER0_LO"

7563
  },

7564
  {

7565
   "chips": ["gfx81"],

7566
   "map": {"at": 213252, "to": "mm"},

7567
   "name": "GRBM_PERFCOUNTER0_HI"

7568
  },

7569
  {

7570
   "chips": ["gfx81"],

7571
   "map": {"at": 213260, "to": "mm"},

7572
   "name": "GRBM_PERFCOUNTER1_LO"

7573
  },

7574
  {

7575
   "chips": ["gfx81"],

7576
   "map": {"at": 213264, "to": "mm"},

7577
   "name": "GRBM_PERFCOUNTER1_HI"

7578
  },

7579
  {

7580
   "chips": ["gfx81"],

7581
   "map": {"at": 213268, "to": "mm"},

7582
   "name": "GRBM_SE0_PERFCOUNTER_LO"

7583
  },

7584
  {

7585
   "chips": ["gfx81"],

7586
   "map": {"at": 213272, "to": "mm"},

7587
   "name": "GRBM_SE0_PERFCOUNTER_HI"

7588
  },

7589
  {

7590
   "chips": ["gfx81"],

7591
   "map": {"at": 213276, "to": "mm"},

7592
   "name": "GRBM_SE1_PERFCOUNTER_LO"

7593
  },

7594
  {

7595
   "chips": ["gfx81"],

7596
   "map": {"at": 213280, "to": "mm"},

7597
   "name": "GRBM_SE1_PERFCOUNTER_HI"

7598
  },

7599
  {

7600
   "chips": ["gfx81"],

7601
   "map": {"at": 213284, "to": "mm"},

7602
   "name": "GRBM_SE2_PERFCOUNTER_LO"

7603
  },

7604
  {

7605
   "chips": ["gfx81"],

7606
   "map": {"at": 213288, "to": "mm"},

7607
   "name": "GRBM_SE2_PERFCOUNTER_HI"

7608
  },

7609
  {

7610
   "chips": ["gfx81"],

7611
   "map": {"at": 213292, "to": "mm"},

7612
   "name": "GRBM_SE3_PERFCOUNTER_LO"

7613
  },

7614
  {

7615
   "chips": ["gfx81"],

7616
   "map": {"at": 213296, "to": "mm"},

7617
   "name": "GRBM_SE3_PERFCOUNTER_HI"

7618
  },

7619
  {

7620
   "chips": ["gfx81"],

7621
   "map": {"at": 213504, "to": "mm"},

7622
   "name": "WD_PERFCOUNTER0_LO"

7623
  },

7624
  {

7625
   "chips": ["gfx81"],

7626
   "map": {"at": 213508, "to": "mm"},

7627
   "name": "WD_PERFCOUNTER0_HI"

7628
  },

7629
  {

7630
   "chips": ["gfx81"],

7631
   "map": {"at": 213512, "to": "mm"},

7632
   "name": "WD_PERFCOUNTER1_LO"

7633
  },

7634
  {

7635
   "chips": ["gfx81"],

7636
   "map": {"at": 213516, "to": "mm"},

7637
   "name": "WD_PERFCOUNTER1_HI"

7638
  },

7639
  {

7640
   "chips": ["gfx81"],

7641
   "map": {"at": 213520, "to": "mm"},

7642
   "name": "WD_PERFCOUNTER2_LO"

7643
  },

7644
  {

7645
   "chips": ["gfx81"],

7646
   "map": {"at": 213524, "to": "mm"},

7647
   "name": "WD_PERFCOUNTER2_HI"

7648
  },

7649
  {

7650
   "chips": ["gfx81"],

7651
   "map": {"at": 213528, "to": "mm"},

7652
   "name": "WD_PERFCOUNTER3_LO"

7653
  },

7654
  {

7655
   "chips": ["gfx81"],

7656
   "map": {"at": 213532, "to": "mm"},

7657
   "name": "WD_PERFCOUNTER3_HI"

7658
  },

7659
  {

7660
   "chips": ["gfx81"],

7661
   "map": {"at": 213536, "to": "mm"},

7662
   "name": "IA_PERFCOUNTER0_LO"

7663
  },

7664
  {

7665
   "chips": ["gfx81"],

7666
   "map": {"at": 213540, "to": "mm"},

7667
   "name": "IA_PERFCOUNTER0_HI"

7668
  },

7669
  {

7670
   "chips": ["gfx81"],

7671
   "map": {"at": 213544, "to": "mm"},

7672
   "name": "IA_PERFCOUNTER1_LO"

7673
  },

7674
  {

7675
   "chips": ["gfx81"],

7676
   "map": {"at": 213548, "to": "mm"},

7677
   "name": "IA_PERFCOUNTER1_HI"

7678
  },

7679
  {

7680
   "chips": ["gfx81"],

7681
   "map": {"at": 213552, "to": "mm"},

7682
   "name": "IA_PERFCOUNTER2_LO"

7683
  },

7684
  {

7685
   "chips": ["gfx81"],

7686
   "map": {"at": 213556, "to": "mm"},

7687
   "name": "IA_PERFCOUNTER2_HI"

7688
  },

7689
  {

7690
   "chips": ["gfx81"],

7691
   "map": {"at": 213560, "to": "mm"},

7692
   "name": "IA_PERFCOUNTER3_LO"

7693
  },

7694
  {

7695
   "chips": ["gfx81"],

7696
   "map": {"at": 213564, "to": "mm"},

7697
   "name": "IA_PERFCOUNTER3_HI"

7698
  },

7699
  {

7700
   "chips": ["gfx81"],

7701
   "map": {"at": 213568, "to": "mm"},

7702
   "name": "VGT_PERFCOUNTER0_LO"

7703
  },

7704
  {

7705
   "chips": ["gfx81"],

7706
   "map": {"at": 213572, "to": "mm"},

7707
   "name": "VGT_PERFCOUNTER0_HI"

7708
  },

7709
  {

7710
   "chips": ["gfx81"],

7711
   "map": {"at": 213576, "to": "mm"},

7712
   "name": "VGT_PERFCOUNTER1_LO"

7713
  },

7714
  {

7715
   "chips": ["gfx81"],

7716
   "map": {"at": 213580, "to": "mm"},

7717
   "name": "VGT_PERFCOUNTER1_HI"

7718
  },

7719
  {

7720
   "chips": ["gfx81"],

7721
   "map": {"at": 213584, "to": "mm"},

7722
   "name": "VGT_PERFCOUNTER2_LO"

7723
  },

7724
  {

7725
   "chips": ["gfx81"],

7726
   "map": {"at": 213588, "to": "mm"},

7727
   "name": "VGT_PERFCOUNTER2_HI"

7728
  },

7729
  {

7730
   "chips": ["gfx81"],

7731
   "map": {"at": 213592, "to": "mm"},

7732
   "name": "VGT_PERFCOUNTER3_LO"

7733
  },

7734
  {

7735
   "chips": ["gfx81"],

7736
   "map": {"at": 213596, "to": "mm"},

7737
   "name": "VGT_PERFCOUNTER3_HI"

7738
  },

7739
  {

7740
   "chips": ["gfx81"],

7741
   "map": {"at": 214016, "to": "mm"},

7742
   "name": "PA_SU_PERFCOUNTER0_LO"

7743
  },

7744
  {

7745
   "chips": ["gfx81"],

7746
   "map": {"at": 214020, "to": "mm"},

7747
   "name": "PA_SU_PERFCOUNTER0_HI",

7748
   "type_ref": "PA_SU_PERFCOUNTER0_HI"

7749
  },

7750
  {

7751
   "chips": ["gfx81"],

7752
   "map": {"at": 214024, "to": "mm"},

7753
   "name": "PA_SU_PERFCOUNTER1_LO"

7754
  },

7755
  {

7756
   "chips": ["gfx81"],

7757
   "map": {"at": 214028, "to": "mm"},

7758
   "name": "PA_SU_PERFCOUNTER1_HI",

7759
   "type_ref": "PA_SU_PERFCOUNTER0_HI"

7760
  },

7761
  {

7762
   "chips": ["gfx81"],

7763
   "map": {"at": 214032, "to": "mm"},

7764
   "name": "PA_SU_PERFCOUNTER2_LO"

7765
  },

7766
  {

7767
   "chips": ["gfx81"],

7768
   "map": {"at": 214036, "to": "mm"},

7769
   "name": "PA_SU_PERFCOUNTER2_HI",

7770
   "type_ref": "PA_SU_PERFCOUNTER0_HI"

7771
  },

7772
  {

7773
   "chips": ["gfx81"],

7774
   "map": {"at": 214040, "to": "mm"},

7775
   "name": "PA_SU_PERFCOUNTER3_LO"

7776
  },

7777
  {

7778
   "chips": ["gfx81"],

7779
   "map": {"at": 214044, "to": "mm"},

7780
   "name": "PA_SU_PERFCOUNTER3_HI",

7781
   "type_ref": "PA_SU_PERFCOUNTER0_HI"

7782
  },

7783
  {

7784
   "chips": ["gfx81"],

7785
   "map": {"at": 214272, "to": "mm"},

7786
   "name": "PA_SC_PERFCOUNTER0_LO"

7787
  },

7788
  {

7789
   "chips": ["gfx81"],

7790
   "map": {"at": 214276, "to": "mm"},

7791
   "name": "PA_SC_PERFCOUNTER0_HI"

7792
  },

7793
  {

7794
   "chips": ["gfx81"],

7795
   "map": {"at": 214280, "to": "mm"},

7796
   "name": "PA_SC_PERFCOUNTER1_LO"

7797
  },

7798
  {

7799
   "chips": ["gfx81"],

7800
   "map": {"at": 214284, "to": "mm"},

7801
   "name": "PA_SC_PERFCOUNTER1_HI"

7802
  },

7803
  {

7804
   "chips": ["gfx81"],

7805
   "map": {"at": 214288, "to": "mm"},

7806
   "name": "PA_SC_PERFCOUNTER2_LO"

7807
  },

7808
  {

7809
   "chips": ["gfx81"],

7810
   "map": {"at": 214292, "to": "mm"},

7811
   "name": "PA_SC_PERFCOUNTER2_HI"

7812
  },

7813
  {

7814
   "chips": ["gfx81"],

7815
   "map": {"at": 214296, "to": "mm"},

7816
   "name": "PA_SC_PERFCOUNTER3_LO"

7817
  },

7818
  {

7819
   "chips": ["gfx81"],

7820
   "map": {"at": 214300, "to": "mm"},

7821
   "name": "PA_SC_PERFCOUNTER3_HI"

7822
  },

7823
  {

7824
   "chips": ["gfx81"],

7825
   "map": {"at": 214304, "to": "mm"},

7826
   "name": "PA_SC_PERFCOUNTER4_LO"

7827
  },

7828
  {

7829
   "chips": ["gfx81"],

7830
   "map": {"at": 214308, "to": "mm"},

7831
   "name": "PA_SC_PERFCOUNTER4_HI"

7832
  },

7833
  {

7834
   "chips": ["gfx81"],

7835
   "map": {"at": 214312, "to": "mm"},

7836
   "name": "PA_SC_PERFCOUNTER5_LO"

7837
  },

7838
  {

7839
   "chips": ["gfx81"],

7840
   "map": {"at": 214316, "to": "mm"},

7841
   "name": "PA_SC_PERFCOUNTER5_HI"

7842
  },

7843
  {

7844
   "chips": ["gfx81"],

7845
   "map": {"at": 214320, "to": "mm"},

7846
   "name": "PA_SC_PERFCOUNTER6_LO"

7847
  },

7848
  {

7849
   "chips": ["gfx81"],

7850
   "map": {"at": 214324, "to": "mm"},

7851
   "name": "PA_SC_PERFCOUNTER6_HI"

7852
  },

7853
  {

7854
   "chips": ["gfx81"],

7855
   "map": {"at": 214328, "to": "mm"},

7856
   "name": "PA_SC_PERFCOUNTER7_LO"

7857
  },

7858
  {

7859
   "chips": ["gfx81"],

7860
   "map": {"at": 214332, "to": "mm"},

7861
   "name": "PA_SC_PERFCOUNTER7_HI"

7862
  },

7863
  {

7864
   "chips": ["gfx81"],

7865
   "map": {"at": 214528, "to": "mm"},

7866
   "name": "SPI_PERFCOUNTER0_HI"

7867
  },

7868
  {

7869
   "chips": ["gfx81"],

7870
   "map": {"at": 214532, "to": "mm"},

7871
   "name": "SPI_PERFCOUNTER0_LO"

7872
  },

7873
  {

7874
   "chips": ["gfx81"],

7875
   "map": {"at": 214536, "to": "mm"},

7876
   "name": "SPI_PERFCOUNTER1_HI"

7877
  },

7878
  {

7879
   "chips": ["gfx81"],

7880
   "map": {"at": 214540, "to": "mm"},

7881
   "name": "SPI_PERFCOUNTER1_LO"

7882
  },

7883
  {

7884
   "chips": ["gfx81"],

7885
   "map": {"at": 214544, "to": "mm"},

7886
   "name": "SPI_PERFCOUNTER2_HI"

7887
  },

7888
  {

7889
   "chips": ["gfx81"],

7890
   "map": {"at": 214548, "to": "mm"},

7891
   "name": "SPI_PERFCOUNTER2_LO"

7892
  },

7893
  {

7894
   "chips": ["gfx81"],

7895
   "map": {"at": 214552, "to": "mm"},

7896
   "name": "SPI_PERFCOUNTER3_HI"

7897
  },

7898
  {

7899
   "chips": ["gfx81"],

7900
   "map": {"at": 214556, "to": "mm"},

7901
   "name": "SPI_PERFCOUNTER3_LO"

7902
  },

7903
  {

7904
   "chips": ["gfx81"],

7905
   "map": {"at": 214560, "to": "mm"},

7906
   "name": "SPI_PERFCOUNTER4_HI"

7907
  },

7908
  {

7909
   "chips": ["gfx81"],

7910
   "map": {"at": 214564, "to": "mm"},

7911
   "name": "SPI_PERFCOUNTER4_LO"

7912
  },

7913
  {

7914
   "chips": ["gfx81"],

7915
   "map": {"at": 214568, "to": "mm"},

7916
   "name": "SPI_PERFCOUNTER5_HI"

7917
  },

7918
  {

7919
   "chips": ["gfx81"],

7920
   "map": {"at": 214572, "to": "mm"},

7921
   "name": "SPI_PERFCOUNTER5_LO"

7922
  },

7923
  {

7924
   "chips": ["gfx81"],

7925
   "map": {"at": 214784, "to": "mm"},

7926
   "name": "SQ_PERFCOUNTER0_LO"

7927
  },

7928
  {

7929
   "chips": ["gfx81"],

7930
   "map": {"at": 214788, "to": "mm"},

7931
   "name": "SQ_PERFCOUNTER0_HI"

7932
  },

7933
  {

7934
   "chips": ["gfx81"],

7935
   "map": {"at": 214792, "to": "mm"},

7936
   "name": "SQ_PERFCOUNTER1_LO"

7937
  },

7938
  {

7939
   "chips": ["gfx81"],

7940
   "map": {"at": 214796, "to": "mm"},

7941
   "name": "SQ_PERFCOUNTER1_HI"

7942
  },

7943
  {

7944
   "chips": ["gfx81"],

7945
   "map": {"at": 214800, "to": "mm"},

7946
   "name": "SQ_PERFCOUNTER2_LO"

7947
  },

7948
  {

7949
   "chips": ["gfx81"],

7950
   "map": {"at": 214804, "to": "mm"},

7951
   "name": "SQ_PERFCOUNTER2_HI"

7952
  },

7953
  {

7954
   "chips": ["gfx81"],

7955
   "map": {"at": 214808, "to": "mm"},

7956
   "name": "SQ_PERFCOUNTER3_LO"

7957
  },

7958
  {

7959
   "chips": ["gfx81"],

7960
   "map": {"at": 214812, "to": "mm"},

7961
   "name": "SQ_PERFCOUNTER3_HI"

7962
  },

7963
  {

7964
   "chips": ["gfx81"],

7965
   "map": {"at": 214816, "to": "mm"},

7966
   "name": "SQ_PERFCOUNTER4_LO"

7967
  },

7968
  {

7969
   "chips": ["gfx81"],

7970
   "map": {"at": 214820, "to": "mm"},

7971
   "name": "SQ_PERFCOUNTER4_HI"

7972
  },

7973
  {

7974
   "chips": ["gfx81"],

7975
   "map": {"at": 214824, "to": "mm"},

7976
   "name": "SQ_PERFCOUNTER5_LO"

7977
  },

7978
  {

7979
   "chips": ["gfx81"],

7980
   "map": {"at": 214828, "to": "mm"},

7981
   "name": "SQ_PERFCOUNTER5_HI"

7982
  },

7983
  {

7984
   "chips": ["gfx81"],

7985
   "map": {"at": 214832, "to": "mm"},

7986
   "name": "SQ_PERFCOUNTER6_LO"

7987
  },

7988
  {

7989
   "chips": ["gfx81"],

7990
   "map": {"at": 214836, "to": "mm"},

7991
   "name": "SQ_PERFCOUNTER6_HI"

7992
  },

7993
  {

7994
   "chips": ["gfx81"],

7995
   "map": {"at": 214840, "to": "mm"},

7996
   "name": "SQ_PERFCOUNTER7_LO"

7997
  },

7998
  {

7999
   "chips": ["gfx81"],

8000
   "map": {"at": 214844, "to": "mm"},

8001
   "name": "SQ_PERFCOUNTER7_HI"

8002
  },

8003
  {

8004
   "chips": ["gfx81"],

8005
   "map": {"at": 214848, "to": "mm"},

8006
   "name": "SQ_PERFCOUNTER8_LO"

8007
  },

8008
  {

8009
   "chips": ["gfx81"],

8010
   "map": {"at": 214852, "to": "mm"},

8011
   "name": "SQ_PERFCOUNTER8_HI"

8012
  },

8013
  {

8014
   "chips": ["gfx81"],

8015
   "map": {"at": 214856, "to": "mm"},

8016
   "name": "SQ_PERFCOUNTER9_LO"

8017
  },

8018
  {

8019
   "chips": ["gfx81"],

8020
   "map": {"at": 214860, "to": "mm"},

8021
   "name": "SQ_PERFCOUNTER9_HI"

8022
  },

8023
  {

8024
   "chips": ["gfx81"],

8025
   "map": {"at": 214864, "to": "mm"},

8026
   "name": "SQ_PERFCOUNTER10_LO"

8027
  },

8028
  {

8029
   "chips": ["gfx81"],

8030
   "map": {"at": 214868, "to": "mm"},

8031
   "name": "SQ_PERFCOUNTER10_HI"

8032
  },

8033
  {

8034
   "chips": ["gfx81"],

8035
   "map": {"at": 214872, "to": "mm"},

8036
   "name": "SQ_PERFCOUNTER11_LO"

8037
  },

8038
  {

8039
   "chips": ["gfx81"],

8040
   "map": {"at": 214876, "to": "mm"},

8041
   "name": "SQ_PERFCOUNTER11_HI"

8042
  },

8043
  {

8044
   "chips": ["gfx81"],

8045
   "map": {"at": 214880, "to": "mm"},

8046
   "name": "SQ_PERFCOUNTER12_LO"

8047
  },

8048
  {

8049
   "chips": ["gfx81"],

8050
   "map": {"at": 214884, "to": "mm"},

8051
   "name": "SQ_PERFCOUNTER12_HI"

8052
  },

8053
  {

8054
   "chips": ["gfx81"],

8055
   "map": {"at": 214888, "to": "mm"},

8056
   "name": "SQ_PERFCOUNTER13_LO"

8057
  },

8058
  {

8059
   "chips": ["gfx81"],

8060
   "map": {"at": 214892, "to": "mm"},

8061
   "name": "SQ_PERFCOUNTER13_HI"

8062
  },

8063
  {

8064
   "chips": ["gfx81"],

8065
   "map": {"at": 214896, "to": "mm"},

8066
   "name": "SQ_PERFCOUNTER14_LO"

8067
  },

8068
  {

8069
   "chips": ["gfx81"],

8070
   "map": {"at": 214900, "to": "mm"},

8071
   "name": "SQ_PERFCOUNTER14_HI"

8072
  },

8073
  {

8074
   "chips": ["gfx81"],

8075
   "map": {"at": 214904, "to": "mm"},

8076
   "name": "SQ_PERFCOUNTER15_LO"

8077
  },

8078
  {

8079
   "chips": ["gfx81"],

8080
   "map": {"at": 214908, "to": "mm"},

8081
   "name": "SQ_PERFCOUNTER15_HI"

8082
  },

8083
  {

8084
   "chips": ["gfx81"],

8085
   "map": {"at": 215296, "to": "mm"},

8086
   "name": "SX_PERFCOUNTER0_LO"

8087
  },

8088
  {

8089
   "chips": ["gfx81"],

8090
   "map": {"at": 215300, "to": "mm"},

8091
   "name": "SX_PERFCOUNTER0_HI"

8092
  },

8093
  {

8094
   "chips": ["gfx81"],

8095
   "map": {"at": 215304, "to": "mm"},

8096
   "name": "SX_PERFCOUNTER1_LO"

8097
  },

8098
  {

8099
   "chips": ["gfx81"],

8100
   "map": {"at": 215308, "to": "mm"},

8101
   "name": "SX_PERFCOUNTER1_HI"

8102
  },

8103
  {

8104
   "chips": ["gfx81"],

8105
   "map": {"at": 215312, "to": "mm"},

8106
   "name": "SX_PERFCOUNTER2_LO"

8107
  },

8108
  {

8109
   "chips": ["gfx81"],

8110
   "map": {"at": 215316, "to": "mm"},

8111
   "name": "SX_PERFCOUNTER2_HI"

8112
  },

8113
  {

8114
   "chips": ["gfx81"],

8115
   "map": {"at": 215320, "to": "mm"},

8116
   "name": "SX_PERFCOUNTER3_LO"

8117
  },

8118
  {

8119
   "chips": ["gfx81"],

8120
   "map": {"at": 215324, "to": "mm"},

8121
   "name": "SX_PERFCOUNTER3_HI"

8122
  },

8123
  {

8124
   "chips": ["gfx81"],

8125
   "map": {"at": 215552, "to": "mm"},

8126
   "name": "GDS_PERFCOUNTER0_LO"

8127
  },

8128
  {

8129
   "chips": ["gfx81"],

8130
   "map": {"at": 215556, "to": "mm"},

8131
   "name": "GDS_PERFCOUNTER0_HI"

8132
  },

8133
  {

8134
   "chips": ["gfx81"],

8135
   "map": {"at": 215560, "to": "mm"},

8136
   "name": "GDS_PERFCOUNTER1_LO"

8137
  },

8138
  {

8139
   "chips": ["gfx81"],

8140
   "map": {"at": 215564, "to": "mm"},

8141
   "name": "GDS_PERFCOUNTER1_HI"

8142
  },

8143
  {

8144
   "chips": ["gfx81"],

8145
   "map": {"at": 215568, "to": "mm"},

8146
   "name": "GDS_PERFCOUNTER2_LO"

8147
  },

8148
  {

8149
   "chips": ["gfx81"],

8150
   "map": {"at": 215572, "to": "mm"},

8151
   "name": "GDS_PERFCOUNTER2_HI"

8152
  },

8153
  {

8154
   "chips": ["gfx81"],

8155
   "map": {"at": 215576, "to": "mm"},

8156
   "name": "GDS_PERFCOUNTER3_LO"

8157
  },

8158
  {

8159
   "chips": ["gfx81"],

8160
   "map": {"at": 215580, "to": "mm"},

8161
   "name": "GDS_PERFCOUNTER3_HI"

8162
  },

8163
  {

8164
   "chips": ["gfx81"],

8165
   "map": {"at": 215808, "to": "mm"},

8166
   "name": "TA_PERFCOUNTER0_LO"

8167
  },

8168
  {

8169
   "chips": ["gfx81"],

8170
   "map": {"at": 215812, "to": "mm"},

8171
   "name": "TA_PERFCOUNTER0_HI"

8172
  },

8173
  {

8174
   "chips": ["gfx81"],

8175
   "map": {"at": 215816, "to": "mm"},

8176
   "name": "TA_PERFCOUNTER1_LO"

8177
  },

8178
  {

8179
   "chips": ["gfx81"],

8180
   "map": {"at": 215820, "to": "mm"},

8181
   "name": "TA_PERFCOUNTER1_HI"

8182
  },

8183
  {

8184
   "chips": ["gfx81"],

8185
   "map": {"at": 216064, "to": "mm"},

8186
   "name": "TD_PERFCOUNTER0_LO"

8187
  },

8188
  {

8189
   "chips": ["gfx81"],

8190
   "map": {"at": 216068, "to": "mm"},

8191
   "name": "TD_PERFCOUNTER0_HI"

8192
  },

8193
  {

8194
   "chips": ["gfx81"],

8195
   "map": {"at": 216072, "to": "mm"},

8196
   "name": "TD_PERFCOUNTER1_LO"

8197
  },

8198
  {

8199
   "chips": ["gfx81"],

8200
   "map": {"at": 216076, "to": "mm"},

8201
   "name": "TD_PERFCOUNTER1_HI"

8202
  },

8203
  {

8204
   "chips": ["gfx81"],

8205
   "map": {"at": 216320, "to": "mm"},

8206
   "name": "TCP_PERFCOUNTER0_LO"

8207
  },

8208
  {

8209
   "chips": ["gfx81"],

8210
   "map": {"at": 216324, "to": "mm"},

8211
   "name": "TCP_PERFCOUNTER0_HI"

8212
  },

8213
  {

8214
   "chips": ["gfx81"],

8215
   "map": {"at": 216328, "to": "mm"},

8216
   "name": "TCP_PERFCOUNTER1_LO"

8217
  },

8218
  {

8219
   "chips": ["gfx81"],

8220
   "map": {"at": 216332, "to": "mm"},

8221
   "name": "TCP_PERFCOUNTER1_HI"

8222
  },

8223
  {

8224
   "chips": ["gfx81"],

8225
   "map": {"at": 216336, "to": "mm"},

8226
   "name": "TCP_PERFCOUNTER2_LO"

8227
  },

8228
  {

8229
   "chips": ["gfx81"],

8230
   "map": {"at": 216340, "to": "mm"},

8231
   "name": "TCP_PERFCOUNTER2_HI"

8232
  },

8233
  {

8234
   "chips": ["gfx81"],

8235
   "map": {"at": 216344, "to": "mm"},

8236
   "name": "TCP_PERFCOUNTER3_LO"

8237
  },

8238
  {

8239
   "chips": ["gfx81"],

8240
   "map": {"at": 216348, "to": "mm"},

8241
   "name": "TCP_PERFCOUNTER3_HI"

8242
  },

8243
  {

8244
   "chips": ["gfx81"],

8245
   "map": {"at": 216576, "to": "mm"},

8246
   "name": "TCC_PERFCOUNTER0_LO"

8247
  },

8248
  {

8249
   "chips": ["gfx81"],

8250
   "map": {"at": 216580, "to": "mm"},

8251
   "name": "TCC_PERFCOUNTER0_HI"

8252
  },

8253
  {

8254
   "chips": ["gfx81"],

8255
   "map": {"at": 216584, "to": "mm"},

8256
   "name": "TCC_PERFCOUNTER1_LO"

8257
  },

8258
  {

8259
   "chips": ["gfx81"],

8260
   "map": {"at": 216588, "to": "mm"},

8261
   "name": "TCC_PERFCOUNTER1_HI"

8262
  },

8263
  {

8264
   "chips": ["gfx81"],

8265
   "map": {"at": 216592, "to": "mm"},

8266
   "name": "TCC_PERFCOUNTER2_LO"

8267
  },

8268
  {

8269
   "chips": ["gfx81"],

8270
   "map": {"at": 216596, "to": "mm"},

8271
   "name": "TCC_PERFCOUNTER2_HI"

8272
  },

8273
  {

8274
   "chips": ["gfx81"],

8275
   "map": {"at": 216600, "to": "mm"},

8276
   "name": "TCC_PERFCOUNTER3_LO"

8277
  },

8278
  {

8279
   "chips": ["gfx81"],

8280
   "map": {"at": 216604, "to": "mm"},

8281
   "name": "TCC_PERFCOUNTER3_HI"

8282
  },

8283
  {

8284
   "chips": ["gfx81"],

8285
   "map": {"at": 216640, "to": "mm"},

8286
   "name": "TCA_PERFCOUNTER0_LO"

8287
  },

8288
  {

8289
   "chips": ["gfx81"],

8290
   "map": {"at": 216644, "to": "mm"},

8291
   "name": "TCA_PERFCOUNTER0_HI"

8292
  },

8293
  {

8294
   "chips": ["gfx81"],

8295
   "map": {"at": 216648, "to": "mm"},

8296
   "name": "TCA_PERFCOUNTER1_LO"

8297
  },

8298
  {

8299
   "chips": ["gfx81"],

8300
   "map": {"at": 216652, "to": "mm"},

8301
   "name": "TCA_PERFCOUNTER1_HI"

8302
  },

8303
  {

8304
   "chips": ["gfx81"],

8305
   "map": {"at": 216656, "to": "mm"},

8306
   "name": "TCA_PERFCOUNTER2_LO"

8307
  },

8308
  {

8309
   "chips": ["gfx81"],

8310
   "map": {"at": 216660, "to": "mm"},

8311
   "name": "TCA_PERFCOUNTER2_HI"

8312
  },

8313
  {

8314
   "chips": ["gfx81"],

8315
   "map": {"at": 216664, "to": "mm"},

8316
   "name": "TCA_PERFCOUNTER3_LO"

8317
  },

8318
  {

8319
   "chips": ["gfx81"],

8320
   "map": {"at": 216668, "to": "mm"},

8321
   "name": "TCA_PERFCOUNTER3_HI"

8322
  },

8323
  {

8324
   "chips": ["gfx81"],

8325
   "map": {"at": 217112, "to": "mm"},

8326
   "name": "CB_PERFCOUNTER0_LO"

8327
  },

8328
  {

8329
   "chips": ["gfx81"],

8330
   "map": {"at": 217116, "to": "mm"},

8331
   "name": "CB_PERFCOUNTER0_HI"

8332
  },

8333
  {

8334
   "chips": ["gfx81"],

8335
   "map": {"at": 217120, "to": "mm"},

8336
   "name": "CB_PERFCOUNTER1_LO"

8337
  },

8338
  {

8339
   "chips": ["gfx81"],

8340
   "map": {"at": 217124, "to": "mm"},

8341
   "name": "CB_PERFCOUNTER1_HI"

8342
  },

8343
  {

8344
   "chips": ["gfx81"],

8345
   "map": {"at": 217128, "to": "mm"},

8346
   "name": "CB_PERFCOUNTER2_LO"

8347
  },

8348
  {

8349
   "chips": ["gfx81"],

8350
   "map": {"at": 217132, "to": "mm"},

8351
   "name": "CB_PERFCOUNTER2_HI"

8352
  },

8353
  {

8354
   "chips": ["gfx81"],

8355
   "map": {"at": 217136, "to": "mm"},

8356
   "name": "CB_PERFCOUNTER3_LO"

8357
  },

8358
  {

8359
   "chips": ["gfx81"],

8360
   "map": {"at": 217140, "to": "mm"},

8361
   "name": "CB_PERFCOUNTER3_HI"

8362
  },

8363
  {

8364
   "chips": ["gfx81"],

8365
   "map": {"at": 217344, "to": "mm"},

8366
   "name": "DB_PERFCOUNTER0_LO"

8367
  },

8368
  {

8369
   "chips": ["gfx81"],

8370
   "map": {"at": 217348, "to": "mm"},

8371
   "name": "DB_PERFCOUNTER0_HI"

8372
  },

8373
  {

8374
   "chips": ["gfx81"],

8375
   "map": {"at": 217352, "to": "mm"},

8376
   "name": "DB_PERFCOUNTER1_LO"

8377
  },

8378
  {

8379
   "chips": ["gfx81"],

8380
   "map": {"at": 217356, "to": "mm"},

8381
   "name": "DB_PERFCOUNTER1_HI"

8382
  },

8383
  {

8384
   "chips": ["gfx81"],

8385
   "map": {"at": 217360, "to": "mm"},

8386
   "name": "DB_PERFCOUNTER2_LO"

8387
  },

8388
  {

8389
   "chips": ["gfx81"],

8390
   "map": {"at": 217364, "to": "mm"},

8391
   "name": "DB_PERFCOUNTER2_HI"

8392
  },

8393
  {

8394
   "chips": ["gfx81"],

8395
   "map": {"at": 217368, "to": "mm"},

8396
   "name": "DB_PERFCOUNTER3_LO"

8397
  },

8398
  {

8399
   "chips": ["gfx81"],

8400
   "map": {"at": 217372, "to": "mm"},

8401
   "name": "DB_PERFCOUNTER3_HI"

8402
  },

8403
  {

8404
   "chips": ["gfx81"],

8405
   "map": {"at": 217600, "to": "mm"},

8406
   "name": "RLC_PERFCOUNTER0_LO"

8407
  },

8408
  {

8409
   "chips": ["gfx81"],

8410
   "map": {"at": 217604, "to": "mm"},

8411
   "name": "RLC_PERFCOUNTER0_HI"

8412
  },

8413
  {

8414
   "chips": ["gfx81"],

8415
   "map": {"at": 217608, "to": "mm"},

8416
   "name": "RLC_PERFCOUNTER1_LO"

8417
  },

8418
  {

8419
   "chips": ["gfx81"],

8420
   "map": {"at": 217612, "to": "mm"},

8421
   "name": "RLC_PERFCOUNTER1_HI"

8422
  },

8423
  {

8424
   "chips": ["gfx81"],

8425
   "map": {"at": 221184, "to": "mm"},

8426
   "name": "CPG_PERFCOUNTER1_SELECT",

8427
   "type_ref": "CPG_PERFCOUNTER1_SELECT"

8428
  },

8429
  {

8430
   "chips": ["gfx81"],

8431
   "map": {"at": 221188, "to": "mm"},

8432
   "name": "CPG_PERFCOUNTER0_SELECT1",

8433
   "type_ref": "CPG_PERFCOUNTER0_SELECT1"

8434
  },

8435
  {

8436
   "chips": ["gfx81"],

8437
   "map": {"at": 221192, "to": "mm"},

8438
   "name": "CPG_PERFCOUNTER0_SELECT",

8439
   "type_ref": "CPG_PERFCOUNTER0_SELECT"

8440
  },

8441
  {

8442
   "chips": ["gfx81"],

8443
   "map": {"at": 221196, "to": "mm"},

8444
   "name": "CPC_PERFCOUNTER1_SELECT",

8445
   "type_ref": "CPG_PERFCOUNTER1_SELECT"

8446
  },

8447
  {

8448
   "chips": ["gfx81"],

8449
   "map": {"at": 221200, "to": "mm"},

8450
   "name": "CPC_PERFCOUNTER0_SELECT1",

8451
   "type_ref": "CPG_PERFCOUNTER0_SELECT1"

8452
  },

8453
  {

8454
   "chips": ["gfx81"],

8455
   "map": {"at": 221204, "to": "mm"},

8456
   "name": "CPF_PERFCOUNTER1_SELECT",

8457
   "type_ref": "CPG_PERFCOUNTER1_SELECT"

8458
  },

8459
  {

8460
   "chips": ["gfx81"],

8461
   "map": {"at": 221208, "to": "mm"},

8462
   "name": "CPF_PERFCOUNTER0_SELECT1",

8463
   "type_ref": "CPG_PERFCOUNTER0_SELECT1"

8464
  },

8465
  {

8466
   "chips": ["gfx81"],

8467
   "map": {"at": 221212, "to": "mm"},

8468
   "name": "CPF_PERFCOUNTER0_SELECT",

8469
   "type_ref": "CPG_PERFCOUNTER0_SELECT"

8470
  },

8471
  {

8472
   "chips": ["gfx81"],

8473
   "map": {"at": 221216, "to": "mm"},

8474
   "name": "CP_PERFMON_CNTL",

8475
   "type_ref": "CP_PERFMON_CNTL"

8476
  },

8477
  {

8478
   "chips": ["gfx81"],

8479
   "map": {"at": 221220, "to": "mm"},

8480
   "name": "CPC_PERFCOUNTER0_SELECT",

8481
   "type_ref": "CPG_PERFCOUNTER0_SELECT"

8482
  },

8483
  {

8484
   "chips": ["gfx81"],

8485
   "map": {"at": 221248, "to": "mm"},

8486
   "name": "CP_DRAW_OBJECT"

8487
  },

8488
  {

8489
   "chips": ["gfx81"],

8490
   "map": {"at": 221252, "to": "mm"},

8491
   "name": "CP_DRAW_OBJECT_COUNTER",

8492
   "type_ref": "CP_DRAW_OBJECT_COUNTER"

8493
  },

8494
  {

8495
   "chips": ["gfx81"],

8496
   "map": {"at": 221256, "to": "mm"},

8497
   "name": "CP_DRAW_WINDOW_MASK_HI"

8498
  },

8499
  {

8500
   "chips": ["gfx81"],

8501
   "map": {"at": 221260, "to": "mm"},

8502
   "name": "CP_DRAW_WINDOW_HI"

8503
  },

8504
  {

8505
   "chips": ["gfx81"],

8506
   "map": {"at": 221264, "to": "mm"},

8507
   "name": "CP_DRAW_WINDOW_LO",

8508
   "type_ref": "CP_DRAW_WINDOW_LO"

8509
  },

8510
  {

8511
   "chips": ["gfx81"],

8512
   "map": {"at": 221268, "to": "mm"},

8513
   "name": "CP_DRAW_WINDOW_CNTL",

8514
   "type_ref": "CP_DRAW_WINDOW_CNTL"

8515
  },

8516
  {

8517
   "chips": ["gfx81"],

8518
   "map": {"at": 221440, "to": "mm"},

8519
   "name": "GRBM_PERFCOUNTER0_SELECT",

8520
   "type_ref": "GRBM_PERFCOUNTER0_SELECT"

8521
  },

8522
  {

8523
   "chips": ["gfx81"],

8524
   "map": {"at": 221444, "to": "mm"},

8525
   "name": "GRBM_PERFCOUNTER1_SELECT",

8526
   "type_ref": "GRBM_PERFCOUNTER0_SELECT"

8527
  },

8528
  {

8529
   "chips": ["gfx81"],

8530
   "map": {"at": 221448, "to": "mm"},

8531
   "name": "GRBM_SE0_PERFCOUNTER_SELECT",

8532
   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"

8533
  },

8534
  {

8535
   "chips": ["gfx81"],

8536
   "map": {"at": 221452, "to": "mm"},

8537
   "name": "GRBM_SE1_PERFCOUNTER_SELECT",

8538
   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"

8539
  },

8540
  {

8541
   "chips": ["gfx81"],

8542
   "map": {"at": 221456, "to": "mm"},

8543
   "name": "GRBM_SE2_PERFCOUNTER_SELECT",

8544
   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"

8545
  },

8546
  {

8547
   "chips": ["gfx81"],

8548
   "map": {"at": 221460, "to": "mm"},

8549
   "name": "GRBM_SE3_PERFCOUNTER_SELECT",

8550
   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"

8551
  },

8552
  {

8553
   "chips": ["gfx81"],

8554
   "map": {"at": 221696, "to": "mm"},

8555
   "name": "WD_PERFCOUNTER0_SELECT",

8556
   "type_ref": "VGT_PERFCOUNTER2_SELECT"

8557
  },

8558
  {

8559
   "chips": ["gfx81"],

8560
   "map": {"at": 221700, "to": "mm"},

8561
   "name": "WD_PERFCOUNTER1_SELECT",

8562
   "type_ref": "VGT_PERFCOUNTER2_SELECT"

8563
  },

8564
  {

8565
   "chips": ["gfx81"],

8566
   "map": {"at": 221704, "to": "mm"},

8567
   "name": "WD_PERFCOUNTER2_SELECT",

8568
   "type_ref": "VGT_PERFCOUNTER2_SELECT"

8569
  },

8570
  {

8571
   "chips": ["gfx81"],

8572
   "map": {"at": 221708, "to": "mm"},

8573
   "name": "WD_PERFCOUNTER3_SELECT",

8574
   "type_ref": "VGT_PERFCOUNTER2_SELECT"

8575
  },

8576
  {

8577
   "chips": ["gfx81"],

8578
   "map": {"at": 221712, "to": "mm"},

8579
   "name": "IA_PERFCOUNTER0_SELECT",

8580
   "type_ref": "DB_PERFCOUNTER0_SELECT"

8581
  },

8582
  {

8583
   "chips": ["gfx81"],

8584
   "map": {"at": 221716, "to": "mm"},

8585
   "name": "IA_PERFCOUNTER1_SELECT",

8586
   "type_ref": "VGT_PERFCOUNTER2_SELECT"

8587
  },

8588
  {

8589
   "chips": ["gfx81"],

8590
   "map": {"at": 221720, "to": "mm"},

8591
   "name": "IA_PERFCOUNTER2_SELECT",

8592
   "type_ref": "VGT_PERFCOUNTER2_SELECT"

8593
  },

8594
  {

8595
   "chips": ["gfx81"],

8596
   "map": {"at": 221724, "to": "mm"},

8597
   "name": "IA_PERFCOUNTER3_SELECT",

8598
   "type_ref": "VGT_PERFCOUNTER2_SELECT"

8599
  },

8600
  {

8601
   "chips": ["gfx81"],

8602
   "map": {"at": 221728, "to": "mm"},

8603
   "name": "IA_PERFCOUNTER0_SELECT1",

8604
   "type_ref": "DB_PERFCOUNTER0_SELECT1"

8605
  },

8606
  {

8607
   "chips": ["gfx81"],

8608
   "map": {"at": 221744, "to": "mm"},

8609
   "name": "VGT_PERFCOUNTER0_SELECT",

8610
   "type_ref": "DB_PERFCOUNTER0_SELECT"

8611
  },

8612
  {

8613
   "chips": ["gfx81"],

8614
   "map": {"at": 221748, "to": "mm"},

8615
   "name": "VGT_PERFCOUNTER1_SELECT",

8616
   "type_ref": "DB_PERFCOUNTER0_SELECT"

8617
  },

8618
  {

8619
   "chips": ["gfx81"],

8620
   "map": {"at": 221752, "to": "mm"},

8621
   "name": "VGT_PERFCOUNTER2_SELECT",

8622
   "type_ref": "VGT_PERFCOUNTER2_SELECT"

8623
  },

8624
  {

8625
   "chips": ["gfx81"],

8626
   "map": {"at": 221756, "to": "mm"},

8627
   "name": "VGT_PERFCOUNTER3_SELECT",

8628
   "type_ref": "VGT_PERFCOUNTER2_SELECT"

8629
  },

8630
  {

8631
   "chips": ["gfx81"],

8632
   "map": {"at": 221760, "to": "mm"},

8633
   "name": "VGT_PERFCOUNTER0_SELECT1",

8634
   "type_ref": "DB_PERFCOUNTER0_SELECT1"

8635
  },

8636
  {

8637
   "chips": ["gfx81"],

8638
   "map": {"at": 221764, "to": "mm"},

8639
   "name": "VGT_PERFCOUNTER1_SELECT1",

8640
   "type_ref": "DB_PERFCOUNTER0_SELECT1"

8641
  },

8642
  {

8643
   "chips": ["gfx81"],

8644
   "map": {"at": 221776, "to": "mm"},

8645
   "name": "VGT_PERFCOUNTER_SEID_MASK",

8646
   "type_ref": "VGT_PERFCOUNTER_SEID_MASK"

8647
  },

8648
  {

8649
   "chips": ["gfx81"],

8650
   "map": {"at": 222208, "to": "mm"},

8651
   "name": "PA_SU_PERFCOUNTER0_SELECT",

8652
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"

8653
  },

8654
  {

8655
   "chips": ["gfx81"],

8656
   "map": {"at": 222212, "to": "mm"},

8657
   "name": "PA_SU_PERFCOUNTER0_SELECT1",

8658
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"

8659
  },

8660
  {

8661
   "chips": ["gfx81"],

8662
   "map": {"at": 222216, "to": "mm"},

8663
   "name": "PA_SU_PERFCOUNTER1_SELECT",

8664
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"

8665
  },

8666
  {

8667
   "chips": ["gfx81"],

8668
   "map": {"at": 222220, "to": "mm"},

8669
   "name": "PA_SU_PERFCOUNTER1_SELECT1",

8670
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"

8671
  },

8672
  {

8673
   "chips": ["gfx81"],

8674
   "map": {"at": 222224, "to": "mm"},

8675
   "name": "PA_SU_PERFCOUNTER2_SELECT",

8676
   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"

8677
  },

8678
  {

8679
   "chips": ["gfx81"],

8680
   "map": {"at": 222228, "to": "mm"},

8681
   "name": "PA_SU_PERFCOUNTER3_SELECT",

8682
   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"

8683
  },

8684
  {

8685
   "chips": ["gfx81"],

8686
   "map": {"at": 222464, "to": "mm"},

8687
   "name": "PA_SC_PERFCOUNTER0_SELECT",

8688
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"

8689
  },

8690
  {

8691
   "chips": ["gfx81"],

8692
   "map": {"at": 222468, "to": "mm"},

8693
   "name": "PA_SC_PERFCOUNTER0_SELECT1",

8694
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"

8695
  },

8696
  {

8697
   "chips": ["gfx81"],

8698
   "map": {"at": 222472, "to": "mm"},

8699
   "name": "PA_SC_PERFCOUNTER1_SELECT",

8700
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"

8701
  },

8702
  {

8703
   "chips": ["gfx81"],

8704
   "map": {"at": 222476, "to": "mm"},

8705
   "name": "PA_SC_PERFCOUNTER2_SELECT",

8706
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"

8707
  },

8708
  {

8709
   "chips": ["gfx81"],

8710
   "map": {"at": 222480, "to": "mm"},

8711
   "name": "PA_SC_PERFCOUNTER3_SELECT",

8712
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"

8713
  },

8714
  {

8715
   "chips": ["gfx81"],

8716
   "map": {"at": 222484, "to": "mm"},

8717
   "name": "PA_SC_PERFCOUNTER4_SELECT",

8718
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"

8719
  },

8720
  {

8721
   "chips": ["gfx81"],

8722
   "map": {"at": 222488, "to": "mm"},

8723
   "name": "PA_SC_PERFCOUNTER5_SELECT",

8724
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"

8725
  },

8726
  {

8727
   "chips": ["gfx81"],

8728
   "map": {"at": 222492, "to": "mm"},

8729
   "name": "PA_SC_PERFCOUNTER6_SELECT",

8730
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"

8731
  },

8732
  {

8733
   "chips": ["gfx81"],

8734
   "map": {"at": 222496, "to": "mm"},

8735
   "name": "PA_SC_PERFCOUNTER7_SELECT",

8736
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"

8737
  },

8738
  {

8739
   "chips": ["gfx81"],

8740
   "map": {"at": 222720, "to": "mm"},

8741
   "name": "SPI_PERFCOUNTER0_SELECT",

8742
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"

8743
  },

8744
  {

8745
   "chips": ["gfx81"],

8746
   "map": {"at": 222724, "to": "mm"},

8747
   "name": "SPI_PERFCOUNTER1_SELECT",

8748
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"

8749
  },

8750
  {

8751
   "chips": ["gfx81"],

8752
   "map": {"at": 222728, "to": "mm"},

8753
   "name": "SPI_PERFCOUNTER2_SELECT",

8754
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"

8755
  },

8756
  {

8757
   "chips": ["gfx81"],

8758
   "map": {"at": 222732, "to": "mm"},

8759
   "name": "SPI_PERFCOUNTER3_SELECT",

8760
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"

8761
  },

8762
  {

8763
   "chips": ["gfx81"],

8764
   "map": {"at": 222736, "to": "mm"},

8765
   "name": "SPI_PERFCOUNTER0_SELECT1",

8766
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"

8767
  },

8768
  {

8769
   "chips": ["gfx81"],

8770
   "map": {"at": 222740, "to": "mm"},

8771
   "name": "SPI_PERFCOUNTER1_SELECT1",

8772
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"

8773
  },

8774
  {

8775
   "chips": ["gfx81"],

8776
   "map": {"at": 222744, "to": "mm"},

8777
   "name": "SPI_PERFCOUNTER2_SELECT1",

8778
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"

8779
  },

8780
  {

8781
   "chips": ["gfx81"],

8782
   "map": {"at": 222748, "to": "mm"},

8783
   "name": "SPI_PERFCOUNTER3_SELECT1",

8784
   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"

8785
  },

8786
  {

8787
   "chips": ["gfx81"],

8788
   "map": {"at": 222752, "to": "mm"},

8789
   "name": "SPI_PERFCOUNTER4_SELECT",

8790
   "type_ref": "SPI_PERFCOUNTER4_SELECT"

8791
  },

8792
  {

8793
   "chips": ["gfx81"],

8794
   "map": {"at": 222756, "to": "mm"},

8795
   "name": "SPI_PERFCOUNTER5_SELECT",

8796
   "type_ref": "SPI_PERFCOUNTER4_SELECT"

8797
  },

8798
  {

8799
   "chips": ["gfx81"],

8800
   "map": {"at": 222760, "to": "mm"},

8801
   "name": "SPI_PERFCOUNTER_BINS",

8802
   "type_ref": "SPI_PERFCOUNTER_BINS"

8803
  },

8804
  {

8805
   "chips": ["gfx81"],

8806
   "map": {"at": 222976, "to": "mm"},

8807
   "name": "SQ_PERFCOUNTER0_SELECT",

8808
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8809
  },

8810
  {

8811
   "chips": ["gfx81"],

8812
   "map": {"at": 222980, "to": "mm"},

8813
   "name": "SQ_PERFCOUNTER1_SELECT",

8814
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8815
  },

8816
  {

8817
   "chips": ["gfx81"],

8818
   "map": {"at": 222984, "to": "mm"},

8819
   "name": "SQ_PERFCOUNTER2_SELECT",

8820
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8821
  },

8822
  {

8823
   "chips": ["gfx81"],

8824
   "map": {"at": 222988, "to": "mm"},

8825
   "name": "SQ_PERFCOUNTER3_SELECT",

8826
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8827
  },

8828
  {

8829
   "chips": ["gfx81"],

8830
   "map": {"at": 222992, "to": "mm"},

8831
   "name": "SQ_PERFCOUNTER4_SELECT",

8832
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8833
  },

8834
  {

8835
   "chips": ["gfx81"],

8836
   "map": {"at": 222996, "to": "mm"},

8837
   "name": "SQ_PERFCOUNTER5_SELECT",

8838
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8839
  },

8840
  {

8841
   "chips": ["gfx81"],

8842
   "map": {"at": 223000, "to": "mm"},

8843
   "name": "SQ_PERFCOUNTER6_SELECT",

8844
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8845
  },

8846
  {

8847
   "chips": ["gfx81"],

8848
   "map": {"at": 223004, "to": "mm"},

8849
   "name": "SQ_PERFCOUNTER7_SELECT",

8850
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8851
  },

8852
  {

8853
   "chips": ["gfx81"],

8854
   "map": {"at": 223008, "to": "mm"},

8855
   "name": "SQ_PERFCOUNTER8_SELECT",

8856
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8857
  },

8858
  {

8859
   "chips": ["gfx81"],

8860
   "map": {"at": 223012, "to": "mm"},

8861
   "name": "SQ_PERFCOUNTER9_SELECT",

8862
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8863
  },

8864
  {

8865
   "chips": ["gfx81"],

8866
   "map": {"at": 223016, "to": "mm"},

8867
   "name": "SQ_PERFCOUNTER10_SELECT",

8868
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8869
  },

8870
  {

8871
   "chips": ["gfx81"],

8872
   "map": {"at": 223020, "to": "mm"},

8873
   "name": "SQ_PERFCOUNTER11_SELECT",

8874
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8875
  },

8876
  {

8877
   "chips": ["gfx81"],

8878
   "map": {"at": 223024, "to": "mm"},

8879
   "name": "SQ_PERFCOUNTER12_SELECT",

8880
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8881
  },

8882
  {

8883
   "chips": ["gfx81"],

8884
   "map": {"at": 223028, "to": "mm"},

8885
   "name": "SQ_PERFCOUNTER13_SELECT",

8886
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8887
  },

8888
  {

8889
   "chips": ["gfx81"],

8890
   "map": {"at": 223032, "to": "mm"},

8891
   "name": "SQ_PERFCOUNTER14_SELECT",

8892
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8893
  },

8894
  {

8895
   "chips": ["gfx81"],

8896
   "map": {"at": 223036, "to": "mm"},

8897
   "name": "SQ_PERFCOUNTER15_SELECT",

8898
   "type_ref": "SQ_PERFCOUNTER0_SELECT"

8899
  },

8900
  {

8901
   "chips": ["gfx81"],

8902
   "map": {"at": 223104, "to": "mm"},

8903
   "name": "SQ_PERFCOUNTER_CTRL",

8904
   "type_ref": "SQ_PERFCOUNTER_CTRL"

8905
  },

8906
  {

8907
   "chips": ["gfx81"],

8908
   "map": {"at": 223108, "to": "mm"},

8909
   "name": "SQ_PERFCOUNTER_MASK",

8910
   "type_ref": "SQ_PERFCOUNTER_MASK"

8911
  },

8912
  {

8913
   "chips": ["gfx81"],

8914
   "map": {"at": 223112, "to": "mm"},

8915
   "name": "SQ_PERFCOUNTER_CTRL2",

8916
   "type_ref": "SQ_PERFCOUNTER_CTRL2"

8917
  },

8918
  {

8919
   "chips": ["gfx81"],

8920
   "map": {"at": 223488, "to": "mm"},

8921
   "name": "SX_PERFCOUNTER0_SELECT",

8922
   "type_ref": "SX_PERFCOUNTER0_SELECT"

8923
  },

8924
  {

8925
   "chips": ["gfx81"],

8926
   "map": {"at": 223492, "to": "mm"},

8927
   "name": "SX_PERFCOUNTER1_SELECT",

8928
   "type_ref": "SX_PERFCOUNTER0_SELECT"

8929
  },

8930
  {

8931
   "chips": ["gfx81"],

8932
   "map": {"at": 223496, "to": "mm"},

8933
   "name": "SX_PERFCOUNTER2_SELECT",

8934
   "type_ref": "SX_PERFCOUNTER0_SELECT"

8935
  },

8936
  {

8937
   "chips": ["gfx81"],

8938
   "map": {"at": 223500, "to": "mm"},

8939
   "name": "SX_PERFCOUNTER3_SELECT",

8940
   "type_ref": "SX_PERFCOUNTER0_SELECT"

8941
  },

8942
  {

8943
   "chips": ["gfx81"],

8944
   "map": {"at": 223504, "to": "mm"},

8945
   "name": "SX_PERFCOUNTER0_SELECT1",

8946
   "type_ref": "SX_PERFCOUNTER0_SELECT1"

8947
  },

8948
  {

8949
   "chips": ["gfx81"],

8950
   "map": {"at": 223508, "to": "mm"},

8951
   "name": "SX_PERFCOUNTER1_SELECT1",

8952
   "type_ref": "SX_PERFCOUNTER0_SELECT1"

8953
  },

8954
  {

8955
   "chips": ["gfx81"],

8956
   "map": {"at": 223744, "to": "mm"},

8957
   "name": "GDS_PERFCOUNTER0_SELECT",

8958
   "type_ref": "SX_PERFCOUNTER0_SELECT"

8959
  },

8960
  {

8961
   "chips": ["gfx81"],

8962
   "map": {"at": 223748, "to": "mm"},

8963
   "name": "GDS_PERFCOUNTER1_SELECT",

8964
   "type_ref": "SX_PERFCOUNTER0_SELECT"

8965
  },

8966
  {

8967
   "chips": ["gfx81"],

8968
   "map": {"at": 223752, "to": "mm"},

8969
   "name": "GDS_PERFCOUNTER2_SELECT",

8970
   "type_ref": "SX_PERFCOUNTER0_SELECT"

8971
  },

8972
  {

8973
   "chips": ["gfx81"],

8974
   "map": {"at": 223756, "to": "mm"},

8975
   "name": "GDS_PERFCOUNTER3_SELECT",

8976
   "type_ref": "SX_PERFCOUNTER0_SELECT"

8977
  },

8978
  {

8979
   "chips": ["gfx81"],

8980
   "map": {"at": 223760, "to": "mm"},

8981
   "name": "GDS_PERFCOUNTER0_SELECT1",

8982
   "type_ref": "SX_PERFCOUNTER0_SELECT1"

8983
  },

8984
  {

8985
   "chips": ["gfx81"],

8986
   "map": {"at": 224000, "to": "mm"},

8987
   "name": "TA_PERFCOUNTER0_SELECT",

8988
   "type_ref": "TD_PERFCOUNTER0_SELECT"

8989
  },

8990
  {

8991
   "chips": ["gfx81"],

8992
   "map": {"at": 224004, "to": "mm"},

8993
   "name": "TA_PERFCOUNTER0_SELECT1",

8994
   "type_ref": "TD_PERFCOUNTER0_SELECT1"

8995
  },

8996
  {

8997
   "chips": ["gfx81"],

8998
   "map": {"at": 224008, "to": "mm"},

8999
   "name": "TA_PERFCOUNTER1_SELECT",

9000
   "type_ref": "TD_PERFCOUNTER0_SELECT"

9001
  },

9002
  {

9003
   "chips": ["gfx81"],

9004
   "map": {"at": 224256, "to": "mm"},

9005
   "name": "TD_PERFCOUNTER0_SELECT",

9006
   "type_ref": "TD_PERFCOUNTER0_SELECT"

9007
  },

9008
  {

9009
   "chips": ["gfx81"],

9010
   "map": {"at": 224260, "to": "mm"},

9011
   "name": "TD_PERFCOUNTER0_SELECT1",

9012
   "type_ref": "TD_PERFCOUNTER0_SELECT1"

9013
  },

9014
  {

9015
   "chips": ["gfx81"],

9016
   "map": {"at": 224264, "to": "mm"},

9017
   "name": "TD_PERFCOUNTER1_SELECT",

9018
   "type_ref": "TD_PERFCOUNTER0_SELECT"

9019
  },

9020
  {

9021
   "chips": ["gfx81"],

9022
   "map": {"at": 224512, "to": "mm"},

9023
   "name": "TCP_PERFCOUNTER0_SELECT",

9024
   "type_ref": "DB_PERFCOUNTER0_SELECT"

9025
  },

9026
  {

9027
   "chips": ["gfx81"],

9028
   "map": {"at": 224516, "to": "mm"},

9029
   "name": "TCP_PERFCOUNTER0_SELECT1",

9030
   "type_ref": "DB_PERFCOUNTER0_SELECT1"

9031
  },

9032
  {

9033
   "chips": ["gfx81"],

9034
   "map": {"at": 224520, "to": "mm"},

9035
   "name": "TCP_PERFCOUNTER1_SELECT",

9036
   "type_ref": "DB_PERFCOUNTER0_SELECT"

9037
  },

9038
  {

9039
   "chips": ["gfx81"],

9040
   "map": {"at": 224524, "to": "mm"},

9041
   "name": "TCP_PERFCOUNTER1_SELECT1",

9042
   "type_ref": "DB_PERFCOUNTER0_SELECT1"

9043
  },

9044
  {

9045
   "chips": ["gfx81"],

9046
   "map": {"at": 224528, "to": "mm"},

9047
   "name": "TCP_PERFCOUNTER2_SELECT",

9048
   "type_ref": "TCC_PERFCOUNTER2_SELECT"

9049
  },

9050
  {

9051
   "chips": ["gfx81"],

9052
   "map": {"at": 224532, "to": "mm"},

9053
   "name": "TCP_PERFCOUNTER3_SELECT",

9054
   "type_ref": "TCC_PERFCOUNTER2_SELECT"

9055
  },

9056
  {

9057
   "chips": ["gfx81"],

9058
   "map": {"at": 224768, "to": "mm"},

9059
   "name": "TCC_PERFCOUNTER0_SELECT",

9060
   "type_ref": "DB_PERFCOUNTER0_SELECT"

9061
  },

9062
  {

9063
   "chips": ["gfx81"],

9064
   "map": {"at": 224772, "to": "mm"},

9065
   "name": "TCC_PERFCOUNTER0_SELECT1",

9066
   "type_ref": "TCC_PERFCOUNTER0_SELECT1"

9067
  },

9068
  {

9069
   "chips": ["gfx81"],

9070
   "map": {"at": 224776, "to": "mm"},

9071
   "name": "TCC_PERFCOUNTER1_SELECT",

9072
   "type_ref": "DB_PERFCOUNTER0_SELECT"

9073
  },

9074
  {

9075
   "chips": ["gfx81"],

9076
   "map": {"at": 224780, "to": "mm"},

9077
   "name": "TCC_PERFCOUNTER1_SELECT1",

9078
   "type_ref": "TCC_PERFCOUNTER0_SELECT1"

9079
  },

9080
  {

9081
   "chips": ["gfx81"],

9082
   "map": {"at": 224784, "to": "mm"},

9083
   "name": "TCC_PERFCOUNTER2_SELECT",

9084
   "type_ref": "TCC_PERFCOUNTER2_SELECT"

9085
  },

9086
  {

9087
   "chips": ["gfx81"],

9088
   "map": {"at": 224788, "to": "mm"},

9089
   "name": "TCC_PERFCOUNTER3_SELECT",

9090
   "type_ref": "TCC_PERFCOUNTER2_SELECT"

9091
  },

9092
  {

9093
   "chips": ["gfx81"],

9094
   "map": {"at": 224832, "to": "mm"},

9095
   "name": "TCA_PERFCOUNTER0_SELECT",

9096
   "type_ref": "DB_PERFCOUNTER0_SELECT"

9097
  },

9098
  {

9099
   "chips": ["gfx81"],

9100
   "map": {"at": 224836, "to": "mm"},

9101
   "name": "TCA_PERFCOUNTER0_SELECT1",

9102
   "type_ref": "TCC_PERFCOUNTER0_SELECT1"

9103
  },

9104
  {

9105
   "chips": ["gfx81"],

9106
   "map": {"at": 224840, "to": "mm"},

9107
   "name": "TCA_PERFCOUNTER1_SELECT",

9108
   "type_ref": "DB_PERFCOUNTER0_SELECT"

9109
  },

9110
  {

9111
   "chips": ["gfx81"],

9112
   "map": {"at": 224844, "to": "mm"},

9113
   "name": "TCA_PERFCOUNTER1_SELECT1",

9114
   "type_ref": "TCC_PERFCOUNTER0_SELECT1"

9115
  },

9116
  {

9117
   "chips": ["gfx81"],

9118
   "map": {"at": 224848, "to": "mm"},

9119
   "name": "TCA_PERFCOUNTER2_SELECT",

9120
   "type_ref": "TCC_PERFCOUNTER2_SELECT"

9121
  },

9122
  {

9123
   "chips": ["gfx81"],

9124
   "map": {"at": 224852, "to": "mm"},

9125
   "name": "TCA_PERFCOUNTER3_SELECT",

9126
   "type_ref": "TCC_PERFCOUNTER2_SELECT"

9127
  },

9128
  {

9129
   "chips": ["gfx81"],

9130
   "map": {"at": 225280, "to": "mm"},

9131
   "name": "CB_PERFCOUNTER_FILTER",

9132
   "type_ref": "CB_PERFCOUNTER_FILTER"

9133
  },

9134
  {

9135
   "chips": ["gfx81"],

9136
   "map": {"at": 225284, "to": "mm"},

9137
   "name": "CB_PERFCOUNTER0_SELECT",

9138
   "type_ref": "CB_PERFCOUNTER0_SELECT"

9139
  },

9140
  {

9141
   "chips": ["gfx81"],

9142
   "map": {"at": 225288, "to": "mm"},

9143
   "name": "CB_PERFCOUNTER0_SELECT1",

9144
   "type_ref": "CB_PERFCOUNTER0_SELECT1"

9145
  },

9146
  {

9147
   "chips": ["gfx81"],

9148
   "map": {"at": 225292, "to": "mm"},

9149
   "name": "CB_PERFCOUNTER1_SELECT",

9150
   "type_ref": "CB_PERFCOUNTER1_SELECT"

9151
  },

9152
  {

9153
   "chips": ["gfx81"],

9154
   "map": {"at": 225296, "to": "mm"},

9155
   "name": "CB_PERFCOUNTER2_SELECT",

9156
   "type_ref": "CB_PERFCOUNTER1_SELECT"

9157
  },

9158
  {

9159
   "chips": ["gfx81"],

9160
   "map": {"at": 225300, "to": "mm"},

9161
   "name": "CB_PERFCOUNTER3_SELECT",

9162
   "type_ref": "CB_PERFCOUNTER1_SELECT"

9163
  },

9164
  {

9165
   "chips": ["gfx81"],

9166
   "map": {"at": 225536, "to": "mm"},

9167
   "name": "DB_PERFCOUNTER0_SELECT",

9168
   "type_ref": "DB_PERFCOUNTER0_SELECT"

9169
  },

9170
  {

9171
   "chips": ["gfx81"],

9172
   "map": {"at": 225540, "to": "mm"},

9173
   "name": "DB_PERFCOUNTER0_SELECT1",

9174
   "type_ref": "DB_PERFCOUNTER0_SELECT1"

9175
  },

9176
  {

9177
   "chips": ["gfx81"],

9178
   "map": {"at": 225544, "to": "mm"},

9179
   "name": "DB_PERFCOUNTER1_SELECT",

9180
   "type_ref": "DB_PERFCOUNTER0_SELECT"

9181
  },

9182
  {

9183
   "chips": ["gfx81"],

9184
   "map": {"at": 225548, "to": "mm"},

9185
   "name": "DB_PERFCOUNTER1_SELECT1",

9186
   "type_ref": "DB_PERFCOUNTER0_SELECT1"

9187
  },

9188
  {

9189
   "chips": ["gfx81"],

9190
   "map": {"at": 225552, "to": "mm"},

9191
   "name": "DB_PERFCOUNTER2_SELECT",

9192
   "type_ref": "DB_PERFCOUNTER0_SELECT"

9193
  },

9194
  {

9195
   "chips": ["gfx81"],

9196
   "map": {"at": 225560, "to": "mm"},

9197
   "name": "DB_PERFCOUNTER3_SELECT",

9198
   "type_ref": "DB_PERFCOUNTER0_SELECT"

9199
  },

9200
  {

9201
   "chips": ["gfx81"],

9202
   "map": {"at": 225792, "to": "mm"},

9203
   "name": "RLC_SPM_PERFMON_CNTL",

9204
   "type_ref": "RLC_SPM_PERFMON_CNTL"

9205
  },

9206
  {

9207
   "chips": ["gfx81"],

9208
   "map": {"at": 225796, "to": "mm"},

9209
   "name": "RLC_SPM_PERFMON_RING_BASE_LO"

9210
  },

9211
  {

9212
   "chips": ["gfx81"],

9213
   "map": {"at": 225800, "to": "mm"},

9214
   "name": "RLC_SPM_PERFMON_RING_BASE_HI",

9215
   "type_ref": "RLC_SPM_PERFMON_RING_BASE_HI"

9216
  },

9217
  {

9218
   "chips": ["gfx81"],

9219
   "map": {"at": 225804, "to": "mm"},

9220
   "name": "RLC_SPM_PERFMON_RING_SIZE"

9221
  },

9222
  {

9223
   "chips": ["gfx81"],

9224
   "map": {"at": 225808, "to": "mm"},

9225
   "name": "RLC_SPM_PERFMON_SEGMENT_SIZE",

9226
   "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"

9227
  },

9228
  {

9229
   "chips": ["gfx81"],

9230
   "map": {"at": 225812, "to": "mm"},

9231
   "name": "RLC_SPM_SE_MUXSEL_ADDR"

9232
  },

9233
  {

9234
   "chips": ["gfx81"],

9235
   "map": {"at": 225816, "to": "mm"},

9236
   "name": "RLC_SPM_SE_MUXSEL_DATA"

9237
  },

9238
  {

9239
   "chips": ["gfx81"],

9240
   "map": {"at": 225820, "to": "mm"},

9241
   "name": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY",

9242
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9243
  },

9244
  {

9245
   "chips": ["gfx81"],

9246
   "map": {"at": 225824, "to": "mm"},

9247
   "name": "RLC_SPM_CPC_PERFMON_SAMPLE_DELAY",

9248
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9249
  },

9250
  {

9251
   "chips": ["gfx81"],

9252
   "map": {"at": 225828, "to": "mm"},

9253
   "name": "RLC_SPM_CPF_PERFMON_SAMPLE_DELAY",

9254
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9255
  },

9256
  {

9257
   "chips": ["gfx81"],

9258
   "map": {"at": 225832, "to": "mm"},

9259
   "name": "RLC_SPM_CB_PERFMON_SAMPLE_DELAY",

9260
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9261
  },

9262
  {

9263
   "chips": ["gfx81"],

9264
   "map": {"at": 225836, "to": "mm"},

9265
   "name": "RLC_SPM_DB_PERFMON_SAMPLE_DELAY",

9266
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9267
  },

9268
  {

9269
   "chips": ["gfx81"],

9270
   "map": {"at": 225840, "to": "mm"},

9271
   "name": "RLC_SPM_PA_PERFMON_SAMPLE_DELAY",

9272
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9273
  },

9274
  {

9275
   "chips": ["gfx81"],

9276
   "map": {"at": 225844, "to": "mm"},

9277
   "name": "RLC_SPM_GDS_PERFMON_SAMPLE_DELAY",

9278
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9279
  },

9280
  {

9281
   "chips": ["gfx81"],

9282
   "map": {"at": 225848, "to": "mm"},

9283
   "name": "RLC_SPM_IA_PERFMON_SAMPLE_DELAY",

9284
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9285
  },

9286
  {

9287
   "chips": ["gfx81"],

9288
   "map": {"at": 225856, "to": "mm"},

9289
   "name": "RLC_SPM_SC_PERFMON_SAMPLE_DELAY",

9290
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9291
  },

9292
  {

9293
   "chips": ["gfx81"],

9294
   "map": {"at": 225860, "to": "mm"},

9295
   "name": "RLC_SPM_TCC_PERFMON_SAMPLE_DELAY",

9296
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9297
  },

9298
  {

9299
   "chips": ["gfx81"],

9300
   "map": {"at": 225864, "to": "mm"},

9301
   "name": "RLC_SPM_TCA_PERFMON_SAMPLE_DELAY",

9302
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9303
  },

9304
  {

9305
   "chips": ["gfx81"],

9306
   "map": {"at": 225868, "to": "mm"},

9307
   "name": "RLC_SPM_TCP_PERFMON_SAMPLE_DELAY",

9308
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9309
  },

9310
  {

9311
   "chips": ["gfx81"],

9312
   "map": {"at": 225872, "to": "mm"},

9313
   "name": "RLC_SPM_TA_PERFMON_SAMPLE_DELAY",

9314
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9315
  },

9316
  {

9317
   "chips": ["gfx81"],

9318
   "map": {"at": 225876, "to": "mm"},

9319
   "name": "RLC_SPM_TD_PERFMON_SAMPLE_DELAY",

9320
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9321
  },

9322
  {

9323
   "chips": ["gfx81"],

9324
   "map": {"at": 225880, "to": "mm"},

9325
   "name": "RLC_SPM_VGT_PERFMON_SAMPLE_DELAY",

9326
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9327
  },

9328
  {

9329
   "chips": ["gfx81"],

9330
   "map": {"at": 225884, "to": "mm"},

9331
   "name": "RLC_SPM_SPI_PERFMON_SAMPLE_DELAY",

9332
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9333
  },

9334
  {

9335
   "chips": ["gfx81"],

9336
   "map": {"at": 225888, "to": "mm"},

9337
   "name": "RLC_SPM_SQG_PERFMON_SAMPLE_DELAY",

9338
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9339
  },

9340
  {

9341
   "chips": ["gfx81"],

9342
   "map": {"at": 225896, "to": "mm"},

9343
   "name": "RLC_SPM_SX_PERFMON_SAMPLE_DELAY",

9344
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"

9345
  },

9346
  {

9347
   "chips": ["gfx81"],

9348
   "map": {"at": 225900, "to": "mm"},

9349
   "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR"

9350
  },

9351
  {

9352
   "chips": ["gfx81"],

9353
   "map": {"at": 225904, "to": "mm"},

9354
   "name": "RLC_SPM_GLOBAL_MUXSEL_DATA"

9355
  },

9356
  {

9357
   "chips": ["gfx81"],

9358
   "map": {"at": 225908, "to": "mm"},

9359
   "name": "RLC_SPM_RING_RDPTR"

9360
  },

9361
  {

9362
   "chips": ["gfx81"],

9363
   "map": {"at": 225912, "to": "mm"},

9364
   "name": "RLC_SPM_SEGMENT_THRESHOLD"

9365
  },

9366
  {

9367
   "chips": ["gfx81"],

9368
   "map": {"at": 226044, "to": "mm"},

9369
   "name": "RLC_PERFMON_CLK_CNTL",

9370
   "type_ref": "RLC_PERFMON_CLK_CNTL"

9371
  },

9372
  {

9373
   "chips": ["gfx81"],

9374
   "map": {"at": 226048, "to": "mm"},

9375
   "name": "RLC_PERFMON_CNTL",

9376
   "type_ref": "RLC_PERFMON_CNTL"

9377
  },

9378
  {

9379
   "chips": ["gfx81"],

9380
   "map": {"at": 226052, "to": "mm"},

9381
   "name": "RLC_PERFCOUNTER0_SELECT",

9382
   "type_ref": "RLC_PERFCOUNTER0_SELECT"

9383
  },

9384
  {

9385
   "chips": ["gfx81"],

9386
   "map": {"at": 226056, "to": "mm"},

9387
   "name": "RLC_PERFCOUNTER1_SELECT",

9388
   "type_ref": "RLC_PERFCOUNTER0_SELECT"

9389
  }

9390
 ],

9391
 "register_types": {

9392
  "CB_BLEND0_CONTROL": {

9393
   "fields": [

9394
    {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},

9395
    {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},

9396
    {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},

9397
    {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},

9398
    {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},

9399
    {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},

9400
    {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},

9401
    {"bits": [30, 30], "name": "ENABLE"},

9402
    {"bits": [31, 31], "name": "DISABLE_ROP3"}

9403
   ]

9404
  },

9405
  "CB_COLOR0_ATTRIB": {

9406
   "fields": [

9407
    {"bits": [0, 4], "name": "TILE_MODE_INDEX"},

9408
    {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},

9409
    {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},

9410
    {"bits": [12, 14], "name": "NUM_SAMPLES"},

9411
    {"bits": [15, 16], "name": "NUM_FRAGMENTS"},

9412
    {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"}

9413
   ]

9414
  },

9415
  "CB_COLOR0_CMASK_SLICE": {

9416
   "fields": [

9417
    {"bits": [0, 13], "name": "TILE_MAX"}

9418
   ]

9419
  },

9420
  "CB_COLOR0_DCC_CONTROL": {

9421
   "fields": [

9422
    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},

9423
    {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"},

9424
    {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},

9425
    {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},

9426
    {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},

9427
    {"bits": [7, 8], "name": "COLOR_TRANSFORM"},

9428
    {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},

9429
    {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"},

9430
    {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"}

9431
   ]

9432
  },

9433
  "CB_COLOR0_INFO": {

9434
   "fields": [

9435
    {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},

9436
    {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},

9437
    {"bits": [7, 7], "name": "LINEAR_GENERAL"},

9438
    {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},

9439
    {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},

9440
    {"bits": [13, 13], "name": "FAST_CLEAR"},

9441
    {"bits": [14, 14], "name": "COMPRESSION"},

9442
    {"bits": [15, 15], "name": "BLEND_CLAMP"},

9443
    {"bits": [16, 16], "name": "BLEND_BYPASS"},

9444
    {"bits": [17, 17], "name": "SIMPLE_FLOAT"},

9445
    {"bits": [18, 18], "name": "ROUND_MODE"},

9446
    {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},

9447
    {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},

9448
    {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},

9449
    {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"},

9450
    {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"},

9451
    {"bits": [28, 28], "name": "DCC_ENABLE"},

9452
    {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"}

9453
   ]

9454
  },

9455
  "CB_COLOR0_PITCH": {

9456
   "fields": [

9457
    {"bits": [0, 10], "name": "TILE_MAX"},

9458
    {"bits": [20, 30], "name": "FMASK_TILE_MAX"}

9459
   ]

9460
  },

9461
  "CB_COLOR0_SLICE": {

9462
   "fields": [

9463
    {"bits": [0, 21], "name": "TILE_MAX"}

9464
   ]

9465
  },

9466
  "CB_COLOR0_VIEW": {

9467
   "fields": [

9468
    {"bits": [0, 10], "name": "SLICE_START"},

9469
    {"bits": [13, 23], "name": "SLICE_MAX"}

9470
   ]

9471
  },

9472
  "CB_COLOR_CONTROL": {

9473
   "fields": [

9474
    {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},

9475
    {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},

9476
    {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},

9477
    {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}

9478
   ]

9479
  },

9480
  "CB_DCC_CONTROL": {

9481
   "fields": [

9482
    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},

9483
    {"bits": [1, 1], "name": "OVERWRITE_COMBINER_MRT_SHARING_DISABLE"},

9484
    {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"}

9485
   ]

9486
  },

9487
  "CB_PERFCOUNTER0_SELECT": {

9488
   "fields": [

9489
    {"bits": [0, 8], "name": "PERF_SEL"},

9490
    {"bits": [10, 18], "name": "PERF_SEL1"},

9491
    {"bits": [20, 23], "name": "CNTR_MODE"},

9492
    {"bits": [24, 27], "name": "PERF_MODE1"},

9493
    {"bits": [28, 31], "name": "PERF_MODE"}

9494
   ]

9495
  },

9496
  "CB_PERFCOUNTER0_SELECT1": {

9497
   "fields": [

9498
    {"bits": [0, 8], "name": "PERF_SEL2"},

9499
    {"bits": [10, 18], "name": "PERF_SEL3"},

9500
    {"bits": [24, 27], "name": "PERF_MODE3"},

9501
    {"bits": [28, 31], "name": "PERF_MODE2"}

9502
   ]

9503
  },

9504
  "CB_PERFCOUNTER1_SELECT": {

9505
   "fields": [

9506
    {"bits": [0, 8], "name": "PERF_SEL"},

9507
    {"bits": [28, 31], "name": "PERF_MODE"}

9508
   ]

9509
  },

9510
  "CB_PERFCOUNTER_FILTER": {

9511
   "fields": [

9512
    {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},

9513
    {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},

9514
    {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},

9515
    {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},

9516
    {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},

9517
    {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},

9518
    {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},

9519
    {"bits": [13, 15], "name": "MRT_FILTER_SEL"},

9520
    {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},

9521
    {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},

9522
    {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},

9523
    {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}

9524
   ]

9525
  },

9526
  "CB_SHADER_MASK": {

9527
   "fields": [

9528
    {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},

9529
    {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},

9530
    {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},

9531
    {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},

9532
    {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},

9533
    {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},

9534
    {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},

9535
    {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}

9536
   ]

9537
  },

9538
  "CB_TARGET_MASK": {

9539
   "fields": [

9540
    {"bits": [0, 3], "name": "TARGET0_ENABLE"},

9541
    {"bits": [4, 7], "name": "TARGET1_ENABLE"},

9542
    {"bits": [8, 11], "name": "TARGET2_ENABLE"},

9543
    {"bits": [12, 15], "name": "TARGET3_ENABLE"},

9544
    {"bits": [16, 19], "name": "TARGET4_ENABLE"},

9545
    {"bits": [20, 23], "name": "TARGET5_ENABLE"},

9546
    {"bits": [24, 27], "name": "TARGET6_ENABLE"},

9547
    {"bits": [28, 31], "name": "TARGET7_ENABLE"}

9548
   ]

9549
  },

9550
  "COMPUTE_DISPATCH_INITIATOR": {

9551
   "fields": [

9552
    {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},

9553
    {"bits": [1, 1], "name": "PARTIAL_TG_EN"},

9554
    {"bits": [2, 2], "name": "FORCE_START_AT_000"},

9555
    {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},

9556
    {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},

9557
    {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},

9558
    {"bits": [6, 6], "name": "ORDER_MODE"},

9559
    {"bits": [7, 9], "name": "DISPATCH_CACHE_CNTL"},

9560
    {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},

9561
    {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},

9562
    {"bits": [12, 12], "name": "DATA_ATC"},

9563
    {"bits": [14, 14], "name": "RESTORE"}

9564
   ]

9565
  },

9566
  "COMPUTE_MISC_RESERVED": {

9567
   "fields": [

9568
    {"bits": [0, 1], "name": "SEND_SEID"},

9569
    {"bits": [2, 2], "name": "RESERVED2"},

9570
    {"bits": [3, 3], "name": "RESERVED3"},

9571
    {"bits": [4, 4], "name": "RESERVED4"},

9572
    {"bits": [5, 16], "name": "WAVE_ID_BASE"}

9573
   ]

9574
  },

9575
  "COMPUTE_NUM_THREAD_X": {

9576
   "fields": [

9577
    {"bits": [0, 15], "name": "NUM_THREAD_FULL"},

9578
    {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}

9579
   ]

9580
  },

9581
  "COMPUTE_PERFCOUNT_ENABLE": {

9582
   "fields": [

9583
    {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}

9584
   ]

9585
  },

9586
  "COMPUTE_PGM_HI": {

9587
   "fields": [

9588
    {"bits": [0, 7], "name": "DATA"},

9589
    {"bits": [8, 8], "name": "INST_ATC"}

9590
   ]

9591
  },

9592
  "COMPUTE_PGM_RSRC1": {

9593
   "fields": [

9594
    {"bits": [0, 5], "name": "VGPRS"},

9595
    {"bits": [6, 9], "name": "SGPRS"},

9596
    {"bits": [10, 11], "name": "PRIORITY"},

9597
    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},

9598
    {"bits": [20, 20], "name": "PRIV"},

9599
    {"bits": [21, 21], "name": "DX10_CLAMP"},

9600
    {"bits": [22, 22], "name": "DEBUG_MODE"},

9601
    {"bits": [23, 23], "name": "IEEE_MODE"},

9602
    {"bits": [24, 24], "name": "BULKY"},

9603
    {"bits": [25, 25], "name": "CDBG_USER"}

9604
   ]

9605
  },

9606
  "COMPUTE_PGM_RSRC2": {

9607
   "fields": [

9608
    {"bits": [0, 0], "name": "SCRATCH_EN"},

9609
    {"bits": [1, 5], "name": "USER_SGPR"},

9610
    {"bits": [6, 6], "name": "TRAP_PRESENT"},

9611
    {"bits": [7, 7], "name": "TGID_X_EN"},

9612
    {"bits": [8, 8], "name": "TGID_Y_EN"},

9613
    {"bits": [9, 9], "name": "TGID_Z_EN"},

9614
    {"bits": [10, 10], "name": "TG_SIZE_EN"},

9615
    {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},

9616
    {"bits": [13, 14], "name": "EXCP_EN_MSB"},

9617
    {"bits": [15, 23], "name": "LDS_SIZE"},

9618
    {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}

9619
   ]

9620
  },

9621
  "COMPUTE_PIPELINESTAT_ENABLE": {

9622
   "fields": [

9623
    {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}

9624
   ]

9625
  },

9626
  "COMPUTE_RELAUNCH": {

9627
   "fields": [

9628
    {"bits": [0, 29], "name": "PAYLOAD"},

9629
    {"bits": [30, 30], "name": "IS_EVENT"},

9630
    {"bits": [31, 31], "name": "IS_STATE"}

9631
   ]

9632
  },

9633
  "COMPUTE_RESOURCE_LIMITS": {

9634
   "fields": [

9635
    {"bits": [0, 9], "name": "WAVES_PER_SH"},

9636
    {"bits": [12, 15], "name": "TG_PER_CU"},

9637
    {"bits": [16, 21], "name": "LOCK_THRESHOLD"},

9638
    {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},

9639
    {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},

9640
    {"bits": [24, 26], "name": "CU_GROUP_COUNT"}

9641
   ]

9642
  },

9643
  "COMPUTE_STATIC_THREAD_MGMT_SE0": {

9644
   "fields": [

9645
    {"bits": [0, 15], "name": "SH0_CU_EN"},

9646
    {"bits": [16, 31], "name": "SH1_CU_EN"}

9647
   ]

9648
  },

9649
  "COMPUTE_TBA_HI": {

9650
   "fields": [

9651
    {"bits": [0, 7], "name": "DATA"}

9652
   ]

9653
  },

9654
  "COMPUTE_THREAD_TRACE_ENABLE": {

9655
   "fields": [

9656
    {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}

9657
   ]

9658
  },

9659
  "COMPUTE_TMPRING_SIZE": {

9660
   "fields": [

9661
    {"bits": [0, 11], "name": "WAVES"},

9662
    {"bits": [12, 24], "name": "WAVESIZE"}

9663
   ]

9664
  },

9665
  "COMPUTE_VMID": {

9666
   "fields": [

9667
    {"bits": [0, 3], "name": "DATA"}

9668
   ]

9669
  },

9670
  "COMPUTE_WAVE_RESTORE_ADDR_HI": {

9671
   "fields": [

9672
    {"bits": [0, 15], "name": "ADDR"}

9673
   ]

9674
  },

9675
  "COMPUTE_WAVE_RESTORE_CONTROL": {

9676
   "fields": [

9677
    {"bits": [0, 0], "name": "ATC"},

9678
    {"bits": [1, 2], "name": "MTYPE"}

9679
   ]

9680
  },

9681
  "CPG_PERFCOUNTER0_SELECT": {

9682
   "fields": [

9683
    {"bits": [0, 5], "name": "PERF_SEL"},

9684
    {"bits": [10, 15], "name": "PERF_SEL1"},

9685
    {"bits": [20, 23], "name": "CNTR_MODE"}

9686
   ]

9687
  },

9688
  "CPG_PERFCOUNTER0_SELECT1": {

9689
   "fields": [

9690
    {"bits": [0, 5], "name": "PERF_SEL2"},

9691
    {"bits": [10, 15], "name": "PERF_SEL3"}

9692
   ]

9693
  },

9694
  "CPG_PERFCOUNTER1_SELECT": {

9695
   "fields": [

9696
    {"bits": [0, 5], "name": "PERF_SEL"}

9697
   ]

9698
  },

9699
  "CP_APPEND_ADDR_HI": {

9700
   "fields": [

9701
    {"bits": [0, 15], "name": "MEM_ADDR_HI"},

9702
    {"bits": [16, 16], "name": "CS_PS_SEL"},

9703
    {"bits": [25, 25], "name": "CACHE_POLICY"},

9704
    {"bits": [27, 28], "name": "MTYPE"},

9705
    {"bits": [29, 31], "name": "COMMAND"}

9706
   ]

9707
  },

9708
  "CP_APPEND_ADDR_LO": {

9709
   "fields": [

9710
    {"bits": [2, 31], "name": "MEM_ADDR_LO"}

9711
   ]

9712
  },

9713
  "CP_CE_IB1_BASE_HI": {

9714
   "fields": [

9715
    {"bits": [0, 15], "name": "IB1_BASE_HI"}

9716
   ]

9717
  },

9718
  "CP_CE_IB1_BASE_LO": {

9719
   "fields": [

9720
    {"bits": [2, 31], "name": "IB1_BASE_LO"}

9721
   ]

9722
  },

9723
  "CP_CE_IB1_BUFSZ": {

9724
   "fields": [

9725
    {"bits": [0, 19], "name": "IB1_BUFSZ"}

9726
   ]

9727
  },

9728
  "CP_CE_IB2_BASE_HI": {

9729
   "fields": [

9730
    {"bits": [0, 15], "name": "IB2_BASE_HI"}

9731
   ]

9732
  },

9733
  "CP_CE_IB2_BASE_LO": {

9734
   "fields": [

9735
    {"bits": [2, 31], "name": "IB2_BASE_LO"}

9736
   ]

9737
  },

9738
  "CP_CE_IB2_BUFSZ": {

9739
   "fields": [

9740
    {"bits": [0, 19], "name": "IB2_BUFSZ"}

9741
   ]

9742
  },

9743
  "CP_CE_INIT_BASE_HI": {

9744
   "fields": [

9745
    {"bits": [0, 15], "name": "INIT_BASE_HI"}

9746
   ]

9747
  },

9748
  "CP_CE_INIT_BASE_LO": {

9749
   "fields": [

9750
    {"bits": [5, 31], "name": "INIT_BASE_LO"}

9751
   ]

9752
  },

9753
  "CP_CE_INIT_BUFSZ": {

9754
   "fields": [

9755
    {"bits": [0, 11], "name": "INIT_BUFSZ"}

9756
   ]

9757
  },

9758
  "CP_COHER_BASE_HI": {

9759
   "fields": [

9760
    {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}

9761
   ]

9762
  },

9763
  "CP_COHER_CNTL": {

9764
   "fields": [

9765
    {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},

9766
    {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},

9767
    {"bits": [2, 2], "name": "TC_SD_ACTION_ENA"},

9768
    {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"},

9769
    {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},

9770
    {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},

9771
    {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},

9772
    {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},

9773
    {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},

9774
    {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},

9775
    {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},

9776
    {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},

9777
    {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},

9778
    {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},

9779
    {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},

9780
    {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},

9781
    {"bits": [21, 21], "name": "DEST_BASE_3_ENA"},

9782
    {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},

9783
    {"bits": [23, 23], "name": "TC_ACTION_ENA"},

9784
    {"bits": [25, 25], "name": "CB_ACTION_ENA"},

9785
    {"bits": [26, 26], "name": "DB_ACTION_ENA"},

9786
    {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},

9787
    {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},

9788
    {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"},

9789
    {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"},

9790
    {"bits": [31, 31], "name": "SH_SD_ACTION_ENA"}

9791
   ]

9792
  },

9793
  "CP_COHER_SIZE_HI": {

9794
   "fields": [

9795
    {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}

9796
   ]

9797
  },

9798
  "CP_COHER_START_DELAY": {

9799
   "fields": [

9800
    {"bits": [0, 5], "name": "START_DELAY_COUNT"}

9801
   ]

9802
  },

9803
  "CP_COHER_STATUS": {

9804
   "fields": [

9805
    {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},

9806
    {"bits": [24, 25], "name": "MEID"},

9807
    {"bits": [30, 30], "name": "PHASE1_STATUS"},

9808
    {"bits": [31, 31], "name": "STATUS"}

9809
   ]

9810
  },

9811
  "CP_CPC_BUSY_STAT": {

9812
   "fields": [

9813
    {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},

9814
    {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"},

9815
    {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},

9816
    {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},

9817
    {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},

9818
    {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},

9819
    {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},

9820
    {"bits": [7, 7], "name": "MEC1_TC_BUSY"},

9821
    {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},

9822
    {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},

9823
    {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},

9824
    {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},

9825
    {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},

9826
    {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},

9827
    {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},

9828
    {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"},

9829
    {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},

9830
    {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},

9831
    {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},

9832
    {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},

9833
    {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},

9834
    {"bits": [23, 23], "name": "MEC2_TC_BUSY"},

9835
    {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},

9836
    {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},

9837
    {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},

9838
    {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},

9839
    {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},

9840
    {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}

9841
   ]

9842
  },

9843
  "CP_CPC_GRBM_FREE_COUNT": {

9844
   "fields": [

9845
    {"bits": [0, 5], "name": "FREE_COUNT"}

9846
   ]

9847
  },

9848
  "CP_CPC_HALT_HYST_COUNT": {

9849
   "fields": [

9850
    {"bits": [0, 3], "name": "COUNT"}

9851
   ]

9852
  },

9853
  "CP_CPC_SCRATCH_INDEX": {

9854
   "fields": [

9855
    {"bits": [0, 8], "name": "SCRATCH_INDEX"}

9856
   ]

9857
  },

9858
  "CP_CPC_STALLED_STAT1": {

9859
   "fields": [

9860
    {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},

9861
    {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},

9862
    {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},

9863
    {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},

9864
    {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},

9865
    {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},

9866
    {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},

9867
    {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},

9868
    {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},

9869
    {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},

9870
    {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},

9871
    {"bits": [22, 22], "name": "ATCL2IU_WAITING_ON_FREE"},

9872
    {"bits": [23, 23], "name": "ATCL2IU_WAITING_ON_TAGS"},

9873
    {"bits": [24, 24], "name": "ATCL1_WAITING_ON_TRANS"}

9874
   ]

9875
  },

9876
  "CP_CPC_STATUS": {

9877
   "fields": [

9878
    {"bits": [0, 0], "name": "MEC1_BUSY"},

9879
    {"bits": [1, 1], "name": "MEC2_BUSY"},

9880
    {"bits": [2, 2], "name": "DC0_BUSY"},

9881
    {"bits": [3, 3], "name": "DC1_BUSY"},

9882
    {"bits": [4, 4], "name": "RCIU1_BUSY"},

9883
    {"bits": [5, 5], "name": "RCIU2_BUSY"},

9884
    {"bits": [6, 6], "name": "ROQ1_BUSY"},

9885
    {"bits": [7, 7], "name": "ROQ2_BUSY"},

9886
    {"bits": [10, 10], "name": "TCIU_BUSY"},

9887
    {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},

9888
    {"bits": [12, 12], "name": "QU_BUSY"},

9889
    {"bits": [13, 13], "name": "ATCL2IU_BUSY"},

9890
    {"bits": [29, 29], "name": "CPG_CPC_BUSY"},

9891
    {"bits": [30, 30], "name": "CPF_CPC_BUSY"},

9892
    {"bits": [31, 31], "name": "CPC_BUSY"}

9893
   ]

9894
  },

9895
  "CP_CPF_BUSY_STAT": {

9896
   "fields": [

9897
    {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},

9898
    {"bits": [1, 1], "name": "CSF_RING_BUSY"},

9899
    {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},

9900
    {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},

9901
    {"bits": [4, 4], "name": "CSF_STATE_BUSY"},

9902
    {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},

9903
    {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},

9904
    {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},

9905
    {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},

9906
    {"bits": [9, 9], "name": "OUTSTANDING_READ_TAGS"},

9907
    {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},

9908
    {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},

9909
    {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},

9910
    {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},

9911
    {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},

9912
    {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},

9913
    {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},

9914
    {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},

9915
    {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},

9916
    {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},

9917
    {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},

9918
    {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},

9919
    {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},

9920
    {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},

9921
    {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},

9922
    {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},

9923
    {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},

9924
    {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},

9925
    {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},

9926
    {"bits": [30, 30], "name": "HQD_PQ_BUSY"},

9927
    {"bits": [31, 31], "name": "HQD_IB_BUSY"}

9928
   ]

9929
  },

9930
  "CP_CPF_STALLED_STAT1": {

9931
   "fields": [

9932
    {"bits": [0, 0], "name": "RING_FETCHING_DATA"},

9933
    {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},

9934
    {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},

9935
    {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},

9936
    {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},

9937
    {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},

9938
    {"bits": [7, 7], "name": "ATCL2IU_WAITING_ON_FREE"},

9939
    {"bits": [8, 8], "name": "ATCL2IU_WAITING_ON_TAGS"},

9940
    {"bits": [9, 9], "name": "ATCL1_WAITING_ON_TRANS"}

9941
   ]

9942
  },

9943
  "CP_CPF_STATUS": {

9944
   "fields": [

9945
    {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},

9946
    {"bits": [1, 1], "name": "CSF_BUSY"},

9947
    {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},

9948
    {"bits": [5, 5], "name": "ROQ_RING_BUSY"},

9949
    {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},

9950
    {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},

9951
    {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},

9952
    {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},

9953
    {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},

9954
    {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},

9955
    {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},

9956
    {"bits": [13, 13], "name": "INTERRUPT_BUSY"},

9957
    {"bits": [14, 14], "name": "TCIU_BUSY"},

9958
    {"bits": [15, 15], "name": "HQD_BUSY"},

9959
    {"bits": [16, 16], "name": "PRT_BUSY"},

9960
    {"bits": [17, 17], "name": "ATCL2IU_BUSY"},

9961
    {"bits": [26, 26], "name": "CPF_GFX_BUSY"},

9962
    {"bits": [27, 27], "name": "CPF_CMP_BUSY"},

9963
    {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},

9964
    {"bits": [30, 30], "name": "CPC_CPF_BUSY"},

9965
    {"bits": [31, 31], "name": "CPF_BUSY"}

9966
   ]

9967
  },

9968
  "CP_DMA_CNTL": {

9969
   "fields": [

9970
    {"bits": [4, 5], "name": "MIN_AVAILSZ"},

9971
    {"bits": [16, 19], "name": "BUFFER_DEPTH"},

9972
    {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},

9973
    {"bits": [29, 29], "name": "PIO_FIFO_FULL"},

9974
    {"bits": [30, 31], "name": "PIO_COUNT"}

9975
   ]

9976
  },

9977
  "CP_DMA_ME_COMMAND": {

9978
   "fields": [

9979
    {"bits": [0, 20], "name": "BYTE_COUNT"},

9980
    {"bits": [21, 21], "name": "DIS_WC"},

9981
    {"bits": [22, 23], "name": "SRC_SWAP"},

9982
    {"bits": [24, 25], "name": "DST_SWAP"},

9983
    {"bits": [26, 26], "name": "SAS"},

9984
    {"bits": [27, 27], "name": "DAS"},

9985
    {"bits": [28, 28], "name": "SAIC"},

9986
    {"bits": [29, 29], "name": "DAIC"},

9987
    {"bits": [30, 30], "name": "RAW_WAIT"}

9988
   ]

9989
  },

9990
  "CP_DMA_ME_CONTROL": {

9991
   "fields": [

9992
    {"bits": [10, 11], "name": "SRC_MTYPE"},

9993
    {"bits": [12, 12], "name": "SRC_ATC"},

9994
    {"bits": [13, 13], "name": "SRC_CACHE_POLICY"},

9995
    {"bits": [20, 21], "name": "DST_SELECT"},

9996
    {"bits": [22, 23], "name": "DST_MTYPE"},

9997
    {"bits": [24, 24], "name": "DST_ATC"},

9998
    {"bits": [25, 25], "name": "DST_CACHE_POLICY"},

9999
    {"bits": [29, 30], "name": "SRC_SELECT"}

10000
   ]

10001
  },

10002
  "CP_DMA_ME_DST_ADDR_HI": {

10003
   "fields": [

10004
    {"bits": [0, 15], "name": "DST_ADDR_HI"}

10005
   ]

10006
  },

10007
  "CP_DMA_ME_SRC_ADDR_HI": {

10008
   "fields": [

10009
    {"bits": [0, 15], "name": "SRC_ADDR_HI"}

10010
   ]

10011
  },

10012
  "CP_DMA_READ_TAGS": {

10013
   "fields": [

10014
    {"bits": [0, 25], "name": "DMA_READ_TAG"},

10015
    {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}

10016
   ]

10017
  },

10018
  "CP_DRAW_OBJECT_COUNTER": {

10019
   "fields": [

10020
    {"bits": [0, 15], "name": "COUNT"}

10021
   ]

10022
  },

10023
  "CP_DRAW_WINDOW_CNTL": {

10024
   "fields": [

10025
    {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},

10026
    {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},

10027
    {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},

10028
    {"bits": [8, 8], "name": "MODE"}

10029
   ]

10030
  },

10031
  "CP_DRAW_WINDOW_LO": {

10032
   "fields": [

10033
    {"bits": [0, 15], "name": "MIN"},

10034
    {"bits": [16, 31], "name": "MAX"}

10035
   ]

10036
  },

10037
  "CP_EOP_DONE_ADDR_HI": {

10038
   "fields": [

10039
    {"bits": [0, 15], "name": "ADDR_HI"}

10040
   ]

10041
  },

10042
  "CP_EOP_DONE_ADDR_LO": {

10043
   "fields": [

10044
    {"bits": [2, 31], "name": "ADDR_LO"}

10045
   ]

10046
  },

10047
  "CP_EOP_DONE_CNTX_ID": {

10048
   "fields": [

10049
    {"bits": [0, 27], "name": "CNTX_ID"}

10050
   ]

10051
  },

10052
  "CP_EOP_DONE_DATA_CNTL": {

10053
   "fields": [

10054
    {"bits": [0, 15], "name": "CNTX_ID"},

10055
    {"bits": [16, 17], "name": "DST_SEL"},

10056
    {"bits": [24, 26], "name": "INT_SEL"},

10057
    {"bits": [29, 31], "name": "DATA_SEL"}

10058
   ]

10059
  },

10060
  "CP_EOP_DONE_EVENT_CNTL": {

10061
   "fields": [

10062
    {"bits": [0, 6], "name": "WBINV_TC_OP"},

10063
    {"bits": [12, 17], "name": "WBINV_ACTION_ENA"},

10064
    {"bits": [25, 25], "name": "CACHE_CONTROL"},

10065
    {"bits": [27, 28], "name": "MTYPE"}

10066
   ]

10067
  },

10068
  "CP_IB1_OFFSET": {

10069
   "fields": [

10070
    {"bits": [0, 19], "name": "IB1_OFFSET"}

10071
   ]

10072
  },

10073
  "CP_IB1_PREAMBLE_BEGIN": {

10074
   "fields": [

10075
    {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"}

10076
   ]

10077
  },

10078
  "CP_IB1_PREAMBLE_END": {

10079
   "fields": [

10080
    {"bits": [0, 19], "name": "IB1_PREAMBLE_END"}

10081
   ]

10082
  },

10083
  "CP_IB2_OFFSET": {

10084
   "fields": [

10085
    {"bits": [0, 19], "name": "IB2_OFFSET"}

10086
   ]

10087
  },

10088
  "CP_IB2_PREAMBLE_BEGIN": {

10089
   "fields": [

10090
    {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}

10091
   ]

10092
  },

10093
  "CP_IB2_PREAMBLE_END": {

10094
   "fields": [

10095
    {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}

10096
   ]

10097
  },

10098
  "CP_INDEX_TYPE": {

10099
   "fields": [

10100
    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}

10101
   ]

10102
  },

10103
  "CP_ME_MC_RADDR_HI": {

10104
   "fields": [

10105
    {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},

10106
    {"bits": [20, 21], "name": "MTYPE"},

10107
    {"bits": [22, 22], "name": "CACHE_POLICY"}

10108
   ]

10109
  },

10110
  "CP_ME_MC_RADDR_LO": {

10111
   "fields": [

10112
    {"bits": [0, 1], "name": "ME_MC_RADDR_SWAP"},

10113
    {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}

10114
   ]

10115
  },

10116
  "CP_ME_MC_WADDR_HI": {

10117
   "fields": [

10118
    {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},

10119
    {"bits": [20, 21], "name": "MTYPE"},

10120
    {"bits": [22, 22], "name": "CACHE_POLICY"}

10121
   ]

10122
  },

10123
  "CP_ME_MC_WADDR_LO": {

10124
   "fields": [

10125
    {"bits": [0, 1], "name": "ME_MC_WADDR_SWAP"},

10126
    {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}

10127
   ]

10128
  },

10129
  "CP_PERFMON_CNTL": {

10130
   "fields": [

10131
    {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},

10132
    {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},

10133
    {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},

10134
    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}

10135
   ]

10136
  },

10137
  "CP_PERFMON_CNTX_CNTL": {

10138
   "fields": [

10139
    {"bits": [31, 31], "name": "PERFMON_ENABLE"}

10140
   ]

10141
  },

10142
  "CP_PFP_COMPLETION_STATUS": {

10143
   "fields": [

10144
    {"bits": [0, 1], "name": "STATUS"}

10145
   ]

10146
  },

10147
  "CP_PFP_IB_CONTROL": {

10148
   "fields": [

10149
    {"bits": [0, 7], "name": "IB_EN"}

10150
   ]

10151
  },

10152
  "CP_PFP_LOAD_CONTROL": {

10153
   "fields": [

10154
    {"bits": [0, 0], "name": "CONFIG_REG_EN"},

10155
    {"bits": [1, 1], "name": "CNTX_REG_EN"},

10156
    {"bits": [16, 16], "name": "SH_GFX_REG_EN"},

10157
    {"bits": [24, 24], "name": "SH_CS_REG_EN"}

10158
   ]

10159
  },

10160
  "CP_PIPE_STATS_ADDR_HI": {

10161
   "fields": [

10162
    {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}

10163
   ]

10164
  },

10165
  "CP_PIPE_STATS_ADDR_LO": {

10166
   "fields": [

10167
    {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}

10168
   ]

10169
  },

10170
  "CP_PIPE_STATS_CONTROL": {

10171
   "fields": [

10172
    {"bits": [25, 25], "name": "CACHE_CONTROL"},

10173
    {"bits": [27, 28], "name": "MTYPE"}

10174
   ]

10175
  },

10176
  "CP_PRED_NOT_VISIBLE": {

10177
   "fields": [

10178
    {"bits": [0, 0], "name": "NOT_VISIBLE"}

10179
   ]

10180
  },

10181
  "CP_RB_OFFSET": {

10182
   "fields": [

10183
    {"bits": [0, 19], "name": "RB_OFFSET"}

10184
   ]

10185
  },

10186
  "CP_RINGID": {

10187
   "fields": [

10188
    {"bits": [0, 1], "name": "RINGID"}

10189
   ]

10190
  },

10191
  "CP_SAMPLE_STATUS": {

10192
   "fields": [

10193
    {"bits": [0, 0], "name": "Z_PASS_ACITVE"},

10194
    {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},

10195
    {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},

10196
    {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},

10197
    {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},

10198
    {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},

10199
    {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},

10200
    {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}

10201
   ]

10202
  },

10203
  "CP_SCRATCH_INDEX": {

10204
   "fields": [

10205
    {"bits": [0, 7], "name": "SCRATCH_INDEX"}

10206
   ]

10207
  },

10208
  "CP_SIG_SEM_ADDR_HI": {

10209
   "fields": [

10210
    {"bits": [0, 15], "name": "SEM_ADDR_HI"},

10211
    {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},

10212
    {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},

10213
    {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},

10214
    {"bits": [29, 31], "name": "SEM_SELECT"}

10215
   ]

10216
  },

10217
  "CP_SIG_SEM_ADDR_LO": {

10218
   "fields": [

10219
    {"bits": [0, 1], "name": "SEM_ADDR_SWAP"},

10220
    {"bits": [3, 31], "name": "SEM_ADDR_LO"}

10221
   ]

10222
  },

10223
  "CP_STREAM_OUT_ADDR_HI": {

10224
   "fields": [

10225
    {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"}

10226
   ]

10227
  },

10228
  "CP_STREAM_OUT_ADDR_LO": {

10229
   "fields": [

10230
    {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}

10231
   ]

10232
  },

10233
  "CP_STRMOUT_CNTL": {

10234
   "fields": [

10235
    {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}

10236
   ]

10237
  },

10238
  "CP_ST_BASE_HI": {

10239
   "fields": [

10240
    {"bits": [0, 15], "name": "ST_BASE_HI"}

10241
   ]

10242
  },

10243
  "CP_ST_BASE_LO": {

10244
   "fields": [

10245
    {"bits": [2, 31], "name": "ST_BASE_LO"}

10246
   ]

10247
  },

10248
  "CP_ST_BUFSZ": {

10249
   "fields": [

10250
    {"bits": [0, 19], "name": "ST_BUFSZ"}

10251
   ]

10252
  },

10253
  "CP_VMID": {

10254
   "fields": [

10255
    {"bits": [0, 3], "name": "VMID"}

10256
   ]

10257
  },

10258
  "CS_COPY_STATE": {

10259
   "fields": [

10260
    {"bits": [0, 2], "name": "SRC_STATE_ID"}

10261
   ]

10262
  },

10263
  "DB_ALPHA_TO_MASK": {

10264
   "fields": [

10265
    {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},

10266
    {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},

10267
    {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},

10268
    {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},

10269
    {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},

10270
    {"bits": [16, 16], "name": "OFFSET_ROUND"}

10271
   ]

10272
  },

10273
  "DB_COUNT_CONTROL": {

10274
   "fields": [

10275
    {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},

10276
    {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},

10277
    {"bits": [4, 6], "name": "SAMPLE_RATE"},

10278
    {"bits": [8, 11], "name": "ZPASS_ENABLE"},

10279
    {"bits": [12, 15], "name": "ZFAIL_ENABLE"},

10280
    {"bits": [16, 19], "name": "SFAIL_ENABLE"},

10281
    {"bits": [20, 23], "name": "DBFAIL_ENABLE"},

10282
    {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},

10283
    {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}

10284
   ]

10285
  },

10286
  "DB_DEPTH_CONTROL": {

10287
   "fields": [

10288
    {"bits": [0, 0], "name": "STENCIL_ENABLE"},

10289
    {"bits": [1, 1], "name": "Z_ENABLE"},

10290
    {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},

10291
    {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},

10292
    {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},

10293
    {"bits": [7, 7], "name": "BACKFACE_ENABLE"},

10294
    {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},

10295
    {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},

10296
    {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},

10297
    {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}

10298
   ]

10299
  },

10300
  "DB_DEPTH_INFO": {

10301
   "fields": [

10302
    {"bits": [0, 3], "name": "ADDR5_SWIZZLE_MASK"},

10303
    {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},

10304
    {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},

10305
    {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},

10306
    {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},

10307
    {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},

10308
    {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"}

10309
   ]

10310
  },

10311
  "DB_DEPTH_SIZE": {

10312
   "fields": [

10313
    {"bits": [0, 10], "name": "PITCH_TILE_MAX"},

10314
    {"bits": [11, 21], "name": "HEIGHT_TILE_MAX"}

10315
   ]

10316
  },

10317
  "DB_DEPTH_SLICE": {

10318
   "fields": [

10319
    {"bits": [0, 21], "name": "SLICE_TILE_MAX"}

10320
   ]

10321
  },

10322
  "DB_DEPTH_VIEW": {

10323
   "fields": [

10324
    {"bits": [0, 10], "name": "SLICE_START"},

10325
    {"bits": [13, 23], "name": "SLICE_MAX"},

10326
    {"bits": [24, 24], "name": "Z_READ_ONLY"},

10327
    {"bits": [25, 25], "name": "STENCIL_READ_ONLY"}

10328
   ]

10329
  },

10330
  "DB_EQAA": {

10331
   "fields": [

10332
    {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},

10333
    {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},

10334
    {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},

10335
    {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},

10336
    {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},

10337
    {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},

10338
    {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},

10339
    {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},

10340
    {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},

10341
    {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},

10342
    {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},

10343
    {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}

10344
   ]

10345
  },

10346
  "DB_HTILE_SURFACE": {

10347
   "fields": [

10348
    {"bits": [0, 0], "name": "LINEAR"},

10349
    {"bits": [1, 1], "name": "FULL_CACHE"},

10350
    {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"},

10351
    {"bits": [3, 3], "name": "PRELOAD"},

10352
    {"bits": [4, 9], "name": "PREFETCH_WIDTH"},

10353
    {"bits": [10, 15], "name": "PREFETCH_HEIGHT"},

10354
    {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},

10355
    {"bits": [17, 17], "name": "TC_COMPATIBLE"}

10356
   ]

10357
  },

10358
  "DB_PERFCOUNTER0_SELECT": {

10359
   "fields": [

10360
    {"bits": [0, 9], "name": "PERF_SEL"},

10361
    {"bits": [10, 19], "name": "PERF_SEL1"},

10362
    {"bits": [20, 23], "name": "CNTR_MODE"},

10363
    {"bits": [24, 27], "name": "PERF_MODE1"},

10364
    {"bits": [28, 31], "name": "PERF_MODE"}

10365
   ]

10366
  },

10367
  "DB_PERFCOUNTER0_SELECT1": {

10368
   "fields": [

10369
    {"bits": [0, 9], "name": "PERF_SEL2"},

10370
    {"bits": [10, 19], "name": "PERF_SEL3"},

10371
    {"bits": [24, 27], "name": "PERF_MODE3"},

10372
    {"bits": [28, 31], "name": "PERF_MODE2"}

10373
   ]

10374
  },

10375
  "DB_PRELOAD_CONTROL": {

10376
   "fields": [

10377
    {"bits": [0, 7], "name": "START_X"},

10378
    {"bits": [8, 15], "name": "START_Y"},

10379
    {"bits": [16, 23], "name": "MAX_X"},

10380
    {"bits": [24, 31], "name": "MAX_Y"}

10381
   ]

10382
  },

10383
  "DB_RENDER_CONTROL": {

10384
   "fields": [

10385
    {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},

10386
    {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},

10387
    {"bits": [2, 2], "name": "DEPTH_COPY"},

10388
    {"bits": [3, 3], "name": "STENCIL_COPY"},

10389
    {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},

10390
    {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},

10391
    {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},

10392
    {"bits": [7, 7], "name": "COPY_CENTROID"},

10393
    {"bits": [8, 11], "name": "COPY_SAMPLE"},

10394
    {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"}

10395
   ]

10396
  },

10397
  "DB_RENDER_OVERRIDE": {

10398
   "fields": [

10399
    {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},

10400
    {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},

10401
    {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},

10402
    {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},

10403
    {"bits": [7, 7], "name": "FAST_Z_DISABLE"},

10404
    {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},

10405
    {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},

10406
    {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},

10407
    {"bits": [11, 11], "name": "FORCE_Z_READ"},

10408
    {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},

10409
    {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},

10410
    {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},

10411
    {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},

10412
    {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},

10413
    {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},

10414
    {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},

10415
    {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},

10416
    {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},

10417
    {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},

10418
    {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},

10419
    {"bits": [29, 29], "name": "FORCE_Z_VALID"},

10420
    {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},

10421
    {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}

10422
   ]

10423
  },

10424
  "DB_RENDER_OVERRIDE2": {

10425
   "fields": [

10426
    {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},

10427
    {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},

10428
    {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},

10429
    {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},

10430
    {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},

10431
    {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},

10432
    {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},

10433
    {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},

10434
    {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},

10435
    {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},

10436
    {"bits": [15, 17], "name": "HIS_SFUNC_FF"},

10437
    {"bits": [18, 20], "name": "HIS_SFUNC_BF"},

10438
    {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},

10439
    {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},

10440
    {"bits": [23, 23], "name": "DISABLE_FAST_PASS"}

10441
   ]

10442
  },

10443
  "DB_SHADER_CONTROL": {

10444
   "fields": [

10445
    {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},

10446
    {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},

10447
    {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},

10448
    {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},

10449
    {"bits": [6, 6], "name": "KILL_ENABLE"},

10450
    {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},

10451
    {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},

10452
    {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},

10453
    {"bits": [10, 10], "name": "EXEC_ON_NOOP"},

10454
    {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},

10455
    {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},

10456
    {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},

10457
    {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"}

10458
   ]

10459
  },

10460
  "DB_SRESULTS_COMPARE_STATE0": {

10461
   "fields": [

10462
    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},

10463
    {"bits": [4, 11], "name": "COMPAREVALUE0"},

10464
    {"bits": [12, 19], "name": "COMPAREMASK0"},

10465
    {"bits": [24, 24], "name": "ENABLE0"}

10466
   ]

10467
  },

10468
  "DB_SRESULTS_COMPARE_STATE1": {

10469
   "fields": [

10470
    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},

10471
    {"bits": [4, 11], "name": "COMPAREVALUE1"},

10472
    {"bits": [12, 19], "name": "COMPAREMASK1"},

10473
    {"bits": [24, 24], "name": "ENABLE1"}

10474
   ]

10475
  },

10476
  "DB_STENCILREFMASK": {

10477
   "fields": [

10478
    {"bits": [0, 7], "name": "STENCILTESTVAL"},

10479
    {"bits": [8, 15], "name": "STENCILMASK"},

10480
    {"bits": [16, 23], "name": "STENCILWRITEMASK"},

10481
    {"bits": [24, 31], "name": "STENCILOPVAL"}

10482
   ]

10483
  },

10484
  "DB_STENCILREFMASK_BF": {

10485
   "fields": [

10486
    {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},

10487
    {"bits": [8, 15], "name": "STENCILMASK_BF"},

10488
    {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},

10489
    {"bits": [24, 31], "name": "STENCILOPVAL_BF"}

10490
   ]

10491
  },

10492
  "DB_STENCIL_CLEAR": {

10493
   "fields": [

10494
    {"bits": [0, 7], "name": "CLEAR"}

10495
   ]

10496
  },

10497
  "DB_STENCIL_CONTROL": {

10498
   "fields": [

10499
    {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},

10500
    {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},

10501
    {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},

10502
    {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},

10503
    {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},

10504
    {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}

10505
   ]

10506
  },

10507
  "DB_STENCIL_INFO": {

10508
   "fields": [

10509
    {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},

10510
    {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},

10511
    {"bits": [20, 22], "name": "TILE_MODE_INDEX"},

10512
    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},

10513
    {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"},

10514
    {"bits": [30, 30], "name": "CLEAR_DISALLOWED"}

10515
   ]

10516
  },

10517
  "DB_ZPASS_COUNT_HI": {

10518
   "fields": [

10519
    {"bits": [0, 30], "name": "COUNT_HI"}

10520
   ]

10521
  },

10522
  "DB_Z_INFO": {

10523
   "fields": [

10524
    {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},

10525
    {"bits": [2, 3], "name": "NUM_SAMPLES"},

10526
    {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},

10527
    {"bits": [20, 22], "name": "TILE_MODE_INDEX"},

10528
    {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},

10529
    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},

10530
    {"bits": [28, 28], "name": "READ_SIZE"},

10531
    {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},

10532
    {"bits": [30, 30], "name": "CLEAR_DISALLOWED"},

10533
    {"bits": [31, 31], "name": "ZRANGE_PRECISION"}

10534
   ]

10535
  },

10536
  "GB_ADDR_CONFIG": {

10537
   "fields": [

10538
    {"bits": [0, 2], "name": "NUM_PIPES"},

10539
    {"bits": [4, 6], "name": "PIPE_INTERLEAVE_SIZE"},

10540
    {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"},

10541
    {"bits": [12, 13], "name": "NUM_SHADER_ENGINES"},

10542
    {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"},

10543
    {"bits": [20, 22], "name": "NUM_GPUS"},

10544
    {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"},

10545
    {"bits": [28, 29], "name": "ROW_SIZE"},

10546
    {"bits": [30, 30], "name": "NUM_LOWER_PIPES"}

10547
   ]

10548
  },

10549
  "GB_MACROTILE_MODE0": {

10550
   "fields": [

10551
    {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},

10552
    {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},

10553
    {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},

10554
    {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"}

10555
   ]

10556
  },

10557
  "GB_TILE_MODE0": {

10558
   "fields": [

10559
    {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},

10560
    {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},

10561
    {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},

10562
    {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},

10563
    {"bits": [25, 26], "name": "SAMPLE_SPLIT"}

10564
   ]

10565
  },

10566
  "GDS_ATOM_BASE": {

10567
   "fields": [

10568
    {"bits": [0, 15], "name": "BASE"},

10569
    {"bits": [16, 31], "name": "UNUSED"}

10570
   ]

10571
  },

10572
  "GDS_ATOM_CNTL": {

10573
   "fields": [

10574
    {"bits": [0, 5], "name": "AINC"},

10575
    {"bits": [6, 7], "name": "UNUSED1"},

10576
    {"bits": [8, 9], "name": "DMODE"},

10577
    {"bits": [10, 31], "name": "UNUSED2"}

10578
   ]

10579
  },

10580
  "GDS_ATOM_COMPLETE": {

10581
   "fields": [

10582
    {"bits": [0, 0], "name": "COMPLETE"},

10583
    {"bits": [1, 31], "name": "UNUSED"}

10584
   ]

10585
  },

10586
  "GDS_ATOM_OFFSET0": {

10587
   "fields": [

10588
    {"bits": [0, 7], "name": "OFFSET0"},

10589
    {"bits": [8, 31], "name": "UNUSED"}

10590
   ]

10591
  },

10592
  "GDS_ATOM_OFFSET1": {

10593
   "fields": [

10594
    {"bits": [0, 7], "name": "OFFSET1"},

10595
    {"bits": [8, 31], "name": "UNUSED"}

10596
   ]

10597
  },

10598
  "GDS_ATOM_OP": {

10599
   "fields": [

10600
    {"bits": [0, 7], "name": "OP"},

10601
    {"bits": [8, 31], "name": "UNUSED"}

10602
   ]

10603
  },

10604
  "GDS_ATOM_SIZE": {

10605
   "fields": [

10606
    {"bits": [0, 15], "name": "SIZE"},

10607
    {"bits": [16, 31], "name": "UNUSED"}

10608
   ]

10609
  },

10610
  "GDS_GWS_RESOURCE": {

10611
   "fields": [

10612
    {"bits": [0, 0], "name": "FLAG"},

10613
    {"bits": [1, 12], "name": "COUNTER"},

10614
    {"bits": [13, 13], "name": "TYPE"},

10615
    {"bits": [14, 14], "name": "DED"},

10616
    {"bits": [15, 15], "name": "RELEASE_ALL"},

10617
    {"bits": [16, 27], "name": "HEAD_QUEUE"},

10618
    {"bits": [28, 28], "name": "HEAD_VALID"},

10619
    {"bits": [29, 29], "name": "HEAD_FLAG"},

10620
    {"bits": [30, 31], "name": "UNUSED1"}

10621
   ]

10622
  },

10623
  "GDS_GWS_RESOURCE_CNT": {

10624
   "fields": [

10625
    {"bits": [0, 15], "name": "RESOURCE_CNT"},

10626
    {"bits": [16, 31], "name": "UNUSED"}

10627
   ]

10628
  },

10629
  "GDS_GWS_RESOURCE_CNTL": {

10630
   "fields": [

10631
    {"bits": [0, 5], "name": "INDEX"},

10632
    {"bits": [6, 31], "name": "UNUSED"}

10633
   ]

10634
  },

10635
  "GDS_OA_ADDRESS": {

10636
   "fields": [

10637
    {"bits": [0, 15], "name": "DS_ADDRESS"},

10638
    {"bits": [16, 19], "name": "CRAWLER"},

10639
    {"bits": [20, 21], "name": "CRAWLER_TYPE"},

10640
    {"bits": [22, 29], "name": "UNUSED"},

10641
    {"bits": [30, 30], "name": "NO_ALLOC"},

10642
    {"bits": [31, 31], "name": "ENABLE"}

10643
   ]

10644
  },

10645
  "GDS_OA_CNTL": {

10646
   "fields": [

10647
    {"bits": [0, 3], "name": "INDEX"},

10648
    {"bits": [4, 31], "name": "UNUSED"}

10649
   ]

10650
  },

10651
  "GDS_OA_INCDEC": {

10652
   "fields": [

10653
    {"bits": [0, 30], "name": "VALUE"},

10654
    {"bits": [31, 31], "name": "INCDEC"}

10655
   ]

10656
  },

10657
  "GRBM_GFX_INDEX": {

10658
   "fields": [

10659
    {"bits": [0, 7], "name": "INSTANCE_INDEX"},

10660
    {"bits": [8, 15], "name": "SH_INDEX"},

10661
    {"bits": [16, 23], "name": "SE_INDEX"},

10662
    {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"},

10663
    {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},

10664
    {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}

10665
   ]

10666
  },

10667
  "GRBM_PERFCOUNTER0_SELECT": {

10668
   "fields": [

10669
    {"bits": [0, 5], "name": "PERF_SEL"},

10670
    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},

10671
    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},

10672
    {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"},

10673
    {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},

10674
    {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},

10675
    {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},

10676
    {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},

10677
    {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},

10678
    {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},

10679
    {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},

10680
    {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},

10681
    {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},

10682
    {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"},

10683
    {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},

10684
    {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},

10685
    {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},

10686
    {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"},

10687
    {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"}

10688
   ]

10689
  },

10690
  "GRBM_SE0_PERFCOUNTER_SELECT": {

10691
   "fields": [

10692
    {"bits": [0, 5], "name": "PERF_SEL"},

10693
    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},

10694
    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},

10695
    {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},

10696
    {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},

10697
    {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},

10698
    {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},

10699
    {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},

10700
    {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},

10701
    {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"},

10702
    {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},

10703
    {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"}

10704
   ]

10705
  },

10706
  "GRBM_STATUS": {

10707
   "fields": [

10708
    {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},

10709
    {"bits": [5, 5], "name": "SRBM_RQ_PENDING"},

10710
    {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},

10711
    {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},

10712
    {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},

10713
    {"bits": [12, 12], "name": "DB_CLEAN"},

10714
    {"bits": [13, 13], "name": "CB_CLEAN"},

10715
    {"bits": [14, 14], "name": "TA_BUSY"},

10716
    {"bits": [15, 15], "name": "GDS_BUSY"},

10717
    {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"},

10718
    {"bits": [17, 17], "name": "VGT_BUSY"},

10719
    {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"},

10720
    {"bits": [19, 19], "name": "IA_BUSY"},

10721
    {"bits": [20, 20], "name": "SX_BUSY"},

10722
    {"bits": [21, 21], "name": "WD_BUSY"},

10723
    {"bits": [22, 22], "name": "SPI_BUSY"},

10724
    {"bits": [23, 23], "name": "BCI_BUSY"},

10725
    {"bits": [24, 24], "name": "SC_BUSY"},

10726
    {"bits": [25, 25], "name": "PA_BUSY"},

10727
    {"bits": [26, 26], "name": "DB_BUSY"},

10728
    {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},

10729
    {"bits": [29, 29], "name": "CP_BUSY"},

10730
    {"bits": [30, 30], "name": "CB_BUSY"},

10731
    {"bits": [31, 31], "name": "GUI_ACTIVE"}

10732
   ]

10733
  },

10734
  "GRBM_STATUS2": {

10735
   "fields": [

10736
    {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},

10737
    {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},

10738
    {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},

10739
    {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},

10740
    {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},

10741
    {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},

10742
    {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},

10743
    {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},

10744
    {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},

10745
    {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},

10746
    {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},

10747
    {"bits": [14, 14], "name": "RLC_RQ_PENDING"},

10748
    {"bits": [24, 24], "name": "RLC_BUSY"},

10749
    {"bits": [25, 25], "name": "TC_BUSY"},

10750
    {"bits": [26, 26], "name": "TCC_CC_RESIDENT"},

10751
    {"bits": [28, 28], "name": "CPF_BUSY"},

10752
    {"bits": [29, 29], "name": "CPC_BUSY"},

10753
    {"bits": [30, 30], "name": "CPG_BUSY"}

10754
   ]

10755
  },

10756
  "GRBM_STATUS_SE0": {

10757
   "fields": [

10758
    {"bits": [1, 1], "name": "DB_CLEAN"},

10759
    {"bits": [2, 2], "name": "CB_CLEAN"},

10760
    {"bits": [22, 22], "name": "BCI_BUSY"},

10761
    {"bits": [23, 23], "name": "VGT_BUSY"},

10762
    {"bits": [24, 24], "name": "PA_BUSY"},

10763
    {"bits": [25, 25], "name": "TA_BUSY"},

10764
    {"bits": [26, 26], "name": "SX_BUSY"},

10765
    {"bits": [27, 27], "name": "SPI_BUSY"},

10766
    {"bits": [29, 29], "name": "SC_BUSY"},

10767
    {"bits": [30, 30], "name": "DB_BUSY"},

10768
    {"bits": [31, 31], "name": "CB_BUSY"}

10769
   ]

10770
  },

10771
  "IA_MULTI_VGT_PARAM": {

10772
   "fields": [

10773
    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},

10774
    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},

10775
    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},

10776
    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},

10777
    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},

10778
    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"},

10779
    {"bits": [28, 31], "name": "MAX_PRIMGRP_IN_WAVE"}

10780
   ]

10781
  },

10782
  "PA_CL_CLIP_CNTL": {

10783
   "fields": [

10784
    {"bits": [0, 0], "name": "UCP_ENA_0"},

10785
    {"bits": [1, 1], "name": "UCP_ENA_1"},

10786
    {"bits": [2, 2], "name": "UCP_ENA_2"},

10787
    {"bits": [3, 3], "name": "UCP_ENA_3"},

10788
    {"bits": [4, 4], "name": "UCP_ENA_4"},

10789
    {"bits": [5, 5], "name": "UCP_ENA_5"},

10790
    {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},

10791
    {"bits": [14, 15], "name": "PS_UCP_MODE"},

10792
    {"bits": [16, 16], "name": "CLIP_DISABLE"},

10793
    {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},

10794
    {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},

10795
    {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},

10796
    {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},

10797
    {"bits": [21, 21], "name": "VTX_KILL_OR"},

10798
    {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},

10799
    {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},

10800
    {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},

10801
    {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},

10802
    {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"}

10803
   ]

10804
  },

10805
  "PA_CL_NANINF_CNTL": {

10806
   "fields": [

10807
    {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},

10808
    {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},

10809
    {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},

10810
    {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},

10811
    {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},

10812
    {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},

10813
    {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},

10814
    {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},

10815
    {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},

10816
    {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},

10817
    {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},

10818
    {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},

10819
    {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},

10820
    {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},

10821
    {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},

10822
    {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}

10823
   ]

10824
  },

10825
  "PA_CL_VS_OUT_CNTL": {

10826
   "fields": [

10827
    {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},

10828
    {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},

10829
    {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},

10830
    {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},

10831
    {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},

10832
    {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},

10833
    {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},

10834
    {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},

10835
    {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},

10836
    {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},

10837
    {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},

10838
    {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},

10839
    {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},

10840
    {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},

10841
    {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},

10842
    {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},

10843
    {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},

10844
    {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},

10845
    {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},

10846
    {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},

10847
    {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},

10848
    {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},

10849
    {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},

10850
    {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},

10851
    {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},

10852
    {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},

10853
    {"bits": [26, 26], "name": "USE_VTX_LINE_WIDTH"}

10854
   ]

10855
  },

10856
  "PA_CL_VTE_CNTL": {

10857
   "fields": [

10858
    {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},

10859
    {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},

10860
    {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},

10861
    {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},

10862
    {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},

10863
    {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},

10864
    {"bits": [8, 8], "name": "VTX_XY_FMT"},

10865
    {"bits": [9, 9], "name": "VTX_Z_FMT"},

10866
    {"bits": [10, 10], "name": "VTX_W0_FMT"},

10867
    {"bits": [11, 11], "name": "PERFCOUNTER_REF"}

10868
   ]

10869
  },

10870
  "PA_SC_AA_CONFIG": {

10871
   "fields": [

10872
    {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},

10873
    {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},

10874
    {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},

10875
    {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},

10876
    {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"}

10877
   ]

10878
  },

10879
  "PA_SC_AA_MASK_X0Y0_X1Y0": {

10880
   "fields": [

10881
    {"bits": [0, 15], "name": "AA_MASK_X0Y0"},

10882
    {"bits": [16, 31], "name": "AA_MASK_X1Y0"}

10883
   ]

10884
  },

10885
  "PA_SC_AA_MASK_X0Y1_X1Y1": {

10886
   "fields": [

10887
    {"bits": [0, 15], "name": "AA_MASK_X0Y1"},

10888
    {"bits": [16, 31], "name": "AA_MASK_X1Y1"}

10889
   ]

10890
  },

10891
  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": {

10892
   "fields": [

10893
    {"bits": [0, 3], "name": "S0_X"},

10894
    {"bits": [4, 7], "name": "S0_Y"},

10895
    {"bits": [8, 11], "name": "S1_X"},

10896
    {"bits": [12, 15], "name": "S1_Y"},

10897
    {"bits": [16, 19], "name": "S2_X"},

10898
    {"bits": [20, 23], "name": "S2_Y"},

10899
    {"bits": [24, 27], "name": "S3_X"},

10900
    {"bits": [28, 31], "name": "S3_Y"}

10901
   ]

10902
  },

10903
  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": {

10904
   "fields": [

10905
    {"bits": [0, 3], "name": "S4_X"},

10906
    {"bits": [4, 7], "name": "S4_Y"},

10907
    {"bits": [8, 11], "name": "S5_X"},

10908
    {"bits": [12, 15], "name": "S5_Y"},

10909
    {"bits": [16, 19], "name": "S6_X"},

10910
    {"bits": [20, 23], "name": "S6_Y"},

10911
    {"bits": [24, 27], "name": "S7_X"},

10912
    {"bits": [28, 31], "name": "S7_Y"}

10913
   ]

10914
  },

10915
  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": {

10916
   "fields": [

10917
    {"bits": [0, 3], "name": "S8_X"},

10918
    {"bits": [4, 7], "name": "S8_Y"},

10919
    {"bits": [8, 11], "name": "S9_X"},

10920
    {"bits": [12, 15], "name": "S9_Y"},

10921
    {"bits": [16, 19], "name": "S10_X"},

10922
    {"bits": [20, 23], "name": "S10_Y"},

10923
    {"bits": [24, 27], "name": "S11_X"},

10924
    {"bits": [28, 31], "name": "S11_Y"}

10925
   ]

10926
  },

10927
  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": {

10928
   "fields": [

10929
    {"bits": [0, 3], "name": "S12_X"},

10930
    {"bits": [4, 7], "name": "S12_Y"},

10931
    {"bits": [8, 11], "name": "S13_X"},

10932
    {"bits": [12, 15], "name": "S13_Y"},

10933
    {"bits": [16, 19], "name": "S14_X"},

10934
    {"bits": [20, 23], "name": "S14_Y"},

10935
    {"bits": [24, 27], "name": "S15_X"},

10936
    {"bits": [28, 31], "name": "S15_Y"}

10937
   ]

10938
  },

10939
  "PA_SC_CENTROID_PRIORITY_0": {

10940
   "fields": [

10941
    {"bits": [0, 3], "name": "DISTANCE_0"},

10942
    {"bits": [4, 7], "name": "DISTANCE_1"},

10943
    {"bits": [8, 11], "name": "DISTANCE_2"},

10944
    {"bits": [12, 15], "name": "DISTANCE_3"},

10945
    {"bits": [16, 19], "name": "DISTANCE_4"},

10946
    {"bits": [20, 23], "name": "DISTANCE_5"},

10947
    {"bits": [24, 27], "name": "DISTANCE_6"},

10948
    {"bits": [28, 31], "name": "DISTANCE_7"}

10949
   ]

10950
  },

10951
  "PA_SC_CENTROID_PRIORITY_1": {

10952
   "fields": [

10953
    {"bits": [0, 3], "name": "DISTANCE_8"},

10954
    {"bits": [4, 7], "name": "DISTANCE_9"},

10955
    {"bits": [8, 11], "name": "DISTANCE_10"},

10956
    {"bits": [12, 15], "name": "DISTANCE_11"},

10957
    {"bits": [16, 19], "name": "DISTANCE_12"},

10958
    {"bits": [20, 23], "name": "DISTANCE_13"},

10959
    {"bits": [24, 27], "name": "DISTANCE_14"},

10960
    {"bits": [28, 31], "name": "DISTANCE_15"}

10961
   ]

10962
  },

10963
  "PA_SC_CLIPRECT_0_BR": {

10964
   "fields": [

10965
    {"bits": [0, 14], "name": "BR_X"},

10966
    {"bits": [16, 30], "name": "BR_Y"}

10967
   ]

10968
  },

10969
  "PA_SC_CLIPRECT_0_TL": {

10970
   "fields": [

10971
    {"bits": [0, 14], "name": "TL_X"},

10972
    {"bits": [16, 30], "name": "TL_Y"}

10973
   ]

10974
  },

10975
  "PA_SC_CLIPRECT_RULE": {

10976
   "fields": [

10977
    {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}

10978
   ]

10979
  },

10980
  "PA_SC_EDGERULE": {

10981
   "fields": [

10982
    {"bits": [0, 3], "name": "ER_TRI"},

10983
    {"bits": [4, 7], "name": "ER_POINT"},

10984
    {"bits": [8, 11], "name": "ER_RECT"},

10985
    {"bits": [12, 17], "name": "ER_LINE_LR"},

10986
    {"bits": [18, 23], "name": "ER_LINE_RL"},

10987
    {"bits": [24, 27], "name": "ER_LINE_TB"},

10988
    {"bits": [28, 31], "name": "ER_LINE_BT"}

10989
   ]

10990
  },

10991
  "PA_SC_GENERIC_SCISSOR_TL": {

10992
   "fields": [

10993
    {"bits": [0, 14], "name": "TL_X"},

10994
    {"bits": [16, 30], "name": "TL_Y"},

10995
    {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}

10996
   ]

10997
  },

10998
  "PA_SC_LINE_CNTL": {

10999
   "fields": [

11000
    {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},

11001
    {"bits": [10, 10], "name": "LAST_PIXEL"},

11002
    {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},

11003
    {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"}

11004
   ]

11005
  },

11006
  "PA_SC_LINE_STIPPLE": {

11007
   "fields": [

11008
    {"bits": [0, 15], "name": "LINE_PATTERN"},

11009
    {"bits": [16, 23], "name": "REPEAT_COUNT"},

11010
    {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},

11011
    {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}

11012
   ]

11013
  },

11014
  "PA_SC_LINE_STIPPLE_STATE": {

11015
   "fields": [

11016
    {"bits": [0, 3], "name": "CURRENT_PTR"},

11017
    {"bits": [8, 15], "name": "CURRENT_COUNT"}

11018
   ]

11019
  },

11020
  "PA_SC_MODE_CNTL_0": {

11021
   "fields": [

11022
    {"bits": [0, 0], "name": "MSAA_ENABLE"},

11023
    {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},

11024
    {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},

11025
    {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"}

11026
   ]

11027
  },

11028
  "PA_SC_MODE_CNTL_1": {

11029
   "fields": [

11030
    {"bits": [0, 0], "name": "WALK_SIZE"},

11031
    {"bits": [1, 1], "name": "WALK_ALIGNMENT"},

11032
    {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},

11033
    {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},

11034
    {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},

11035
    {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},

11036
    {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},

11037
    {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},

11038
    {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},

11039
    {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},

11040
    {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},

11041
    {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},

11042
    {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},

11043
    {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},

11044
    {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},

11045
    {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},

11046
    {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},

11047
    {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},

11048
    {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},

11049
    {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},

11050
    {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},

11051
    {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},

11052
    {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},

11053
    {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}

11054
   ]

11055
  },

11056
  "PA_SC_P3D_TRAP_SCREEN_H": {

11057
   "fields": [

11058
    {"bits": [0, 13], "name": "X_COORD"}

11059
   ]

11060
  },

11061
  "PA_SC_P3D_TRAP_SCREEN_HV_EN": {

11062
   "fields": [

11063
    {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},

11064
    {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}

11065
   ]

11066
  },

11067
  "PA_SC_P3D_TRAP_SCREEN_V": {

11068
   "fields": [

11069
    {"bits": [0, 13], "name": "Y_COORD"}

11070
   ]

11071
  },

11072
  "PA_SC_PERFCOUNTER1_SELECT": {

11073
   "fields": [

11074
    {"bits": [0, 9], "name": "PERF_SEL"}

11075
   ]

11076
  },

11077
  "PA_SC_RASTER_CONFIG": {

11078
   "fields": [

11079
    {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},

11080
    {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},

11081
    {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},

11082
    {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},

11083
    {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},

11084
    {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},

11085
    {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},

11086
    {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},

11087
    {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},

11088
    {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},

11089
    {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},

11090
    {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},

11091
    {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},

11092
    {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},

11093
    {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}

11094
   ]

11095
  },

11096
  "PA_SC_RASTER_CONFIG_1": {

11097
   "fields": [

11098
    {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},

11099
    {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},

11100
    {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}

11101
   ]

11102
  },

11103
  "PA_SC_SCREEN_EXTENT_CONTROL": {

11104
   "fields": [

11105
    {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},

11106
    {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}

11107
   ]

11108
  },

11109
  "PA_SC_SCREEN_EXTENT_MIN_0": {

11110
   "fields": [

11111
    {"bits": [0, 15], "name": "X"},

11112
    {"bits": [16, 31], "name": "Y"}

11113
   ]

11114
  },

11115
  "PA_SC_SCREEN_SCISSOR_BR": {

11116
   "fields": [

11117
    {"bits": [0, 15], "name": "BR_X"},

11118
    {"bits": [16, 31], "name": "BR_Y"}

11119
   ]

11120
  },

11121
  "PA_SC_SCREEN_SCISSOR_TL": {

11122
   "fields": [

11123
    {"bits": [0, 15], "name": "TL_X"},

11124
    {"bits": [16, 31], "name": "TL_Y"}

11125
   ]

11126
  },

11127
  "PA_SC_SHADER_CONTROL": {

11128
   "fields": [

11129
    {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"}

11130
   ]

11131
  },

11132
  "PA_SC_WINDOW_OFFSET": {

11133
   "fields": [

11134
    {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},

11135
    {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}

11136
   ]

11137
  },

11138
  "PA_SU_HARDWARE_SCREEN_OFFSET": {

11139
   "fields": [

11140
    {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},

11141
    {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}

11142
   ]

11143
  },

11144
  "PA_SU_LINE_CNTL": {

11145
   "fields": [

11146
    {"bits": [0, 15], "name": "WIDTH"}

11147
   ]

11148
  },

11149
  "PA_SU_LINE_STIPPLE_CNTL": {

11150
   "fields": [

11151
    {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},

11152
    {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},

11153
    {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},

11154
    {"bits": [4, 4], "name": "DIAMOND_ADJUST"}

11155
   ]

11156
  },

11157
  "PA_SU_LINE_STIPPLE_VALUE": {

11158
   "fields": [

11159
    {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}

11160
   ]

11161
  },

11162
  "PA_SU_PERFCOUNTER0_HI": {

11163
   "fields": [

11164
    {"bits": [0, 15], "name": "PERFCOUNTER_HI"}

11165
   ]

11166
  },

11167
  "PA_SU_PERFCOUNTER0_SELECT": {

11168
   "fields": [

11169
    {"bits": [0, 9], "name": "PERF_SEL"},

11170
    {"bits": [10, 19], "name": "PERF_SEL1"},

11171
    {"bits": [20, 23], "name": "CNTR_MODE"}

11172
   ]

11173
  },

11174
  "PA_SU_PERFCOUNTER0_SELECT1": {

11175
   "fields": [

11176
    {"bits": [0, 9], "name": "PERF_SEL2"},

11177
    {"bits": [10, 19], "name": "PERF_SEL3"}

11178
   ]

11179
  },

11180
  "PA_SU_PERFCOUNTER2_SELECT": {

11181
   "fields": [

11182
    {"bits": [0, 9], "name": "PERF_SEL"},

11183
    {"bits": [20, 23], "name": "CNTR_MODE"}

11184
   ]

11185
  },

11186
  "PA_SU_POINT_MINMAX": {

11187
   "fields": [

11188
    {"bits": [0, 15], "name": "MIN_SIZE"},

11189
    {"bits": [16, 31], "name": "MAX_SIZE"}

11190
   ]

11191
  },

11192
  "PA_SU_POINT_SIZE": {

11193
   "fields": [

11194
    {"bits": [0, 15], "name": "HEIGHT"},

11195
    {"bits": [16, 31], "name": "WIDTH"}

11196
   ]

11197
  },

11198
  "PA_SU_POLY_OFFSET_DB_FMT_CNTL": {

11199
   "fields": [

11200
    {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},

11201
    {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}

11202
   ]

11203
  },

11204
  "PA_SU_PRIM_FILTER_CNTL": {

11205
   "fields": [

11206
    {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},

11207
    {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},

11208
    {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},

11209
    {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},

11210
    {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},

11211
    {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},

11212
    {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},

11213
    {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},

11214
    {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},

11215
    {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},

11216
    {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}

11217
   ]

11218
  },

11219
  "PA_SU_SC_MODE_CNTL": {

11220
   "fields": [

11221
    {"bits": [0, 0], "name": "CULL_FRONT"},

11222
    {"bits": [1, 1], "name": "CULL_BACK"},

11223
    {"bits": [2, 2], "name": "FACE"},

11224
    {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},

11225
    {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},

11226
    {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},

11227
    {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},

11228
    {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},

11229
    {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},

11230
    {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},

11231
    {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},

11232
    {"bits": [20, 20], "name": "PERSP_CORR_DIS"},

11233
    {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"}

11234
   ]

11235
  },

11236
  "PA_SU_VTX_CNTL": {

11237
   "fields": [

11238
    {"bits": [0, 0], "name": "PIX_CENTER"},

11239
    {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},

11240
    {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}

11241
   ]

11242
  },

11243
  "RLC_PERFCOUNTER0_SELECT": {

11244
   "fields": [

11245
    {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}

11246
   ]

11247
  },

11248
  "RLC_PERFMON_CLK_CNTL": {

11249
   "fields": [

11250
    {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"}

11251
   ]

11252
  },

11253
  "RLC_PERFMON_CNTL": {

11254
   "fields": [

11255
    {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},

11256
    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}

11257
   ]

11258
  },

11259
  "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY": {

11260
   "fields": [

11261
    {"bits": [0, 7], "name": "PERFMON_SAMPLE_DELAY"},

11262
    {"bits": [8, 31], "name": "RESERVED"}

11263
   ]

11264
  },

11265
  "RLC_SPM_PERFMON_CNTL": {

11266
   "fields": [

11267
    {"bits": [0, 11], "name": "RESERVED1"},

11268
    {"bits": [12, 13], "name": "PERFMON_RING_MODE"},

11269
    {"bits": [14, 15], "name": "RESERVED"},

11270
    {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}

11271
   ]

11272
  },

11273
  "RLC_SPM_PERFMON_RING_BASE_HI": {

11274
   "fields": [

11275
    {"bits": [0, 15], "name": "RING_BASE_HI"},

11276
    {"bits": [16, 31], "name": "RESERVED"}

11277
   ]

11278
  },

11279
  "RLC_SPM_PERFMON_SEGMENT_SIZE": {

11280
   "fields": [

11281
    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},

11282
    {"bits": [8, 10], "name": "RESERVED1"},

11283
    {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"},

11284
    {"bits": [16, 20], "name": "SE0_NUM_LINE"},

11285
    {"bits": [21, 25], "name": "SE1_NUM_LINE"},

11286
    {"bits": [26, 30], "name": "SE2_NUM_LINE"},

11287
    {"bits": [31, 31], "name": "RESERVED"}

11288
   ]

11289
  },

11290
  "SCRATCH_UMSK": {

11291
   "fields": [

11292
    {"bits": [0, 7], "name": "OBSOLETE_UMSK"},

11293
    {"bits": [16, 17], "name": "OBSOLETE_SWAP"}

11294
   ]

11295
  },

11296
  "SPI_BARYC_CNTL": {

11297
   "fields": [

11298
    {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},

11299
    {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},

11300
    {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},

11301
    {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},

11302
    {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},

11303
    {"bits": [20, 20], "name": "POS_FLOAT_ULC"},

11304
    {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}

11305
   ]

11306
  },

11307
  "SPI_CONFIG_CNTL": {

11308
   "fields": [

11309
    {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},

11310
    {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},

11311
    {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},

11312
    {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},

11313
    {"bits": [26, 26], "name": "RSRC_MGMT_RESET"},

11314
    {"bits": [27, 27], "name": "TTRACE_STALL_ALL"}

11315
   ]

11316
  },

11317
  "SPI_INTERP_CONTROL_0": {

11318
   "fields": [

11319
    {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},

11320
    {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},

11321
    {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},

11322
    {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},

11323
    {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},

11324
    {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},

11325
    {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}

11326
   ]

11327
  },

11328
  "SPI_PERFCOUNTER4_SELECT": {

11329
   "fields": [

11330
    {"bits": [0, 7], "name": "PERF_SEL"}

11331
   ]

11332
  },

11333
  "SPI_PERFCOUNTER_BINS": {

11334
   "fields": [

11335
    {"bits": [0, 3], "name": "BIN0_MIN"},

11336
    {"bits": [4, 7], "name": "BIN0_MAX"},

11337
    {"bits": [8, 11], "name": "BIN1_MIN"},

11338
    {"bits": [12, 15], "name": "BIN1_MAX"},

11339
    {"bits": [16, 19], "name": "BIN2_MIN"},

11340
    {"bits": [20, 23], "name": "BIN2_MAX"},

11341
    {"bits": [24, 27], "name": "BIN3_MIN"},

11342
    {"bits": [28, 31], "name": "BIN3_MAX"}

11343
   ]

11344
  },

11345
  "SPI_PS_INPUT_CNTL_0": {

11346
   "fields": [

11347
    {"bits": [0, 5], "name": "OFFSET"},

11348
    {"bits": [8, 9], "name": "DEFAULT_VAL"},

11349
    {"bits": [10, 10], "name": "FLAT_SHADE"},

11350
    {"bits": [13, 16], "name": "CYL_WRAP"},

11351
    {"bits": [17, 17], "name": "PT_SPRITE_TEX"},

11352
    {"bits": [18, 18], "name": "DUP"},

11353
    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},

11354
    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},

11355
    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},

11356
    {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},

11357
    {"bits": [24, 24], "name": "ATTR0_VALID"},

11358
    {"bits": [25, 25], "name": "ATTR1_VALID"}

11359
   ]

11360
  },

11361
  "SPI_PS_INPUT_CNTL_20": {

11362
   "fields": [

11363
    {"bits": [0, 5], "name": "OFFSET"},

11364
    {"bits": [8, 9], "name": "DEFAULT_VAL"},

11365
    {"bits": [10, 10], "name": "FLAT_SHADE"},

11366
    {"bits": [18, 18], "name": "DUP"},

11367
    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},

11368
    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},

11369
    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},

11370
    {"bits": [24, 24], "name": "ATTR0_VALID"},

11371
    {"bits": [25, 25], "name": "ATTR1_VALID"}

11372
   ]

11373
  },

11374
  "SPI_PS_INPUT_ENA": {

11375
   "fields": [

11376
    {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},

11377
    {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},

11378
    {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},

11379
    {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},

11380
    {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},

11381
    {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},

11382
    {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},

11383
    {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},

11384
    {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},

11385
    {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},

11386
    {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},

11387
    {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},

11388
    {"bits": [12, 12], "name": "FRONT_FACE_ENA"},

11389
    {"bits": [13, 13], "name": "ANCILLARY_ENA"},

11390
    {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},

11391
    {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}

11392
   ]

11393
  },

11394
  "SPI_PS_IN_CONTROL": {

11395
   "fields": [

11396
    {"bits": [0, 5], "name": "NUM_INTERP"},

11397
    {"bits": [6, 6], "name": "PARAM_GEN"},

11398
    {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"}

11399
   ]

11400
  },

11401
  "SPI_SHADER_COL_FORMAT": {

11402
   "fields": [

11403
    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},

11404
    {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},

11405
    {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},

11406
    {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},

11407
    {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},

11408
    {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},

11409
    {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},

11410
    {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}

11411
   ]

11412
  },

11413
  "SPI_SHADER_LATE_ALLOC_VS": {

11414
   "fields": [

11415
    {"bits": [0, 5], "name": "LIMIT"}

11416
   ]

11417
  },

11418
  "SPI_SHADER_PGM_RSRC1_GS": {

11419
   "fields": [

11420
    {"bits": [0, 5], "name": "VGPRS"},

11421
    {"bits": [6, 9], "name": "SGPRS"},

11422
    {"bits": [10, 11], "name": "PRIORITY"},

11423
    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},

11424
    {"bits": [20, 20], "name": "PRIV"},

11425
    {"bits": [21, 21], "name": "DX10_CLAMP"},

11426
    {"bits": [22, 22], "name": "DEBUG_MODE"},

11427
    {"bits": [23, 23], "name": "IEEE_MODE"},

11428
    {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},

11429
    {"bits": [25, 27], "name": "CACHE_CTL"},

11430
    {"bits": [28, 28], "name": "CDBG_USER"}

11431
   ]

11432
  },

11433
  "SPI_SHADER_PGM_RSRC1_HS": {

11434
   "fields": [

11435
    {"bits": [0, 5], "name": "VGPRS"},

11436
    {"bits": [6, 9], "name": "SGPRS"},

11437
    {"bits": [10, 11], "name": "PRIORITY"},

11438
    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},

11439
    {"bits": [20, 20], "name": "PRIV"},

11440
    {"bits": [21, 21], "name": "DX10_CLAMP"},

11441
    {"bits": [22, 22], "name": "DEBUG_MODE"},

11442
    {"bits": [23, 23], "name": "IEEE_MODE"},

11443
    {"bits": [24, 26], "name": "CACHE_CTL"},

11444
    {"bits": [27, 27], "name": "CDBG_USER"}

11445
   ]

11446
  },

11447
  "SPI_SHADER_PGM_RSRC1_LS": {

11448
   "fields": [

11449
    {"bits": [0, 5], "name": "VGPRS"},

11450
    {"bits": [6, 9], "name": "SGPRS"},

11451
    {"bits": [10, 11], "name": "PRIORITY"},

11452
    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},

11453
    {"bits": [20, 20], "name": "PRIV"},

11454
    {"bits": [21, 21], "name": "DX10_CLAMP"},

11455
    {"bits": [22, 22], "name": "DEBUG_MODE"},

11456
    {"bits": [23, 23], "name": "IEEE_MODE"},

11457
    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},

11458
    {"bits": [26, 28], "name": "CACHE_CTL"},

11459
    {"bits": [29, 29], "name": "CDBG_USER"}

11460
   ]

11461
  },

11462
  "SPI_SHADER_PGM_RSRC1_PS": {

11463
   "fields": [

11464
    {"bits": [0, 5], "name": "VGPRS"},

11465
    {"bits": [6, 9], "name": "SGPRS"},

11466
    {"bits": [10, 11], "name": "PRIORITY"},

11467
    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},

11468
    {"bits": [20, 20], "name": "PRIV"},

11469
    {"bits": [21, 21], "name": "DX10_CLAMP"},

11470
    {"bits": [22, 22], "name": "DEBUG_MODE"},

11471
    {"bits": [23, 23], "name": "IEEE_MODE"},

11472
    {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},

11473
    {"bits": [25, 27], "name": "CACHE_CTL"},

11474
    {"bits": [28, 28], "name": "CDBG_USER"}

11475
   ]

11476
  },

11477
  "SPI_SHADER_PGM_RSRC1_VS": {

11478
   "fields": [

11479
    {"bits": [0, 5], "name": "VGPRS"},

11480
    {"bits": [6, 9], "name": "SGPRS"},

11481
    {"bits": [10, 11], "name": "PRIORITY"},

11482
    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},

11483
    {"bits": [20, 20], "name": "PRIV"},

11484
    {"bits": [21, 21], "name": "DX10_CLAMP"},

11485
    {"bits": [22, 22], "name": "DEBUG_MODE"},

11486
    {"bits": [23, 23], "name": "IEEE_MODE"},

11487
    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},

11488
    {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},

11489
    {"bits": [27, 29], "name": "CACHE_CTL"},

11490
    {"bits": [30, 30], "name": "CDBG_USER"}

11491
   ]

11492
  },

11493
  "SPI_SHADER_PGM_RSRC2_ES_VS": {

11494
   "fields": [

11495
    {"bits": [0, 0], "name": "SCRATCH_EN"},

11496
    {"bits": [1, 5], "name": "USER_SGPR"},

11497
    {"bits": [6, 6], "name": "TRAP_PRESENT"},

11498
    {"bits": [7, 7], "name": "OC_LDS_EN"},

11499
    {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},

11500
    {"bits": [20, 28], "name": "LDS_SIZE"}

11501
   ]

11502
  },

11503
  "SPI_SHADER_PGM_RSRC2_GS": {

11504
   "fields": [

11505
    {"bits": [0, 0], "name": "SCRATCH_EN"},

11506
    {"bits": [1, 5], "name": "USER_SGPR"},

11507
    {"bits": [6, 6], "name": "TRAP_PRESENT"},

11508
    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}

11509
   ]

11510
  },

11511
  "SPI_SHADER_PGM_RSRC2_HS": {

11512
   "fields": [

11513
    {"bits": [0, 0], "name": "SCRATCH_EN"},

11514
    {"bits": [1, 5], "name": "USER_SGPR"},

11515
    {"bits": [6, 6], "name": "TRAP_PRESENT"},

11516
    {"bits": [7, 7], "name": "OC_LDS_EN"},

11517
    {"bits": [8, 8], "name": "TG_SIZE_EN"},

11518
    {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}

11519
   ]

11520
  },

11521
  "SPI_SHADER_PGM_RSRC2_LS_VS": {

11522
   "fields": [

11523
    {"bits": [0, 0], "name": "SCRATCH_EN"},

11524
    {"bits": [1, 5], "name": "USER_SGPR"},

11525
    {"bits": [6, 6], "name": "TRAP_PRESENT"},

11526
    {"bits": [7, 15], "name": "LDS_SIZE"},

11527
    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}

11528
   ]

11529
  },

11530
  "SPI_SHADER_PGM_RSRC2_PS": {

11531
   "fields": [

11532
    {"bits": [0, 0], "name": "SCRATCH_EN"},

11533
    {"bits": [1, 5], "name": "USER_SGPR"},

11534
    {"bits": [6, 6], "name": "TRAP_PRESENT"},

11535
    {"bits": [7, 7], "name": "WAVE_CNT_EN"},

11536
    {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},

11537
    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}

11538
   ]

11539
  },

11540
  "SPI_SHADER_PGM_RSRC2_VS": {

11541
   "fields": [

11542
    {"bits": [0, 0], "name": "SCRATCH_EN"},

11543
    {"bits": [1, 5], "name": "USER_SGPR"},

11544
    {"bits": [6, 6], "name": "TRAP_PRESENT"},

11545
    {"bits": [7, 7], "name": "OC_LDS_EN"},

11546
    {"bits": [8, 8], "name": "SO_BASE0_EN"},

11547
    {"bits": [9, 9], "name": "SO_BASE1_EN"},

11548
    {"bits": [10, 10], "name": "SO_BASE2_EN"},

11549
    {"bits": [11, 11], "name": "SO_BASE3_EN"},

11550
    {"bits": [12, 12], "name": "SO_EN"},

11551
    {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},

11552
    {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"}

11553
   ]

11554
  },

11555
  "SPI_SHADER_PGM_RSRC3_GS": {

11556
   "fields": [

11557
    {"bits": [0, 15], "name": "CU_EN"},

11558
    {"bits": [16, 21], "name": "WAVE_LIMIT"},

11559
    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},

11560
    {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"}

11561
   ]

11562
  },

11563
  "SPI_SHADER_PGM_RSRC3_HS": {

11564
   "fields": [

11565
    {"bits": [0, 5], "name": "WAVE_LIMIT"},

11566
    {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},

11567
    {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"}

11568
   ]

11569
  },

11570
  "SPI_SHADER_PGM_RSRC3_PS": {

11571
   "fields": [

11572
    {"bits": [0, 15], "name": "CU_EN"},

11573
    {"bits": [16, 21], "name": "WAVE_LIMIT"},

11574
    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}

11575
   ]

11576
  },

11577
  "SPI_SHADER_POS_FORMAT": {

11578
   "fields": [

11579
    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},

11580
    {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},

11581
    {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},

11582
    {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"}

11583
   ]

11584
  },

11585
  "SPI_SHADER_TBA_HI_PS": {

11586
   "fields": [

11587
    {"bits": [0, 7], "name": "MEM_BASE"}

11588
   ]

11589
  },

11590
  "SPI_SHADER_Z_FORMAT": {

11591
   "fields": [

11592
    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}

11593
   ]

11594
  },

11595
  "SPI_VS_OUT_CONFIG": {

11596
   "fields": [

11597
    {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},

11598
    {"bits": [6, 6], "name": "VS_HALF_PACK"}

11599
   ]

11600
  },

11601
  "SQC_CACHES": {

11602
   "fields": [

11603
    {"bits": [0, 0], "name": "TARGET_INST"},

11604
    {"bits": [1, 1], "name": "TARGET_DATA"},

11605
    {"bits": [2, 2], "name": "INVALIDATE"},

11606
    {"bits": [3, 3], "name": "WRITEBACK"},

11607
    {"bits": [4, 4], "name": "VOL"},

11608
    {"bits": [16, 16], "name": "COMPLETE"}

11609
   ]

11610
  },

11611
  "SQC_WRITEBACK": {

11612
   "fields": [

11613
    {"bits": [0, 0], "name": "DWB"},

11614
    {"bits": [1, 1], "name": "DIRTY"}

11615
   ]

11616
  },

11617
  "SQ_BUF_RSRC_WORD1": {

11618
   "fields": [

11619
    {"bits": [0, 15], "name": "BASE_ADDRESS_HI"},

11620
    {"bits": [16, 29], "name": "STRIDE"},

11621
    {"bits": [30, 30], "name": "CACHE_SWIZZLE"},

11622
    {"bits": [31, 31], "name": "SWIZZLE_ENABLE"}

11623
   ]

11624
  },

11625
  "SQ_BUF_RSRC_WORD3": {

11626
   "fields": [

11627
    {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},

11628
    {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},

11629
    {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},

11630
    {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},

11631
    {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"},

11632
    {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"},

11633
    {"bits": [19, 20], "name": "ELEMENT_SIZE"},

11634
    {"bits": [21, 22], "name": "INDEX_STRIDE"},

11635
    {"bits": [23, 23], "name": "ADD_TID_ENABLE"},

11636
    {"bits": [24, 24], "name": "ATC"},

11637
    {"bits": [25, 25], "name": "HASH_ENABLE"},

11638
    {"bits": [26, 26], "name": "HEAP"},

11639
    {"bits": [27, 29], "name": "MTYPE"},

11640
    {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"}

11641
   ]

11642
  },

11643
  "SQ_IMG_RSRC_WORD1": {

11644
   "fields": [

11645
    {"bits": [0, 7], "name": "BASE_ADDRESS_HI"},

11646
    {"bits": [8, 19], "name": "MIN_LOD"},

11647
    {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"},

11648
    {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"},

11649
    {"bits": [30, 31], "name": "MTYPE"}

11650
   ]

11651
  },

11652
  "SQ_IMG_RSRC_WORD2": {

11653
   "fields": [

11654
    {"bits": [0, 13], "name": "WIDTH"},

11655
    {"bits": [14, 27], "name": "HEIGHT"},

11656
    {"bits": [28, 30], "name": "PERF_MOD"},

11657
    {"bits": [31, 31], "name": "INTERLACED"}

11658
   ]

11659
  },

11660
  "SQ_IMG_RSRC_WORD3": {

11661
   "fields": [

11662
    {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},

11663
    {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},

11664
    {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},

11665
    {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},

11666
    {"bits": [12, 15], "name": "BASE_LEVEL"},

11667
    {"bits": [16, 19], "name": "LAST_LEVEL"},

11668
    {"bits": [20, 24], "name": "TILING_INDEX"},

11669
    {"bits": [25, 25], "name": "POW2_PAD"},

11670
    {"bits": [26, 26], "name": "MTYPE"},

11671
    {"bits": [27, 27], "name": "ATC"},

11672
    {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"}

11673
   ]

11674
  },

11675
  "SQ_IMG_RSRC_WORD4": {

11676
   "fields": [

11677
    {"bits": [0, 12], "name": "DEPTH"},

11678
    {"bits": [13, 26], "name": "PITCH"}

11679
   ]

11680
  },

11681
  "SQ_IMG_RSRC_WORD5": {

11682
   "fields": [

11683
    {"bits": [0, 12], "name": "BASE_ARRAY"},

11684
    {"bits": [13, 25], "name": "LAST_ARRAY"}

11685
   ]

11686
  },

11687
  "SQ_IMG_RSRC_WORD6": {

11688
   "fields": [

11689
    {"bits": [0, 11], "name": "MIN_LOD_WARN"},

11690
    {"bits": [12, 19], "name": "COUNTER_BANK_ID"},

11691
    {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"},

11692
    {"bits": [21, 21], "name": "COMPRESSION_EN"},

11693
    {"bits": [22, 22], "name": "ALPHA_IS_ON_MSB"},

11694
    {"bits": [23, 23], "name": "COLOR_TRANSFORM"},

11695
    {"bits": [24, 27], "name": "LOST_ALPHA_BITS"},

11696
    {"bits": [28, 31], "name": "LOST_COLOR_BITS"}

11697
   ]

11698
  },

11699
  "SQ_IMG_SAMP_WORD0": {

11700
   "fields": [

11701
    {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"},

11702
    {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"},

11703
    {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"},

11704
    {"bits": [9, 11], "name": "MAX_ANISO_RATIO"},

11705
    {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"},

11706
    {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"},

11707
    {"bits": [16, 18], "name": "ANISO_THRESHOLD"},

11708
    {"bits": [19, 19], "name": "MC_COORD_TRUNC"},

11709
    {"bits": [20, 20], "name": "FORCE_DEGAMMA"},

11710
    {"bits": [21, 26], "name": "ANISO_BIAS"},

11711
    {"bits": [27, 27], "name": "TRUNC_COORD"},

11712
    {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"},

11713
    {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"},

11714
    {"bits": [31, 31], "name": "COMPAT_MODE"}

11715
   ]

11716
  },

11717
  "SQ_IMG_SAMP_WORD1": {

11718
   "fields": [

11719
    {"bits": [0, 11], "name": "MIN_LOD"},

11720
    {"bits": [12, 23], "name": "MAX_LOD"},

11721
    {"bits": [24, 27], "name": "PERF_MIP"},

11722
    {"bits": [28, 31], "name": "PERF_Z"}

11723
   ]

11724
  },

11725
  "SQ_IMG_SAMP_WORD2": {

11726
   "fields": [

11727
    {"bits": [0, 13], "name": "LOD_BIAS"},

11728
    {"bits": [14, 19], "name": "LOD_BIAS_SEC"},

11729
    {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"},

11730
    {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"},

11731
    {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"},

11732
    {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"},

11733
    {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"},

11734
    {"bits": [29, 29], "name": "DISABLE_LSB_CEIL"},

11735
    {"bits": [30, 30], "name": "FILTER_PREC_FIX"},

11736
    {"bits": [31, 31], "name": "ANISO_OVERRIDE"}

11737
   ]

11738
  },

11739
  "SQ_IMG_SAMP_WORD3": {

11740
   "fields": [

11741
    {"bits": [0, 11], "name": "BORDER_COLOR_PTR"},

11742
    {"bits": [29, 29], "name": "UPGRADED_DEPTH"},

11743
    {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"}

11744
   ]

11745
  },

11746
  "SQ_PERFCOUNTER0_SELECT": {

11747
   "fields": [

11748
    {"bits": [0, 8], "name": "PERF_SEL"},

11749
    {"bits": [12, 15], "name": "SQC_BANK_MASK"},

11750
    {"bits": [16, 19], "name": "SQC_CLIENT_MASK"},

11751
    {"bits": [20, 23], "name": "SPM_MODE"},

11752
    {"bits": [24, 27], "name": "SIMD_MASK"},

11753
    {"bits": [28, 31], "name": "PERF_MODE"}

11754
   ]

11755
  },

11756
  "SQ_PERFCOUNTER_CTRL": {

11757
   "fields": [

11758
    {"bits": [0, 0], "name": "PS_EN"},

11759
    {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},

11760
    {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},

11761
    {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},

11762
    {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},

11763
    {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},

11764
    {"bits": [6, 6], "name": "CS_EN"},

11765
    {"bits": [8, 12], "name": "CNTR_RATE"},

11766
    {"bits": [13, 13], "name": "DISABLE_FLUSH"}

11767
   ]

11768
  },

11769
  "SQ_PERFCOUNTER_CTRL2": {

11770
   "fields": [

11771
    {"bits": [0, 0], "name": "FORCE_EN"}

11772
   ]

11773
  },

11774
  "SQ_PERFCOUNTER_MASK": {

11775
   "fields": [

11776
    {"bits": [0, 15], "name": "SH0_MASK"},

11777
    {"bits": [16, 31], "name": "SH1_MASK"}

11778
   ]

11779
  },

11780
  "SQ_THREAD_TRACE_BASE2": {

11781
   "fields": [

11782
    {"bits": [0, 3], "name": "ADDR_HI"}

11783
   ]

11784
  },

11785
  "SQ_THREAD_TRACE_CTRL": {

11786
   "fields": [

11787
    {"bits": [31, 31], "name": "RESET_BUFFER"}

11788
   ]

11789
  },

11790
  "SQ_THREAD_TRACE_HIWATER": {

11791
   "fields": [

11792
    {"bits": [0, 2], "name": "HIWATER"}

11793
   ]

11794
  },

11795
  "SQ_THREAD_TRACE_MASK": {

11796
   "fields": [

11797
    {"bits": [0, 4], "name": "CU_SEL"},

11798
    {"bits": [5, 5], "name": "SH_SEL"},

11799
    {"bits": [7, 7], "name": "REG_STALL_EN"},

11800
    {"bits": [8, 11], "name": "SIMD_EN"},

11801
    {"bits": [12, 13], "name": "VM_ID_MASK"},

11802
    {"bits": [14, 14], "name": "SPI_STALL_EN"},

11803
    {"bits": [15, 15], "name": "SQ_STALL_EN"},

11804
    {"bits": [16, 31], "name": "RANDOM_SEED"}

11805
   ]

11806
  },

11807
  "SQ_THREAD_TRACE_MODE": {

11808
   "fields": [

11809
    {"bits": [0, 2], "name": "MASK_PS"},

11810
    {"bits": [3, 5], "name": "MASK_VS"},

11811
    {"bits": [6, 8], "name": "MASK_GS"},

11812
    {"bits": [9, 11], "name": "MASK_ES"},

11813
    {"bits": [12, 14], "name": "MASK_HS"},

11814
    {"bits": [15, 17], "name": "MASK_LS"},

11815
    {"bits": [18, 20], "name": "MASK_CS"},

11816
    {"bits": [21, 22], "name": "MODE"},

11817
    {"bits": [23, 24], "name": "CAPTURE_MODE"},

11818
    {"bits": [25, 25], "name": "AUTOFLUSH_EN"},

11819
    {"bits": [26, 26], "name": "PRIV"},

11820
    {"bits": [27, 28], "name": "ISSUE_MASK"},

11821
    {"bits": [29, 29], "name": "TEST_MODE"},

11822
    {"bits": [30, 30], "name": "INTERRUPT_EN"},

11823
    {"bits": [31, 31], "name": "WRAP"}

11824
   ]

11825
  },

11826
  "SQ_THREAD_TRACE_SIZE": {

11827
   "fields": [

11828
    {"bits": [0, 21], "name": "SIZE"}

11829
   ]

11830
  },

11831
  "SQ_THREAD_TRACE_STATUS": {

11832
   "fields": [

11833
    {"bits": [0, 9], "name": "FINISH_PENDING"},

11834
    {"bits": [16, 25], "name": "FINISH_DONE"},

11835
    {"bits": [29, 29], "name": "NEW_BUF"},

11836
    {"bits": [30, 30], "name": "BUSY"},

11837
    {"bits": [31, 31], "name": "FULL"}

11838
   ]

11839
  },

11840
  "SQ_THREAD_TRACE_TOKEN_MASK": {

11841
   "fields": [

11842
    {"bits": [0, 15], "name": "TOKEN_MASK"},

11843
    {"bits": [16, 23], "name": "REG_MASK"},

11844
    {"bits": [24, 24], "name": "REG_DROP_ON_STALL"}

11845
   ]

11846
  },

11847
  "SQ_THREAD_TRACE_WPTR": {

11848
   "fields": [

11849
    {"bits": [0, 29], "name": "WPTR"},

11850
    {"bits": [30, 31], "name": "READ_OFFSET"}

11851
   ]

11852
  },

11853
  "SQ_WAVE_GPR_ALLOC": {

11854
   "fields": [

11855
    {"bits": [0, 5], "name": "VGPR_BASE"},

11856
    {"bits": [8, 13], "name": "VGPR_SIZE"},

11857
    {"bits": [16, 21], "name": "SGPR_BASE"},

11858
    {"bits": [24, 27], "name": "SGPR_SIZE"}

11859
   ]

11860
  },

11861
  "SQ_WAVE_HW_ID": {

11862
   "fields": [

11863
    {"bits": [0, 3], "name": "WAVE_ID"},

11864
    {"bits": [4, 5], "name": "SIMD_ID"},

11865
    {"bits": [6, 7], "name": "PIPE_ID"},

11866
    {"bits": [8, 11], "name": "CU_ID"},

11867
    {"bits": [12, 12], "name": "SH_ID"},

11868
    {"bits": [13, 14], "name": "SE_ID"},

11869
    {"bits": [16, 19], "name": "TG_ID"},

11870
    {"bits": [20, 23], "name": "VM_ID"},

11871
    {"bits": [24, 26], "name": "QUEUE_ID"},

11872
    {"bits": [27, 29], "name": "STATE_ID"},

11873
    {"bits": [30, 31], "name": "ME_ID"}

11874
   ]

11875
  },

11876
  "SQ_WAVE_IB_DBG0": {

11877
   "fields": [

11878
    {"bits": [0, 2], "name": "IBUF_ST"},

11879
    {"bits": [3, 3], "name": "PC_INVALID"},

11880
    {"bits": [4, 4], "name": "NEED_NEXT_DW"},

11881
    {"bits": [5, 7], "name": "NO_PREFETCH_CNT"},

11882
    {"bits": [8, 9], "name": "IBUF_RPTR"},

11883
    {"bits": [10, 11], "name": "IBUF_WPTR"},

11884
    {"bits": [16, 19], "name": "INST_STR_ST"},

11885
    {"bits": [20, 23], "name": "MISC_CNT"},

11886
    {"bits": [24, 25], "name": "ECC_ST"},

11887
    {"bits": [26, 26], "name": "IS_HYB"},

11888
    {"bits": [27, 28], "name": "HYB_CNT"},

11889
    {"bits": [29, 29], "name": "KILL"},

11890
    {"bits": [30, 30], "name": "NEED_KILL_IFETCH"}

11891
   ]

11892
  },

11893
  "SQ_WAVE_IB_DBG1": {

11894
   "fields": [

11895
    {"bits": [0, 0], "name": "IXNACK"},

11896
    {"bits": [1, 1], "name": "XNACK"},

11897
    {"bits": [2, 2], "name": "TA_NEED_RESET"},

11898
    {"bits": [4, 7], "name": "XCNT"},

11899
    {"bits": [8, 11], "name": "QCNT"}

11900
   ]

11901
  },

11902
  "SQ_WAVE_IB_STS": {

11903
   "fields": [

11904
    {"bits": [0, 3], "name": "VM_CNT"},

11905
    {"bits": [4, 6], "name": "EXP_CNT"},

11906
    {"bits": [8, 11], "name": "LGKM_CNT"},

11907
    {"bits": [12, 14], "name": "VALU_CNT"},

11908
    {"bits": [15, 15], "name": "FIRST_REPLAY"},

11909
    {"bits": [16, 19], "name": "RCNT"}

11910
   ]

11911
  },

11912
  "SQ_WAVE_LDS_ALLOC": {

11913
   "fields": [

11914
    {"bits": [0, 7], "name": "LDS_BASE"},

11915
    {"bits": [12, 20], "name": "LDS_SIZE"}

11916
   ]

11917
  },

11918
  "SQ_WAVE_MODE": {

11919
   "fields": [

11920
    {"bits": [0, 3], "name": "FP_ROUND"},

11921
    {"bits": [4, 7], "name": "FP_DENORM"},

11922
    {"bits": [8, 8], "name": "DX10_CLAMP"},

11923
    {"bits": [9, 9], "name": "IEEE"},

11924
    {"bits": [10, 10], "name": "LOD_CLAMPED"},

11925
    {"bits": [11, 11], "name": "DEBUG_EN"},

11926
    {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},

11927
    {"bits": [27, 27], "name": "GPR_IDX_EN"},

11928
    {"bits": [28, 28], "name": "VSKIP"},

11929
    {"bits": [29, 31], "name": "CSP"}

11930
   ]

11931
  },

11932
  "SQ_WAVE_PC_HI": {

11933
   "fields": [

11934
    {"bits": [0, 15], "name": "PC_HI"}

11935
   ]

11936
  },

11937
  "SQ_WAVE_STATUS": {

11938
   "fields": [

11939
    {"bits": [0, 0], "name": "SCC"},

11940
    {"bits": [1, 2], "name": "SPI_PRIO"},

11941
    {"bits": [3, 4], "name": "USER_PRIO"},

11942
    {"bits": [5, 5], "name": "PRIV"},

11943
    {"bits": [6, 6], "name": "TRAP_EN"},

11944
    {"bits": [7, 7], "name": "TTRACE_EN"},

11945
    {"bits": [8, 8], "name": "EXPORT_RDY"},

11946
    {"bits": [9, 9], "name": "EXECZ"},

11947
    {"bits": [10, 10], "name": "VCCZ"},

11948
    {"bits": [11, 11], "name": "IN_TG"},

11949
    {"bits": [12, 12], "name": "IN_BARRIER"},

11950
    {"bits": [13, 13], "name": "HALT"},

11951
    {"bits": [14, 14], "name": "TRAP"},

11952
    {"bits": [15, 15], "name": "TTRACE_CU_EN"},

11953
    {"bits": [16, 16], "name": "VALID"},

11954
    {"bits": [17, 17], "name": "ECC_ERR"},

11955
    {"bits": [18, 18], "name": "SKIP_EXPORT"},

11956
    {"bits": [19, 19], "name": "PERF_EN"},

11957
    {"bits": [20, 20], "name": "COND_DBG_USER"},

11958
    {"bits": [21, 21], "name": "COND_DBG_SYS"},

11959
    {"bits": [22, 22], "name": "ALLOW_REPLAY"},

11960
    {"bits": [23, 23], "name": "INST_ATC"},

11961
    {"bits": [27, 27], "name": "MUST_EXPORT"}

11962
   ]

11963
  },

11964
  "SQ_WAVE_TBA_HI": {

11965
   "fields": [

11966
    {"bits": [0, 7], "name": "ADDR_HI"}

11967
   ]

11968
  },

11969
  "SQ_WAVE_TRAPSTS": {

11970
   "fields": [

11971
    {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},

11972
    {"bits": [10, 10], "name": "SAVECTX"},

11973
    {"bits": [16, 21], "name": "EXCP_CYCLE"},

11974
    {"bits": [29, 31], "name": "DP_RATE"}

11975
   ]

11976
  },

11977
  "SX_BLEND_OPT_CONTROL": {

11978
   "fields": [

11979
    {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},

11980
    {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},

11981
    {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},

11982
    {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},

11983
    {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},

11984
    {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},

11985
    {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},

11986
    {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},

11987
    {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},

11988
    {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},

11989
    {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},

11990
    {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},

11991
    {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},

11992
    {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},

11993
    {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},

11994
    {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},

11995
    {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}

11996
   ]

11997
  },

11998
  "SX_BLEND_OPT_EPSILON": {

11999
   "fields": [

12000
    {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},

12001
    {"bits": [4, 7], "name": "MRT1_EPSILON"},

12002
    {"bits": [8, 11], "name": "MRT2_EPSILON"},

12003
    {"bits": [12, 15], "name": "MRT3_EPSILON"},

12004
    {"bits": [16, 19], "name": "MRT4_EPSILON"},

12005
    {"bits": [20, 23], "name": "MRT5_EPSILON"},

12006
    {"bits": [24, 27], "name": "MRT6_EPSILON"},

12007
    {"bits": [28, 31], "name": "MRT7_EPSILON"}

12008
   ]

12009
  },

12010
  "SX_MRT0_BLEND_OPT": {

12011
   "fields": [

12012
    {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},

12013
    {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},

12014
    {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},

12015
    {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},

12016
    {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},

12017
    {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}

12018
   ]

12019
  },

12020
  "SX_PERFCOUNTER0_SELECT": {

12021
   "fields": [

12022
    {"bits": [0, 9], "name": "PERFCOUNTER_SELECT"},

12023
    {"bits": [10, 19], "name": "PERFCOUNTER_SELECT1"},

12024
    {"bits": [20, 23], "name": "CNTR_MODE"}

12025
   ]

12026
  },

12027
  "SX_PERFCOUNTER0_SELECT1": {

12028
   "fields": [

12029
    {"bits": [0, 9], "name": "PERFCOUNTER_SELECT2"},

12030
    {"bits": [10, 19], "name": "PERFCOUNTER_SELECT3"}

12031
   ]

12032
  },

12033
  "SX_PS_DOWNCONVERT": {

12034
   "fields": [

12035
    {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},

12036
    {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},

12037
    {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},

12038
    {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},

12039
    {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},

12040
    {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},

12041
    {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},

12042
    {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}

12043
   ]

12044
  },

12045
  "TA_BC_BASE_ADDR_HI": {

12046
   "fields": [

12047
    {"bits": [0, 7], "name": "ADDRESS"}

12048
   ]

12049
  },

12050
  "TCC_PERFCOUNTER0_SELECT1": {

12051
   "fields": [

12052
    {"bits": [0, 9], "name": "PERF_SEL2"},

12053
    {"bits": [10, 19], "name": "PERF_SEL3"},

12054
    {"bits": [24, 27], "name": "PERF_MODE2"},

12055
    {"bits": [28, 31], "name": "PERF_MODE3"}

12056
   ]

12057
  },

12058
  "TCC_PERFCOUNTER2_SELECT": {

12059
   "fields": [

12060
    {"bits": [0, 9], "name": "PERF_SEL"},

12061
    {"bits": [20, 23], "name": "CNTR_MODE"},

12062
    {"bits": [28, 31], "name": "PERF_MODE"}

12063
   ]

12064
  },

12065
  "TD_PERFCOUNTER0_SELECT": {

12066
   "fields": [

12067
    {"bits": [0, 7], "name": "PERF_SEL"},

12068
    {"bits": [10, 17], "name": "PERF_SEL1"},

12069
    {"bits": [20, 23], "name": "CNTR_MODE"},

12070
    {"bits": [24, 27], "name": "PERF_MODE1"},

12071
    {"bits": [28, 31], "name": "PERF_MODE"}

12072
   ]

12073
  },

12074
  "TD_PERFCOUNTER0_SELECT1": {

12075
   "fields": [

12076
    {"bits": [0, 7], "name": "PERF_SEL2"},

12077
    {"bits": [10, 17], "name": "PERF_SEL3"},

12078
    {"bits": [24, 27], "name": "PERF_MODE3"},

12079
    {"bits": [28, 31], "name": "PERF_MODE2"}

12080
   ]

12081
  },

12082
  "VGT_DMA_BASE_HI": {

12083
   "fields": [

12084
    {"bits": [0, 7], "name": "BASE_ADDR"}

12085
   ]

12086
  },

12087
  "VGT_DMA_INDEX_TYPE": {

12088
   "fields": [

12089
    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},

12090
    {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},

12091
    {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},

12092
    {"bits": [6, 6], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},

12093
    {"bits": [9, 9], "name": "NOT_EOP"},

12094
    {"bits": [10, 10], "name": "REQ_PATH"},

12095
    {"bits": [11, 12], "name": "MTYPE"}

12096
   ]

12097
  },

12098
  "VGT_DRAW_INITIATOR": {

12099
   "fields": [

12100
    {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},

12101
    {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},

12102
    {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},

12103
    {"bits": [5, 5], "name": "NOT_EOP"},

12104
    {"bits": [6, 6], "name": "USE_OPAQUE"}

12105
   ]

12106
  },

12107
  "VGT_ESGS_RING_ITEMSIZE": {

12108
   "fields": [

12109
    {"bits": [0, 14], "name": "ITEMSIZE"}

12110
   ]

12111
  },

12112
  "VGT_ES_PER_GS": {

12113
   "fields": [

12114
    {"bits": [0, 10], "name": "ES_PER_GS"}

12115
   ]

12116
  },

12117
  "VGT_EVENT_ADDRESS_REG": {

12118
   "fields": [

12119
    {"bits": [0, 27], "name": "ADDRESS_LOW"}

12120
   ]

12121
  },

12122
  "VGT_EVENT_INITIATOR": {

12123
   "fields": [

12124
    {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},

12125
    {"bits": [18, 26], "name": "ADDRESS_HI"},

12126
    {"bits": [27, 27], "name": "EXTENDED_EVENT"}

12127
   ]

12128
  },

12129
  "VGT_GROUP_DECR": {

12130
   "fields": [

12131
    {"bits": [0, 3], "name": "DECR"}

12132
   ]

12133
  },

12134
  "VGT_GROUP_FIRST_DECR": {

12135
   "fields": [

12136
    {"bits": [0, 3], "name": "FIRST_DECR"}

12137
   ]

12138
  },

12139
  "VGT_GROUP_PRIM_TYPE": {

12140
   "fields": [

12141
    {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},

12142
    {"bits": [14, 14], "name": "RETAIN_ORDER"},

12143
    {"bits": [15, 15], "name": "RETAIN_QUADS"},

12144
    {"bits": [16, 18], "name": "PRIM_ORDER"}

12145
   ]

12146
  },

12147
  "VGT_GROUP_VECT_0_CNTL": {

12148
   "fields": [

12149
    {"bits": [0, 0], "name": "COMP_X_EN"},

12150
    {"bits": [1, 1], "name": "COMP_Y_EN"},

12151
    {"bits": [2, 2], "name": "COMP_Z_EN"},

12152
    {"bits": [3, 3], "name": "COMP_W_EN"},

12153
    {"bits": [8, 15], "name": "STRIDE"},

12154
    {"bits": [16, 23], "name": "SHIFT"}

12155
   ]

12156
  },

12157
  "VGT_GROUP_VECT_0_FMT_CNTL": {

12158
   "fields": [

12159
    {"bits": [0, 3], "name": "X_CONV"},

12160
    {"bits": [4, 7], "name": "X_OFFSET"},

12161
    {"bits": [8, 11], "name": "Y_CONV"},

12162
    {"bits": [12, 15], "name": "Y_OFFSET"},

12163
    {"bits": [16, 19], "name": "Z_CONV"},

12164
    {"bits": [20, 23], "name": "Z_OFFSET"},

12165
    {"bits": [24, 27], "name": "W_CONV"},

12166
    {"bits": [28, 31], "name": "W_OFFSET"}

12167
   ]

12168
  },

12169
  "VGT_GSVS_RING_OFFSET_1": {

12170
   "fields": [

12171
    {"bits": [0, 14], "name": "OFFSET"}

12172
   ]

12173
  },

12174
  "VGT_GS_INSTANCE_CNT": {

12175
   "fields": [

12176
    {"bits": [0, 0], "name": "ENABLE"},

12177
    {"bits": [2, 8], "name": "CNT"}

12178
   ]

12179
  },

12180
  "VGT_GS_MAX_VERT_OUT": {

12181
   "fields": [

12182
    {"bits": [0, 10], "name": "MAX_VERT_OUT"}

12183
   ]

12184
  },

12185
  "VGT_GS_MODE": {

12186
   "fields": [

12187
    {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},

12188
    {"bits": [3, 3], "name": "RESERVED_0"},

12189
    {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},

12190
    {"bits": [6, 10], "name": "RESERVED_1"},

12191
    {"bits": [11, 11], "name": "GS_C_PACK_EN"},

12192
    {"bits": [12, 12], "name": "RESERVED_2"},

12193
    {"bits": [13, 13], "name": "ES_PASSTHRU"},

12194
    {"bits": [14, 14], "name": "RESERVED_3"},

12195
    {"bits": [15, 15], "name": "RESERVED_4"},

12196
    {"bits": [16, 16], "name": "RESERVED_5"},

12197
    {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},

12198
    {"bits": [18, 18], "name": "SUPPRESS_CUTS"},

12199
    {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},

12200
    {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},

12201
    {"bits": [21, 22], "name": "ONCHIP"}

12202
   ]

12203
  },

12204
  "VGT_GS_ONCHIP_CNTL": {

12205
   "fields": [

12206
    {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"},

12207
    {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"}

12208
   ]

12209
  },

12210
  "VGT_GS_OUT_PRIM_TYPE": {

12211
   "fields": [

12212
    {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},

12213
    {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},

12214
    {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},

12215
    {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},

12216
    {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}

12217
   ]

12218
  },

12219
  "VGT_GS_PER_ES": {

12220
   "fields": [

12221
    {"bits": [0, 10], "name": "GS_PER_ES"}

12222
   ]

12223
  },

12224
  "VGT_GS_PER_VS": {

12225
   "fields": [

12226
    {"bits": [0, 3], "name": "GS_PER_VS"}

12227
   ]

12228
  },

12229
  "VGT_HOS_CNTL": {

12230
   "fields": [

12231
    {"bits": [0, 1], "name": "TESS_MODE"}

12232
   ]

12233
  },

12234
  "VGT_HOS_REUSE_DEPTH": {

12235
   "fields": [

12236
    {"bits": [0, 7], "name": "REUSE_DEPTH"}

12237
   ]

12238
  },

12239
  "VGT_HS_OFFCHIP_PARAM": {

12240
   "fields": [

12241
    {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"},

12242
    {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}

12243
   ]

12244
  },

12245
  "VGT_LS_HS_CONFIG": {

12246
   "fields": [

12247
    {"bits": [0, 7], "name": "NUM_PATCHES"},

12248
    {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},

12249
    {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}

12250
   ]

12251
  },

12252
  "VGT_MULTI_PRIM_IB_RESET_EN": {

12253
   "fields": [

12254
    {"bits": [0, 0], "name": "RESET_EN"}

12255
   ]

12256
  },

12257
  "VGT_OUTPUT_PATH_CNTL": {

12258
   "fields": [

12259
    {"bits": [0, 2], "name": "PATH_SELECT"}

12260
   ]

12261
  },

12262
  "VGT_OUT_DEALLOC_CNTL": {

12263
   "fields": [

12264
    {"bits": [0, 6], "name": "DEALLOC_DIST"}

12265
   ]

12266
  },

12267
  "VGT_PERFCOUNTER2_SELECT": {

12268
   "fields": [

12269
    {"bits": [0, 7], "name": "PERF_SEL"},

12270
    {"bits": [28, 31], "name": "PERF_MODE"}

12271
   ]

12272
  },

12273
  "VGT_PERFCOUNTER_SEID_MASK": {

12274
   "fields": [

12275
    {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"}

12276
   ]

12277
  },

12278
  "VGT_PRIMITIVEID_EN": {

12279
   "fields": [

12280
    {"bits": [0, 0], "name": "PRIMITIVEID_EN"},

12281
    {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"}

12282
   ]

12283
  },

12284
  "VGT_PRIMITIVE_TYPE": {

12285
   "fields": [

12286
    {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}

12287
   ]

12288
  },

12289
  "VGT_REUSE_OFF": {

12290
   "fields": [

12291
    {"bits": [0, 0], "name": "REUSE_OFF"}

12292
   ]

12293
  },

12294
  "VGT_SHADER_STAGES_EN": {

12295
   "fields": [

12296
    {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},

12297
    {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},

12298
    {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},

12299
    {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},

12300
    {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},

12301
    {"bits": [8, 8], "name": "DYNAMIC_HS"},

12302
    {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"},

12303
    {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"},

12304
    {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"},

12305
    {"bits": [12, 12], "name": "VS_WAVE_ID_EN"}

12306
   ]

12307
  },

12308
  "VGT_STRMOUT_BUFFER_CONFIG": {

12309
   "fields": [

12310
    {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},

12311
    {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},

12312
    {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},

12313
    {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}

12314
   ]

12315
  },

12316
  "VGT_STRMOUT_CONFIG": {

12317
   "fields": [

12318
    {"bits": [0, 0], "name": "STREAMOUT_0_EN"},

12319
    {"bits": [1, 1], "name": "STREAMOUT_1_EN"},

12320
    {"bits": [2, 2], "name": "STREAMOUT_2_EN"},

12321
    {"bits": [3, 3], "name": "STREAMOUT_3_EN"},

12322
    {"bits": [4, 6], "name": "RAST_STREAM"},

12323
    {"bits": [8, 11], "name": "RAST_STREAM_MASK"},

12324
    {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}

12325
   ]

12326
  },

12327
  "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": {

12328
   "fields": [

12329
    {"bits": [0, 8], "name": "VERTEX_STRIDE"}

12330
   ]

12331
  },

12332
  "VGT_STRMOUT_VTX_STRIDE_0": {

12333
   "fields": [

12334
    {"bits": [0, 9], "name": "STRIDE"}

12335
   ]

12336
  },

12337
  "VGT_TESS_DISTRIBUTION": {

12338
   "fields": [

12339
    {"bits": [0, 7], "name": "ACCUM_ISOLINE"},

12340
    {"bits": [8, 15], "name": "ACCUM_TRI"},

12341
    {"bits": [16, 23], "name": "ACCUM_QUAD"},

12342
    {"bits": [24, 31], "name": "DONUT_SPLIT"}

12343
   ]

12344
  },

12345
  "VGT_TF_PARAM": {

12346
   "fields": [

12347
    {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},

12348
    {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},

12349
    {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},

12350
    {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},

12351
    {"bits": [9, 9], "name": "DEPRECATED"},

12352
    {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},

12353
    {"bits": [14, 14], "name": "DISABLE_DONUTS"},

12354
    {"bits": [15, 15], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},

12355
    {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},

12356
    {"bits": [19, 20], "name": "MTYPE"}

12357
   ]

12358
  },

12359
  "VGT_TF_RING_SIZE": {

12360
   "fields": [

12361
    {"bits": [0, 15], "name": "SIZE"}

12362
   ]

12363
  },

12364
  "VGT_VERTEX_REUSE_BLOCK_CNTL": {

12365
   "fields": [

12366
    {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}

12367
   ]

12368
  },

12369
  "VGT_VTX_CNT_EN": {

12370
   "fields": [

12371
    {"bits": [0, 0], "name": "VTX_CNT_EN"}

12372
   ]

12373
  }

12374
 }

12375
}

12376


12377