CoCalc -- gfx9.json

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/amd/registers/gfx9.json
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{
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 "enums": {
3
  "ArrayMode": {
4
   "entries": [
5
    {"name": "ARRAY_LINEAR_GENERAL", "value": 0},
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    {"name": "ARRAY_LINEAR_ALIGNED", "value": 1},
7
    {"name": "ARRAY_1D_TILED_THIN1", "value": 2},
8
    {"name": "ARRAY_1D_TILED_THICK", "value": 3},
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    {"name": "ARRAY_2D_TILED_THIN1", "value": 4},
10
    {"name": "ARRAY_PRT_TILED_THIN1", "value": 5},
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    {"name": "ARRAY_PRT_2D_TILED_THIN1", "value": 6},
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    {"name": "ARRAY_2D_TILED_THICK", "value": 7},
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    {"name": "ARRAY_2D_TILED_XTHICK", "value": 8},
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    {"name": "ARRAY_PRT_TILED_THICK", "value": 9},
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    {"name": "ARRAY_PRT_2D_TILED_THICK", "value": 10},
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    {"name": "ARRAY_PRT_3D_TILED_THIN1", "value": 11},
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    {"name": "ARRAY_3D_TILED_THIN1", "value": 12},
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    {"name": "ARRAY_3D_TILED_THICK", "value": 13},
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    {"name": "ARRAY_3D_TILED_XTHICK", "value": 14},
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    {"name": "ARRAY_PRT_3D_TILED_THICK", "value": 15}
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   ]
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  },
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  "BUF_DATA_FORMAT": {
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   "entries": [
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    {"name": "BUF_DATA_FORMAT_INVALID", "value": 0},
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    {"name": "BUF_DATA_FORMAT_8", "value": 1},
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    {"name": "BUF_DATA_FORMAT_16", "value": 2},
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    {"name": "BUF_DATA_FORMAT_8_8", "value": 3},
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    {"name": "BUF_DATA_FORMAT_32", "value": 4},
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    {"name": "BUF_DATA_FORMAT_16_16", "value": 5},
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    {"name": "BUF_DATA_FORMAT_10_11_11", "value": 6},
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    {"name": "BUF_DATA_FORMAT_11_11_10", "value": 7},
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    {"name": "BUF_DATA_FORMAT_10_10_10_2", "value": 8},
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    {"name": "BUF_DATA_FORMAT_2_10_10_10", "value": 9},
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    {"name": "BUF_DATA_FORMAT_8_8_8_8", "value": 10},
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    {"name": "BUF_DATA_FORMAT_32_32", "value": 11},
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    {"name": "BUF_DATA_FORMAT_16_16_16_16", "value": 12},
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    {"name": "BUF_DATA_FORMAT_32_32_32", "value": 13},
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    {"name": "BUF_DATA_FORMAT_32_32_32_32", "value": 14},
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    {"name": "BUF_DATA_FORMAT_RESERVED_15", "value": 15}
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   ]
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  },
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  "BUF_NUM_FORMAT": {
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   "entries": [
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    {"name": "BUF_NUM_FORMAT_UNORM", "value": 0},
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    {"name": "BUF_NUM_FORMAT_SNORM", "value": 1},
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    {"name": "BUF_NUM_FORMAT_USCALED", "value": 2},
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    {"name": "BUF_NUM_FORMAT_SSCALED", "value": 3},
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    {"name": "BUF_NUM_FORMAT_UINT", "value": 4},
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    {"name": "BUF_NUM_FORMAT_SINT", "value": 5},
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    {"name": "BUF_NUM_FORMAT_UNORM_UINT", "value": 6},
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    {"name": "BUF_NUM_FORMAT_FLOAT", "value": 7}
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   ]
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  },
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  "BankHeight": {
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   "entries": [
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    {"name": "ADDR_SURF_BANK_HEIGHT_1", "value": 0},
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    {"name": "ADDR_SURF_BANK_HEIGHT_2", "value": 1},
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    {"name": "ADDR_SURF_BANK_HEIGHT_4", "value": 2},
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    {"name": "ADDR_SURF_BANK_HEIGHT_8", "value": 3}
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   ]
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  },
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  "BankWidth": {
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   "entries": [
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    {"name": "ADDR_SURF_BANK_WIDTH_1", "value": 0},
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    {"name": "ADDR_SURF_BANK_WIDTH_2", "value": 1},
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    {"name": "ADDR_SURF_BANK_WIDTH_4", "value": 2},
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    {"name": "ADDR_SURF_BANK_WIDTH_8", "value": 3}
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   ]
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  },
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  "BinningMode": {
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   "entries": [
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    {"name": "BINNING_ALLOWED", "value": 0},
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    {"name": "FORCE_BINNING_ON", "value": 1},
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    {"name": "DISABLE_BINNING_USE_NEW_SC", "value": 2},
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    {"name": "DISABLE_BINNING_USE_LEGACY_SC", "value": 3}
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   ]
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  },
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  "BlendOp": {
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   "entries": [
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    {"name": "BLEND_ZERO", "value": 0},
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    {"name": "BLEND_ONE", "value": 1},
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    {"name": "BLEND_SRC_COLOR", "value": 2},
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    {"name": "BLEND_ONE_MINUS_SRC_COLOR", "value": 3},
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    {"name": "BLEND_SRC_ALPHA", "value": 4},
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    {"name": "BLEND_ONE_MINUS_SRC_ALPHA", "value": 5},
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    {"name": "BLEND_DST_ALPHA", "value": 6},
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    {"name": "BLEND_ONE_MINUS_DST_ALPHA", "value": 7},
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    {"name": "BLEND_DST_COLOR", "value": 8},
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    {"name": "BLEND_ONE_MINUS_DST_COLOR", "value": 9},
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    {"name": "BLEND_SRC_ALPHA_SATURATE", "value": 10},
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    {"name": "BLEND_BOTH_SRC_ALPHA", "value": 11},
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    {"name": "BLEND_BOTH_INV_SRC_ALPHA", "value": 12},
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    {"name": "BLEND_CONSTANT_COLOR", "value": 13},
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    {"name": "BLEND_ONE_MINUS_CONSTANT_COLOR", "value": 14},
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    {"name": "BLEND_SRC1_COLOR", "value": 15},
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    {"name": "BLEND_INV_SRC1_COLOR", "value": 16},
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    {"name": "BLEND_SRC1_ALPHA", "value": 17},
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    {"name": "BLEND_INV_SRC1_ALPHA", "value": 18},
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    {"name": "BLEND_CONSTANT_ALPHA", "value": 19},
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    {"name": "BLEND_ONE_MINUS_CONSTANT_ALPHA", "value": 20}
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   ]
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  },
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  "BlendOpt": {
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   "entries": [
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    {"name": "FORCE_OPT_AUTO", "value": 0},
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    {"name": "FORCE_OPT_DISABLE", "value": 1},
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    {"name": "FORCE_OPT_ENABLE_IF_SRC_A_0", "value": 2},
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    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_0", "value": 3},
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    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_0", "value": 4},
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    {"name": "FORCE_OPT_ENABLE_IF_SRC_A_1", "value": 5},
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    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_1", "value": 6},
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    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_1", "value": 7}
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   ]
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  },
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  "CBMode": {
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   "entries": [
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    {"name": "CB_DISABLE", "value": 0},
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    {"name": "CB_NORMAL", "value": 1},
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    {"name": "CB_ELIMINATE_FAST_CLEAR", "value": 2},
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    {"name": "CB_RESOLVE", "value": 3},
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    {"name": "CB_DECOMPRESS", "value": 4},
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    {"name": "CB_FMASK_DECOMPRESS", "value": 5},
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    {"name": "CB_DCC_DECOMPRESS", "value": 6}
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   ]
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  },
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  "CBPerfClearFilterSel": {
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   "entries": [
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    {"name": "CB_PERF_CLEAR_FILTER_SEL_NONCLEAR", "value": 0},
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    {"name": "CB_PERF_CLEAR_FILTER_SEL_CLEAR", "value": 1}
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   ]
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  },
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  "CBPerfOpFilterSel": {
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   "entries": [
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    {"name": "CB_PERF_OP_FILTER_SEL_WRITE_ONLY", "value": 0},
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    {"name": "CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION", "value": 1},
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    {"name": "CB_PERF_OP_FILTER_SEL_RESOLVE", "value": 2},
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    {"name": "CB_PERF_OP_FILTER_SEL_DECOMPRESS", "value": 3},
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    {"name": "CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS", "value": 4},
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    {"name": "CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR", "value": 5}
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   ]
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  },
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  "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE": {
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   "entries": [
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    {"name": "MAX_BLOCK_SIZE_64B", "value": 0},
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    {"name": "MAX_BLOCK_SIZE_128B", "value": 1},
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    {"name": "MAX_BLOCK_SIZE_256B", "value": 2}
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   ]
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  },
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  "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE": {
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   "entries": [
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    {"name": "MIN_BLOCK_SIZE_32B", "value": 0},
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    {"name": "MIN_BLOCK_SIZE_64B", "value": 1}
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   ]
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  },
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  "CLIP_RULE": {
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   "entries": [
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    {"name": "OUT", "value": 1},
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    {"name": "IN_0", "value": 2},
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    {"name": "IN_1", "value": 4},
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    {"name": "IN_10", "value": 8},
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    {"name": "IN_2", "value": 16},
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    {"name": "IN_20", "value": 32},
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    {"name": "IN_21", "value": 64},
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    {"name": "IN_210", "value": 128},
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    {"name": "IN_3", "value": 256},
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    {"name": "IN_30", "value": 512},
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    {"name": "IN_31", "value": 1024},
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    {"name": "IN_310", "value": 2048},
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    {"name": "IN_32", "value": 4096},
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    {"name": "IN_320", "value": 8192},
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    {"name": "IN_321", "value": 16384},
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    {"name": "IN_3210", "value": 32768}
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   ]
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  },
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  "CP_PERFMON_ENABLE_MODE": {
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   "entries": [
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    {"name": "CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT", "value": 0},
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    {"name": "CP_PERFMON_ENABLE_MODE_RESERVED_1", "value": 1},
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    {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE", "value": 2},
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    {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE", "value": 3}
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   ]
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  },
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  "CP_PERFMON_STATE": {
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   "entries": [
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    {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
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    {"name": "CP_PERFMON_STATE_START_COUNTING", "value": 1},
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    {"name": "CP_PERFMON_STATE_STOP_COUNTING", "value": 2},
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    {"name": "CP_PERFMON_STATE_RESERVED_3", "value": 3},
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    {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
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    {"name": "CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
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   ]
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  },
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  "CmaskAddr": {
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   "entries": [
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    {"name": "CMASK_ADDR_TILED", "value": 0},
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    {"name": "CMASK_ADDR_LINEAR", "value": 1},
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    {"name": "CMASK_ADDR_COMPATIBLE", "value": 2}
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   ]
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  },
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  "ColorFormat": {
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   "entries": [
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    {"name": "COLOR_INVALID", "value": 0},
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    {"name": "COLOR_8", "value": 1},
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    {"name": "COLOR_16", "value": 2},
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    {"name": "COLOR_8_8", "value": 3},
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    {"name": "COLOR_32", "value": 4},
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    {"name": "COLOR_16_16", "value": 5},
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    {"name": "COLOR_10_11_11", "value": 6},
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    {"name": "COLOR_11_11_10", "value": 7},
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    {"name": "COLOR_10_10_10_2", "value": 8},
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    {"name": "COLOR_2_10_10_10", "value": 9},
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    {"name": "COLOR_8_8_8_8", "value": 10},
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    {"name": "COLOR_32_32", "value": 11},
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    {"name": "COLOR_16_16_16_16", "value": 12},
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    {"name": "COLOR_RESERVED_13", "value": 13},
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    {"name": "COLOR_32_32_32_32", "value": 14},
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    {"name": "COLOR_RESERVED_15", "value": 15},
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    {"name": "COLOR_5_6_5", "value": 16},
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    {"name": "COLOR_1_5_5_5", "value": 17},
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    {"name": "COLOR_5_5_5_1", "value": 18},
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    {"name": "COLOR_4_4_4_4", "value": 19},
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    {"name": "COLOR_8_24", "value": 20},
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    {"name": "COLOR_24_8", "value": 21},
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    {"name": "COLOR_X24_8_32_FLOAT", "value": 22},
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    {"name": "COLOR_RESERVED_23", "value": 23},
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    {"name": "COLOR_RESERVED_24", "value": 24},
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    {"name": "COLOR_RESERVED_25", "value": 25},
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    {"name": "COLOR_RESERVED_26", "value": 26},
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    {"name": "COLOR_RESERVED_27", "value": 27},
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    {"name": "COLOR_RESERVED_28", "value": 28},
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    {"name": "COLOR_RESERVED_29", "value": 29},
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    {"name": "COLOR_RESERVED_30", "value": 30},
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    {"name": "COLOR_2_10_10_10_6E4", "value": 31}
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   ]
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  },
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  "CombFunc": {
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   "entries": [
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    {"name": "COMB_DST_PLUS_SRC", "value": 0},
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    {"name": "COMB_SRC_MINUS_DST", "value": 1},
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    {"name": "COMB_MIN_DST_SRC", "value": 2},
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    {"name": "COMB_MAX_DST_SRC", "value": 3},
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    {"name": "COMB_DST_MINUS_SRC", "value": 4}
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   ]
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  },
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  "CompareFrag": {
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   "entries": [
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    {"name": "FRAG_NEVER", "value": 0},
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    {"name": "FRAG_LESS", "value": 1},
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    {"name": "FRAG_EQUAL", "value": 2},
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    {"name": "FRAG_LEQUAL", "value": 3},
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    {"name": "FRAG_GREATER", "value": 4},
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    {"name": "FRAG_NOTEQUAL", "value": 5},
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    {"name": "FRAG_GEQUAL", "value": 6},
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    {"name": "FRAG_ALWAYS", "value": 7}
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   ]
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  },
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  "ConservativeZExport": {
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   "entries": [
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    {"name": "EXPORT_ANY_Z", "value": 0},
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    {"name": "EXPORT_LESS_THAN_Z", "value": 1},
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    {"name": "EXPORT_GREATER_THAN_Z", "value": 2},
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    {"name": "EXPORT_RESERVED", "value": 3}
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   ]
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  },
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  "CovToShaderSel": {
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   "entries": [
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    {"name": "INPUT_COVERAGE", "value": 0},
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    {"name": "INPUT_INNER_COVERAGE", "value": 1},
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    {"name": "INPUT_DEPTH_COVERAGE", "value": 2},
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    {"name": "RAW", "value": 3}
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   ]
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  },
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  "DB_DFSM_CONTROL__PUNCHOUT_MODE": {
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   "entries": [
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    {"name": "AUTO", "value": 0},
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    {"name": "FORCE_ON", "value": 1},
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    {"name": "FORCE_OFF", "value": 2},
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    {"name": "RESERVED", "value": 3}
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   ]
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  },
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  "DbPRTFaultBehavior": {
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   "entries": [
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    {"name": "FAULT_ZERO", "value": 0},
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    {"name": "FAULT_ONE", "value": 1},
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    {"name": "FAULT_FAIL", "value": 2},
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    {"name": "FAULT_PASS", "value": 3}
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   ]
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  },
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  "DbPSLControl": {
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   "entries": [
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    {"name": "PSLC_AUTO", "value": 0},
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    {"name": "PSLC_ON_HANG_ONLY", "value": 1},
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    {"name": "PSLC_ASAP", "value": 2},
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    {"name": "PSLC_COUNTDOWN", "value": 3}
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   ]
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  },
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  "EXCP_EN": {
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   "entries": [
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    {"name": "INVALID", "value": 1},
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    {"name": "INPUT_DENORMAL", "value": 2},
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    {"name": "DIVIDE_BY_ZERO", "value": 4},
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    {"name": "OVERFLOW", "value": 8},
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    {"name": "UNDERFLOW", "value": 16},
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    {"name": "INEXACT", "value": 32},
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    {"name": "INT_DIVIDE_BY_ZERO", "value": 64},
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    {"name": "ADDRESS_WATCH", "value": 128},
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    {"name": "MEMORY_VIOLATION", "value": 256}
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   ]
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  },
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  "FLOAT_MODE": {
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   "entries": [
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    {"name": "FP_32_DENORMS", "value": 48},
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    {"name": "FP_64_DENORMS", "value": 192},
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    {"name": "FP_ALL_DENORMS", "value": 240}
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   ]
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  },
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  "ForceControl": {
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   "entries": [
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    {"name": "FORCE_OFF", "value": 0},
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    {"name": "FORCE_ENABLE", "value": 1},
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    {"name": "FORCE_DISABLE", "value": 2},
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    {"name": "FORCE_RESERVED", "value": 3}
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   ]
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  },
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  "IMG_DATA_FORMAT": {
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   "entries": [
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    {"name": "IMG_DATA_FORMAT_INVALID", "value": 0},
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    {"name": "IMG_DATA_FORMAT_8", "value": 1},
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    {"name": "IMG_DATA_FORMAT_16", "value": 2},
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    {"name": "IMG_DATA_FORMAT_8_8", "value": 3},
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    {"name": "IMG_DATA_FORMAT_32", "value": 4},
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    {"name": "IMG_DATA_FORMAT_16_16", "value": 5},
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    {"name": "IMG_DATA_FORMAT_10_11_11", "value": 6},
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    {"name": "IMG_DATA_FORMAT_11_11_10", "value": 7},
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    {"name": "IMG_DATA_FORMAT_10_10_10_2", "value": 8},
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    {"name": "IMG_DATA_FORMAT_2_10_10_10", "value": 9},
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    {"name": "IMG_DATA_FORMAT_8_8_8_8", "value": 10},
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    {"name": "IMG_DATA_FORMAT_32_32", "value": 11},
340
    {"name": "IMG_DATA_FORMAT_16_16_16_16", "value": 12},
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    {"name": "IMG_DATA_FORMAT_32_32_32", "value": 13},
342
    {"name": "IMG_DATA_FORMAT_32_32_32_32", "value": 14},
343
    {"name": "IMG_DATA_FORMAT_RESERVED_15", "value": 15},
344
    {"name": "IMG_DATA_FORMAT_5_6_5", "value": 16},
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    {"name": "IMG_DATA_FORMAT_1_5_5_5", "value": 17},
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    {"name": "IMG_DATA_FORMAT_5_5_5_1", "value": 18},
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    {"name": "IMG_DATA_FORMAT_4_4_4_4", "value": 19},
348
    {"name": "IMG_DATA_FORMAT_8_24", "value": 20},
349
    {"name": "IMG_DATA_FORMAT_24_8", "value": 21},
350
    {"name": "IMG_DATA_FORMAT_X24_8_32", "value": 22},
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    {"name": "IMG_DATA_FORMAT_8_AS_8_8_8_8", "value": 23},
352
    {"name": "IMG_DATA_FORMAT_ETC2_RGB", "value": 24},
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    {"name": "IMG_DATA_FORMAT_ETC2_RGBA", "value": 25},
354
    {"name": "IMG_DATA_FORMAT_ETC2_R", "value": 26},
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    {"name": "IMG_DATA_FORMAT_ETC2_RG", "value": 27},
356
    {"name": "IMG_DATA_FORMAT_ETC2_RGBA1", "value": 28},
357
    {"name": "IMG_DATA_FORMAT_RESERVED_29", "value": 29},
358
    {"name": "IMG_DATA_FORMAT_RESERVED_30", "value": 30},
359
    {"name": "IMG_DATA_FORMAT_6E4", "value": 31},
360
    {"name": "IMG_DATA_FORMAT_GB_GR", "value": 32},
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    {"name": "IMG_DATA_FORMAT_BG_RG", "value": 33},
362
    {"name": "IMG_DATA_FORMAT_5_9_9_9", "value": 34},
363
    {"name": "IMG_DATA_FORMAT_BC1", "value": 35},
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    {"name": "IMG_DATA_FORMAT_BC2", "value": 36},
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    {"name": "IMG_DATA_FORMAT_BC3", "value": 37},
366
    {"name": "IMG_DATA_FORMAT_BC4", "value": 38},
367
    {"name": "IMG_DATA_FORMAT_BC5", "value": 39},
368
    {"name": "IMG_DATA_FORMAT_BC6", "value": 40},
369
    {"name": "IMG_DATA_FORMAT_BC7", "value": 41},
370
    {"name": "IMG_DATA_FORMAT_16_AS_32_32", "value": 42},
371
    {"name": "IMG_DATA_FORMAT_16_AS_16_16_16_16", "value": 43},
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    {"name": "IMG_DATA_FORMAT_16_AS_32_32_32_32", "value": 44},
373
    {"name": "IMG_DATA_FORMAT_FMASK", "value": 45},
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    {"name": "IMG_DATA_FORMAT_ASTC_2D_LDR", "value": 46},
375
    {"name": "IMG_DATA_FORMAT_ASTC_2D_HDR", "value": 47},
376
    {"name": "IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB", "value": 48},
377
    {"name": "IMG_DATA_FORMAT_ASTC_3D_LDR", "value": 49},
378
    {"name": "IMG_DATA_FORMAT_ASTC_3D_HDR", "value": 50},
379
    {"name": "IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB", "value": 51},
380
    {"name": "IMG_DATA_FORMAT_N_IN_16", "value": 52},
381
    {"name": "IMG_DATA_FORMAT_N_IN_16_16", "value": 53},
382
    {"name": "IMG_DATA_FORMAT_N_IN_16_16_16_16", "value": 54},
383
    {"name": "IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16", "value": 55},
384
    {"name": "IMG_DATA_FORMAT_RESERVED_56", "value": 56},
385
    {"name": "IMG_DATA_FORMAT_4_4", "value": 57},
386
    {"name": "IMG_DATA_FORMAT_6_5_5", "value": 58},
387
    {"name": "IMG_DATA_FORMAT_RESERVED_59", "value": 59},
388
    {"name": "IMG_DATA_FORMAT_RESERVED_60", "value": 60},
389
    {"name": "IMG_DATA_FORMAT_8_AS_32", "value": 61},
390
    {"name": "IMG_DATA_FORMAT_8_AS_32_32", "value": 62},
391
    {"name": "IMG_DATA_FORMAT_32_AS_32_32_32_32", "value": 63}
392
   ]
393
  },
394
  "IMG_DATA_FORMAT_STENCIL": {
395
   "entries": [
396
    {"name": "IMG_DATA_FORMAT_S8_16", "value": 59},
397
    {"name": "IMG_DATA_FORMAT_S8_32", "value": 60}
398
   ]
399
  },
400
  "IMG_NUM_FORMAT": {
401
   "entries": [
402
    {"name": "IMG_NUM_FORMAT_UNORM", "value": 0},
403
    {"name": "IMG_NUM_FORMAT_SNORM", "value": 1},
404
    {"name": "IMG_NUM_FORMAT_USCALED", "value": 2},
405
    {"name": "IMG_NUM_FORMAT_SSCALED", "value": 3},
406
    {"name": "IMG_NUM_FORMAT_UINT", "value": 4},
407
    {"name": "IMG_NUM_FORMAT_SINT", "value": 5},
408
    {"name": "IMG_NUM_FORMAT_UNORM_UINT", "value": 6},
409
    {"name": "IMG_NUM_FORMAT_FLOAT", "value": 7},
410
    {"name": "IMG_NUM_FORMAT_RESERVED_8", "value": 8},
411
    {"name": "IMG_NUM_FORMAT_SRGB", "value": 9},
412
    {"name": "IMG_NUM_FORMAT_RESERVED_10", "value": 10},
413
    {"name": "IMG_NUM_FORMAT_RESERVED_11", "value": 11},
414
    {"name": "IMG_NUM_FORMAT_RESERVED_12", "value": 12},
415
    {"name": "IMG_NUM_FORMAT_RESERVED_13", "value": 13},
416
    {"name": "IMG_NUM_FORMAT_RESERVED_14", "value": 14},
417
    {"name": "IMG_NUM_FORMAT_RESERVED_15", "value": 15}
418
   ]
419
  },
420
  "IMG_NUM_FORMAT_FMASK": {
421
   "entries": [
422
    {"name": "IMG_NUM_FORMAT_FMASK_8_2_1", "value": 0},
423
    {"name": "IMG_NUM_FORMAT_FMASK_8_4_1", "value": 1},
424
    {"name": "IMG_NUM_FORMAT_FMASK_8_8_1", "value": 2},
425
    {"name": "IMG_NUM_FORMAT_FMASK_8_2_2", "value": 3},
426
    {"name": "IMG_NUM_FORMAT_FMASK_8_4_2", "value": 4},
427
    {"name": "IMG_NUM_FORMAT_FMASK_8_4_4", "value": 5},
428
    {"name": "IMG_NUM_FORMAT_FMASK_16_16_1", "value": 6},
429
    {"name": "IMG_NUM_FORMAT_FMASK_16_8_2", "value": 7},
430
    {"name": "IMG_NUM_FORMAT_FMASK_32_16_2", "value": 8},
431
    {"name": "IMG_NUM_FORMAT_FMASK_32_8_4", "value": 9},
432
    {"name": "IMG_NUM_FORMAT_FMASK_32_8_8", "value": 10},
433
    {"name": "IMG_NUM_FORMAT_FMASK_64_16_4", "value": 11},
434
    {"name": "IMG_NUM_FORMAT_FMASK_64_16_8", "value": 12},
435
    {"name": "IMG_NUM_FORMAT_FMASK_RESERVED_13", "value": 13},
436
    {"name": "IMG_NUM_FORMAT_FMASK_RESERVED_14", "value": 14},
437
    {"name": "IMG_NUM_FORMAT_FMASK_RESERVED_15", "value": 15}
438
   ]
439
  },
440
  "MacroTileAspect": {
441
   "entries": [
442
    {"name": "ADDR_SURF_MACRO_ASPECT_1", "value": 0},
443
    {"name": "ADDR_SURF_MACRO_ASPECT_2", "value": 1},
444
    {"name": "ADDR_SURF_MACRO_ASPECT_4", "value": 2},
445
    {"name": "ADDR_SURF_MACRO_ASPECT_8", "value": 3}
446
   ]
447
  },
448
  "MicroTileMode": {
449
   "entries": [
450
    {"name": "ADDR_SURF_DISPLAY_MICRO_TILING", "value": 0},
451
    {"name": "ADDR_SURF_THIN_MICRO_TILING", "value": 1},
452
    {"name": "ADDR_SURF_DEPTH_MICRO_TILING", "value": 2},
453
    {"name": "ADDR_SURF_ROTATED_MICRO_TILING", "value": 3},
454
    {"name": "ADDR_SURF_THICK_MICRO_TILING", "value": 4}
455
   ]
456
  },
457
  "NumBanks": {
458
   "entries": [
459
    {"name": "ADDR_SURF_2_BANK", "value": 0},
460
    {"name": "ADDR_SURF_4_BANK", "value": 1},
461
    {"name": "ADDR_SURF_8_BANK", "value": 2},
462
    {"name": "ADDR_SURF_16_BANK", "value": 3}
463
   ]
464
  },
465
  "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE": {
466
   "entries": [
467
    {"name": "X_DRAW_POINTS", "value": 0},
468
    {"name": "X_DRAW_LINES", "value": 1},
469
    {"name": "X_DRAW_TRIANGLES", "value": 2}
470
   ]
471
  },
472
  "PA_SU_SC_MODE_CNTL__POLY_MODE": {
473
   "entries": [
474
    {"name": "X_DISABLE_POLY_MODE", "value": 0},
475
    {"name": "X_DUAL_MODE", "value": 1}
476
   ]
477
  },
478
  "PA_SU_VTX_CNTL__ROUND_MODE": {
479
   "entries": [
480
    {"name": "X_TRUNCATE", "value": 0},
481
    {"name": "X_ROUND", "value": 1},
482
    {"name": "X_ROUND_TO_EVEN", "value": 2},
483
    {"name": "X_ROUND_TO_ODD", "value": 3}
484
   ]
485
  },
486
  "PipeConfig": {
487
   "entries": [
488
    {"name": "ADDR_SURF_P2", "value": 0},
489
    {"name": "ADDR_SURF_P2_RESERVED0", "value": 1},
490
    {"name": "ADDR_SURF_P2_RESERVED1", "value": 2},
491
    {"name": "ADDR_SURF_P2_RESERVED2", "value": 3},
492
    {"name": "ADDR_SURF_P4_8x16", "value": 4},
493
    {"name": "ADDR_SURF_P4_16x16", "value": 5},
494
    {"name": "ADDR_SURF_P4_16x32", "value": 6},
495
    {"name": "ADDR_SURF_P4_32x32", "value": 7},
496
    {"name": "ADDR_SURF_P8_16x16_8x16", "value": 8},
497
    {"name": "ADDR_SURF_P8_16x32_8x16", "value": 9},
498
    {"name": "ADDR_SURF_P8_32x32_8x16", "value": 10},
499
    {"name": "ADDR_SURF_P8_16x32_16x16", "value": 11},
500
    {"name": "ADDR_SURF_P8_32x32_16x16", "value": 12},
501
    {"name": "ADDR_SURF_P8_32x32_16x32", "value": 13},
502
    {"name": "ADDR_SURF_P8_32x64_32x32", "value": 14},
503
    {"name": "ADDR_SURF_P8_RESERVED0", "value": 15},
504
    {"name": "ADDR_SURF_P16_32x32_8x16", "value": 16},
505
    {"name": "ADDR_SURF_P16_32x32_16x16", "value": 17}
506
   ]
507
  },
508
  "PkrMap": {
509
   "entries": [
510
    {"name": "RASTER_CONFIG_PKR_MAP_0", "value": 0},
511
    {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},
512
    {"name": "RASTER_CONFIG_PKR_MAP_2", "value": 2},
513
    {"name": "RASTER_CONFIG_PKR_MAP_3", "value": 3}
514
   ]
515
  },
516
  "PkrXsel": {
517
   "entries": [
518
    {"name": "RASTER_CONFIG_PKR_XSEL_0", "value": 0},
519
    {"name": "RASTER_CONFIG_PKR_XSEL_1", "value": 1},
520
    {"name": "RASTER_CONFIG_PKR_XSEL_2", "value": 2},
521
    {"name": "RASTER_CONFIG_PKR_XSEL_3", "value": 3}
522
   ]
523
  },
524
  "PkrXsel2": {
525
   "entries": [
526
    {"name": "RASTER_CONFIG_PKR_XSEL2_0", "value": 0},
527
    {"name": "RASTER_CONFIG_PKR_XSEL2_1", "value": 1},
528
    {"name": "RASTER_CONFIG_PKR_XSEL2_2", "value": 2},
529
    {"name": "RASTER_CONFIG_PKR_XSEL2_3", "value": 3}
530
   ]
531
  },
532
  "PkrYsel": {
533
   "entries": [
534
    {"name": "RASTER_CONFIG_PKR_YSEL_0", "value": 0},
535
    {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},
536
    {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},
537
    {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}
538
   ]
539
  },
540
  "QUANT_MODE": {
541
   "entries": [
542
    {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},
543
    {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
544
    {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
545
    {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
546
    {"name": "X_16_8_FIXED_POINT_1", "value": 4},
547
    {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
548
    {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
549
    {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
550
   ]
551
  },
552
  "ROP3": {
553
   "entries": [
554
    {"name": "ROP3_CLEAR", "value": 0},
555
    {"name": "X_0X05", "value": 5},
556
    {"name": "X_0X0A", "value": 10},
557
    {"name": "X_0X0F", "value": 15},
558
    {"name": "ROP3_NOR", "value": 17},
559
    {"name": "ROP3_AND_INVERTED", "value": 34},
560
    {"name": "ROP3_COPY_INVERTED", "value": 51},
561
    {"name": "ROP3_AND_REVERSE", "value": 68},
562
    {"name": "X_0X50", "value": 80},
563
    {"name": "ROP3_INVERT", "value": 85},
564
    {"name": "X_0X5A", "value": 90},
565
    {"name": "X_0X5F", "value": 95},
566
    {"name": "ROP3_XOR", "value": 102},
567
    {"name": "ROP3_NAND", "value": 119},
568
    {"name": "ROP3_AND", "value": 136},
569
    {"name": "ROP3_EQUIVALENT", "value": 153},
570
    {"name": "X_0XA0", "value": 160},
571
    {"name": "X_0XA5", "value": 165},
572
    {"name": "ROP3_NO_OP", "value": 170},
573
    {"name": "X_0XAF", "value": 175},
574
    {"name": "ROP3_OR_INVERTED", "value": 187},
575
    {"name": "ROP3_COPY", "value": 204},
576
    {"name": "ROP3_OR_REVERSE", "value": 221},
577
    {"name": "ROP3_OR", "value": 238},
578
    {"name": "X_0XF0", "value": 240},
579
    {"name": "X_0XF5", "value": 245},
580
    {"name": "X_0XFA", "value": 250},
581
    {"name": "ROP3_SET", "value": 255}
582
   ]
583
  },
584
  "RbMap": {
585
   "entries": [
586
    {"name": "RASTER_CONFIG_RB_MAP_0", "value": 0},
587
    {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},
588
    {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},
589
    {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}
590
   ]
591
  },
592
  "RbXsel": {
593
   "entries": [
594
    {"name": "RASTER_CONFIG_RB_XSEL_0", "value": 0},
595
    {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}
596
   ]
597
  },
598
  "RbXsel2": {
599
   "entries": [
600
    {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},
601
    {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},
602
    {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},
603
    {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}
604
   ]
605
  },
606
  "RbYsel": {
607
   "entries": [
608
    {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},
609
    {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}
610
   ]
611
  },
612
  "SPI_PNT_SPRITE_OVERRIDE": {
613
   "entries": [
614
    {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},
615
    {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},
616
    {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},
617
    {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},
618
    {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}
619
   ]
620
  },
621
  "SPI_SHADER_EX_FORMAT": {
622
   "entries": [
623
    {"name": "SPI_SHADER_ZERO", "value": 0},
624
    {"name": "SPI_SHADER_32_R", "value": 1},
625
    {"name": "SPI_SHADER_32_GR", "value": 2},
626
    {"name": "SPI_SHADER_32_AR", "value": 3},
627
    {"name": "SPI_SHADER_FP16_ABGR", "value": 4},
628
    {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},
629
    {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},
630
    {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},
631
    {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},
632
    {"name": "SPI_SHADER_32_ABGR", "value": 9}
633
   ]
634
  },
635
  "SPI_SHADER_FORMAT": {
636
   "entries": [
637
    {"name": "SPI_SHADER_NONE", "value": 0},
638
    {"name": "SPI_SHADER_1COMP", "value": 1},
639
    {"name": "SPI_SHADER_2COMP", "value": 2},
640
    {"name": "SPI_SHADER_4COMPRESS", "value": 3},
641
    {"name": "SPI_SHADER_4COMP", "value": 4}
642
   ]
643
  },
644
  "SPM_PERFMON_STATE": {
645
   "entries": [
646
    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
647
    {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},
648
    {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},
649
    {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},
650
    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
651
    {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
652
   ]
653
  },
654
  "SQ_IMG_FILTER_TYPE": {
655
   "entries": [
656
    {"name": "SQ_IMG_FILTER_MODE_BLEND", "value": 0},
657
    {"name": "SQ_IMG_FILTER_MODE_MIN", "value": 1},
658
    {"name": "SQ_IMG_FILTER_MODE_MAX", "value": 2}
659
   ]
660
  },
661
  "SQ_IMG_RSRC_WORD4__BC_SWIZZLE": {
662
   "entries": [
663
    {"name": "BC_SWIZZLE_XYZW", "value": 0},
664
    {"name": "BC_SWIZZLE_XWYZ", "value": 1},
665
    {"name": "BC_SWIZZLE_WZYX", "value": 2},
666
    {"name": "BC_SWIZZLE_WXYZ", "value": 3},
667
    {"name": "BC_SWIZZLE_ZYXW", "value": 4},
668
    {"name": "BC_SWIZZLE_YXWZ", "value": 5}
669
   ]
670
  },
671
  "SQ_RSRC_BUF_TYPE": {
672
   "entries": [
673
    {"name": "SQ_RSRC_BUF", "value": 0},
674
    {"name": "SQ_RSRC_BUF_RSVD_1", "value": 1},
675
    {"name": "SQ_RSRC_BUF_RSVD_2", "value": 2},
676
    {"name": "SQ_RSRC_BUF_RSVD_3", "value": 3}
677
   ]
678
  },
679
  "SQ_RSRC_IMG_TYPE": {
680
   "entries": [
681
    {"name": "SQ_RSRC_IMG_RSVD_0", "value": 0},
682
    {"name": "SQ_RSRC_IMG_RSVD_1", "value": 1},
683
    {"name": "SQ_RSRC_IMG_RSVD_2", "value": 2},
684
    {"name": "SQ_RSRC_IMG_RSVD_3", "value": 3},
685
    {"name": "SQ_RSRC_IMG_RSVD_4", "value": 4},
686
    {"name": "SQ_RSRC_IMG_RSVD_5", "value": 5},
687
    {"name": "SQ_RSRC_IMG_RSVD_6", "value": 6},
688
    {"name": "SQ_RSRC_IMG_RSVD_7", "value": 7},
689
    {"name": "SQ_RSRC_IMG_1D", "value": 8},
690
    {"name": "SQ_RSRC_IMG_2D", "value": 9},
691
    {"name": "SQ_RSRC_IMG_3D", "value": 10},
692
    {"name": "SQ_RSRC_IMG_CUBE", "value": 11},
693
    {"name": "SQ_RSRC_IMG_1D_ARRAY", "value": 12},
694
    {"name": "SQ_RSRC_IMG_2D_ARRAY", "value": 13},
695
    {"name": "SQ_RSRC_IMG_2D_MSAA", "value": 14},
696
    {"name": "SQ_RSRC_IMG_2D_MSAA_ARRAY", "value": 15}
697
   ]
698
  },
699
  "SQ_SEL_XYZW01": {
700
   "entries": [
701
    {"name": "SQ_SEL_0", "value": 0},
702
    {"name": "SQ_SEL_1", "value": 1},
703
    {"name": "SQ_SEL_RESERVED_0", "value": 2},
704
    {"name": "SQ_SEL_RESERVED_1", "value": 3},
705
    {"name": "SQ_SEL_X", "value": 4},
706
    {"name": "SQ_SEL_Y", "value": 5},
707
    {"name": "SQ_SEL_Z", "value": 6},
708
    {"name": "SQ_SEL_W", "value": 7}
709
   ]
710
  },
711
  "SQ_TEX_BORDER_COLOR": {
712
   "entries": [
713
    {"name": "SQ_TEX_BORDER_COLOR_TRANS_BLACK", "value": 0},
714
    {"name": "SQ_TEX_BORDER_COLOR_OPAQUE_BLACK", "value": 1},
715
    {"name": "SQ_TEX_BORDER_COLOR_OPAQUE_WHITE", "value": 2},
716
    {"name": "SQ_TEX_BORDER_COLOR_REGISTER", "value": 3}
717
   ]
718
  },
719
  "SQ_TEX_CLAMP": {
720
   "entries": [
721
    {"name": "SQ_TEX_WRAP", "value": 0},
722
    {"name": "SQ_TEX_MIRROR", "value": 1},
723
    {"name": "SQ_TEX_CLAMP_LAST_TEXEL", "value": 2},
724
    {"name": "SQ_TEX_MIRROR_ONCE_LAST_TEXEL", "value": 3},
725
    {"name": "SQ_TEX_CLAMP_HALF_BORDER", "value": 4},
726
    {"name": "SQ_TEX_MIRROR_ONCE_HALF_BORDER", "value": 5},
727
    {"name": "SQ_TEX_CLAMP_BORDER", "value": 6},
728
    {"name": "SQ_TEX_MIRROR_ONCE_BORDER", "value": 7}
729
   ]
730
  },
731
  "SQ_TEX_DEPTH_COMPARE": {
732
   "entries": [
733
    {"name": "SQ_TEX_DEPTH_COMPARE_NEVER", "value": 0},
734
    {"name": "SQ_TEX_DEPTH_COMPARE_LESS", "value": 1},
735
    {"name": "SQ_TEX_DEPTH_COMPARE_EQUAL", "value": 2},
736
    {"name": "SQ_TEX_DEPTH_COMPARE_LESSEQUAL", "value": 3},
737
    {"name": "SQ_TEX_DEPTH_COMPARE_GREATER", "value": 4},
738
    {"name": "SQ_TEX_DEPTH_COMPARE_NOTEQUAL", "value": 5},
739
    {"name": "SQ_TEX_DEPTH_COMPARE_GREATEREQUAL", "value": 6},
740
    {"name": "SQ_TEX_DEPTH_COMPARE_ALWAYS", "value": 7}
741
   ]
742
  },
743
  "SQ_TEX_MIP_FILTER": {
744
   "entries": [
745
    {"name": "SQ_TEX_MIP_FILTER_NONE", "value": 0},
746
    {"name": "SQ_TEX_MIP_FILTER_POINT", "value": 1},
747
    {"name": "SQ_TEX_MIP_FILTER_LINEAR", "value": 2},
748
    {"name": "SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ", "value": 3}
749
   ]
750
  },
751
  "SQ_TEX_XY_FILTER": {
752
   "entries": [
753
    {"name": "SQ_TEX_XY_FILTER_POINT", "value": 0},
754
    {"name": "SQ_TEX_XY_FILTER_BILINEAR", "value": 1},
755
    {"name": "SQ_TEX_XY_FILTER_ANISO_POINT", "value": 2},
756
    {"name": "SQ_TEX_XY_FILTER_ANISO_BILINEAR", "value": 3}
757
   ]
758
  },
759
  "SQ_TEX_Z_FILTER": {
760
   "entries": [
761
    {"name": "SQ_TEX_Z_FILTER_NONE", "value": 0},
762
    {"name": "SQ_TEX_Z_FILTER_POINT", "value": 1},
763
    {"name": "SQ_TEX_Z_FILTER_LINEAR", "value": 2}
764
   ]
765
  },
766
  "SX_BLEND_OPT": {
767
   "entries": [
768
    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_ALL", "value": 0},
769
    {"name": "BLEND_OPT_PRESERVE_ALL_IGNORE_NONE", "value": 1},
770
    {"name": "BLEND_OPT_PRESERVE_C1_IGNORE_C0", "value": 2},
771
    {"name": "BLEND_OPT_PRESERVE_C0_IGNORE_C1", "value": 3},
772
    {"name": "BLEND_OPT_PRESERVE_A1_IGNORE_A0", "value": 4},
773
    {"name": "BLEND_OPT_PRESERVE_A0_IGNORE_A1", "value": 5},
774
    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_A0", "value": 6},
775
    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_NONE", "value": 7}
776
   ]
777
  },
778
  "SX_BLEND_OPT_EPSILON__MRT0_EPSILON": {
779
   "entries": [
780
    {"name": "EXACT", "value": 0},
781
    {"name": "11BIT_FORMAT", "value": 1},
782
    {"name": "10BIT_FORMAT", "value": 3},
783
    {"name": "8BIT_FORMAT", "value": 6},
784
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785
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786
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787
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788
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802
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803
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804
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807
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808
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809
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810
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811
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812
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813
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814
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816
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818
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819
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820
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821
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822
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823
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824
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825
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826
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827
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828
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829
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830
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831
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832
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833
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837
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838
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839
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840
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841
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843
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844
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845
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846
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847
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848
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851
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852
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853
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854
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855
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856
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857
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858
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859
    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE", "value": 1},
860
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861
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862
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863
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864
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865
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866
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867
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868
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869
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870
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871
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872
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873
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874
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875
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876
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877
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878
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879
    {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3},
880
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881
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882
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883
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884
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885
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886
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887
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888
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889
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890
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891
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892
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893
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894
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895
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896
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897
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898
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899
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900
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901
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902
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903
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904
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905
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906
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907
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908
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909
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910
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911
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912
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913
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914
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915
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916
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917
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919
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920
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921
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922
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924
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925
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927
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929
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930
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931
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932
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933
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934
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935
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936
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937
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938
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939
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940
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941
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942
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944
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945
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950
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951
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952
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953
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954
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955
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956
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957
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958
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960
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961
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962
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963
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964
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966
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968
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969
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970
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971
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977
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978
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979
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980
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981
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987
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988
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989
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990
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995
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1003
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1018
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1019
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1020
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1021
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1024
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1025
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1026
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1027
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1028
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1029
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1030
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1031
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1032
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1033
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1034
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1035
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1036
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1037
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1038
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1039
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1040
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1041
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1042
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1043
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1044
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1045
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1046
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1047
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1048
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1049
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1050
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1051
    {"name": "Available_0x1c", "value": 28},
1052
    {"name": "Available_0x1d", "value": 29},
1053
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1054
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1055
    {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
1056
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1057
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1058
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1059
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1060
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1061
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1062
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1063
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1064
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1065
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1066
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1067
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1068
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1069
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1070
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1071
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1072
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1073
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1074
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1075
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1076
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1077
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1078
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1079
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1080
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1081
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1082
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1083
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1084
    {"name": "ENABLE_NGG_PIPELINE", "value": 61},
1085
    {"name": "ENABLE_LEGACY_PIPELINE", "value": 62},
1086
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1087
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1088
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1089
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1090
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1091
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1092
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1093
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1094
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1095
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1096
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1097
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1098
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1099
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1100
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1101
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1102
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1103
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1104
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1105
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1106
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1107
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1108
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1109
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1110
    {"name": "LINESTRIP", "value": 1},
1111
    {"name": "TRISTRIP", "value": 2},
1112
    {"name": "RECTLIST", "value": 3}
1113
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1114
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1115
  "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY": {
1116
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1117
    {"name": "X_8K_DWORDS", "value": 0},
1118
    {"name": "X_4K_DWORDS", "value": 1},
1119
    {"name": "X_2K_DWORDS", "value": 2},
1120
    {"name": "X_1K_DWORDS", "value": 3}
1121
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1122
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1123
  "VGT_INDEX_TYPE_MODE": {
1124
   "entries": [
1125
    {"name": "VGT_INDEX_16", "value": 0},
1126
    {"name": "VGT_INDEX_32", "value": 1},
1127
    {"name": "VGT_INDEX_8", "value": 2}
1128
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1129
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1130
  "VGT_RDREQ_POLICY": {
1131
   "entries": [
1132
    {"name": "VGT_POLICY_LRU", "value": 0},
1133
    {"name": "VGT_POLICY_STREAM", "value": 1}
1134
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1135
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1136
  "VGT_STAGES_ES_EN": {
1137
   "entries": [
1138
    {"name": "ES_STAGE_OFF", "value": 0},
1139
    {"name": "ES_STAGE_DS", "value": 1},
1140
    {"name": "ES_STAGE_REAL", "value": 2},
1141
    {"name": "RESERVED_ES", "value": 3}
1142
   ]
1143
  },
1144
  "VGT_STAGES_GS_EN": {
1145
   "entries": [
1146
    {"name": "GS_STAGE_OFF", "value": 0},
1147
    {"name": "GS_STAGE_ON", "value": 1}
1148
   ]
1149
  },
1150
  "VGT_STAGES_HS_EN": {
1151
   "entries": [
1152
    {"name": "HS_STAGE_OFF", "value": 0},
1153
    {"name": "HS_STAGE_ON", "value": 1}
1154
   ]
1155
  },
1156
  "VGT_STAGES_LS_EN": {
1157
   "entries": [
1158
    {"name": "LS_STAGE_OFF", "value": 0},
1159
    {"name": "LS_STAGE_ON", "value": 1},
1160
    {"name": "CS_STAGE_ON", "value": 2},
1161
    {"name": "RESERVED_LS", "value": 3}
1162
   ]
1163
  },
1164
  "VGT_STAGES_VS_EN": {
1165
   "entries": [
1166
    {"name": "VS_STAGE_REAL", "value": 0},
1167
    {"name": "VS_STAGE_DS", "value": 1},
1168
    {"name": "VS_STAGE_COPY_SHADER", "value": 2},
1169
    {"name": "RESERVED_VS", "value": 3}
1170
   ]
1171
  },
1172
  "VGT_TESS_PARTITION": {
1173
   "entries": [
1174
    {"name": "PART_INTEGER", "value": 0},
1175
    {"name": "PART_POW2", "value": 1},
1176
    {"name": "PART_FRAC_ODD", "value": 2},
1177
    {"name": "PART_FRAC_EVEN", "value": 3}
1178
   ]
1179
  },
1180
  "VGT_TESS_TOPOLOGY": {
1181
   "entries": [
1182
    {"name": "OUTPUT_POINT", "value": 0},
1183
    {"name": "OUTPUT_LINE", "value": 1},
1184
    {"name": "OUTPUT_TRIANGLE_CW", "value": 2},
1185
    {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}
1186
   ]
1187
  },
1188
  "VGT_TESS_TYPE": {
1189
   "entries": [
1190
    {"name": "TESS_ISOLINE", "value": 0},
1191
    {"name": "TESS_TRIANGLE", "value": 1},
1192
    {"name": "TESS_QUAD", "value": 2}
1193
   ]
1194
  },
1195
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1196
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1197
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1198
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1199
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1200
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1201
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1202
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1203
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1204
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1205
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1206
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1207
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1208
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1209
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1210
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1211
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1212
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1213
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1214
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1215
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1216
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1217
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1218
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1219
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1220
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1221
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1222
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1223
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1224
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1225
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1226
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1227
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1228
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1229
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1230
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1231
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1232
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1233
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1234
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1235
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1236
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1237
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1238
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1240
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1241
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1242
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1243
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1244
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1246
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1247
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1248
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1249
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1252
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1253
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1254
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1255
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1258
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1259
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1260
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1261
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1264
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1266
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1269
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1270
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1271
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1272
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1275
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1277
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1278
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1280
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1281
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1282
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1285
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1286
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1287
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1288
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1291
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1292
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1293
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1294
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1295
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1297
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1298
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1299
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1300
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1301
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1302
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1303
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1304
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1307
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1308
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1309
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1310
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1312
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1313
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1314
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1315
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1316
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1317
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1318
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1319
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1320
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1321
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1322
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1323
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1324
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1325
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1326
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1327
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1328
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1329
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1330
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1331
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1332
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1333
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1334
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1335
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1336
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1337
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1338
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1339
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1340
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1341
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1342
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1343
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1344
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1345
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1346
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1347
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1348
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1349
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1350
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1351
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1352
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1353
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1354
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1355
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1356
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1357
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1358
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1359
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1360
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1361
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1362
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1363
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1364
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1365
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1366
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1367
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1368
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1369
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1370
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1371
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1372
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1373
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1374
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1375
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1376
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1377
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1378
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1379
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1380
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1381
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1382
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1383
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1384
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1385
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1386
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1387
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1388
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1389
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1390
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1391
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1392
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1393
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1394
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1395
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1396
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1397
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1398
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1399
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1400
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1401
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1402
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1403
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1404
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1405
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1406
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1407
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1408
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1409
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1410
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1411
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1412
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1413
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1414
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1415
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1416
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1417
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1418
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1419
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1420
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1421
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1422
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1423
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1424
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1425
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1426
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1427
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1428
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1429
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1430
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1431
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1432
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1433
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1434
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1435
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1436
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1437
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1438
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1439
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1440
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1441
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1442
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1443
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1444
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1445
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1446
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1447
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1448
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1449
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1450
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1451
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1452
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1453
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1454
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1455
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1456
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1457
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1458
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1459
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1460
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1461
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1462
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1463
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1464
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1465
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1466
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1467
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1468
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1469
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1470
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1471
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1472
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1473
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1474
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1475
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1476
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1477
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1478
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1479
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1480
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1481
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1482
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1483
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1484
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1485
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1486
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1487
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1488
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1489
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1490
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1491
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1492
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1493
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1494
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1495
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1496
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1497
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1498
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1499
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1500
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1501
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1502
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1503
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1504
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1505
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1506
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1507
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1508
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1509
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1510
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1511
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1512
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1513
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1514
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1515
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1516
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1517
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1518
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1519
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1520
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1521
   "map": {"at": 36624, "to": "mm"},
1522
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1523
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1524
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1525
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1526
   "map": {"at": 36628, "to": "mm"},
1527
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1528
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1529
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1530
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1531
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1532
   "map": {"at": 36632, "to": "mm"},
1533
   "name": "SQ_IMG_RSRC_WORD2",
1534
   "type_ref": "SQ_IMG_RSRC_WORD2"
1535
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1536
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1537
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1538
   "map": {"at": 36636, "to": "mm"},
1539
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1540
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1541
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1542
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1543
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1544
   "map": {"at": 36640, "to": "mm"},
1545
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1546
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1547
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1548
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1549
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1550
   "map": {"at": 36644, "to": "mm"},
1551
   "name": "SQ_IMG_RSRC_WORD5",
1552
   "type_ref": "SQ_IMG_RSRC_WORD5"
1553
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1554
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1555
   "chips": ["gfx9"],
1556
   "map": {"at": 36648, "to": "mm"},
1557
   "name": "SQ_IMG_RSRC_WORD6",
1558
   "type_ref": "SQ_IMG_RSRC_WORD6"
1559
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1560
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1561
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1562
   "map": {"at": 36652, "to": "mm"},
1563
   "name": "SQ_IMG_RSRC_WORD7"
1564
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1565
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1566
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1567
   "map": {"at": 36656, "to": "mm"},
1568
   "name": "SQ_IMG_SAMP_WORD0",
1569
   "type_ref": "SQ_IMG_SAMP_WORD0"
1570
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1571
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1572
   "chips": ["gfx9"],
1573
   "map": {"at": 36660, "to": "mm"},
1574
   "name": "SQ_IMG_SAMP_WORD1",
1575
   "type_ref": "SQ_IMG_SAMP_WORD1"
1576
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1577
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1578
   "chips": ["gfx9"],
1579
   "map": {"at": 36664, "to": "mm"},
1580
   "name": "SQ_IMG_SAMP_WORD2",
1581
   "type_ref": "SQ_IMG_SAMP_WORD2"
1582
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1583
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1584
   "chips": ["gfx9"],
1585
   "map": {"at": 36668, "to": "mm"},
1586
   "name": "SQ_IMG_SAMP_WORD3",
1587
   "type_ref": "SQ_IMG_SAMP_WORD3"
1588
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1589
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1590
   "chips": ["gfx9"],
1591
   "map": {"at": 39160, "to": "mm"},
1592
   "name": "GB_ADDR_CONFIG",
1593
   "type_ref": "GB_ADDR_CONFIG"
1594
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1595
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1596
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1597
   "map": {"at": 39184, "to": "mm"},
1598
   "name": "GB_TILE_MODE0",
1599
   "type_ref": "GB_TILE_MODE0"
1600
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1601
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1602
   "chips": ["gfx9"],
1603
   "map": {"at": 39188, "to": "mm"},
1604
   "name": "GB_TILE_MODE1",
1605
   "type_ref": "GB_TILE_MODE0"
1606
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1607
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1608
   "chips": ["gfx9"],
1609
   "map": {"at": 39192, "to": "mm"},
1610
   "name": "GB_TILE_MODE2",
1611
   "type_ref": "GB_TILE_MODE0"
1612
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1613
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1614
   "chips": ["gfx9"],
1615
   "map": {"at": 39196, "to": "mm"},
1616
   "name": "GB_TILE_MODE3",
1617
   "type_ref": "GB_TILE_MODE0"
1618
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1619
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1620
   "chips": ["gfx9"],
1621
   "map": {"at": 39200, "to": "mm"},
1622
   "name": "GB_TILE_MODE4",
1623
   "type_ref": "GB_TILE_MODE0"
1624
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1625
  {
1626
   "chips": ["gfx9"],
1627
   "map": {"at": 39204, "to": "mm"},
1628
   "name": "GB_TILE_MODE5",
1629
   "type_ref": "GB_TILE_MODE0"
1630
  },
1631
  {
1632
   "chips": ["gfx9"],
1633
   "map": {"at": 39208, "to": "mm"},
1634
   "name": "GB_TILE_MODE6",
1635
   "type_ref": "GB_TILE_MODE0"
1636
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1637
  {
1638
   "chips": ["gfx9"],
1639
   "map": {"at": 39212, "to": "mm"},
1640
   "name": "GB_TILE_MODE7",
1641
   "type_ref": "GB_TILE_MODE0"
1642
  },
1643
  {
1644
   "chips": ["gfx9"],
1645
   "map": {"at": 39216, "to": "mm"},
1646
   "name": "GB_TILE_MODE8",
1647
   "type_ref": "GB_TILE_MODE0"
1648
  },
1649
  {
1650
   "chips": ["gfx9"],
1651
   "map": {"at": 39220, "to": "mm"},
1652
   "name": "GB_TILE_MODE9",
1653
   "type_ref": "GB_TILE_MODE0"
1654
  },
1655
  {
1656
   "chips": ["gfx9"],
1657
   "map": {"at": 39224, "to": "mm"},
1658
   "name": "GB_TILE_MODE10",
1659
   "type_ref": "GB_TILE_MODE0"
1660
  },
1661
  {
1662
   "chips": ["gfx9"],
1663
   "map": {"at": 39228, "to": "mm"},
1664
   "name": "GB_TILE_MODE11",
1665
   "type_ref": "GB_TILE_MODE0"
1666
  },
1667
  {
1668
   "chips": ["gfx9"],
1669
   "map": {"at": 39232, "to": "mm"},
1670
   "name": "GB_TILE_MODE12",
1671
   "type_ref": "GB_TILE_MODE0"
1672
  },
1673
  {
1674
   "chips": ["gfx9"],
1675
   "map": {"at": 39236, "to": "mm"},
1676
   "name": "GB_TILE_MODE13",
1677
   "type_ref": "GB_TILE_MODE0"
1678
  },
1679
  {
1680
   "chips": ["gfx9"],
1681
   "map": {"at": 39240, "to": "mm"},
1682
   "name": "GB_TILE_MODE14",
1683
   "type_ref": "GB_TILE_MODE0"
1684
  },
1685
  {
1686
   "chips": ["gfx9"],
1687
   "map": {"at": 39244, "to": "mm"},
1688
   "name": "GB_TILE_MODE15",
1689
   "type_ref": "GB_TILE_MODE0"
1690
  },
1691
  {
1692
   "chips": ["gfx9"],
1693
   "map": {"at": 39248, "to": "mm"},
1694
   "name": "GB_TILE_MODE16",
1695
   "type_ref": "GB_TILE_MODE0"
1696
  },
1697
  {
1698
   "chips": ["gfx9"],
1699
   "map": {"at": 39252, "to": "mm"},
1700
   "name": "GB_TILE_MODE17",
1701
   "type_ref": "GB_TILE_MODE0"
1702
  },
1703
  {
1704
   "chips": ["gfx9"],
1705
   "map": {"at": 39256, "to": "mm"},
1706
   "name": "GB_TILE_MODE18",
1707
   "type_ref": "GB_TILE_MODE0"
1708
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1709
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1710
   "chips": ["gfx9"],
1711
   "map": {"at": 39260, "to": "mm"},
1712
   "name": "GB_TILE_MODE19",
1713
   "type_ref": "GB_TILE_MODE0"
1714
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1715
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1716
   "chips": ["gfx9"],
1717
   "map": {"at": 39264, "to": "mm"},
1718
   "name": "GB_TILE_MODE20",
1719
   "type_ref": "GB_TILE_MODE0"
1720
  },
1721
  {
1722
   "chips": ["gfx9"],
1723
   "map": {"at": 39268, "to": "mm"},
1724
   "name": "GB_TILE_MODE21",
1725
   "type_ref": "GB_TILE_MODE0"
1726
  },
1727
  {
1728
   "chips": ["gfx9"],
1729
   "map": {"at": 39272, "to": "mm"},
1730
   "name": "GB_TILE_MODE22",
1731
   "type_ref": "GB_TILE_MODE0"
1732
  },
1733
  {
1734
   "chips": ["gfx9"],
1735
   "map": {"at": 39276, "to": "mm"},
1736
   "name": "GB_TILE_MODE23",
1737
   "type_ref": "GB_TILE_MODE0"
1738
  },
1739
  {
1740
   "chips": ["gfx9"],
1741
   "map": {"at": 39280, "to": "mm"},
1742
   "name": "GB_TILE_MODE24",
1743
   "type_ref": "GB_TILE_MODE0"
1744
  },
1745
  {
1746
   "chips": ["gfx9"],
1747
   "map": {"at": 39284, "to": "mm"},
1748
   "name": "GB_TILE_MODE25",
1749
   "type_ref": "GB_TILE_MODE0"
1750
  },
1751
  {
1752
   "chips": ["gfx9"],
1753
   "map": {"at": 39288, "to": "mm"},
1754
   "name": "GB_TILE_MODE26",
1755
   "type_ref": "GB_TILE_MODE0"
1756
  },
1757
  {
1758
   "chips": ["gfx9"],
1759
   "map": {"at": 39292, "to": "mm"},
1760
   "name": "GB_TILE_MODE27",
1761
   "type_ref": "GB_TILE_MODE0"
1762
  },
1763
  {
1764
   "chips": ["gfx9"],
1765
   "map": {"at": 39296, "to": "mm"},
1766
   "name": "GB_TILE_MODE28",
1767
   "type_ref": "GB_TILE_MODE0"
1768
  },
1769
  {
1770
   "chips": ["gfx9"],
1771
   "map": {"at": 39300, "to": "mm"},
1772
   "name": "GB_TILE_MODE29",
1773
   "type_ref": "GB_TILE_MODE0"
1774
  },
1775
  {
1776
   "chips": ["gfx9"],
1777
   "map": {"at": 39304, "to": "mm"},
1778
   "name": "GB_TILE_MODE30",
1779
   "type_ref": "GB_TILE_MODE0"
1780
  },
1781
  {
1782
   "chips": ["gfx9"],
1783
   "map": {"at": 39308, "to": "mm"},
1784
   "name": "GB_TILE_MODE31",
1785
   "type_ref": "GB_TILE_MODE0"
1786
  },
1787
  {
1788
   "chips": ["gfx9"],
1789
   "map": {"at": 39312, "to": "mm"},
1790
   "name": "GB_MACROTILE_MODE0",
1791
   "type_ref": "GB_MACROTILE_MODE0"
1792
  },
1793
  {
1794
   "chips": ["gfx9"],
1795
   "map": {"at": 39316, "to": "mm"},
1796
   "name": "GB_MACROTILE_MODE1",
1797
   "type_ref": "GB_MACROTILE_MODE0"
1798
  },
1799
  {
1800
   "chips": ["gfx9"],
1801
   "map": {"at": 39320, "to": "mm"},
1802
   "name": "GB_MACROTILE_MODE2",
1803
   "type_ref": "GB_MACROTILE_MODE0"
1804
  },
1805
  {
1806
   "chips": ["gfx9"],
1807
   "map": {"at": 39324, "to": "mm"},
1808
   "name": "GB_MACROTILE_MODE3",
1809
   "type_ref": "GB_MACROTILE_MODE0"
1810
  },
1811
  {
1812
   "chips": ["gfx9"],
1813
   "map": {"at": 39328, "to": "mm"},
1814
   "name": "GB_MACROTILE_MODE4",
1815
   "type_ref": "GB_MACROTILE_MODE0"
1816
  },
1817
  {
1818
   "chips": ["gfx9"],
1819
   "map": {"at": 39332, "to": "mm"},
1820
   "name": "GB_MACROTILE_MODE5",
1821
   "type_ref": "GB_MACROTILE_MODE0"
1822
  },
1823
  {
1824
   "chips": ["gfx9"],
1825
   "map": {"at": 39336, "to": "mm"},
1826
   "name": "GB_MACROTILE_MODE6",
1827
   "type_ref": "GB_MACROTILE_MODE0"
1828
  },
1829
  {
1830
   "chips": ["gfx9"],
1831
   "map": {"at": 39340, "to": "mm"},
1832
   "name": "GB_MACROTILE_MODE7",
1833
   "type_ref": "GB_MACROTILE_MODE0"
1834
  },
1835
  {
1836
   "chips": ["gfx9"],
1837
   "map": {"at": 39344, "to": "mm"},
1838
   "name": "GB_MACROTILE_MODE8",
1839
   "type_ref": "GB_MACROTILE_MODE0"
1840
  },
1841
  {
1842
   "chips": ["gfx9"],
1843
   "map": {"at": 39348, "to": "mm"},
1844
   "name": "GB_MACROTILE_MODE9",
1845
   "type_ref": "GB_MACROTILE_MODE0"
1846
  },
1847
  {
1848
   "chips": ["gfx9"],
1849
   "map": {"at": 39352, "to": "mm"},
1850
   "name": "GB_MACROTILE_MODE10",
1851
   "type_ref": "GB_MACROTILE_MODE0"
1852
  },
1853
  {
1854
   "chips": ["gfx9"],
1855
   "map": {"at": 39356, "to": "mm"},
1856
   "name": "GB_MACROTILE_MODE11",
1857
   "type_ref": "GB_MACROTILE_MODE0"
1858
  },
1859
  {
1860
   "chips": ["gfx9"],
1861
   "map": {"at": 39360, "to": "mm"},
1862
   "name": "GB_MACROTILE_MODE12",
1863
   "type_ref": "GB_MACROTILE_MODE0"
1864
  },
1865
  {
1866
   "chips": ["gfx9"],
1867
   "map": {"at": 39364, "to": "mm"},
1868
   "name": "GB_MACROTILE_MODE13",
1869
   "type_ref": "GB_MACROTILE_MODE0"
1870
  },
1871
  {
1872
   "chips": ["gfx9"],
1873
   "map": {"at": 39368, "to": "mm"},
1874
   "name": "GB_MACROTILE_MODE14",
1875
   "type_ref": "GB_MACROTILE_MODE0"
1876
  },
1877
  {
1878
   "chips": ["gfx9"],
1879
   "map": {"at": 39372, "to": "mm"},
1880
   "name": "GB_MACROTILE_MODE15",
1881
   "type_ref": "GB_MACROTILE_MODE0"
1882
  },
1883
  {
1884
   "chips": ["gfx9"],
1885
   "map": {"at": 45084, "to": "mm"},
1886
   "name": "SPI_SHADER_PGM_RSRC3_PS",
1887
   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1888
  },
1889
  {
1890
   "chips": ["gfx9"],
1891
   "map": {"at": 45088, "to": "mm"},
1892
   "name": "SPI_SHADER_PGM_LO_PS"
1893
  },
1894
  {
1895
   "chips": ["gfx9"],
1896
   "map": {"at": 45092, "to": "mm"},
1897
   "name": "SPI_SHADER_PGM_HI_PS",
1898
   "type_ref": "SPI_SHADER_PGM_HI_PS"
1899
  },
1900
  {
1901
   "chips": ["gfx9"],
1902
   "map": {"at": 45096, "to": "mm"},
1903
   "name": "SPI_SHADER_PGM_RSRC1_PS",
1904
   "type_ref": "SPI_SHADER_PGM_RSRC1_PS"
1905
  },
1906
  {
1907
   "chips": ["gfx9"],
1908
   "map": {"at": 45100, "to": "mm"},
1909
   "name": "SPI_SHADER_PGM_RSRC2_PS",
1910
   "type_ref": "SPI_SHADER_PGM_RSRC2_PS"
1911
  },
1912
  {
1913
   "chips": ["gfx9"],
1914
   "map": {"at": 45104, "to": "mm"},
1915
   "name": "SPI_SHADER_USER_DATA_PS_0"
1916
  },
1917
  {
1918
   "chips": ["gfx9"],
1919
   "map": {"at": 45108, "to": "mm"},
1920
   "name": "SPI_SHADER_USER_DATA_PS_1"
1921
  },
1922
  {
1923
   "chips": ["gfx9"],
1924
   "map": {"at": 45112, "to": "mm"},
1925
   "name": "SPI_SHADER_USER_DATA_PS_2"
1926
  },
1927
  {
1928
   "chips": ["gfx9"],
1929
   "map": {"at": 45116, "to": "mm"},
1930
   "name": "SPI_SHADER_USER_DATA_PS_3"
1931
  },
1932
  {
1933
   "chips": ["gfx9"],
1934
   "map": {"at": 45120, "to": "mm"},
1935
   "name": "SPI_SHADER_USER_DATA_PS_4"
1936
  },
1937
  {
1938
   "chips": ["gfx9"],
1939
   "map": {"at": 45124, "to": "mm"},
1940
   "name": "SPI_SHADER_USER_DATA_PS_5"
1941
  },
1942
  {
1943
   "chips": ["gfx9"],
1944
   "map": {"at": 45128, "to": "mm"},
1945
   "name": "SPI_SHADER_USER_DATA_PS_6"
1946
  },
1947
  {
1948
   "chips": ["gfx9"],
1949
   "map": {"at": 45132, "to": "mm"},
1950
   "name": "SPI_SHADER_USER_DATA_PS_7"
1951
  },
1952
  {
1953
   "chips": ["gfx9"],
1954
   "map": {"at": 45136, "to": "mm"},
1955
   "name": "SPI_SHADER_USER_DATA_PS_8"
1956
  },
1957
  {
1958
   "chips": ["gfx9"],
1959
   "map": {"at": 45140, "to": "mm"},
1960
   "name": "SPI_SHADER_USER_DATA_PS_9"
1961
  },
1962
  {
1963
   "chips": ["gfx9"],
1964
   "map": {"at": 45144, "to": "mm"},
1965
   "name": "SPI_SHADER_USER_DATA_PS_10"
1966
  },
1967
  {
1968
   "chips": ["gfx9"],
1969
   "map": {"at": 45148, "to": "mm"},
1970
   "name": "SPI_SHADER_USER_DATA_PS_11"
1971
  },
1972
  {
1973
   "chips": ["gfx9"],
1974
   "map": {"at": 45152, "to": "mm"},
1975
   "name": "SPI_SHADER_USER_DATA_PS_12"
1976
  },
1977
  {
1978
   "chips": ["gfx9"],
1979
   "map": {"at": 45156, "to": "mm"},
1980
   "name": "SPI_SHADER_USER_DATA_PS_13"
1981
  },
1982
  {
1983
   "chips": ["gfx9"],
1984
   "map": {"at": 45160, "to": "mm"},
1985
   "name": "SPI_SHADER_USER_DATA_PS_14"
1986
  },
1987
  {
1988
   "chips": ["gfx9"],
1989
   "map": {"at": 45164, "to": "mm"},
1990
   "name": "SPI_SHADER_USER_DATA_PS_15"
1991
  },
1992
  {
1993
   "chips": ["gfx9"],
1994
   "map": {"at": 45168, "to": "mm"},
1995
   "name": "SPI_SHADER_USER_DATA_PS_16"
1996
  },
1997
  {
1998
   "chips": ["gfx9"],
1999
   "map": {"at": 45172, "to": "mm"},
2000
   "name": "SPI_SHADER_USER_DATA_PS_17"
2001
  },
2002
  {
2003
   "chips": ["gfx9"],
2004
   "map": {"at": 45176, "to": "mm"},
2005
   "name": "SPI_SHADER_USER_DATA_PS_18"
2006
  },
2007
  {
2008
   "chips": ["gfx9"],
2009
   "map": {"at": 45180, "to": "mm"},
2010
   "name": "SPI_SHADER_USER_DATA_PS_19"
2011
  },
2012
  {
2013
   "chips": ["gfx9"],
2014
   "map": {"at": 45184, "to": "mm"},
2015
   "name": "SPI_SHADER_USER_DATA_PS_20"
2016
  },
2017
  {
2018
   "chips": ["gfx9"],
2019
   "map": {"at": 45188, "to": "mm"},
2020
   "name": "SPI_SHADER_USER_DATA_PS_21"
2021
  },
2022
  {
2023
   "chips": ["gfx9"],
2024
   "map": {"at": 45192, "to": "mm"},
2025
   "name": "SPI_SHADER_USER_DATA_PS_22"
2026
  },
2027
  {
2028
   "chips": ["gfx9"],
2029
   "map": {"at": 45196, "to": "mm"},
2030
   "name": "SPI_SHADER_USER_DATA_PS_23"
2031
  },
2032
  {
2033
   "chips": ["gfx9"],
2034
   "map": {"at": 45200, "to": "mm"},
2035
   "name": "SPI_SHADER_USER_DATA_PS_24"
2036
  },
2037
  {
2038
   "chips": ["gfx9"],
2039
   "map": {"at": 45204, "to": "mm"},
2040
   "name": "SPI_SHADER_USER_DATA_PS_25"
2041
  },
2042
  {
2043
   "chips": ["gfx9"],
2044
   "map": {"at": 45208, "to": "mm"},
2045
   "name": "SPI_SHADER_USER_DATA_PS_26"
2046
  },
2047
  {
2048
   "chips": ["gfx9"],
2049
   "map": {"at": 45212, "to": "mm"},
2050
   "name": "SPI_SHADER_USER_DATA_PS_27"
2051
  },
2052
  {
2053
   "chips": ["gfx9"],
2054
   "map": {"at": 45216, "to": "mm"},
2055
   "name": "SPI_SHADER_USER_DATA_PS_28"
2056
  },
2057
  {
2058
   "chips": ["gfx9"],
2059
   "map": {"at": 45220, "to": "mm"},
2060
   "name": "SPI_SHADER_USER_DATA_PS_29"
2061
  },
2062
  {
2063
   "chips": ["gfx9"],
2064
   "map": {"at": 45224, "to": "mm"},
2065
   "name": "SPI_SHADER_USER_DATA_PS_30"
2066
  },
2067
  {
2068
   "chips": ["gfx9"],
2069
   "map": {"at": 45228, "to": "mm"},
2070
   "name": "SPI_SHADER_USER_DATA_PS_31"
2071
  },
2072
  {
2073
   "chips": ["gfx9"],
2074
   "map": {"at": 45336, "to": "mm"},
2075
   "name": "SPI_SHADER_PGM_RSRC3_VS",
2076
   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
2077
  },
2078
  {
2079
   "chips": ["gfx9"],
2080
   "map": {"at": 45340, "to": "mm"},
2081
   "name": "SPI_SHADER_LATE_ALLOC_VS",
2082
   "type_ref": "SPI_SHADER_LATE_ALLOC_VS"
2083
  },
2084
  {
2085
   "chips": ["gfx9"],
2086
   "map": {"at": 45344, "to": "mm"},
2087
   "name": "SPI_SHADER_PGM_LO_VS"
2088
  },
2089
  {
2090
   "chips": ["gfx9"],
2091
   "map": {"at": 45348, "to": "mm"},
2092
   "name": "SPI_SHADER_PGM_HI_VS",
2093
   "type_ref": "SPI_SHADER_PGM_HI_PS"
2094
  },
2095
  {
2096
   "chips": ["gfx9"],
2097
   "map": {"at": 45352, "to": "mm"},
2098
   "name": "SPI_SHADER_PGM_RSRC1_VS",
2099
   "type_ref": "SPI_SHADER_PGM_RSRC1_VS"
2100
  },
2101
  {
2102
   "chips": ["gfx9"],
2103
   "map": {"at": 45356, "to": "mm"},
2104
   "name": "SPI_SHADER_PGM_RSRC2_VS",
2105
   "type_ref": "SPI_SHADER_PGM_RSRC2_VS"
2106
  },
2107
  {
2108
   "chips": ["gfx9"],
2109
   "map": {"at": 45360, "to": "mm"},
2110
   "name": "SPI_SHADER_USER_DATA_VS_0"
2111
  },
2112
  {
2113
   "chips": ["gfx9"],
2114
   "map": {"at": 45364, "to": "mm"},
2115
   "name": "SPI_SHADER_USER_DATA_VS_1"
2116
  },
2117
  {
2118
   "chips": ["gfx9"],
2119
   "map": {"at": 45368, "to": "mm"},
2120
   "name": "SPI_SHADER_USER_DATA_VS_2"
2121
  },
2122
  {
2123
   "chips": ["gfx9"],
2124
   "map": {"at": 45372, "to": "mm"},
2125
   "name": "SPI_SHADER_USER_DATA_VS_3"
2126
  },
2127
  {
2128
   "chips": ["gfx9"],
2129
   "map": {"at": 45376, "to": "mm"},
2130
   "name": "SPI_SHADER_USER_DATA_VS_4"
2131
  },
2132
  {
2133
   "chips": ["gfx9"],
2134
   "map": {"at": 45380, "to": "mm"},
2135
   "name": "SPI_SHADER_USER_DATA_VS_5"
2136
  },
2137
  {
2138
   "chips": ["gfx9"],
2139
   "map": {"at": 45384, "to": "mm"},
2140
   "name": "SPI_SHADER_USER_DATA_VS_6"
2141
  },
2142
  {
2143
   "chips": ["gfx9"],
2144
   "map": {"at": 45388, "to": "mm"},
2145
   "name": "SPI_SHADER_USER_DATA_VS_7"
2146
  },
2147
  {
2148
   "chips": ["gfx9"],
2149
   "map": {"at": 45392, "to": "mm"},
2150
   "name": "SPI_SHADER_USER_DATA_VS_8"
2151
  },
2152
  {
2153
   "chips": ["gfx9"],
2154
   "map": {"at": 45396, "to": "mm"},
2155
   "name": "SPI_SHADER_USER_DATA_VS_9"
2156
  },
2157
  {
2158
   "chips": ["gfx9"],
2159
   "map": {"at": 45400, "to": "mm"},
2160
   "name": "SPI_SHADER_USER_DATA_VS_10"
2161
  },
2162
  {
2163
   "chips": ["gfx9"],
2164
   "map": {"at": 45404, "to": "mm"},
2165
   "name": "SPI_SHADER_USER_DATA_VS_11"
2166
  },
2167
  {
2168
   "chips": ["gfx9"],
2169
   "map": {"at": 45408, "to": "mm"},
2170
   "name": "SPI_SHADER_USER_DATA_VS_12"
2171
  },
2172
  {
2173
   "chips": ["gfx9"],
2174
   "map": {"at": 45412, "to": "mm"},
2175
   "name": "SPI_SHADER_USER_DATA_VS_13"
2176
  },
2177
  {
2178
   "chips": ["gfx9"],
2179
   "map": {"at": 45416, "to": "mm"},
2180
   "name": "SPI_SHADER_USER_DATA_VS_14"
2181
  },
2182
  {
2183
   "chips": ["gfx9"],
2184
   "map": {"at": 45420, "to": "mm"},
2185
   "name": "SPI_SHADER_USER_DATA_VS_15"
2186
  },
2187
  {
2188
   "chips": ["gfx9"],
2189
   "map": {"at": 45424, "to": "mm"},
2190
   "name": "SPI_SHADER_USER_DATA_VS_16"
2191
  },
2192
  {
2193
   "chips": ["gfx9"],
2194
   "map": {"at": 45428, "to": "mm"},
2195
   "name": "SPI_SHADER_USER_DATA_VS_17"
2196
  },
2197
  {
2198
   "chips": ["gfx9"],
2199
   "map": {"at": 45432, "to": "mm"},
2200
   "name": "SPI_SHADER_USER_DATA_VS_18"
2201
  },
2202
  {
2203
   "chips": ["gfx9"],
2204
   "map": {"at": 45436, "to": "mm"},
2205
   "name": "SPI_SHADER_USER_DATA_VS_19"
2206
  },
2207
  {
2208
   "chips": ["gfx9"],
2209
   "map": {"at": 45440, "to": "mm"},
2210
   "name": "SPI_SHADER_USER_DATA_VS_20"
2211
  },
2212
  {
2213
   "chips": ["gfx9"],
2214
   "map": {"at": 45444, "to": "mm"},
2215
   "name": "SPI_SHADER_USER_DATA_VS_21"
2216
  },
2217
  {
2218
   "chips": ["gfx9"],
2219
   "map": {"at": 45448, "to": "mm"},
2220
   "name": "SPI_SHADER_USER_DATA_VS_22"
2221
  },
2222
  {
2223
   "chips": ["gfx9"],
2224
   "map": {"at": 45452, "to": "mm"},
2225
   "name": "SPI_SHADER_USER_DATA_VS_23"
2226
  },
2227
  {
2228
   "chips": ["gfx9"],
2229
   "map": {"at": 45456, "to": "mm"},
2230
   "name": "SPI_SHADER_USER_DATA_VS_24"
2231
  },
2232
  {
2233
   "chips": ["gfx9"],
2234
   "map": {"at": 45460, "to": "mm"},
2235
   "name": "SPI_SHADER_USER_DATA_VS_25"
2236
  },
2237
  {
2238
   "chips": ["gfx9"],
2239
   "map": {"at": 45464, "to": "mm"},
2240
   "name": "SPI_SHADER_USER_DATA_VS_26"
2241
  },
2242
  {
2243
   "chips": ["gfx9"],
2244
   "map": {"at": 45468, "to": "mm"},
2245
   "name": "SPI_SHADER_USER_DATA_VS_27"
2246
  },
2247
  {
2248
   "chips": ["gfx9"],
2249
   "map": {"at": 45472, "to": "mm"},
2250
   "name": "SPI_SHADER_USER_DATA_VS_28"
2251
  },
2252
  {
2253
   "chips": ["gfx9"],
2254
   "map": {"at": 45476, "to": "mm"},
2255
   "name": "SPI_SHADER_USER_DATA_VS_29"
2256
  },
2257
  {
2258
   "chips": ["gfx9"],
2259
   "map": {"at": 45480, "to": "mm"},
2260
   "name": "SPI_SHADER_USER_DATA_VS_30"
2261
  },
2262
  {
2263
   "chips": ["gfx9"],
2264
   "map": {"at": 45484, "to": "mm"},
2265
   "name": "SPI_SHADER_USER_DATA_VS_31"
2266
  },
2267
  {
2268
   "chips": ["gfx9"],
2269
   "map": {"at": 45552, "to": "mm"},
2270
   "name": "SPI_SHADER_PGM_RSRC2_GS_VS",
2271
   "type_ref": "SPI_SHADER_PGM_RSRC2_GS_VS"
2272
  },
2273
  {
2274
   "chips": ["gfx9"],
2275
   "map": {"at": 45572, "to": "mm"},
2276
   "name": "SPI_SHADER_PGM_RSRC4_GS",
2277
   "type_ref": "SPI_SHADER_PGM_RSRC4_GS"
2278
  },
2279
  {
2280
   "chips": ["gfx9"],
2281
   "map": {"at": 45576, "to": "mm"},
2282
   "name": "SPI_SHADER_USER_DATA_ADDR_LO_GS"
2283
  },
2284
  {
2285
   "chips": ["gfx9"],
2286
   "map": {"at": 45580, "to": "mm"},
2287
   "name": "SPI_SHADER_USER_DATA_ADDR_HI_GS"
2288
  },
2289
  {
2290
   "chips": ["gfx9"],
2291
   "map": {"at": 45584, "to": "mm"},
2292
   "name": "SPI_SHADER_PGM_LO_ES"
2293
  },
2294
  {
2295
   "chips": ["gfx9"],
2296
   "map": {"at": 45588, "to": "mm"},
2297
   "name": "SPI_SHADER_PGM_HI_ES",
2298
   "type_ref": "SPI_SHADER_PGM_HI_PS"
2299
  },
2300
  {
2301
   "chips": ["gfx9"],
2302
   "map": {"at": 45596, "to": "mm"},
2303
   "name": "SPI_SHADER_PGM_RSRC3_GS",
2304
   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
2305
  },
2306
  {
2307
   "chips": ["gfx9"],
2308
   "map": {"at": 45600, "to": "mm"},
2309
   "name": "SPI_SHADER_PGM_LO_GS"
2310
  },
2311
  {
2312
   "chips": ["gfx9"],
2313
   "map": {"at": 45604, "to": "mm"},
2314
   "name": "SPI_SHADER_PGM_HI_GS",
2315
   "type_ref": "SPI_SHADER_PGM_HI_PS"
2316
  },
2317
  {
2318
   "chips": ["gfx9"],
2319
   "map": {"at": 45608, "to": "mm"},
2320
   "name": "SPI_SHADER_PGM_RSRC1_GS",
2321
   "type_ref": "SPI_SHADER_PGM_RSRC1_GS"
2322
  },
2323
  {
2324
   "chips": ["gfx9"],
2325
   "map": {"at": 45612, "to": "mm"},
2326
   "name": "SPI_SHADER_PGM_RSRC2_GS",
2327
   "type_ref": "SPI_SHADER_PGM_RSRC2_GS"
2328
  },
2329
  {
2330
   "chips": ["gfx9"],
2331
   "map": {"at": 45872, "to": "mm"},
2332
   "name": "SPI_SHADER_USER_DATA_ES_0"
2333
  },
2334
  {
2335
   "chips": ["gfx9"],
2336
   "map": {"at": 45876, "to": "mm"},
2337
   "name": "SPI_SHADER_USER_DATA_ES_1"
2338
  },
2339
  {
2340
   "chips": ["gfx9"],
2341
   "map": {"at": 45880, "to": "mm"},
2342
   "name": "SPI_SHADER_USER_DATA_ES_2"
2343
  },
2344
  {
2345
   "chips": ["gfx9"],
2346
   "map": {"at": 45884, "to": "mm"},
2347
   "name": "SPI_SHADER_USER_DATA_ES_3"
2348
  },
2349
  {
2350
   "chips": ["gfx9"],
2351
   "map": {"at": 45888, "to": "mm"},
2352
   "name": "SPI_SHADER_USER_DATA_ES_4"
2353
  },
2354
  {
2355
   "chips": ["gfx9"],
2356
   "map": {"at": 45892, "to": "mm"},
2357
   "name": "SPI_SHADER_USER_DATA_ES_5"
2358
  },
2359
  {
2360
   "chips": ["gfx9"],
2361
   "map": {"at": 45896, "to": "mm"},
2362
   "name": "SPI_SHADER_USER_DATA_ES_6"
2363
  },
2364
  {
2365
   "chips": ["gfx9"],
2366
   "map": {"at": 45900, "to": "mm"},
2367
   "name": "SPI_SHADER_USER_DATA_ES_7"
2368
  },
2369
  {
2370
   "chips": ["gfx9"],
2371
   "map": {"at": 45904, "to": "mm"},
2372
   "name": "SPI_SHADER_USER_DATA_ES_8"
2373
  },
2374
  {
2375
   "chips": ["gfx9"],
2376
   "map": {"at": 45908, "to": "mm"},
2377
   "name": "SPI_SHADER_USER_DATA_ES_9"
2378
  },
2379
  {
2380
   "chips": ["gfx9"],
2381
   "map": {"at": 45912, "to": "mm"},
2382
   "name": "SPI_SHADER_USER_DATA_ES_10"
2383
  },
2384
  {
2385
   "chips": ["gfx9"],
2386
   "map": {"at": 45916, "to": "mm"},
2387
   "name": "SPI_SHADER_USER_DATA_ES_11"
2388
  },
2389
  {
2390
   "chips": ["gfx9"],
2391
   "map": {"at": 45920, "to": "mm"},
2392
   "name": "SPI_SHADER_USER_DATA_ES_12"
2393
  },
2394
  {
2395
   "chips": ["gfx9"],
2396
   "map": {"at": 45924, "to": "mm"},
2397
   "name": "SPI_SHADER_USER_DATA_ES_13"
2398
  },
2399
  {
2400
   "chips": ["gfx9"],
2401
   "map": {"at": 45928, "to": "mm"},
2402
   "name": "SPI_SHADER_USER_DATA_ES_14"
2403
  },
2404
  {
2405
   "chips": ["gfx9"],
2406
   "map": {"at": 45932, "to": "mm"},
2407
   "name": "SPI_SHADER_USER_DATA_ES_15"
2408
  },
2409
  {
2410
   "chips": ["gfx9"],
2411
   "map": {"at": 45936, "to": "mm"},
2412
   "name": "SPI_SHADER_USER_DATA_ES_16"
2413
  },
2414
  {
2415
   "chips": ["gfx9"],
2416
   "map": {"at": 45940, "to": "mm"},
2417
   "name": "SPI_SHADER_USER_DATA_ES_17"
2418
  },
2419
  {
2420
   "chips": ["gfx9"],
2421
   "map": {"at": 45944, "to": "mm"},
2422
   "name": "SPI_SHADER_USER_DATA_ES_18"
2423
  },
2424
  {
2425
   "chips": ["gfx9"],
2426
   "map": {"at": 45948, "to": "mm"},
2427
   "name": "SPI_SHADER_USER_DATA_ES_19"
2428
  },
2429
  {
2430
   "chips": ["gfx9"],
2431
   "map": {"at": 45952, "to": "mm"},
2432
   "name": "SPI_SHADER_USER_DATA_ES_20"
2433
  },
2434
  {
2435
   "chips": ["gfx9"],
2436
   "map": {"at": 45956, "to": "mm"},
2437
   "name": "SPI_SHADER_USER_DATA_ES_21"
2438
  },
2439
  {
2440
   "chips": ["gfx9"],
2441
   "map": {"at": 45960, "to": "mm"},
2442
   "name": "SPI_SHADER_USER_DATA_ES_22"
2443
  },
2444
  {
2445
   "chips": ["gfx9"],
2446
   "map": {"at": 45964, "to": "mm"},
2447
   "name": "SPI_SHADER_USER_DATA_ES_23"
2448
  },
2449
  {
2450
   "chips": ["gfx9"],
2451
   "map": {"at": 45968, "to": "mm"},
2452
   "name": "SPI_SHADER_USER_DATA_ES_24"
2453
  },
2454
  {
2455
   "chips": ["gfx9"],
2456
   "map": {"at": 45972, "to": "mm"},
2457
   "name": "SPI_SHADER_USER_DATA_ES_25"
2458
  },
2459
  {
2460
   "chips": ["gfx9"],
2461
   "map": {"at": 45976, "to": "mm"},
2462
   "name": "SPI_SHADER_USER_DATA_ES_26"
2463
  },
2464
  {
2465
   "chips": ["gfx9"],
2466
   "map": {"at": 45980, "to": "mm"},
2467
   "name": "SPI_SHADER_USER_DATA_ES_27"
2468
  },
2469
  {
2470
   "chips": ["gfx9"],
2471
   "map": {"at": 45984, "to": "mm"},
2472
   "name": "SPI_SHADER_USER_DATA_ES_28"
2473
  },
2474
  {
2475
   "chips": ["gfx9"],
2476
   "map": {"at": 45988, "to": "mm"},
2477
   "name": "SPI_SHADER_USER_DATA_ES_29"
2478
  },
2479
  {
2480
   "chips": ["gfx9"],
2481
   "map": {"at": 45992, "to": "mm"},
2482
   "name": "SPI_SHADER_USER_DATA_ES_30"
2483
  },
2484
  {
2485
   "chips": ["gfx9"],
2486
   "map": {"at": 45996, "to": "mm"},
2487
   "name": "SPI_SHADER_USER_DATA_ES_31"
2488
  },
2489
  {
2490
   "chips": ["gfx9"],
2491
   "map": {"at": 46084, "to": "mm"},
2492
   "name": "SPI_SHADER_PGM_RSRC4_HS",
2493
   "type_ref": "SPI_SHADER_PGM_RSRC4_HS"
2494
  },
2495
  {
2496
   "chips": ["gfx9"],
2497
   "map": {"at": 46088, "to": "mm"},
2498
   "name": "SPI_SHADER_USER_DATA_ADDR_LO_HS"
2499
  },
2500
  {
2501
   "chips": ["gfx9"],
2502
   "map": {"at": 46092, "to": "mm"},
2503
   "name": "SPI_SHADER_USER_DATA_ADDR_HI_HS"
2504
  },
2505
  {
2506
   "chips": ["gfx9"],
2507
   "map": {"at": 46096, "to": "mm"},
2508
   "name": "SPI_SHADER_PGM_LO_LS"
2509
  },
2510
  {
2511
   "chips": ["gfx9"],
2512
   "map": {"at": 46100, "to": "mm"},
2513
   "name": "SPI_SHADER_PGM_HI_LS",
2514
   "type_ref": "SPI_SHADER_PGM_HI_PS"
2515
  },
2516
  {
2517
   "chips": ["gfx9"],
2518
   "map": {"at": 46108, "to": "mm"},
2519
   "name": "SPI_SHADER_PGM_RSRC3_HS",
2520
   "type_ref": "SPI_SHADER_PGM_RSRC3_HS"
2521
  },
2522
  {
2523
   "chips": ["gfx9"],
2524
   "map": {"at": 46112, "to": "mm"},
2525
   "name": "SPI_SHADER_PGM_LO_HS"
2526
  },
2527
  {
2528
   "chips": ["gfx9"],
2529
   "map": {"at": 46116, "to": "mm"},
2530
   "name": "SPI_SHADER_PGM_HI_HS",
2531
   "type_ref": "SPI_SHADER_PGM_HI_PS"
2532
  },
2533
  {
2534
   "chips": ["gfx9"],
2535
   "map": {"at": 46120, "to": "mm"},
2536
   "name": "SPI_SHADER_PGM_RSRC1_HS",
2537
   "type_ref": "SPI_SHADER_PGM_RSRC1_HS"
2538
  },
2539
  {
2540
   "chips": ["gfx9"],
2541
   "map": {"at": 46124, "to": "mm"},
2542
   "name": "SPI_SHADER_PGM_RSRC2_HS",
2543
   "type_ref": "SPI_SHADER_PGM_RSRC2_HS"
2544
  },
2545
  {
2546
   "chips": ["gfx9"],
2547
   "map": {"at": 46128, "to": "mm"},
2548
   "name": "SPI_SHADER_USER_DATA_LS_0"
2549
  },
2550
  {
2551
   "chips": ["gfx9"],
2552
   "map": {"at": 46132, "to": "mm"},
2553
   "name": "SPI_SHADER_USER_DATA_LS_1"
2554
  },
2555
  {
2556
   "chips": ["gfx9"],
2557
   "map": {"at": 46136, "to": "mm"},
2558
   "name": "SPI_SHADER_USER_DATA_LS_2"
2559
  },
2560
  {
2561
   "chips": ["gfx9"],
2562
   "map": {"at": 46140, "to": "mm"},
2563
   "name": "SPI_SHADER_USER_DATA_LS_3"
2564
  },
2565
  {
2566
   "chips": ["gfx9"],
2567
   "map": {"at": 46144, "to": "mm"},
2568
   "name": "SPI_SHADER_USER_DATA_LS_4"
2569
  },
2570
  {
2571
   "chips": ["gfx9"],
2572
   "map": {"at": 46148, "to": "mm"},
2573
   "name": "SPI_SHADER_USER_DATA_LS_5"
2574
  },
2575
  {
2576
   "chips": ["gfx9"],
2577
   "map": {"at": 46152, "to": "mm"},
2578
   "name": "SPI_SHADER_USER_DATA_LS_6"
2579
  },
2580
  {
2581
   "chips": ["gfx9"],
2582
   "map": {"at": 46156, "to": "mm"},
2583
   "name": "SPI_SHADER_USER_DATA_LS_7"
2584
  },
2585
  {
2586
   "chips": ["gfx9"],
2587
   "map": {"at": 46160, "to": "mm"},
2588
   "name": "SPI_SHADER_USER_DATA_LS_8"
2589
  },
2590
  {
2591
   "chips": ["gfx9"],
2592
   "map": {"at": 46164, "to": "mm"},
2593
   "name": "SPI_SHADER_USER_DATA_LS_9"
2594
  },
2595
  {
2596
   "chips": ["gfx9"],
2597
   "map": {"at": 46168, "to": "mm"},
2598
   "name": "SPI_SHADER_USER_DATA_LS_10"
2599
  },
2600
  {
2601
   "chips": ["gfx9"],
2602
   "map": {"at": 46172, "to": "mm"},
2603
   "name": "SPI_SHADER_USER_DATA_LS_11"
2604
  },
2605
  {
2606
   "chips": ["gfx9"],
2607
   "map": {"at": 46176, "to": "mm"},
2608
   "name": "SPI_SHADER_USER_DATA_LS_12"
2609
  },
2610
  {
2611
   "chips": ["gfx9"],
2612
   "map": {"at": 46180, "to": "mm"},
2613
   "name": "SPI_SHADER_USER_DATA_LS_13"
2614
  },
2615
  {
2616
   "chips": ["gfx9"],
2617
   "map": {"at": 46184, "to": "mm"},
2618
   "name": "SPI_SHADER_USER_DATA_LS_14"
2619
  },
2620
  {
2621
   "chips": ["gfx9"],
2622
   "map": {"at": 46188, "to": "mm"},
2623
   "name": "SPI_SHADER_USER_DATA_LS_15"
2624
  },
2625
  {
2626
   "chips": ["gfx9"],
2627
   "map": {"at": 46192, "to": "mm"},
2628
   "name": "SPI_SHADER_USER_DATA_LS_16"
2629
  },
2630
  {
2631
   "chips": ["gfx9"],
2632
   "map": {"at": 46196, "to": "mm"},
2633
   "name": "SPI_SHADER_USER_DATA_LS_17"
2634
  },
2635
  {
2636
   "chips": ["gfx9"],
2637
   "map": {"at": 46200, "to": "mm"},
2638
   "name": "SPI_SHADER_USER_DATA_LS_18"
2639
  },
2640
  {
2641
   "chips": ["gfx9"],
2642
   "map": {"at": 46204, "to": "mm"},
2643
   "name": "SPI_SHADER_USER_DATA_LS_19"
2644
  },
2645
  {
2646
   "chips": ["gfx9"],
2647
   "map": {"at": 46208, "to": "mm"},
2648
   "name": "SPI_SHADER_USER_DATA_LS_20"
2649
  },
2650
  {
2651
   "chips": ["gfx9"],
2652
   "map": {"at": 46212, "to": "mm"},
2653
   "name": "SPI_SHADER_USER_DATA_LS_21"
2654
  },
2655
  {
2656
   "chips": ["gfx9"],
2657
   "map": {"at": 46216, "to": "mm"},
2658
   "name": "SPI_SHADER_USER_DATA_LS_22"
2659
  },
2660
  {
2661
   "chips": ["gfx9"],
2662
   "map": {"at": 46220, "to": "mm"},
2663
   "name": "SPI_SHADER_USER_DATA_LS_23"
2664
  },
2665
  {
2666
   "chips": ["gfx9"],
2667
   "map": {"at": 46224, "to": "mm"},
2668
   "name": "SPI_SHADER_USER_DATA_LS_24"
2669
  },
2670
  {
2671
   "chips": ["gfx9"],
2672
   "map": {"at": 46228, "to": "mm"},
2673
   "name": "SPI_SHADER_USER_DATA_LS_25"
2674
  },
2675
  {
2676
   "chips": ["gfx9"],
2677
   "map": {"at": 46232, "to": "mm"},
2678
   "name": "SPI_SHADER_USER_DATA_LS_26"
2679
  },
2680
  {
2681
   "chips": ["gfx9"],
2682
   "map": {"at": 46236, "to": "mm"},
2683
   "name": "SPI_SHADER_USER_DATA_LS_27"
2684
  },
2685
  {
2686
   "chips": ["gfx9"],
2687
   "map": {"at": 46240, "to": "mm"},
2688
   "name": "SPI_SHADER_USER_DATA_LS_28"
2689
  },
2690
  {
2691
   "chips": ["gfx9"],
2692
   "map": {"at": 46244, "to": "mm"},
2693
   "name": "SPI_SHADER_USER_DATA_LS_29"
2694
  },
2695
  {
2696
   "chips": ["gfx9"],
2697
   "map": {"at": 46248, "to": "mm"},
2698
   "name": "SPI_SHADER_USER_DATA_LS_30"
2699
  },
2700
  {
2701
   "chips": ["gfx9"],
2702
   "map": {"at": 46252, "to": "mm"},
2703
   "name": "SPI_SHADER_USER_DATA_LS_31"
2704
  },
2705
  {
2706
   "chips": ["gfx9"],
2707
   "map": {"at": 46384, "to": "mm"},
2708
   "name": "SPI_SHADER_USER_DATA_COMMON_0"
2709
  },
2710
  {
2711
   "chips": ["gfx9"],
2712
   "map": {"at": 46388, "to": "mm"},
2713
   "name": "SPI_SHADER_USER_DATA_COMMON_1"
2714
  },
2715
  {
2716
   "chips": ["gfx9"],
2717
   "map": {"at": 46392, "to": "mm"},
2718
   "name": "SPI_SHADER_USER_DATA_COMMON_2"
2719
  },
2720
  {
2721
   "chips": ["gfx9"],
2722
   "map": {"at": 46396, "to": "mm"},
2723
   "name": "SPI_SHADER_USER_DATA_COMMON_3"
2724
  },
2725
  {
2726
   "chips": ["gfx9"],
2727
   "map": {"at": 46400, "to": "mm"},
2728
   "name": "SPI_SHADER_USER_DATA_COMMON_4"
2729
  },
2730
  {
2731
   "chips": ["gfx9"],
2732
   "map": {"at": 46404, "to": "mm"},
2733
   "name": "SPI_SHADER_USER_DATA_COMMON_5"
2734
  },
2735
  {
2736
   "chips": ["gfx9"],
2737
   "map": {"at": 46408, "to": "mm"},
2738
   "name": "SPI_SHADER_USER_DATA_COMMON_6"
2739
  },
2740
  {
2741
   "chips": ["gfx9"],
2742
   "map": {"at": 46412, "to": "mm"},
2743
   "name": "SPI_SHADER_USER_DATA_COMMON_7"
2744
  },
2745
  {
2746
   "chips": ["gfx9"],
2747
   "map": {"at": 46416, "to": "mm"},
2748
   "name": "SPI_SHADER_USER_DATA_COMMON_8"
2749
  },
2750
  {
2751
   "chips": ["gfx9"],
2752
   "map": {"at": 46420, "to": "mm"},
2753
   "name": "SPI_SHADER_USER_DATA_COMMON_9"
2754
  },
2755
  {
2756
   "chips": ["gfx9"],
2757
   "map": {"at": 46424, "to": "mm"},
2758
   "name": "SPI_SHADER_USER_DATA_COMMON_10"
2759
  },
2760
  {
2761
   "chips": ["gfx9"],
2762
   "map": {"at": 46428, "to": "mm"},
2763
   "name": "SPI_SHADER_USER_DATA_COMMON_11"
2764
  },
2765
  {
2766
   "chips": ["gfx9"],
2767
   "map": {"at": 46432, "to": "mm"},
2768
   "name": "SPI_SHADER_USER_DATA_COMMON_12"
2769
  },
2770
  {
2771
   "chips": ["gfx9"],
2772
   "map": {"at": 46436, "to": "mm"},
2773
   "name": "SPI_SHADER_USER_DATA_COMMON_13"
2774
  },
2775
  {
2776
   "chips": ["gfx9"],
2777
   "map": {"at": 46440, "to": "mm"},
2778
   "name": "SPI_SHADER_USER_DATA_COMMON_14"
2779
  },
2780
  {
2781
   "chips": ["gfx9"],
2782
   "map": {"at": 46444, "to": "mm"},
2783
   "name": "SPI_SHADER_USER_DATA_COMMON_15"
2784
  },
2785
  {
2786
   "chips": ["gfx9"],
2787
   "map": {"at": 46448, "to": "mm"},
2788
   "name": "SPI_SHADER_USER_DATA_COMMON_16"
2789
  },
2790
  {
2791
   "chips": ["gfx9"],
2792
   "map": {"at": 46452, "to": "mm"},
2793
   "name": "SPI_SHADER_USER_DATA_COMMON_17"
2794
  },
2795
  {
2796
   "chips": ["gfx9"],
2797
   "map": {"at": 46456, "to": "mm"},
2798
   "name": "SPI_SHADER_USER_DATA_COMMON_18"
2799
  },
2800
  {
2801
   "chips": ["gfx9"],
2802
   "map": {"at": 46460, "to": "mm"},
2803
   "name": "SPI_SHADER_USER_DATA_COMMON_19"
2804
  },
2805
  {
2806
   "chips": ["gfx9"],
2807
   "map": {"at": 46464, "to": "mm"},
2808
   "name": "SPI_SHADER_USER_DATA_COMMON_20"
2809
  },
2810
  {
2811
   "chips": ["gfx9"],
2812
   "map": {"at": 46468, "to": "mm"},
2813
   "name": "SPI_SHADER_USER_DATA_COMMON_21"
2814
  },
2815
  {
2816
   "chips": ["gfx9"],
2817
   "map": {"at": 46472, "to": "mm"},
2818
   "name": "SPI_SHADER_USER_DATA_COMMON_22"
2819
  },
2820
  {
2821
   "chips": ["gfx9"],
2822
   "map": {"at": 46476, "to": "mm"},
2823
   "name": "SPI_SHADER_USER_DATA_COMMON_23"
2824
  },
2825
  {
2826
   "chips": ["gfx9"],
2827
   "map": {"at": 46480, "to": "mm"},
2828
   "name": "SPI_SHADER_USER_DATA_COMMON_24"
2829
  },
2830
  {
2831
   "chips": ["gfx9"],
2832
   "map": {"at": 46484, "to": "mm"},
2833
   "name": "SPI_SHADER_USER_DATA_COMMON_25"
2834
  },
2835
  {
2836
   "chips": ["gfx9"],
2837
   "map": {"at": 46488, "to": "mm"},
2838
   "name": "SPI_SHADER_USER_DATA_COMMON_26"
2839
  },
2840
  {
2841
   "chips": ["gfx9"],
2842
   "map": {"at": 46492, "to": "mm"},
2843
   "name": "SPI_SHADER_USER_DATA_COMMON_27"
2844
  },
2845
  {
2846
   "chips": ["gfx9"],
2847
   "map": {"at": 46496, "to": "mm"},
2848
   "name": "SPI_SHADER_USER_DATA_COMMON_28"
2849
  },
2850
  {
2851
   "chips": ["gfx9"],
2852
   "map": {"at": 46500, "to": "mm"},
2853
   "name": "SPI_SHADER_USER_DATA_COMMON_29"
2854
  },
2855
  {
2856
   "chips": ["gfx9"],
2857
   "map": {"at": 46504, "to": "mm"},
2858
   "name": "SPI_SHADER_USER_DATA_COMMON_30"
2859
  },
2860
  {
2861
   "chips": ["gfx9"],
2862
   "map": {"at": 46508, "to": "mm"},
2863
   "name": "SPI_SHADER_USER_DATA_COMMON_31"
2864
  },
2865
  {
2866
   "chips": ["gfx9"],
2867
   "map": {"at": 47104, "to": "mm"},
2868
   "name": "COMPUTE_DISPATCH_INITIATOR",
2869
   "type_ref": "COMPUTE_DISPATCH_INITIATOR"
2870
  },
2871
  {
2872
   "chips": ["gfx9"],
2873
   "map": {"at": 47108, "to": "mm"},
2874
   "name": "COMPUTE_DIM_X"
2875
  },
2876
  {
2877
   "chips": ["gfx9"],
2878
   "map": {"at": 47112, "to": "mm"},
2879
   "name": "COMPUTE_DIM_Y"
2880
  },
2881
  {
2882
   "chips": ["gfx9"],
2883
   "map": {"at": 47116, "to": "mm"},
2884
   "name": "COMPUTE_DIM_Z"
2885
  },
2886
  {
2887
   "chips": ["gfx9"],
2888
   "map": {"at": 47120, "to": "mm"},
2889
   "name": "COMPUTE_START_X"
2890
  },
2891
  {
2892
   "chips": ["gfx9"],
2893
   "map": {"at": 47124, "to": "mm"},
2894
   "name": "COMPUTE_START_Y"
2895
  },
2896
  {
2897
   "chips": ["gfx9"],
2898
   "map": {"at": 47128, "to": "mm"},
2899
   "name": "COMPUTE_START_Z"
2900
  },
2901
  {
2902
   "chips": ["gfx9"],
2903
   "map": {"at": 47132, "to": "mm"},
2904
   "name": "COMPUTE_NUM_THREAD_X",
2905
   "type_ref": "COMPUTE_NUM_THREAD_X"
2906
  },
2907
  {
2908
   "chips": ["gfx9"],
2909
   "map": {"at": 47136, "to": "mm"},
2910
   "name": "COMPUTE_NUM_THREAD_Y",
2911
   "type_ref": "COMPUTE_NUM_THREAD_X"
2912
  },
2913
  {
2914
   "chips": ["gfx9"],
2915
   "map": {"at": 47140, "to": "mm"},
2916
   "name": "COMPUTE_NUM_THREAD_Z",
2917
   "type_ref": "COMPUTE_NUM_THREAD_X"
2918
  },
2919
  {
2920
   "chips": ["gfx9"],
2921
   "map": {"at": 47144, "to": "mm"},
2922
   "name": "COMPUTE_PIPELINESTAT_ENABLE",
2923
   "type_ref": "COMPUTE_PIPELINESTAT_ENABLE"
2924
  },
2925
  {
2926
   "chips": ["gfx9"],
2927
   "map": {"at": 47148, "to": "mm"},
2928
   "name": "COMPUTE_PERFCOUNT_ENABLE",
2929
   "type_ref": "COMPUTE_PERFCOUNT_ENABLE"
2930
  },
2931
  {
2932
   "chips": ["gfx9"],
2933
   "map": {"at": 47152, "to": "mm"},
2934
   "name": "COMPUTE_PGM_LO"
2935
  },
2936
  {
2937
   "chips": ["gfx9"],
2938
   "map": {"at": 47156, "to": "mm"},
2939
   "name": "COMPUTE_PGM_HI",
2940
   "type_ref": "COMPUTE_PGM_HI"
2941
  },
2942
  {
2943
   "chips": ["gfx9"],
2944
   "map": {"at": 47160, "to": "mm"},
2945
   "name": "COMPUTE_DISPATCH_PKT_ADDR_LO"
2946
  },
2947
  {
2948
   "chips": ["gfx9"],
2949
   "map": {"at": 47164, "to": "mm"},
2950
   "name": "COMPUTE_DISPATCH_PKT_ADDR_HI",
2951
   "type_ref": "COMPUTE_PGM_HI"
2952
  },
2953
  {
2954
   "chips": ["gfx9"],
2955
   "map": {"at": 47168, "to": "mm"},
2956
   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_LO"
2957
  },
2958
  {
2959
   "chips": ["gfx9"],
2960
   "map": {"at": 47172, "to": "mm"},
2961
   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_HI",
2962
   "type_ref": "COMPUTE_PGM_HI"
2963
  },
2964
  {
2965
   "chips": ["gfx9"],
2966
   "map": {"at": 47176, "to": "mm"},
2967
   "name": "COMPUTE_PGM_RSRC1",
2968
   "type_ref": "COMPUTE_PGM_RSRC1"
2969
  },
2970
  {
2971
   "chips": ["gfx9"],
2972
   "map": {"at": 47180, "to": "mm"},
2973
   "name": "COMPUTE_PGM_RSRC2",
2974
   "type_ref": "COMPUTE_PGM_RSRC2"
2975
  },
2976
  {
2977
   "chips": ["gfx9"],
2978
   "map": {"at": 47184, "to": "mm"},
2979
   "name": "COMPUTE_VMID",
2980
   "type_ref": "COMPUTE_VMID"
2981
  },
2982
  {
2983
   "chips": ["gfx9"],
2984
   "map": {"at": 47188, "to": "mm"},
2985
   "name": "COMPUTE_RESOURCE_LIMITS",
2986
   "type_ref": "COMPUTE_RESOURCE_LIMITS"
2987
  },
2988
  {
2989
   "chips": ["gfx9"],
2990
   "map": {"at": 47192, "to": "mm"},
2991
   "name": "COMPUTE_STATIC_THREAD_MGMT_SE0",
2992
   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
2993
  },
2994
  {
2995
   "chips": ["gfx9"],
2996
   "map": {"at": 47196, "to": "mm"},
2997
   "name": "COMPUTE_STATIC_THREAD_MGMT_SE1",
2998
   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
2999
  },
3000
  {
3001
   "chips": ["gfx9"],
3002
   "map": {"at": 47200, "to": "mm"},
3003
   "name": "COMPUTE_TMPRING_SIZE",
3004
   "type_ref": "COMPUTE_TMPRING_SIZE"
3005
  },
3006
  {
3007
   "chips": ["gfx9"],
3008
   "map": {"at": 47204, "to": "mm"},
3009
   "name": "COMPUTE_STATIC_THREAD_MGMT_SE2",
3010
   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
3011
  },
3012
  {
3013
   "chips": ["gfx9"],
3014
   "map": {"at": 47208, "to": "mm"},
3015
   "name": "COMPUTE_STATIC_THREAD_MGMT_SE3",
3016
   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
3017
  },
3018
  {
3019
   "chips": ["gfx9"],
3020
   "map": {"at": 47212, "to": "mm"},
3021
   "name": "COMPUTE_RESTART_X"
3022
  },
3023
  {
3024
   "chips": ["gfx9"],
3025
   "map": {"at": 47216, "to": "mm"},
3026
   "name": "COMPUTE_RESTART_Y"
3027
  },
3028
  {
3029
   "chips": ["gfx9"],
3030
   "map": {"at": 47220, "to": "mm"},
3031
   "name": "COMPUTE_RESTART_Z"
3032
  },
3033
  {
3034
   "chips": ["gfx9"],
3035
   "map": {"at": 47224, "to": "mm"},
3036
   "name": "COMPUTE_THREAD_TRACE_ENABLE",
3037
   "type_ref": "COMPUTE_THREAD_TRACE_ENABLE"
3038
  },
3039
  {
3040
   "chips": ["gfx9"],
3041
   "map": {"at": 47228, "to": "mm"},
3042
   "name": "COMPUTE_MISC_RESERVED",
3043
   "type_ref": "COMPUTE_MISC_RESERVED"
3044
  },
3045
  {
3046
   "chips": ["gfx9"],
3047
   "map": {"at": 47232, "to": "mm"},
3048
   "name": "COMPUTE_DISPATCH_ID"
3049
  },
3050
  {
3051
   "chips": ["gfx9"],
3052
   "map": {"at": 47236, "to": "mm"},
3053
   "name": "COMPUTE_THREADGROUP_ID"
3054
  },
3055
  {
3056
   "chips": ["gfx9"],
3057
   "map": {"at": 47240, "to": "mm"},
3058
   "name": "COMPUTE_RELAUNCH",
3059
   "type_ref": "COMPUTE_RELAUNCH"
3060
  },
3061
  {
3062
   "chips": ["gfx9"],
3063
   "map": {"at": 47244, "to": "mm"},
3064
   "name": "COMPUTE_WAVE_RESTORE_ADDR_LO"
3065
  },
3066
  {
3067
   "chips": ["gfx9"],
3068
   "map": {"at": 47248, "to": "mm"},
3069
   "name": "COMPUTE_WAVE_RESTORE_ADDR_HI",
3070
   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_HI"
3071
  },
3072
  {
3073
   "chips": ["gfx9"],
3074
   "map": {"at": 47252, "to": "mm"},
3075
   "name": "COMPUTE_SHADER_CHKSUM"
3076
  },
3077
  {
3078
   "chips": ["gfx9"],
3079
   "map": {"at": 47360, "to": "mm"},
3080
   "name": "COMPUTE_USER_DATA_0"
3081
  },
3082
  {
3083
   "chips": ["gfx9"],
3084
   "map": {"at": 47364, "to": "mm"},
3085
   "name": "COMPUTE_USER_DATA_1"
3086
  },
3087
  {
3088
   "chips": ["gfx9"],
3089
   "map": {"at": 47368, "to": "mm"},
3090
   "name": "COMPUTE_USER_DATA_2"
3091
  },
3092
  {
3093
   "chips": ["gfx9"],
3094
   "map": {"at": 47372, "to": "mm"},
3095
   "name": "COMPUTE_USER_DATA_3"
3096
  },
3097
  {
3098
   "chips": ["gfx9"],
3099
   "map": {"at": 47376, "to": "mm"},
3100
   "name": "COMPUTE_USER_DATA_4"
3101
  },
3102
  {
3103
   "chips": ["gfx9"],
3104
   "map": {"at": 47380, "to": "mm"},
3105
   "name": "COMPUTE_USER_DATA_5"
3106
  },
3107
  {
3108
   "chips": ["gfx9"],
3109
   "map": {"at": 47384, "to": "mm"},
3110
   "name": "COMPUTE_USER_DATA_6"
3111
  },
3112
  {
3113
   "chips": ["gfx9"],
3114
   "map": {"at": 47388, "to": "mm"},
3115
   "name": "COMPUTE_USER_DATA_7"
3116
  },
3117
  {
3118
   "chips": ["gfx9"],
3119
   "map": {"at": 47392, "to": "mm"},
3120
   "name": "COMPUTE_USER_DATA_8"
3121
  },
3122
  {
3123
   "chips": ["gfx9"],
3124
   "map": {"at": 47396, "to": "mm"},
3125
   "name": "COMPUTE_USER_DATA_9"
3126
  },
3127
  {
3128
   "chips": ["gfx9"],
3129
   "map": {"at": 47400, "to": "mm"},
3130
   "name": "COMPUTE_USER_DATA_10"
3131
  },
3132
  {
3133
   "chips": ["gfx9"],
3134
   "map": {"at": 47404, "to": "mm"},
3135
   "name": "COMPUTE_USER_DATA_11"
3136
  },
3137
  {
3138
   "chips": ["gfx9"],
3139
   "map": {"at": 47408, "to": "mm"},
3140
   "name": "COMPUTE_USER_DATA_12"
3141
  },
3142
  {
3143
   "chips": ["gfx9"],
3144
   "map": {"at": 47412, "to": "mm"},
3145
   "name": "COMPUTE_USER_DATA_13"
3146
  },
3147
  {
3148
   "chips": ["gfx9"],
3149
   "map": {"at": 47416, "to": "mm"},
3150
   "name": "COMPUTE_USER_DATA_14"
3151
  },
3152
  {
3153
   "chips": ["gfx9"],
3154
   "map": {"at": 47420, "to": "mm"},
3155
   "name": "COMPUTE_USER_DATA_15"
3156
  },
3157
  {
3158
   "chips": ["gfx9"],
3159
   "map": {"at": 47608, "to": "mm"},
3160
   "name": "COMPUTE_DISPATCH_END"
3161
  },
3162
  {
3163
   "chips": ["gfx9"],
3164
   "map": {"at": 47612, "to": "mm"},
3165
   "name": "COMPUTE_NOWHERE"
3166
  },
3167
  {
3168
   "chips": ["gfx9"],
3169
   "map": {"at": 163840, "to": "mm"},
3170
   "name": "DB_RENDER_CONTROL",
3171
   "type_ref": "DB_RENDER_CONTROL"
3172
  },
3173
  {
3174
   "chips": ["gfx9"],
3175
   "map": {"at": 163844, "to": "mm"},
3176
   "name": "DB_COUNT_CONTROL",
3177
   "type_ref": "DB_COUNT_CONTROL"
3178
  },
3179
  {
3180
   "chips": ["gfx9"],
3181
   "map": {"at": 163848, "to": "mm"},
3182
   "name": "DB_DEPTH_VIEW",
3183
   "type_ref": "DB_DEPTH_VIEW"
3184
  },
3185
  {
3186
   "chips": ["gfx9"],
3187
   "map": {"at": 163852, "to": "mm"},
3188
   "name": "DB_RENDER_OVERRIDE",
3189
   "type_ref": "DB_RENDER_OVERRIDE"
3190
  },
3191
  {
3192
   "chips": ["gfx9"],
3193
   "map": {"at": 163856, "to": "mm"},
3194
   "name": "DB_RENDER_OVERRIDE2",
3195
   "type_ref": "DB_RENDER_OVERRIDE2"
3196
  },
3197
  {
3198
   "chips": ["gfx9"],
3199
   "map": {"at": 163860, "to": "mm"},
3200
   "name": "DB_HTILE_DATA_BASE"
3201
  },
3202
  {
3203
   "chips": ["gfx9"],
3204
   "map": {"at": 163864, "to": "mm"},
3205
   "name": "DB_HTILE_DATA_BASE_HI",
3206
   "type_ref": "DB_HTILE_DATA_BASE_HI"
3207
  },
3208
  {
3209
   "chips": ["gfx9"],
3210
   "map": {"at": 163868, "to": "mm"},
3211
   "name": "DB_DEPTH_SIZE",
3212
   "type_ref": "DB_DEPTH_SIZE"
3213
  },
3214
  {
3215
   "chips": ["gfx9"],
3216
   "map": {"at": 163872, "to": "mm"},
3217
   "name": "DB_DEPTH_BOUNDS_MIN"
3218
  },
3219
  {
3220
   "chips": ["gfx9"],
3221
   "map": {"at": 163876, "to": "mm"},
3222
   "name": "DB_DEPTH_BOUNDS_MAX"
3223
  },
3224
  {
3225
   "chips": ["gfx9"],
3226
   "map": {"at": 163880, "to": "mm"},
3227
   "name": "DB_STENCIL_CLEAR",
3228
   "type_ref": "DB_STENCIL_CLEAR"
3229
  },
3230
  {
3231
   "chips": ["gfx9"],
3232
   "map": {"at": 163884, "to": "mm"},
3233
   "name": "DB_DEPTH_CLEAR"
3234
  },
3235
  {
3236
   "chips": ["gfx9"],
3237
   "map": {"at": 163888, "to": "mm"},
3238
   "name": "PA_SC_SCREEN_SCISSOR_TL",
3239
   "type_ref": "PA_SC_SCREEN_SCISSOR_TL"
3240
  },
3241
  {
3242
   "chips": ["gfx9"],
3243
   "map": {"at": 163892, "to": "mm"},
3244
   "name": "PA_SC_SCREEN_SCISSOR_BR",
3245
   "type_ref": "PA_SC_SCREEN_SCISSOR_BR"
3246
  },
3247
  {
3248
   "chips": ["gfx9"],
3249
   "map": {"at": 163896, "to": "mm"},
3250
   "name": "DB_Z_INFO",
3251
   "type_ref": "DB_Z_INFO"
3252
  },
3253
  {
3254
   "chips": ["gfx9"],
3255
   "map": {"at": 163900, "to": "mm"},
3256
   "name": "DB_STENCIL_INFO",
3257
   "type_ref": "DB_STENCIL_INFO"
3258
  },
3259
  {
3260
   "chips": ["gfx9"],
3261
   "map": {"at": 163904, "to": "mm"},
3262
   "name": "DB_Z_READ_BASE"
3263
  },
3264
  {
3265
   "chips": ["gfx9"],
3266
   "map": {"at": 163908, "to": "mm"},
3267
   "name": "DB_Z_READ_BASE_HI",
3268
   "type_ref": "DB_HTILE_DATA_BASE_HI"
3269
  },
3270
  {
3271
   "chips": ["gfx9"],
3272
   "map": {"at": 163912, "to": "mm"},
3273
   "name": "DB_STENCIL_READ_BASE"
3274
  },
3275
  {
3276
   "chips": ["gfx9"],
3277
   "map": {"at": 163916, "to": "mm"},
3278
   "name": "DB_STENCIL_READ_BASE_HI",
3279
   "type_ref": "DB_HTILE_DATA_BASE_HI"
3280
  },
3281
  {
3282
   "chips": ["gfx9"],
3283
   "map": {"at": 163920, "to": "mm"},
3284
   "name": "DB_Z_WRITE_BASE"
3285
  },
3286
  {
3287
   "chips": ["gfx9"],
3288
   "map": {"at": 163924, "to": "mm"},
3289
   "name": "DB_Z_WRITE_BASE_HI",
3290
   "type_ref": "DB_HTILE_DATA_BASE_HI"
3291
  },
3292
  {
3293
   "chips": ["gfx9"],
3294
   "map": {"at": 163928, "to": "mm"},
3295
   "name": "DB_STENCIL_WRITE_BASE"
3296
  },
3297
  {
3298
   "chips": ["gfx9"],
3299
   "map": {"at": 163932, "to": "mm"},
3300
   "name": "DB_STENCIL_WRITE_BASE_HI",
3301
   "type_ref": "DB_HTILE_DATA_BASE_HI"
3302
  },
3303
  {
3304
   "chips": ["gfx9"],
3305
   "map": {"at": 163936, "to": "mm"},
3306
   "name": "DB_DFSM_CONTROL",
3307
   "type_ref": "DB_DFSM_CONTROL"
3308
  },
3309
  {
3310
   "chips": ["gfx9"],
3311
   "map": {"at": 163944, "to": "mm"},
3312
   "name": "DB_Z_INFO2",
3313
   "type_ref": "DB_Z_INFO2"
3314
  },
3315
  {
3316
   "chips": ["gfx9"],
3317
   "map": {"at": 163948, "to": "mm"},
3318
   "name": "DB_STENCIL_INFO2",
3319
   "type_ref": "DB_Z_INFO2"
3320
  },
3321
  {
3322
   "chips": ["gfx9"],
3323
   "map": {"at": 163968, "to": "mm"},
3324
   "name": "TA_BC_BASE_ADDR"
3325
  },
3326
  {
3327
   "chips": ["gfx9"],
3328
   "map": {"at": 163972, "to": "mm"},
3329
   "name": "TA_BC_BASE_ADDR_HI",
3330
   "type_ref": "TA_BC_BASE_ADDR_HI"
3331
  },
3332
  {
3333
   "chips": ["gfx9"],
3334
   "map": {"at": 164328, "to": "mm"},
3335
   "name": "COHER_DEST_BASE_HI_0",
3336
   "type_ref": "COHER_DEST_BASE_HI_0"
3337
  },
3338
  {
3339
   "chips": ["gfx9"],
3340
   "map": {"at": 164332, "to": "mm"},
3341
   "name": "COHER_DEST_BASE_HI_1",
3342
   "type_ref": "COHER_DEST_BASE_HI_0"
3343
  },
3344
  {
3345
   "chips": ["gfx9"],
3346
   "map": {"at": 164336, "to": "mm"},
3347
   "name": "COHER_DEST_BASE_HI_2",
3348
   "type_ref": "COHER_DEST_BASE_HI_0"
3349
  },
3350
  {
3351
   "chips": ["gfx9"],
3352
   "map": {"at": 164340, "to": "mm"},
3353
   "name": "COHER_DEST_BASE_HI_3",
3354
   "type_ref": "COHER_DEST_BASE_HI_0"
3355
  },
3356
  {
3357
   "chips": ["gfx9"],
3358
   "map": {"at": 164344, "to": "mm"},
3359
   "name": "COHER_DEST_BASE_2"
3360
  },
3361
  {
3362
   "chips": ["gfx9"],
3363
   "map": {"at": 164348, "to": "mm"},
3364
   "name": "COHER_DEST_BASE_3"
3365
  },
3366
  {
3367
   "chips": ["gfx9"],
3368
   "map": {"at": 164352, "to": "mm"},
3369
   "name": "PA_SC_WINDOW_OFFSET",
3370
   "type_ref": "PA_SC_WINDOW_OFFSET"
3371
  },
3372
  {
3373
   "chips": ["gfx9"],
3374
   "map": {"at": 164356, "to": "mm"},
3375
   "name": "PA_SC_WINDOW_SCISSOR_TL",
3376
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3377
  },
3378
  {
3379
   "chips": ["gfx9"],
3380
   "map": {"at": 164360, "to": "mm"},
3381
   "name": "PA_SC_WINDOW_SCISSOR_BR",
3382
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3383
  },
3384
  {
3385
   "chips": ["gfx9"],
3386
   "map": {"at": 164364, "to": "mm"},
3387
   "name": "PA_SC_CLIPRECT_RULE",
3388
   "type_ref": "PA_SC_CLIPRECT_RULE"
3389
  },
3390
  {
3391
   "chips": ["gfx9"],
3392
   "map": {"at": 164368, "to": "mm"},
3393
   "name": "PA_SC_CLIPRECT_0_TL",
3394
   "type_ref": "PA_SC_CLIPRECT_0_TL"
3395
  },
3396
  {
3397
   "chips": ["gfx9"],
3398
   "map": {"at": 164372, "to": "mm"},
3399
   "name": "PA_SC_CLIPRECT_0_BR",
3400
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3401
  },
3402
  {
3403
   "chips": ["gfx9"],
3404
   "map": {"at": 164376, "to": "mm"},
3405
   "name": "PA_SC_CLIPRECT_1_TL",
3406
   "type_ref": "PA_SC_CLIPRECT_0_TL"
3407
  },
3408
  {
3409
   "chips": ["gfx9"],
3410
   "map": {"at": 164380, "to": "mm"},
3411
   "name": "PA_SC_CLIPRECT_1_BR",
3412
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3413
  },
3414
  {
3415
   "chips": ["gfx9"],
3416
   "map": {"at": 164384, "to": "mm"},
3417
   "name": "PA_SC_CLIPRECT_2_TL",
3418
   "type_ref": "PA_SC_CLIPRECT_0_TL"
3419
  },
3420
  {
3421
   "chips": ["gfx9"],
3422
   "map": {"at": 164388, "to": "mm"},
3423
   "name": "PA_SC_CLIPRECT_2_BR",
3424
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3425
  },
3426
  {
3427
   "chips": ["gfx9"],
3428
   "map": {"at": 164392, "to": "mm"},
3429
   "name": "PA_SC_CLIPRECT_3_TL",
3430
   "type_ref": "PA_SC_CLIPRECT_0_TL"
3431
  },
3432
  {
3433
   "chips": ["gfx9"],
3434
   "map": {"at": 164396, "to": "mm"},
3435
   "name": "PA_SC_CLIPRECT_3_BR",
3436
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3437
  },
3438
  {
3439
   "chips": ["gfx9"],
3440
   "map": {"at": 164400, "to": "mm"},
3441
   "name": "PA_SC_EDGERULE",
3442
   "type_ref": "PA_SC_EDGERULE"
3443
  },
3444
  {
3445
   "chips": ["gfx9"],
3446
   "map": {"at": 164404, "to": "mm"},
3447
   "name": "PA_SU_HARDWARE_SCREEN_OFFSET",
3448
   "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET"
3449
  },
3450
  {
3451
   "chips": ["gfx9"],
3452
   "map": {"at": 164408, "to": "mm"},
3453
   "name": "CB_TARGET_MASK",
3454
   "type_ref": "CB_TARGET_MASK"
3455
  },
3456
  {
3457
   "chips": ["gfx9"],
3458
   "map": {"at": 164412, "to": "mm"},
3459
   "name": "CB_SHADER_MASK",
3460
   "type_ref": "CB_SHADER_MASK"
3461
  },
3462
  {
3463
   "chips": ["gfx9"],
3464
   "map": {"at": 164416, "to": "mm"},
3465
   "name": "PA_SC_GENERIC_SCISSOR_TL",
3466
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3467
  },
3468
  {
3469
   "chips": ["gfx9"],
3470
   "map": {"at": 164420, "to": "mm"},
3471
   "name": "PA_SC_GENERIC_SCISSOR_BR",
3472
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3473
  },
3474
  {
3475
   "chips": ["gfx9"],
3476
   "map": {"at": 164424, "to": "mm"},
3477
   "name": "COHER_DEST_BASE_0"
3478
  },
3479
  {
3480
   "chips": ["gfx9"],
3481
   "map": {"at": 164428, "to": "mm"},
3482
   "name": "COHER_DEST_BASE_1"
3483
  },
3484
  {
3485
   "chips": ["gfx9"],
3486
   "map": {"at": 164432, "to": "mm"},
3487
   "name": "PA_SC_VPORT_SCISSOR_0_TL",
3488
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3489
  },
3490
  {
3491
   "chips": ["gfx9"],
3492
   "map": {"at": 164436, "to": "mm"},
3493
   "name": "PA_SC_VPORT_SCISSOR_0_BR",
3494
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3495
  },
3496
  {
3497
   "chips": ["gfx9"],
3498
   "map": {"at": 164440, "to": "mm"},
3499
   "name": "PA_SC_VPORT_SCISSOR_1_TL",
3500
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3501
  },
3502
  {
3503
   "chips": ["gfx9"],
3504
   "map": {"at": 164444, "to": "mm"},
3505
   "name": "PA_SC_VPORT_SCISSOR_1_BR",
3506
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3507
  },
3508
  {
3509
   "chips": ["gfx9"],
3510
   "map": {"at": 164448, "to": "mm"},
3511
   "name": "PA_SC_VPORT_SCISSOR_2_TL",
3512
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3513
  },
3514
  {
3515
   "chips": ["gfx9"],
3516
   "map": {"at": 164452, "to": "mm"},
3517
   "name": "PA_SC_VPORT_SCISSOR_2_BR",
3518
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3519
  },
3520
  {
3521
   "chips": ["gfx9"],
3522
   "map": {"at": 164456, "to": "mm"},
3523
   "name": "PA_SC_VPORT_SCISSOR_3_TL",
3524
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3525
  },
3526
  {
3527
   "chips": ["gfx9"],
3528
   "map": {"at": 164460, "to": "mm"},
3529
   "name": "PA_SC_VPORT_SCISSOR_3_BR",
3530
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3531
  },
3532
  {
3533
   "chips": ["gfx9"],
3534
   "map": {"at": 164464, "to": "mm"},
3535
   "name": "PA_SC_VPORT_SCISSOR_4_TL",
3536
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3537
  },
3538
  {
3539
   "chips": ["gfx9"],
3540
   "map": {"at": 164468, "to": "mm"},
3541
   "name": "PA_SC_VPORT_SCISSOR_4_BR",
3542
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3543
  },
3544
  {
3545
   "chips": ["gfx9"],
3546
   "map": {"at": 164472, "to": "mm"},
3547
   "name": "PA_SC_VPORT_SCISSOR_5_TL",
3548
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3549
  },
3550
  {
3551
   "chips": ["gfx9"],
3552
   "map": {"at": 164476, "to": "mm"},
3553
   "name": "PA_SC_VPORT_SCISSOR_5_BR",
3554
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3555
  },
3556
  {
3557
   "chips": ["gfx9"],
3558
   "map": {"at": 164480, "to": "mm"},
3559
   "name": "PA_SC_VPORT_SCISSOR_6_TL",
3560
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3561
  },
3562
  {
3563
   "chips": ["gfx9"],
3564
   "map": {"at": 164484, "to": "mm"},
3565
   "name": "PA_SC_VPORT_SCISSOR_6_BR",
3566
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3567
  },
3568
  {
3569
   "chips": ["gfx9"],
3570
   "map": {"at": 164488, "to": "mm"},
3571
   "name": "PA_SC_VPORT_SCISSOR_7_TL",
3572
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3573
  },
3574
  {
3575
   "chips": ["gfx9"],
3576
   "map": {"at": 164492, "to": "mm"},
3577
   "name": "PA_SC_VPORT_SCISSOR_7_BR",
3578
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3579
  },
3580
  {
3581
   "chips": ["gfx9"],
3582
   "map": {"at": 164496, "to": "mm"},
3583
   "name": "PA_SC_VPORT_SCISSOR_8_TL",
3584
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3585
  },
3586
  {
3587
   "chips": ["gfx9"],
3588
   "map": {"at": 164500, "to": "mm"},
3589
   "name": "PA_SC_VPORT_SCISSOR_8_BR",
3590
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3591
  },
3592
  {
3593
   "chips": ["gfx9"],
3594
   "map": {"at": 164504, "to": "mm"},
3595
   "name": "PA_SC_VPORT_SCISSOR_9_TL",
3596
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3597
  },
3598
  {
3599
   "chips": ["gfx9"],
3600
   "map": {"at": 164508, "to": "mm"},
3601
   "name": "PA_SC_VPORT_SCISSOR_9_BR",
3602
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3603
  },
3604
  {
3605
   "chips": ["gfx9"],
3606
   "map": {"at": 164512, "to": "mm"},
3607
   "name": "PA_SC_VPORT_SCISSOR_10_TL",
3608
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3609
  },
3610
  {
3611
   "chips": ["gfx9"],
3612
   "map": {"at": 164516, "to": "mm"},
3613
   "name": "PA_SC_VPORT_SCISSOR_10_BR",
3614
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3615
  },
3616
  {
3617
   "chips": ["gfx9"],
3618
   "map": {"at": 164520, "to": "mm"},
3619
   "name": "PA_SC_VPORT_SCISSOR_11_TL",
3620
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3621
  },
3622
  {
3623
   "chips": ["gfx9"],
3624
   "map": {"at": 164524, "to": "mm"},
3625
   "name": "PA_SC_VPORT_SCISSOR_11_BR",
3626
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3627
  },
3628
  {
3629
   "chips": ["gfx9"],
3630
   "map": {"at": 164528, "to": "mm"},
3631
   "name": "PA_SC_VPORT_SCISSOR_12_TL",
3632
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3633
  },
3634
  {
3635
   "chips": ["gfx9"],
3636
   "map": {"at": 164532, "to": "mm"},
3637
   "name": "PA_SC_VPORT_SCISSOR_12_BR",
3638
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3639
  },
3640
  {
3641
   "chips": ["gfx9"],
3642
   "map": {"at": 164536, "to": "mm"},
3643
   "name": "PA_SC_VPORT_SCISSOR_13_TL",
3644
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3645
  },
3646
  {
3647
   "chips": ["gfx9"],
3648
   "map": {"at": 164540, "to": "mm"},
3649
   "name": "PA_SC_VPORT_SCISSOR_13_BR",
3650
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3651
  },
3652
  {
3653
   "chips": ["gfx9"],
3654
   "map": {"at": 164544, "to": "mm"},
3655
   "name": "PA_SC_VPORT_SCISSOR_14_TL",
3656
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3657
  },
3658
  {
3659
   "chips": ["gfx9"],
3660
   "map": {"at": 164548, "to": "mm"},
3661
   "name": "PA_SC_VPORT_SCISSOR_14_BR",
3662
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3663
  },
3664
  {
3665
   "chips": ["gfx9"],
3666
   "map": {"at": 164552, "to": "mm"},
3667
   "name": "PA_SC_VPORT_SCISSOR_15_TL",
3668
   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3669
  },
3670
  {
3671
   "chips": ["gfx9"],
3672
   "map": {"at": 164556, "to": "mm"},
3673
   "name": "PA_SC_VPORT_SCISSOR_15_BR",
3674
   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3675
  },
3676
  {
3677
   "chips": ["gfx9"],
3678
   "map": {"at": 164560, "to": "mm"},
3679
   "name": "PA_SC_VPORT_ZMIN_0"
3680
  },
3681
  {
3682
   "chips": ["gfx9"],
3683
   "map": {"at": 164564, "to": "mm"},
3684
   "name": "PA_SC_VPORT_ZMAX_0"
3685
  },
3686
  {
3687
   "chips": ["gfx9"],
3688
   "map": {"at": 164568, "to": "mm"},
3689
   "name": "PA_SC_VPORT_ZMIN_1"
3690
  },
3691
  {
3692
   "chips": ["gfx9"],
3693
   "map": {"at": 164572, "to": "mm"},
3694
   "name": "PA_SC_VPORT_ZMAX_1"
3695
  },
3696
  {
3697
   "chips": ["gfx9"],
3698
   "map": {"at": 164576, "to": "mm"},
3699
   "name": "PA_SC_VPORT_ZMIN_2"
3700
  },
3701
  {
3702
   "chips": ["gfx9"],
3703
   "map": {"at": 164580, "to": "mm"},
3704
   "name": "PA_SC_VPORT_ZMAX_2"
3705
  },
3706
  {
3707
   "chips": ["gfx9"],
3708
   "map": {"at": 164584, "to": "mm"},
3709
   "name": "PA_SC_VPORT_ZMIN_3"
3710
  },
3711
  {
3712
   "chips": ["gfx9"],
3713
   "map": {"at": 164588, "to": "mm"},
3714
   "name": "PA_SC_VPORT_ZMAX_3"
3715
  },
3716
  {
3717
   "chips": ["gfx9"],
3718
   "map": {"at": 164592, "to": "mm"},
3719
   "name": "PA_SC_VPORT_ZMIN_4"
3720
  },
3721
  {
3722
   "chips": ["gfx9"],
3723
   "map": {"at": 164596, "to": "mm"},
3724
   "name": "PA_SC_VPORT_ZMAX_4"
3725
  },
3726
  {
3727
   "chips": ["gfx9"],
3728
   "map": {"at": 164600, "to": "mm"},
3729
   "name": "PA_SC_VPORT_ZMIN_5"
3730
  },
3731
  {
3732
   "chips": ["gfx9"],
3733
   "map": {"at": 164604, "to": "mm"},
3734
   "name": "PA_SC_VPORT_ZMAX_5"
3735
  },
3736
  {
3737
   "chips": ["gfx9"],
3738
   "map": {"at": 164608, "to": "mm"},
3739
   "name": "PA_SC_VPORT_ZMIN_6"
3740
  },
3741
  {
3742
   "chips": ["gfx9"],
3743
   "map": {"at": 164612, "to": "mm"},
3744
   "name": "PA_SC_VPORT_ZMAX_6"
3745
  },
3746
  {
3747
   "chips": ["gfx9"],
3748
   "map": {"at": 164616, "to": "mm"},
3749
   "name": "PA_SC_VPORT_ZMIN_7"
3750
  },
3751
  {
3752
   "chips": ["gfx9"],
3753
   "map": {"at": 164620, "to": "mm"},
3754
   "name": "PA_SC_VPORT_ZMAX_7"
3755
  },
3756
  {
3757
   "chips": ["gfx9"],
3758
   "map": {"at": 164624, "to": "mm"},
3759
   "name": "PA_SC_VPORT_ZMIN_8"
3760
  },
3761
  {
3762
   "chips": ["gfx9"],
3763
   "map": {"at": 164628, "to": "mm"},
3764
   "name": "PA_SC_VPORT_ZMAX_8"
3765
  },
3766
  {
3767
   "chips": ["gfx9"],
3768
   "map": {"at": 164632, "to": "mm"},
3769
   "name": "PA_SC_VPORT_ZMIN_9"
3770
  },
3771
  {
3772
   "chips": ["gfx9"],
3773
   "map": {"at": 164636, "to": "mm"},
3774
   "name": "PA_SC_VPORT_ZMAX_9"
3775
  },
3776
  {
3777
   "chips": ["gfx9"],
3778
   "map": {"at": 164640, "to": "mm"},
3779
   "name": "PA_SC_VPORT_ZMIN_10"
3780
  },
3781
  {
3782
   "chips": ["gfx9"],
3783
   "map": {"at": 164644, "to": "mm"},
3784
   "name": "PA_SC_VPORT_ZMAX_10"
3785
  },
3786
  {
3787
   "chips": ["gfx9"],
3788
   "map": {"at": 164648, "to": "mm"},
3789
   "name": "PA_SC_VPORT_ZMIN_11"
3790
  },
3791
  {
3792
   "chips": ["gfx9"],
3793
   "map": {"at": 164652, "to": "mm"},
3794
   "name": "PA_SC_VPORT_ZMAX_11"
3795
  },
3796
  {
3797
   "chips": ["gfx9"],
3798
   "map": {"at": 164656, "to": "mm"},
3799
   "name": "PA_SC_VPORT_ZMIN_12"
3800
  },
3801
  {
3802
   "chips": ["gfx9"],
3803
   "map": {"at": 164660, "to": "mm"},
3804
   "name": "PA_SC_VPORT_ZMAX_12"
3805
  },
3806
  {
3807
   "chips": ["gfx9"],
3808
   "map": {"at": 164664, "to": "mm"},
3809
   "name": "PA_SC_VPORT_ZMIN_13"
3810
  },
3811
  {
3812
   "chips": ["gfx9"],
3813
   "map": {"at": 164668, "to": "mm"},
3814
   "name": "PA_SC_VPORT_ZMAX_13"
3815
  },
3816
  {
3817
   "chips": ["gfx9"],
3818
   "map": {"at": 164672, "to": "mm"},
3819
   "name": "PA_SC_VPORT_ZMIN_14"
3820
  },
3821
  {
3822
   "chips": ["gfx9"],
3823
   "map": {"at": 164676, "to": "mm"},
3824
   "name": "PA_SC_VPORT_ZMAX_14"
3825
  },
3826
  {
3827
   "chips": ["gfx9"],
3828
   "map": {"at": 164680, "to": "mm"},
3829
   "name": "PA_SC_VPORT_ZMIN_15"
3830
  },
3831
  {
3832
   "chips": ["gfx9"],
3833
   "map": {"at": 164684, "to": "mm"},
3834
   "name": "PA_SC_VPORT_ZMAX_15"
3835
  },
3836
  {
3837
   "chips": ["gfx9"],
3838
   "map": {"at": 164688, "to": "mm"},
3839
   "name": "PA_SC_RASTER_CONFIG",
3840
   "type_ref": "PA_SC_RASTER_CONFIG"
3841
  },
3842
  {
3843
   "chips": ["gfx9"],
3844
   "map": {"at": 164692, "to": "mm"},
3845
   "name": "PA_SC_RASTER_CONFIG_1",
3846
   "type_ref": "PA_SC_RASTER_CONFIG_1"
3847
  },
3848
  {
3849
   "chips": ["gfx9"],
3850
   "map": {"at": 164696, "to": "mm"},
3851
   "name": "PA_SC_SCREEN_EXTENT_CONTROL",
3852
   "type_ref": "PA_SC_SCREEN_EXTENT_CONTROL"
3853
  },
3854
  {
3855
   "chips": ["gfx9"],
3856
   "map": {"at": 164700, "to": "mm"},
3857
   "name": "PA_SC_TILE_STEERING_OVERRIDE",
3858
   "type_ref": "PA_SC_TILE_STEERING_OVERRIDE"
3859
  },
3860
  {
3861
   "chips": ["gfx9"],
3862
   "map": {"at": 164704, "to": "mm"},
3863
   "name": "CP_PERFMON_CNTX_CNTL",
3864
   "type_ref": "CP_PERFMON_CNTX_CNTL"
3865
  },
3866
  {
3867
   "chips": ["gfx9"],
3868
   "map": {"at": 164708, "to": "mm"},
3869
   "name": "CP_PIPEID",
3870
   "type_ref": "CP_PIPEID"
3871
  },
3872
  {
3873
   "chips": ["gfx9"],
3874
   "map": {"at": 164712, "to": "mm"},
3875
   "name": "CP_VMID",
3876
   "type_ref": "CP_VMID"
3877
  },
3878
  {
3879
   "chips": ["gfx9"],
3880
   "map": {"at": 164768, "to": "mm"},
3881
   "name": "PA_SC_RIGHT_VERT_GRID",
3882
   "type_ref": "PA_SC_RIGHT_VERT_GRID"
3883
  },
3884
  {
3885
   "chips": ["gfx9"],
3886
   "map": {"at": 164772, "to": "mm"},
3887
   "name": "PA_SC_LEFT_VERT_GRID",
3888
   "type_ref": "PA_SC_RIGHT_VERT_GRID"
3889
  },
3890
  {
3891
   "chips": ["gfx9"],
3892
   "map": {"at": 164776, "to": "mm"},
3893
   "name": "PA_SC_HORIZ_GRID",
3894
   "type_ref": "PA_SC_HORIZ_GRID"
3895
  },
3896
  {
3897
   "chips": ["gfx9"],
3898
   "map": {"at": 164876, "to": "mm"},
3899
   "name": "VGT_MULTI_PRIM_IB_RESET_INDX"
3900
  },
3901
  {
3902
   "chips": ["gfx9"],
3903
   "map": {"at": 164884, "to": "mm"},
3904
   "name": "CB_BLEND_RED"
3905
  },
3906
  {
3907
   "chips": ["gfx9"],
3908
   "map": {"at": 164888, "to": "mm"},
3909
   "name": "CB_BLEND_GREEN"
3910
  },
3911
  {
3912
   "chips": ["gfx9"],
3913
   "map": {"at": 164892, "to": "mm"},
3914
   "name": "CB_BLEND_BLUE"
3915
  },
3916
  {
3917
   "chips": ["gfx9"],
3918
   "map": {"at": 164896, "to": "mm"},
3919
   "name": "CB_BLEND_ALPHA"
3920
  },
3921
  {
3922
   "chips": ["gfx9"],
3923
   "map": {"at": 164900, "to": "mm"},
3924
   "name": "CB_DCC_CONTROL",
3925
   "type_ref": "CB_DCC_CONTROL"
3926
  },
3927
  {
3928
   "chips": ["gfx9"],
3929
   "map": {"at": 164908, "to": "mm"},
3930
   "name": "DB_STENCIL_CONTROL",
3931
   "type_ref": "DB_STENCIL_CONTROL"
3932
  },
3933
  {
3934
   "chips": ["gfx9"],
3935
   "map": {"at": 164912, "to": "mm"},
3936
   "name": "DB_STENCILREFMASK",
3937
   "type_ref": "DB_STENCILREFMASK"
3938
  },
3939
  {
3940
   "chips": ["gfx9"],
3941
   "map": {"at": 164916, "to": "mm"},
3942
   "name": "DB_STENCILREFMASK_BF",
3943
   "type_ref": "DB_STENCILREFMASK_BF"
3944
  },
3945
  {
3946
   "chips": ["gfx9"],
3947
   "map": {"at": 164924, "to": "mm"},
3948
   "name": "PA_CL_VPORT_XSCALE"
3949
  },
3950
  {
3951
   "chips": ["gfx9"],
3952
   "map": {"at": 164928, "to": "mm"},
3953
   "name": "PA_CL_VPORT_XOFFSET"
3954
  },
3955
  {
3956
   "chips": ["gfx9"],
3957
   "map": {"at": 164932, "to": "mm"},
3958
   "name": "PA_CL_VPORT_YSCALE"
3959
  },
3960
  {
3961
   "chips": ["gfx9"],
3962
   "map": {"at": 164936, "to": "mm"},
3963
   "name": "PA_CL_VPORT_YOFFSET"
3964
  },
3965
  {
3966
   "chips": ["gfx9"],
3967
   "map": {"at": 164940, "to": "mm"},
3968
   "name": "PA_CL_VPORT_ZSCALE"
3969
  },
3970
  {
3971
   "chips": ["gfx9"],
3972
   "map": {"at": 164944, "to": "mm"},
3973
   "name": "PA_CL_VPORT_ZOFFSET"
3974
  },
3975
  {
3976
   "chips": ["gfx9"],
3977
   "map": {"at": 164948, "to": "mm"},
3978
   "name": "PA_CL_VPORT_XSCALE_1"
3979
  },
3980
  {
3981
   "chips": ["gfx9"],
3982
   "map": {"at": 164952, "to": "mm"},
3983
   "name": "PA_CL_VPORT_XOFFSET_1"
3984
  },
3985
  {
3986
   "chips": ["gfx9"],
3987
   "map": {"at": 164956, "to": "mm"},
3988
   "name": "PA_CL_VPORT_YSCALE_1"
3989
  },
3990
  {
3991
   "chips": ["gfx9"],
3992
   "map": {"at": 164960, "to": "mm"},
3993
   "name": "PA_CL_VPORT_YOFFSET_1"
3994
  },
3995
  {
3996
   "chips": ["gfx9"],
3997
   "map": {"at": 164964, "to": "mm"},
3998
   "name": "PA_CL_VPORT_ZSCALE_1"
3999
  },
4000
  {
4001
   "chips": ["gfx9"],
4002
   "map": {"at": 164968, "to": "mm"},
4003
   "name": "PA_CL_VPORT_ZOFFSET_1"
4004
  },
4005
  {
4006
   "chips": ["gfx9"],
4007
   "map": {"at": 164972, "to": "mm"},
4008
   "name": "PA_CL_VPORT_XSCALE_2"
4009
  },
4010
  {
4011
   "chips": ["gfx9"],
4012
   "map": {"at": 164976, "to": "mm"},
4013
   "name": "PA_CL_VPORT_XOFFSET_2"
4014
  },
4015
  {
4016
   "chips": ["gfx9"],
4017
   "map": {"at": 164980, "to": "mm"},
4018
   "name": "PA_CL_VPORT_YSCALE_2"
4019
  },
4020
  {
4021
   "chips": ["gfx9"],
4022
   "map": {"at": 164984, "to": "mm"},
4023
   "name": "PA_CL_VPORT_YOFFSET_2"
4024
  },
4025
  {
4026
   "chips": ["gfx9"],
4027
   "map": {"at": 164988, "to": "mm"},
4028
   "name": "PA_CL_VPORT_ZSCALE_2"
4029
  },
4030
  {
4031
   "chips": ["gfx9"],
4032
   "map": {"at": 164992, "to": "mm"},
4033
   "name": "PA_CL_VPORT_ZOFFSET_2"
4034
  },
4035
  {
4036
   "chips": ["gfx9"],
4037
   "map": {"at": 164996, "to": "mm"},
4038
   "name": "PA_CL_VPORT_XSCALE_3"
4039
  },
4040
  {
4041
   "chips": ["gfx9"],
4042
   "map": {"at": 165000, "to": "mm"},
4043
   "name": "PA_CL_VPORT_XOFFSET_3"
4044
  },
4045
  {
4046
   "chips": ["gfx9"],
4047
   "map": {"at": 165004, "to": "mm"},
4048
   "name": "PA_CL_VPORT_YSCALE_3"
4049
  },
4050
  {
4051
   "chips": ["gfx9"],
4052
   "map": {"at": 165008, "to": "mm"},
4053
   "name": "PA_CL_VPORT_YOFFSET_3"
4054
  },
4055
  {
4056
   "chips": ["gfx9"],
4057
   "map": {"at": 165012, "to": "mm"},
4058
   "name": "PA_CL_VPORT_ZSCALE_3"
4059
  },
4060
  {
4061
   "chips": ["gfx9"],
4062
   "map": {"at": 165016, "to": "mm"},
4063
   "name": "PA_CL_VPORT_ZOFFSET_3"
4064
  },
4065
  {
4066
   "chips": ["gfx9"],
4067
   "map": {"at": 165020, "to": "mm"},
4068
   "name": "PA_CL_VPORT_XSCALE_4"
4069
  },
4070
  {
4071
   "chips": ["gfx9"],
4072
   "map": {"at": 165024, "to": "mm"},
4073
   "name": "PA_CL_VPORT_XOFFSET_4"
4074
  },
4075
  {
4076
   "chips": ["gfx9"],
4077
   "map": {"at": 165028, "to": "mm"},
4078
   "name": "PA_CL_VPORT_YSCALE_4"
4079
  },
4080
  {
4081
   "chips": ["gfx9"],
4082
   "map": {"at": 165032, "to": "mm"},
4083
   "name": "PA_CL_VPORT_YOFFSET_4"
4084
  },
4085
  {
4086
   "chips": ["gfx9"],
4087
   "map": {"at": 165036, "to": "mm"},
4088
   "name": "PA_CL_VPORT_ZSCALE_4"
4089
  },
4090
  {
4091
   "chips": ["gfx9"],
4092
   "map": {"at": 165040, "to": "mm"},
4093
   "name": "PA_CL_VPORT_ZOFFSET_4"
4094
  },
4095
  {
4096
   "chips": ["gfx9"],
4097
   "map": {"at": 165044, "to": "mm"},
4098
   "name": "PA_CL_VPORT_XSCALE_5"
4099
  },
4100
  {
4101
   "chips": ["gfx9"],
4102
   "map": {"at": 165048, "to": "mm"},
4103
   "name": "PA_CL_VPORT_XOFFSET_5"
4104
  },
4105
  {
4106
   "chips": ["gfx9"],
4107
   "map": {"at": 165052, "to": "mm"},
4108
   "name": "PA_CL_VPORT_YSCALE_5"
4109
  },
4110
  {
4111
   "chips": ["gfx9"],
4112
   "map": {"at": 165056, "to": "mm"},
4113
   "name": "PA_CL_VPORT_YOFFSET_5"
4114
  },
4115
  {
4116
   "chips": ["gfx9"],
4117
   "map": {"at": 165060, "to": "mm"},
4118
   "name": "PA_CL_VPORT_ZSCALE_5"
4119
  },
4120
  {
4121
   "chips": ["gfx9"],
4122
   "map": {"at": 165064, "to": "mm"},
4123
   "name": "PA_CL_VPORT_ZOFFSET_5"
4124
  },
4125
  {
4126
   "chips": ["gfx9"],
4127
   "map": {"at": 165068, "to": "mm"},
4128
   "name": "PA_CL_VPORT_XSCALE_6"
4129
  },
4130
  {
4131
   "chips": ["gfx9"],
4132
   "map": {"at": 165072, "to": "mm"},
4133
   "name": "PA_CL_VPORT_XOFFSET_6"
4134
  },
4135
  {
4136
   "chips": ["gfx9"],
4137
   "map": {"at": 165076, "to": "mm"},
4138
   "name": "PA_CL_VPORT_YSCALE_6"
4139
  },
4140
  {
4141
   "chips": ["gfx9"],
4142
   "map": {"at": 165080, "to": "mm"},
4143
   "name": "PA_CL_VPORT_YOFFSET_6"
4144
  },
4145
  {
4146
   "chips": ["gfx9"],
4147
   "map": {"at": 165084, "to": "mm"},
4148
   "name": "PA_CL_VPORT_ZSCALE_6"
4149
  },
4150
  {
4151
   "chips": ["gfx9"],
4152
   "map": {"at": 165088, "to": "mm"},
4153
   "name": "PA_CL_VPORT_ZOFFSET_6"
4154
  },
4155
  {
4156
   "chips": ["gfx9"],
4157
   "map": {"at": 165092, "to": "mm"},
4158
   "name": "PA_CL_VPORT_XSCALE_7"
4159
  },
4160
  {
4161
   "chips": ["gfx9"],
4162
   "map": {"at": 165096, "to": "mm"},
4163
   "name": "PA_CL_VPORT_XOFFSET_7"
4164
  },
4165
  {
4166
   "chips": ["gfx9"],
4167
   "map": {"at": 165100, "to": "mm"},
4168
   "name": "PA_CL_VPORT_YSCALE_7"
4169
  },
4170
  {
4171
   "chips": ["gfx9"],
4172
   "map": {"at": 165104, "to": "mm"},
4173
   "name": "PA_CL_VPORT_YOFFSET_7"
4174
  },
4175
  {
4176
   "chips": ["gfx9"],
4177
   "map": {"at": 165108, "to": "mm"},
4178
   "name": "PA_CL_VPORT_ZSCALE_7"
4179
  },
4180
  {
4181
   "chips": ["gfx9"],
4182
   "map": {"at": 165112, "to": "mm"},
4183
   "name": "PA_CL_VPORT_ZOFFSET_7"
4184
  },
4185
  {
4186
   "chips": ["gfx9"],
4187
   "map": {"at": 165116, "to": "mm"},
4188
   "name": "PA_CL_VPORT_XSCALE_8"
4189
  },
4190
  {
4191
   "chips": ["gfx9"],
4192
   "map": {"at": 165120, "to": "mm"},
4193
   "name": "PA_CL_VPORT_XOFFSET_8"
4194
  },
4195
  {
4196
   "chips": ["gfx9"],
4197
   "map": {"at": 165124, "to": "mm"},
4198
   "name": "PA_CL_VPORT_YSCALE_8"
4199
  },
4200
  {
4201
   "chips": ["gfx9"],
4202
   "map": {"at": 165128, "to": "mm"},
4203
   "name": "PA_CL_VPORT_YOFFSET_8"
4204
  },
4205
  {
4206
   "chips": ["gfx9"],
4207
   "map": {"at": 165132, "to": "mm"},
4208
   "name": "PA_CL_VPORT_ZSCALE_8"
4209
  },
4210
  {
4211
   "chips": ["gfx9"],
4212
   "map": {"at": 165136, "to": "mm"},
4213
   "name": "PA_CL_VPORT_ZOFFSET_8"
4214
  },
4215
  {
4216
   "chips": ["gfx9"],
4217
   "map": {"at": 165140, "to": "mm"},
4218
   "name": "PA_CL_VPORT_XSCALE_9"
4219
  },
4220
  {
4221
   "chips": ["gfx9"],
4222
   "map": {"at": 165144, "to": "mm"},
4223
   "name": "PA_CL_VPORT_XOFFSET_9"
4224
  },
4225
  {
4226
   "chips": ["gfx9"],
4227
   "map": {"at": 165148, "to": "mm"},
4228
   "name": "PA_CL_VPORT_YSCALE_9"
4229
  },
4230
  {
4231
   "chips": ["gfx9"],
4232
   "map": {"at": 165152, "to": "mm"},
4233
   "name": "PA_CL_VPORT_YOFFSET_9"
4234
  },
4235
  {
4236
   "chips": ["gfx9"],
4237
   "map": {"at": 165156, "to": "mm"},
4238
   "name": "PA_CL_VPORT_ZSCALE_9"
4239
  },
4240
  {
4241
   "chips": ["gfx9"],
4242
   "map": {"at": 165160, "to": "mm"},
4243
   "name": "PA_CL_VPORT_ZOFFSET_9"
4244
  },
4245
  {
4246
   "chips": ["gfx9"],
4247
   "map": {"at": 165164, "to": "mm"},
4248
   "name": "PA_CL_VPORT_XSCALE_10"
4249
  },
4250
  {
4251
   "chips": ["gfx9"],
4252
   "map": {"at": 165168, "to": "mm"},
4253
   "name": "PA_CL_VPORT_XOFFSET_10"
4254
  },
4255
  {
4256
   "chips": ["gfx9"],
4257
   "map": {"at": 165172, "to": "mm"},
4258
   "name": "PA_CL_VPORT_YSCALE_10"
4259
  },
4260
  {
4261
   "chips": ["gfx9"],
4262
   "map": {"at": 165176, "to": "mm"},
4263
   "name": "PA_CL_VPORT_YOFFSET_10"
4264
  },
4265
  {
4266
   "chips": ["gfx9"],
4267
   "map": {"at": 165180, "to": "mm"},
4268
   "name": "PA_CL_VPORT_ZSCALE_10"
4269
  },
4270
  {
4271
   "chips": ["gfx9"],
4272
   "map": {"at": 165184, "to": "mm"},
4273
   "name": "PA_CL_VPORT_ZOFFSET_10"
4274
  },
4275
  {
4276
   "chips": ["gfx9"],
4277
   "map": {"at": 165188, "to": "mm"},
4278
   "name": "PA_CL_VPORT_XSCALE_11"
4279
  },
4280
  {
4281
   "chips": ["gfx9"],
4282
   "map": {"at": 165192, "to": "mm"},
4283
   "name": "PA_CL_VPORT_XOFFSET_11"
4284
  },
4285
  {
4286
   "chips": ["gfx9"],
4287
   "map": {"at": 165196, "to": "mm"},
4288
   "name": "PA_CL_VPORT_YSCALE_11"
4289
  },
4290
  {
4291
   "chips": ["gfx9"],
4292
   "map": {"at": 165200, "to": "mm"},
4293
   "name": "PA_CL_VPORT_YOFFSET_11"
4294
  },
4295
  {
4296
   "chips": ["gfx9"],
4297
   "map": {"at": 165204, "to": "mm"},
4298
   "name": "PA_CL_VPORT_ZSCALE_11"
4299
  },
4300
  {
4301
   "chips": ["gfx9"],
4302
   "map": {"at": 165208, "to": "mm"},
4303
   "name": "PA_CL_VPORT_ZOFFSET_11"
4304
  },
4305
  {
4306
   "chips": ["gfx9"],
4307
   "map": {"at": 165212, "to": "mm"},
4308
   "name": "PA_CL_VPORT_XSCALE_12"
4309
  },
4310
  {
4311
   "chips": ["gfx9"],
4312
   "map": {"at": 165216, "to": "mm"},
4313
   "name": "PA_CL_VPORT_XOFFSET_12"
4314
  },
4315
  {
4316
   "chips": ["gfx9"],
4317
   "map": {"at": 165220, "to": "mm"},
4318
   "name": "PA_CL_VPORT_YSCALE_12"
4319
  },
4320
  {
4321
   "chips": ["gfx9"],
4322
   "map": {"at": 165224, "to": "mm"},
4323
   "name": "PA_CL_VPORT_YOFFSET_12"
4324
  },
4325
  {
4326
   "chips": ["gfx9"],
4327
   "map": {"at": 165228, "to": "mm"},
4328
   "name": "PA_CL_VPORT_ZSCALE_12"
4329
  },
4330
  {
4331
   "chips": ["gfx9"],
4332
   "map": {"at": 165232, "to": "mm"},
4333
   "name": "PA_CL_VPORT_ZOFFSET_12"
4334
  },
4335
  {
4336
   "chips": ["gfx9"],
4337
   "map": {"at": 165236, "to": "mm"},
4338
   "name": "PA_CL_VPORT_XSCALE_13"
4339
  },
4340
  {
4341
   "chips": ["gfx9"],
4342
   "map": {"at": 165240, "to": "mm"},
4343
   "name": "PA_CL_VPORT_XOFFSET_13"
4344
  },
4345
  {
4346
   "chips": ["gfx9"],
4347
   "map": {"at": 165244, "to": "mm"},
4348
   "name": "PA_CL_VPORT_YSCALE_13"
4349
  },
4350
  {
4351
   "chips": ["gfx9"],
4352
   "map": {"at": 165248, "to": "mm"},
4353
   "name": "PA_CL_VPORT_YOFFSET_13"
4354
  },
4355
  {
4356
   "chips": ["gfx9"],
4357
   "map": {"at": 165252, "to": "mm"},
4358
   "name": "PA_CL_VPORT_ZSCALE_13"
4359
  },
4360
  {
4361
   "chips": ["gfx9"],
4362
   "map": {"at": 165256, "to": "mm"},
4363
   "name": "PA_CL_VPORT_ZOFFSET_13"
4364
  },
4365
  {
4366
   "chips": ["gfx9"],
4367
   "map": {"at": 165260, "to": "mm"},
4368
   "name": "PA_CL_VPORT_XSCALE_14"
4369
  },
4370
  {
4371
   "chips": ["gfx9"],
4372
   "map": {"at": 165264, "to": "mm"},
4373
   "name": "PA_CL_VPORT_XOFFSET_14"
4374
  },
4375
  {
4376
   "chips": ["gfx9"],
4377
   "map": {"at": 165268, "to": "mm"},
4378
   "name": "PA_CL_VPORT_YSCALE_14"
4379
  },
4380
  {
4381
   "chips": ["gfx9"],
4382
   "map": {"at": 165272, "to": "mm"},
4383
   "name": "PA_CL_VPORT_YOFFSET_14"
4384
  },
4385
  {
4386
   "chips": ["gfx9"],
4387
   "map": {"at": 165276, "to": "mm"},
4388
   "name": "PA_CL_VPORT_ZSCALE_14"
4389
  },
4390
  {
4391
   "chips": ["gfx9"],
4392
   "map": {"at": 165280, "to": "mm"},
4393
   "name": "PA_CL_VPORT_ZOFFSET_14"
4394
  },
4395
  {
4396
   "chips": ["gfx9"],
4397
   "map": {"at": 165284, "to": "mm"},
4398
   "name": "PA_CL_VPORT_XSCALE_15"
4399
  },
4400
  {
4401
   "chips": ["gfx9"],
4402
   "map": {"at": 165288, "to": "mm"},
4403
   "name": "PA_CL_VPORT_XOFFSET_15"
4404
  },
4405
  {
4406
   "chips": ["gfx9"],
4407
   "map": {"at": 165292, "to": "mm"},
4408
   "name": "PA_CL_VPORT_YSCALE_15"
4409
  },
4410
  {
4411
   "chips": ["gfx9"],
4412
   "map": {"at": 165296, "to": "mm"},
4413
   "name": "PA_CL_VPORT_YOFFSET_15"
4414
  },
4415
  {
4416
   "chips": ["gfx9"],
4417
   "map": {"at": 165300, "to": "mm"},
4418
   "name": "PA_CL_VPORT_ZSCALE_15"
4419
  },
4420
  {
4421
   "chips": ["gfx9"],
4422
   "map": {"at": 165304, "to": "mm"},
4423
   "name": "PA_CL_VPORT_ZOFFSET_15"
4424
  },
4425
  {
4426
   "chips": ["gfx9"],
4427
   "map": {"at": 165308, "to": "mm"},
4428
   "name": "PA_CL_UCP_0_X"
4429
  },
4430
  {
4431
   "chips": ["gfx9"],
4432
   "map": {"at": 165312, "to": "mm"},
4433
   "name": "PA_CL_UCP_0_Y"
4434
  },
4435
  {
4436
   "chips": ["gfx9"],
4437
   "map": {"at": 165316, "to": "mm"},
4438
   "name": "PA_CL_UCP_0_Z"
4439
  },
4440
  {
4441
   "chips": ["gfx9"],
4442
   "map": {"at": 165320, "to": "mm"},
4443
   "name": "PA_CL_UCP_0_W"
4444
  },
4445
  {
4446
   "chips": ["gfx9"],
4447
   "map": {"at": 165324, "to": "mm"},
4448
   "name": "PA_CL_UCP_1_X"
4449
  },
4450
  {
4451
   "chips": ["gfx9"],
4452
   "map": {"at": 165328, "to": "mm"},
4453
   "name": "PA_CL_UCP_1_Y"
4454
  },
4455
  {
4456
   "chips": ["gfx9"],
4457
   "map": {"at": 165332, "to": "mm"},
4458
   "name": "PA_CL_UCP_1_Z"
4459
  },
4460
  {
4461
   "chips": ["gfx9"],
4462
   "map": {"at": 165336, "to": "mm"},
4463
   "name": "PA_CL_UCP_1_W"
4464
  },
4465
  {
4466
   "chips": ["gfx9"],
4467
   "map": {"at": 165340, "to": "mm"},
4468
   "name": "PA_CL_UCP_2_X"
4469
  },
4470
  {
4471
   "chips": ["gfx9"],
4472
   "map": {"at": 165344, "to": "mm"},
4473
   "name": "PA_CL_UCP_2_Y"
4474
  },
4475
  {
4476
   "chips": ["gfx9"],
4477
   "map": {"at": 165348, "to": "mm"},
4478
   "name": "PA_CL_UCP_2_Z"
4479
  },
4480
  {
4481
   "chips": ["gfx9"],
4482
   "map": {"at": 165352, "to": "mm"},
4483
   "name": "PA_CL_UCP_2_W"
4484
  },
4485
  {
4486
   "chips": ["gfx9"],
4487
   "map": {"at": 165356, "to": "mm"},
4488
   "name": "PA_CL_UCP_3_X"
4489
  },
4490
  {
4491
   "chips": ["gfx9"],
4492
   "map": {"at": 165360, "to": "mm"},
4493
   "name": "PA_CL_UCP_3_Y"
4494
  },
4495
  {
4496
   "chips": ["gfx9"],
4497
   "map": {"at": 165364, "to": "mm"},
4498
   "name": "PA_CL_UCP_3_Z"
4499
  },
4500
  {
4501
   "chips": ["gfx9"],
4502
   "map": {"at": 165368, "to": "mm"},
4503
   "name": "PA_CL_UCP_3_W"
4504
  },
4505
  {
4506
   "chips": ["gfx9"],
4507
   "map": {"at": 165372, "to": "mm"},
4508
   "name": "PA_CL_UCP_4_X"
4509
  },
4510
  {
4511
   "chips": ["gfx9"],
4512
   "map": {"at": 165376, "to": "mm"},
4513
   "name": "PA_CL_UCP_4_Y"
4514
  },
4515
  {
4516
   "chips": ["gfx9"],
4517
   "map": {"at": 165380, "to": "mm"},
4518
   "name": "PA_CL_UCP_4_Z"
4519
  },
4520
  {
4521
   "chips": ["gfx9"],
4522
   "map": {"at": 165384, "to": "mm"},
4523
   "name": "PA_CL_UCP_4_W"
4524
  },
4525
  {
4526
   "chips": ["gfx9"],
4527
   "map": {"at": 165388, "to": "mm"},
4528
   "name": "PA_CL_UCP_5_X"
4529
  },
4530
  {
4531
   "chips": ["gfx9"],
4532
   "map": {"at": 165392, "to": "mm"},
4533
   "name": "PA_CL_UCP_5_Y"
4534
  },
4535
  {
4536
   "chips": ["gfx9"],
4537
   "map": {"at": 165396, "to": "mm"},
4538
   "name": "PA_CL_UCP_5_Z"
4539
  },
4540
  {
4541
   "chips": ["gfx9"],
4542
   "map": {"at": 165400, "to": "mm"},
4543
   "name": "PA_CL_UCP_5_W"
4544
  },
4545
  {
4546
   "chips": ["gfx9"],
4547
   "map": {"at": 165404, "to": "mm"},
4548
   "name": "PA_CL_PROG_NEAR_CLIP_Z"
4549
  },
4550
  {
4551
   "chips": ["gfx9"],
4552
   "map": {"at": 165444, "to": "mm"},
4553
   "name": "SPI_PS_INPUT_CNTL_0",
4554
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4555
  },
4556
  {
4557
   "chips": ["gfx9"],
4558
   "map": {"at": 165448, "to": "mm"},
4559
   "name": "SPI_PS_INPUT_CNTL_1",
4560
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4561
  },
4562
  {
4563
   "chips": ["gfx9"],
4564
   "map": {"at": 165452, "to": "mm"},
4565
   "name": "SPI_PS_INPUT_CNTL_2",
4566
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4567
  },
4568
  {
4569
   "chips": ["gfx9"],
4570
   "map": {"at": 165456, "to": "mm"},
4571
   "name": "SPI_PS_INPUT_CNTL_3",
4572
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4573
  },
4574
  {
4575
   "chips": ["gfx9"],
4576
   "map": {"at": 165460, "to": "mm"},
4577
   "name": "SPI_PS_INPUT_CNTL_4",
4578
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4579
  },
4580
  {
4581
   "chips": ["gfx9"],
4582
   "map": {"at": 165464, "to": "mm"},
4583
   "name": "SPI_PS_INPUT_CNTL_5",
4584
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4585
  },
4586
  {
4587
   "chips": ["gfx9"],
4588
   "map": {"at": 165468, "to": "mm"},
4589
   "name": "SPI_PS_INPUT_CNTL_6",
4590
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4591
  },
4592
  {
4593
   "chips": ["gfx9"],
4594
   "map": {"at": 165472, "to": "mm"},
4595
   "name": "SPI_PS_INPUT_CNTL_7",
4596
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4597
  },
4598
  {
4599
   "chips": ["gfx9"],
4600
   "map": {"at": 165476, "to": "mm"},
4601
   "name": "SPI_PS_INPUT_CNTL_8",
4602
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4603
  },
4604
  {
4605
   "chips": ["gfx9"],
4606
   "map": {"at": 165480, "to": "mm"},
4607
   "name": "SPI_PS_INPUT_CNTL_9",
4608
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4609
  },
4610
  {
4611
   "chips": ["gfx9"],
4612
   "map": {"at": 165484, "to": "mm"},
4613
   "name": "SPI_PS_INPUT_CNTL_10",
4614
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4615
  },
4616
  {
4617
   "chips": ["gfx9"],
4618
   "map": {"at": 165488, "to": "mm"},
4619
   "name": "SPI_PS_INPUT_CNTL_11",
4620
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4621
  },
4622
  {
4623
   "chips": ["gfx9"],
4624
   "map": {"at": 165492, "to": "mm"},
4625
   "name": "SPI_PS_INPUT_CNTL_12",
4626
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4627
  },
4628
  {
4629
   "chips": ["gfx9"],
4630
   "map": {"at": 165496, "to": "mm"},
4631
   "name": "SPI_PS_INPUT_CNTL_13",
4632
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4633
  },
4634
  {
4635
   "chips": ["gfx9"],
4636
   "map": {"at": 165500, "to": "mm"},
4637
   "name": "SPI_PS_INPUT_CNTL_14",
4638
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4639
  },
4640
  {
4641
   "chips": ["gfx9"],
4642
   "map": {"at": 165504, "to": "mm"},
4643
   "name": "SPI_PS_INPUT_CNTL_15",
4644
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4645
  },
4646
  {
4647
   "chips": ["gfx9"],
4648
   "map": {"at": 165508, "to": "mm"},
4649
   "name": "SPI_PS_INPUT_CNTL_16",
4650
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4651
  },
4652
  {
4653
   "chips": ["gfx9"],
4654
   "map": {"at": 165512, "to": "mm"},
4655
   "name": "SPI_PS_INPUT_CNTL_17",
4656
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4657
  },
4658
  {
4659
   "chips": ["gfx9"],
4660
   "map": {"at": 165516, "to": "mm"},
4661
   "name": "SPI_PS_INPUT_CNTL_18",
4662
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4663
  },
4664
  {
4665
   "chips": ["gfx9"],
4666
   "map": {"at": 165520, "to": "mm"},
4667
   "name": "SPI_PS_INPUT_CNTL_19",
4668
   "type_ref": "SPI_PS_INPUT_CNTL_0"
4669
  },
4670
  {
4671
   "chips": ["gfx9"],
4672
   "map": {"at": 165524, "to": "mm"},
4673
   "name": "SPI_PS_INPUT_CNTL_20",
4674
   "type_ref": "SPI_PS_INPUT_CNTL_20"
4675
  },
4676
  {
4677
   "chips": ["gfx9"],
4678
   "map": {"at": 165528, "to": "mm"},
4679
   "name": "SPI_PS_INPUT_CNTL_21",
4680
   "type_ref": "SPI_PS_INPUT_CNTL_20"
4681
  },
4682
  {
4683
   "chips": ["gfx9"],
4684
   "map": {"at": 165532, "to": "mm"},
4685
   "name": "SPI_PS_INPUT_CNTL_22",
4686
   "type_ref": "SPI_PS_INPUT_CNTL_20"
4687
  },
4688
  {
4689
   "chips": ["gfx9"],
4690
   "map": {"at": 165536, "to": "mm"},
4691
   "name": "SPI_PS_INPUT_CNTL_23",
4692
   "type_ref": "SPI_PS_INPUT_CNTL_20"
4693
  },
4694
  {
4695
   "chips": ["gfx9"],
4696
   "map": {"at": 165540, "to": "mm"},
4697
   "name": "SPI_PS_INPUT_CNTL_24",
4698
   "type_ref": "SPI_PS_INPUT_CNTL_20"
4699
  },
4700
  {
4701
   "chips": ["gfx9"],
4702
   "map": {"at": 165544, "to": "mm"},
4703
   "name": "SPI_PS_INPUT_CNTL_25",
4704
   "type_ref": "SPI_PS_INPUT_CNTL_20"
4705
  },
4706
  {
4707
   "chips": ["gfx9"],
4708
   "map": {"at": 165548, "to": "mm"},
4709
   "name": "SPI_PS_INPUT_CNTL_26",
4710
   "type_ref": "SPI_PS_INPUT_CNTL_20"
4711
  },
4712
  {
4713
   "chips": ["gfx9"],
4714
   "map": {"at": 165552, "to": "mm"},
4715
   "name": "SPI_PS_INPUT_CNTL_27",
4716
   "type_ref": "SPI_PS_INPUT_CNTL_20"
4717
  },
4718
  {
4719
   "chips": ["gfx9"],
4720
   "map": {"at": 165556, "to": "mm"},
4721
   "name": "SPI_PS_INPUT_CNTL_28",
4722
   "type_ref": "SPI_PS_INPUT_CNTL_20"
4723
  },
4724
  {
4725
   "chips": ["gfx9"],
4726
   "map": {"at": 165560, "to": "mm"},
4727
   "name": "SPI_PS_INPUT_CNTL_29",
4728
   "type_ref": "SPI_PS_INPUT_CNTL_20"
4729
  },
4730
  {
4731
   "chips": ["gfx9"],
4732
   "map": {"at": 165564, "to": "mm"},
4733
   "name": "SPI_PS_INPUT_CNTL_30",
4734
   "type_ref": "SPI_PS_INPUT_CNTL_20"
4735
  },
4736
  {
4737
   "chips": ["gfx9"],
4738
   "map": {"at": 165568, "to": "mm"},
4739
   "name": "SPI_PS_INPUT_CNTL_31",
4740
   "type_ref": "SPI_PS_INPUT_CNTL_20"
4741
  },
4742
  {
4743
   "chips": ["gfx9"],
4744
   "map": {"at": 165572, "to": "mm"},
4745
   "name": "SPI_VS_OUT_CONFIG",
4746
   "type_ref": "SPI_VS_OUT_CONFIG"
4747
  },
4748
  {
4749
   "chips": ["gfx9"],
4750
   "map": {"at": 165580, "to": "mm"},
4751
   "name": "SPI_PS_INPUT_ENA",
4752
   "type_ref": "SPI_PS_INPUT_ENA"
4753
  },
4754
  {
4755
   "chips": ["gfx9"],
4756
   "map": {"at": 165584, "to": "mm"},
4757
   "name": "SPI_PS_INPUT_ADDR",
4758
   "type_ref": "SPI_PS_INPUT_ENA"
4759
  },
4760
  {
4761
   "chips": ["gfx9"],
4762
   "map": {"at": 165588, "to": "mm"},
4763
   "name": "SPI_INTERP_CONTROL_0",
4764
   "type_ref": "SPI_INTERP_CONTROL_0"
4765
  },
4766
  {
4767
   "chips": ["gfx9"],
4768
   "map": {"at": 165592, "to": "mm"},
4769
   "name": "SPI_PS_IN_CONTROL",
4770
   "type_ref": "SPI_PS_IN_CONTROL"
4771
  },
4772
  {
4773
   "chips": ["gfx9"],
4774
   "map": {"at": 165600, "to": "mm"},
4775
   "name": "SPI_BARYC_CNTL",
4776
   "type_ref": "SPI_BARYC_CNTL"
4777
  },
4778
  {
4779
   "chips": ["gfx9"],
4780
   "map": {"at": 165608, "to": "mm"},
4781
   "name": "SPI_TMPRING_SIZE",
4782
   "type_ref": "COMPUTE_TMPRING_SIZE"
4783
  },
4784
  {
4785
   "chips": ["gfx9"],
4786
   "map": {"at": 165644, "to": "mm"},
4787
   "name": "SPI_SHADER_POS_FORMAT",
4788
   "type_ref": "SPI_SHADER_POS_FORMAT"
4789
  },
4790
  {
4791
   "chips": ["gfx9"],
4792
   "map": {"at": 165648, "to": "mm"},
4793
   "name": "SPI_SHADER_Z_FORMAT",
4794
   "type_ref": "SPI_SHADER_Z_FORMAT"
4795
  },
4796
  {
4797
   "chips": ["gfx9"],
4798
   "map": {"at": 165652, "to": "mm"},
4799
   "name": "SPI_SHADER_COL_FORMAT",
4800
   "type_ref": "SPI_SHADER_COL_FORMAT"
4801
  },
4802
  {
4803
   "chips": ["gfx9"],
4804
   "map": {"at": 165716, "to": "mm"},
4805
   "name": "SX_PS_DOWNCONVERT",
4806
   "type_ref": "SX_PS_DOWNCONVERT"
4807
  },
4808
  {
4809
   "chips": ["gfx9"],
4810
   "map": {"at": 165720, "to": "mm"},
4811
   "name": "SX_BLEND_OPT_EPSILON",
4812
   "type_ref": "SX_BLEND_OPT_EPSILON"
4813
  },
4814
  {
4815
   "chips": ["gfx9"],
4816
   "map": {"at": 165724, "to": "mm"},
4817
   "name": "SX_BLEND_OPT_CONTROL",
4818
   "type_ref": "SX_BLEND_OPT_CONTROL"
4819
  },
4820
  {
4821
   "chips": ["gfx9"],
4822
   "map": {"at": 165728, "to": "mm"},
4823
   "name": "SX_MRT0_BLEND_OPT",
4824
   "type_ref": "SX_MRT0_BLEND_OPT"
4825
  },
4826
  {
4827
   "chips": ["gfx9"],
4828
   "map": {"at": 165732, "to": "mm"},
4829
   "name": "SX_MRT1_BLEND_OPT",
4830
   "type_ref": "SX_MRT0_BLEND_OPT"
4831
  },
4832
  {
4833
   "chips": ["gfx9"],
4834
   "map": {"at": 165736, "to": "mm"},
4835
   "name": "SX_MRT2_BLEND_OPT",
4836
   "type_ref": "SX_MRT0_BLEND_OPT"
4837
  },
4838
  {
4839
   "chips": ["gfx9"],
4840
   "map": {"at": 165740, "to": "mm"},
4841
   "name": "SX_MRT3_BLEND_OPT",
4842
   "type_ref": "SX_MRT0_BLEND_OPT"
4843
  },
4844
  {
4845
   "chips": ["gfx9"],
4846
   "map": {"at": 165744, "to": "mm"},
4847
   "name": "SX_MRT4_BLEND_OPT",
4848
   "type_ref": "SX_MRT0_BLEND_OPT"
4849
  },
4850
  {
4851
   "chips": ["gfx9"],
4852
   "map": {"at": 165748, "to": "mm"},
4853
   "name": "SX_MRT5_BLEND_OPT",
4854
   "type_ref": "SX_MRT0_BLEND_OPT"
4855
  },
4856
  {
4857
   "chips": ["gfx9"],
4858
   "map": {"at": 165752, "to": "mm"},
4859
   "name": "SX_MRT6_BLEND_OPT",
4860
   "type_ref": "SX_MRT0_BLEND_OPT"
4861
  },
4862
  {
4863
   "chips": ["gfx9"],
4864
   "map": {"at": 165756, "to": "mm"},
4865
   "name": "SX_MRT7_BLEND_OPT",
4866
   "type_ref": "SX_MRT0_BLEND_OPT"
4867
  },
4868
  {
4869
   "chips": ["gfx9"],
4870
   "map": {"at": 165760, "to": "mm"},
4871
   "name": "CB_BLEND0_CONTROL",
4872
   "type_ref": "CB_BLEND0_CONTROL"
4873
  },
4874
  {
4875
   "chips": ["gfx9"],
4876
   "map": {"at": 165764, "to": "mm"},
4877
   "name": "CB_BLEND1_CONTROL",
4878
   "type_ref": "CB_BLEND0_CONTROL"
4879
  },
4880
  {
4881
   "chips": ["gfx9"],
4882
   "map": {"at": 165768, "to": "mm"},
4883
   "name": "CB_BLEND2_CONTROL",
4884
   "type_ref": "CB_BLEND0_CONTROL"
4885
  },
4886
  {
4887
   "chips": ["gfx9"],
4888
   "map": {"at": 165772, "to": "mm"},
4889
   "name": "CB_BLEND3_CONTROL",
4890
   "type_ref": "CB_BLEND0_CONTROL"
4891
  },
4892
  {
4893
   "chips": ["gfx9"],
4894
   "map": {"at": 165776, "to": "mm"},
4895
   "name": "CB_BLEND4_CONTROL",
4896
   "type_ref": "CB_BLEND0_CONTROL"
4897
  },
4898
  {
4899
   "chips": ["gfx9"],
4900
   "map": {"at": 165780, "to": "mm"},
4901
   "name": "CB_BLEND5_CONTROL",
4902
   "type_ref": "CB_BLEND0_CONTROL"
4903
  },
4904
  {
4905
   "chips": ["gfx9"],
4906
   "map": {"at": 165784, "to": "mm"},
4907
   "name": "CB_BLEND6_CONTROL",
4908
   "type_ref": "CB_BLEND0_CONTROL"
4909
  },
4910
  {
4911
   "chips": ["gfx9"],
4912
   "map": {"at": 165788, "to": "mm"},
4913
   "name": "CB_BLEND7_CONTROL",
4914
   "type_ref": "CB_BLEND0_CONTROL"
4915
  },
4916
  {
4917
   "chips": ["gfx9"],
4918
   "map": {"at": 165792, "to": "mm"},
4919
   "name": "CB_MRT0_EPITCH",
4920
   "type_ref": "DB_Z_INFO2"
4921
  },
4922
  {
4923
   "chips": ["gfx9"],
4924
   "map": {"at": 165796, "to": "mm"},
4925
   "name": "CB_MRT1_EPITCH",
4926
   "type_ref": "DB_Z_INFO2"
4927
  },
4928
  {
4929
   "chips": ["gfx9"],
4930
   "map": {"at": 165800, "to": "mm"},
4931
   "name": "CB_MRT2_EPITCH",
4932
   "type_ref": "DB_Z_INFO2"
4933
  },
4934
  {
4935
   "chips": ["gfx9"],
4936
   "map": {"at": 165804, "to": "mm"},
4937
   "name": "CB_MRT3_EPITCH",
4938
   "type_ref": "DB_Z_INFO2"
4939
  },
4940
  {
4941
   "chips": ["gfx9"],
4942
   "map": {"at": 165808, "to": "mm"},
4943
   "name": "CB_MRT4_EPITCH",
4944
   "type_ref": "DB_Z_INFO2"
4945
  },
4946
  {
4947
   "chips": ["gfx9"],
4948
   "map": {"at": 165812, "to": "mm"},
4949
   "name": "CB_MRT5_EPITCH",
4950
   "type_ref": "DB_Z_INFO2"
4951
  },
4952
  {
4953
   "chips": ["gfx9"],
4954
   "map": {"at": 165816, "to": "mm"},
4955
   "name": "CB_MRT6_EPITCH",
4956
   "type_ref": "DB_Z_INFO2"
4957
  },
4958
  {
4959
   "chips": ["gfx9"],
4960
   "map": {"at": 165820, "to": "mm"},
4961
   "name": "CB_MRT7_EPITCH",
4962
   "type_ref": "DB_Z_INFO2"
4963
  },
4964
  {
4965
   "chips": ["gfx9"],
4966
   "map": {"at": 165836, "to": "mm"},
4967
   "name": "CS_COPY_STATE",
4968
   "type_ref": "CS_COPY_STATE"
4969
  },
4970
  {
4971
   "chips": ["gfx9"],
4972
   "map": {"at": 165840, "to": "mm"},
4973
   "name": "GFX_COPY_STATE",
4974
   "type_ref": "CS_COPY_STATE"
4975
  },
4976
  {
4977
   "chips": ["gfx9"],
4978
   "map": {"at": 165844, "to": "mm"},
4979
   "name": "PA_CL_POINT_X_RAD"
4980
  },
4981
  {
4982
   "chips": ["gfx9"],
4983
   "map": {"at": 165848, "to": "mm"},
4984
   "name": "PA_CL_POINT_Y_RAD"
4985
  },
4986
  {
4987
   "chips": ["gfx9"],
4988
   "map": {"at": 165852, "to": "mm"},
4989
   "name": "PA_CL_POINT_SIZE"
4990
  },
4991
  {
4992
   "chips": ["gfx9"],
4993
   "map": {"at": 165856, "to": "mm"},
4994
   "name": "PA_CL_POINT_CULL_RAD"
4995
  },
4996
  {
4997
   "chips": ["gfx9"],
4998
   "map": {"at": 165860, "to": "mm"},
4999
   "name": "VGT_DMA_BASE_HI",
5000
   "type_ref": "VGT_DMA_BASE_HI"
5001
  },
5002
  {
5003
   "chips": ["gfx9"],
5004
   "map": {"at": 165864, "to": "mm"},
5005
   "name": "VGT_DMA_BASE"
5006
  },
5007
  {
5008
   "chips": ["gfx9"],
5009
   "map": {"at": 165872, "to": "mm"},
5010
   "name": "VGT_DRAW_INITIATOR",
5011
   "type_ref": "VGT_DRAW_INITIATOR"
5012
  },
5013
  {
5014
   "chips": ["gfx9"],
5015
   "map": {"at": 165876, "to": "mm"},
5016
   "name": "VGT_IMMED_DATA"
5017
  },
5018
  {
5019
   "chips": ["gfx9"],
5020
   "map": {"at": 165880, "to": "mm"},
5021
   "name": "VGT_EVENT_ADDRESS_REG",
5022
   "type_ref": "VGT_EVENT_ADDRESS_REG"
5023
  },
5024
  {
5025
   "chips": ["gfx9"],
5026
   "map": {"at": 165888, "to": "mm"},
5027
   "name": "DB_DEPTH_CONTROL",
5028
   "type_ref": "DB_DEPTH_CONTROL"
5029
  },
5030
  {
5031
   "chips": ["gfx9"],
5032
   "map": {"at": 165892, "to": "mm"},
5033
   "name": "DB_EQAA",
5034
   "type_ref": "DB_EQAA"
5035
  },
5036
  {
5037
   "chips": ["gfx9"],
5038
   "map": {"at": 165896, "to": "mm"},
5039
   "name": "CB_COLOR_CONTROL",
5040
   "type_ref": "CB_COLOR_CONTROL"
5041
  },
5042
  {
5043
   "chips": ["gfx9"],
5044
   "map": {"at": 165900, "to": "mm"},
5045
   "name": "DB_SHADER_CONTROL",
5046
   "type_ref": "DB_SHADER_CONTROL"
5047
  },
5048
  {
5049
   "chips": ["gfx9"],
5050
   "map": {"at": 165904, "to": "mm"},
5051
   "name": "PA_CL_CLIP_CNTL",
5052
   "type_ref": "PA_CL_CLIP_CNTL"
5053
  },
5054
  {
5055
   "chips": ["gfx9"],
5056
   "map": {"at": 165908, "to": "mm"},
5057
   "name": "PA_SU_SC_MODE_CNTL",
5058
   "type_ref": "PA_SU_SC_MODE_CNTL"
5059
  },
5060
  {
5061
   "chips": ["gfx9"],
5062
   "map": {"at": 165912, "to": "mm"},
5063
   "name": "PA_CL_VTE_CNTL",
5064
   "type_ref": "PA_CL_VTE_CNTL"
5065
  },
5066
  {
5067
   "chips": ["gfx9"],
5068
   "map": {"at": 165916, "to": "mm"},
5069
   "name": "PA_CL_VS_OUT_CNTL",
5070
   "type_ref": "PA_CL_VS_OUT_CNTL"
5071
  },
5072
  {
5073
   "chips": ["gfx9"],
5074
   "map": {"at": 165920, "to": "mm"},
5075
   "name": "PA_CL_NANINF_CNTL",
5076
   "type_ref": "PA_CL_NANINF_CNTL"
5077
  },
5078
  {
5079
   "chips": ["gfx9"],
5080
   "map": {"at": 165924, "to": "mm"},
5081
   "name": "PA_SU_LINE_STIPPLE_CNTL",
5082
   "type_ref": "PA_SU_LINE_STIPPLE_CNTL"
5083
  },
5084
  {
5085
   "chips": ["gfx9"],
5086
   "map": {"at": 165928, "to": "mm"},
5087
   "name": "PA_SU_LINE_STIPPLE_SCALE"
5088
  },
5089
  {
5090
   "chips": ["gfx9"],
5091
   "map": {"at": 165932, "to": "mm"},
5092
   "name": "PA_SU_PRIM_FILTER_CNTL",
5093
   "type_ref": "PA_SU_PRIM_FILTER_CNTL"
5094
  },
5095
  {
5096
   "chips": ["gfx9"],
5097
   "map": {"at": 165936, "to": "mm"},
5098
   "name": "PA_SU_SMALL_PRIM_FILTER_CNTL",
5099
   "type_ref": "PA_SU_SMALL_PRIM_FILTER_CNTL"
5100
  },
5101
  {
5102
   "chips": ["gfx9"],
5103
   "map": {"at": 165940, "to": "mm"},
5104
   "name": "PA_CL_OBJPRIM_ID_CNTL",
5105
   "type_ref": "PA_CL_OBJPRIM_ID_CNTL"
5106
  },
5107
  {
5108
   "chips": ["gfx9"],
5109
   "map": {"at": 165944, "to": "mm"},
5110
   "name": "PA_CL_NGG_CNTL",
5111
   "type_ref": "PA_CL_NGG_CNTL"
5112
  },
5113
  {
5114
   "chips": ["gfx9"],
5115
   "map": {"at": 165948, "to": "mm"},
5116
   "name": "PA_SU_OVER_RASTERIZATION_CNTL",
5117
   "type_ref": "PA_SU_OVER_RASTERIZATION_CNTL"
5118
  },
5119
  {
5120
   "chips": ["gfx9"],
5121
   "map": {"at": 165952, "to": "mm"},
5122
   "name": "PA_STEREO_CNTL",
5123
   "type_ref": "PA_STEREO_CNTL"
5124
  },
5125
  {
5126
   "chips": ["gfx9"],
5127
   "map": {"at": 166400, "to": "mm"},
5128
   "name": "PA_SU_POINT_SIZE",
5129
   "type_ref": "PA_SU_POINT_SIZE"
5130
  },
5131
  {
5132
   "chips": ["gfx9"],
5133
   "map": {"at": 166404, "to": "mm"},
5134
   "name": "PA_SU_POINT_MINMAX",
5135
   "type_ref": "PA_SU_POINT_MINMAX"
5136
  },
5137
  {
5138
   "chips": ["gfx9"],
5139
   "map": {"at": 166408, "to": "mm"},
5140
   "name": "PA_SU_LINE_CNTL",
5141
   "type_ref": "PA_SU_LINE_CNTL"
5142
  },
5143
  {
5144
   "chips": ["gfx9"],
5145
   "map": {"at": 166412, "to": "mm"},
5146
   "name": "PA_SC_LINE_STIPPLE",
5147
   "type_ref": "PA_SC_LINE_STIPPLE"
5148
  },
5149
  {
5150
   "chips": ["gfx9"],
5151
   "map": {"at": 166416, "to": "mm"},
5152
   "name": "VGT_OUTPUT_PATH_CNTL",
5153
   "type_ref": "VGT_OUTPUT_PATH_CNTL"
5154
  },
5155
  {
5156
   "chips": ["gfx9"],
5157
   "map": {"at": 166420, "to": "mm"},
5158
   "name": "VGT_HOS_CNTL",
5159
   "type_ref": "VGT_HOS_CNTL"
5160
  },
5161
  {
5162
   "chips": ["gfx9"],
5163
   "map": {"at": 166424, "to": "mm"},
5164
   "name": "VGT_HOS_MAX_TESS_LEVEL"
5165
  },
5166
  {
5167
   "chips": ["gfx9"],
5168
   "map": {"at": 166428, "to": "mm"},
5169
   "name": "VGT_HOS_MIN_TESS_LEVEL"
5170
  },
5171
  {
5172
   "chips": ["gfx9"],
5173
   "map": {"at": 166432, "to": "mm"},
5174
   "name": "VGT_HOS_REUSE_DEPTH",
5175
   "type_ref": "VGT_HOS_REUSE_DEPTH"
5176
  },
5177
  {
5178
   "chips": ["gfx9"],
5179
   "map": {"at": 166436, "to": "mm"},
5180
   "name": "VGT_GROUP_PRIM_TYPE",
5181
   "type_ref": "VGT_GROUP_PRIM_TYPE"
5182
  },
5183
  {
5184
   "chips": ["gfx9"],
5185
   "map": {"at": 166440, "to": "mm"},
5186
   "name": "VGT_GROUP_FIRST_DECR",
5187
   "type_ref": "VGT_GROUP_FIRST_DECR"
5188
  },
5189
  {
5190
   "chips": ["gfx9"],
5191
   "map": {"at": 166444, "to": "mm"},
5192
   "name": "VGT_GROUP_DECR",
5193
   "type_ref": "VGT_GROUP_DECR"
5194
  },
5195
  {
5196
   "chips": ["gfx9"],
5197
   "map": {"at": 166448, "to": "mm"},
5198
   "name": "VGT_GROUP_VECT_0_CNTL",
5199
   "type_ref": "VGT_GROUP_VECT_0_CNTL"
5200
  },
5201
  {
5202
   "chips": ["gfx9"],
5203
   "map": {"at": 166452, "to": "mm"},
5204
   "name": "VGT_GROUP_VECT_1_CNTL",
5205
   "type_ref": "VGT_GROUP_VECT_0_CNTL"
5206
  },
5207
  {
5208
   "chips": ["gfx9"],
5209
   "map": {"at": 166456, "to": "mm"},
5210
   "name": "VGT_GROUP_VECT_0_FMT_CNTL",
5211
   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
5212
  },
5213
  {
5214
   "chips": ["gfx9"],
5215
   "map": {"at": 166460, "to": "mm"},
5216
   "name": "VGT_GROUP_VECT_1_FMT_CNTL",
5217
   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
5218
  },
5219
  {
5220
   "chips": ["gfx9"],
5221
   "map": {"at": 166464, "to": "mm"},
5222
   "name": "VGT_GS_MODE",
5223
   "type_ref": "VGT_GS_MODE"
5224
  },
5225
  {
5226
   "chips": ["gfx9"],
5227
   "map": {"at": 166468, "to": "mm"},
5228
   "name": "VGT_GS_ONCHIP_CNTL",
5229
   "type_ref": "VGT_GS_ONCHIP_CNTL"
5230
  },
5231
  {
5232
   "chips": ["gfx9"],
5233
   "map": {"at": 166472, "to": "mm"},
5234
   "name": "PA_SC_MODE_CNTL_0",
5235
   "type_ref": "PA_SC_MODE_CNTL_0"
5236
  },
5237
  {
5238
   "chips": ["gfx9"],
5239
   "map": {"at": 166476, "to": "mm"},
5240
   "name": "PA_SC_MODE_CNTL_1",
5241
   "type_ref": "PA_SC_MODE_CNTL_1"
5242
  },
5243
  {
5244
   "chips": ["gfx9"],
5245
   "map": {"at": 166480, "to": "mm"},
5246
   "name": "VGT_ENHANCE"
5247
  },
5248
  {
5249
   "chips": ["gfx9"],
5250
   "map": {"at": 166484, "to": "mm"},
5251
   "name": "VGT_GS_PER_ES",
5252
   "type_ref": "VGT_GS_PER_ES"
5253
  },
5254
  {
5255
   "chips": ["gfx9"],
5256
   "map": {"at": 166488, "to": "mm"},
5257
   "name": "VGT_ES_PER_GS",
5258
   "type_ref": "VGT_ES_PER_GS"
5259
  },
5260
  {
5261
   "chips": ["gfx9"],
5262
   "map": {"at": 166492, "to": "mm"},
5263
   "name": "VGT_GS_PER_VS",
5264
   "type_ref": "VGT_GS_PER_VS"
5265
  },
5266
  {
5267
   "chips": ["gfx9"],
5268
   "map": {"at": 166496, "to": "mm"},
5269
   "name": "VGT_GSVS_RING_OFFSET_1",
5270
   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5271
  },
5272
  {
5273
   "chips": ["gfx9"],
5274
   "map": {"at": 166500, "to": "mm"},
5275
   "name": "VGT_GSVS_RING_OFFSET_2",
5276
   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5277
  },
5278
  {
5279
   "chips": ["gfx9"],
5280
   "map": {"at": 166504, "to": "mm"},
5281
   "name": "VGT_GSVS_RING_OFFSET_3",
5282
   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5283
  },
5284
  {
5285
   "chips": ["gfx9"],
5286
   "map": {"at": 166508, "to": "mm"},
5287
   "name": "VGT_GS_OUT_PRIM_TYPE",
5288
   "type_ref": "VGT_GS_OUT_PRIM_TYPE"
5289
  },
5290
  {
5291
   "chips": ["gfx9"],
5292
   "map": {"at": 166512, "to": "mm"},
5293
   "name": "IA_ENHANCE"
5294
  },
5295
  {
5296
   "chips": ["gfx9"],
5297
   "map": {"at": 166516, "to": "mm"},
5298
   "name": "VGT_DMA_SIZE"
5299
  },
5300
  {
5301
   "chips": ["gfx9"],
5302
   "map": {"at": 166520, "to": "mm"},
5303
   "name": "VGT_DMA_MAX_SIZE"
5304
  },
5305
  {
5306
   "chips": ["gfx9"],
5307
   "map": {"at": 166524, "to": "mm"},
5308
   "name": "VGT_DMA_INDEX_TYPE",
5309
   "type_ref": "VGT_DMA_INDEX_TYPE"
5310
  },
5311
  {
5312
   "chips": ["gfx9"],
5313
   "map": {"at": 166528, "to": "mm"},
5314
   "name": "WD_ENHANCE"
5315
  },
5316
  {
5317
   "chips": ["gfx9"],
5318
   "map": {"at": 166532, "to": "mm"},
5319
   "name": "VGT_PRIMITIVEID_EN",
5320
   "type_ref": "VGT_PRIMITIVEID_EN"
5321
  },
5322
  {
5323
   "chips": ["gfx9"],
5324
   "map": {"at": 166536, "to": "mm"},
5325
   "name": "VGT_DMA_NUM_INSTANCES"
5326
  },
5327
  {
5328
   "chips": ["gfx9"],
5329
   "map": {"at": 166540, "to": "mm"},
5330
   "name": "VGT_PRIMITIVEID_RESET"
5331
  },
5332
  {
5333
   "chips": ["gfx9"],
5334
   "map": {"at": 166544, "to": "mm"},
5335
   "name": "VGT_EVENT_INITIATOR",
5336
   "type_ref": "VGT_EVENT_INITIATOR"
5337
  },
5338
  {
5339
   "chips": ["gfx9"],
5340
   "map": {"at": 166548, "to": "mm"},
5341
   "name": "VGT_GS_MAX_PRIMS_PER_SUBGROUP",
5342
   "type_ref": "VGT_GS_MAX_PRIMS_PER_SUBGROUP"
5343
  },
5344
  {
5345
   "chips": ["gfx9"],
5346
   "map": {"at": 166552, "to": "mm"},
5347
   "name": "VGT_DRAW_PAYLOAD_CNTL",
5348
   "type_ref": "VGT_DRAW_PAYLOAD_CNTL"
5349
  },
5350
  {
5351
   "chips": ["gfx9"],
5352
   "map": {"at": 166560, "to": "mm"},
5353
   "name": "VGT_INSTANCE_STEP_RATE_0"
5354
  },
5355
  {
5356
   "chips": ["gfx9"],
5357
   "map": {"at": 166564, "to": "mm"},
5358
   "name": "VGT_INSTANCE_STEP_RATE_1"
5359
  },
5360
  {
5361
   "chips": ["gfx9"],
5362
   "map": {"at": 166572, "to": "mm"},
5363
   "name": "VGT_ESGS_RING_ITEMSIZE",
5364
   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5365
  },
5366
  {
5367
   "chips": ["gfx9"],
5368
   "map": {"at": 166576, "to": "mm"},
5369
   "name": "VGT_GSVS_RING_ITEMSIZE",
5370
   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5371
  },
5372
  {
5373
   "chips": ["gfx9"],
5374
   "map": {"at": 166580, "to": "mm"},
5375
   "name": "VGT_REUSE_OFF",
5376
   "type_ref": "VGT_REUSE_OFF"
5377
  },
5378
  {
5379
   "chips": ["gfx9"],
5380
   "map": {"at": 166584, "to": "mm"},
5381
   "name": "VGT_VTX_CNT_EN",
5382
   "type_ref": "VGT_VTX_CNT_EN"
5383
  },
5384
  {
5385
   "chips": ["gfx9"],
5386
   "map": {"at": 166588, "to": "mm"},
5387
   "name": "DB_HTILE_SURFACE",
5388
   "type_ref": "DB_HTILE_SURFACE"
5389
  },
5390
  {
5391
   "chips": ["gfx9"],
5392
   "map": {"at": 166592, "to": "mm"},
5393
   "name": "DB_SRESULTS_COMPARE_STATE0",
5394
   "type_ref": "DB_SRESULTS_COMPARE_STATE0"
5395
  },
5396
  {
5397
   "chips": ["gfx9"],
5398
   "map": {"at": 166596, "to": "mm"},
5399
   "name": "DB_SRESULTS_COMPARE_STATE1",
5400
   "type_ref": "DB_SRESULTS_COMPARE_STATE1"
5401
  },
5402
  {
5403
   "chips": ["gfx9"],
5404
   "map": {"at": 166600, "to": "mm"},
5405
   "name": "DB_PRELOAD_CONTROL",
5406
   "type_ref": "DB_PRELOAD_CONTROL"
5407
  },
5408
  {
5409
   "chips": ["gfx9"],
5410
   "map": {"at": 166608, "to": "mm"},
5411
   "name": "VGT_STRMOUT_BUFFER_SIZE_0"
5412
  },
5413
  {
5414
   "chips": ["gfx9"],
5415
   "map": {"at": 166612, "to": "mm"},
5416
   "name": "VGT_STRMOUT_VTX_STRIDE_0",
5417
   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5418
  },
5419
  {
5420
   "chips": ["gfx9"],
5421
   "map": {"at": 166620, "to": "mm"},
5422
   "name": "VGT_STRMOUT_BUFFER_OFFSET_0"
5423
  },
5424
  {
5425
   "chips": ["gfx9"],
5426
   "map": {"at": 166624, "to": "mm"},
5427
   "name": "VGT_STRMOUT_BUFFER_SIZE_1"
5428
  },
5429
  {
5430
   "chips": ["gfx9"],
5431
   "map": {"at": 166628, "to": "mm"},
5432
   "name": "VGT_STRMOUT_VTX_STRIDE_1",
5433
   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5434
  },
5435
  {
5436
   "chips": ["gfx9"],
5437
   "map": {"at": 166636, "to": "mm"},
5438
   "name": "VGT_STRMOUT_BUFFER_OFFSET_1"
5439
  },
5440
  {
5441
   "chips": ["gfx9"],
5442
   "map": {"at": 166640, "to": "mm"},
5443
   "name": "VGT_STRMOUT_BUFFER_SIZE_2"
5444
  },
5445
  {
5446
   "chips": ["gfx9"],
5447
   "map": {"at": 166644, "to": "mm"},
5448
   "name": "VGT_STRMOUT_VTX_STRIDE_2",
5449
   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5450
  },
5451
  {
5452
   "chips": ["gfx9"],
5453
   "map": {"at": 166652, "to": "mm"},
5454
   "name": "VGT_STRMOUT_BUFFER_OFFSET_2"
5455
  },
5456
  {
5457
   "chips": ["gfx9"],
5458
   "map": {"at": 166656, "to": "mm"},
5459
   "name": "VGT_STRMOUT_BUFFER_SIZE_3"
5460
  },
5461
  {
5462
   "chips": ["gfx9"],
5463
   "map": {"at": 166660, "to": "mm"},
5464
   "name": "VGT_STRMOUT_VTX_STRIDE_3",
5465
   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5466
  },
5467
  {
5468
   "chips": ["gfx9"],
5469
   "map": {"at": 166668, "to": "mm"},
5470
   "name": "VGT_STRMOUT_BUFFER_OFFSET_3"
5471
  },
5472
  {
5473
   "chips": ["gfx9"],
5474
   "map": {"at": 166696, "to": "mm"},
5475
   "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET"
5476
  },
5477
  {
5478
   "chips": ["gfx9"],
5479
   "map": {"at": 166700, "to": "mm"},
5480
   "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE"
5481
  },
5482
  {
5483
   "chips": ["gfx9"],
5484
   "map": {"at": 166704, "to": "mm"},
5485
   "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",
5486
   "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE"
5487
  },
5488
  {
5489
   "chips": ["gfx9"],
5490
   "map": {"at": 166712, "to": "mm"},
5491
   "name": "VGT_GS_MAX_VERT_OUT",
5492
   "type_ref": "VGT_GS_MAX_VERT_OUT"
5493
  },
5494
  {
5495
   "chips": ["gfx9"],
5496
   "map": {"at": 166736, "to": "mm"},
5497
   "name": "VGT_TESS_DISTRIBUTION",
5498
   "type_ref": "VGT_TESS_DISTRIBUTION"
5499
  },
5500
  {
5501
   "chips": ["gfx9"],
5502
   "map": {"at": 166740, "to": "mm"},
5503
   "name": "VGT_SHADER_STAGES_EN",
5504
   "type_ref": "VGT_SHADER_STAGES_EN"
5505
  },
5506
  {
5507
   "chips": ["gfx9"],
5508
   "map": {"at": 166744, "to": "mm"},
5509
   "name": "VGT_LS_HS_CONFIG",
5510
   "type_ref": "VGT_LS_HS_CONFIG"
5511
  },
5512
  {
5513
   "chips": ["gfx9"],
5514
   "map": {"at": 166748, "to": "mm"},
5515
   "name": "VGT_GS_VERT_ITEMSIZE",
5516
   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5517
  },
5518
  {
5519
   "chips": ["gfx9"],
5520
   "map": {"at": 166752, "to": "mm"},
5521
   "name": "VGT_GS_VERT_ITEMSIZE_1",
5522
   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5523
  },
5524
  {
5525
   "chips": ["gfx9"],
5526
   "map": {"at": 166756, "to": "mm"},
5527
   "name": "VGT_GS_VERT_ITEMSIZE_2",
5528
   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5529
  },
5530
  {
5531
   "chips": ["gfx9"],
5532
   "map": {"at": 166760, "to": "mm"},
5533
   "name": "VGT_GS_VERT_ITEMSIZE_3",
5534
   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5535
  },
5536
  {
5537
   "chips": ["gfx9"],
5538
   "map": {"at": 166764, "to": "mm"},
5539
   "name": "VGT_TF_PARAM",
5540
   "type_ref": "VGT_TF_PARAM"
5541
  },
5542
  {
5543
   "chips": ["gfx9"],
5544
   "map": {"at": 166768, "to": "mm"},
5545
   "name": "DB_ALPHA_TO_MASK",
5546
   "type_ref": "DB_ALPHA_TO_MASK"
5547
  },
5548
  {
5549
   "chips": ["gfx9"],
5550
   "map": {"at": 166772, "to": "mm"},
5551
   "name": "VGT_DISPATCH_DRAW_INDEX"
5552
  },
5553
  {
5554
   "chips": ["gfx9"],
5555
   "map": {"at": 166776, "to": "mm"},
5556
   "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",
5557
   "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL"
5558
  },
5559
  {
5560
   "chips": ["gfx9"],
5561
   "map": {"at": 166780, "to": "mm"},
5562
   "name": "PA_SU_POLY_OFFSET_CLAMP"
5563
  },
5564
  {
5565
   "chips": ["gfx9"],
5566
   "map": {"at": 166784, "to": "mm"},
5567
   "name": "PA_SU_POLY_OFFSET_FRONT_SCALE"
5568
  },
5569
  {
5570
   "chips": ["gfx9"],
5571
   "map": {"at": 166788, "to": "mm"},
5572
   "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5573
  },
5574
  {
5575
   "chips": ["gfx9"],
5576
   "map": {"at": 166792, "to": "mm"},
5577
   "name": "PA_SU_POLY_OFFSET_BACK_SCALE"
5578
  },
5579
  {
5580
   "chips": ["gfx9"],
5581
   "map": {"at": 166796, "to": "mm"},
5582
   "name": "PA_SU_POLY_OFFSET_BACK_OFFSET"
5583
  },
5584
  {
5585
   "chips": ["gfx9"],
5586
   "map": {"at": 166800, "to": "mm"},
5587
   "name": "VGT_GS_INSTANCE_CNT",
5588
   "type_ref": "VGT_GS_INSTANCE_CNT"
5589
  },
5590
  {
5591
   "chips": ["gfx9"],
5592
   "map": {"at": 166804, "to": "mm"},
5593
   "name": "VGT_STRMOUT_CONFIG",
5594
   "type_ref": "VGT_STRMOUT_CONFIG"
5595
  },
5596
  {
5597
   "chips": ["gfx9"],
5598
   "map": {"at": 166808, "to": "mm"},
5599
   "name": "VGT_STRMOUT_BUFFER_CONFIG",
5600
   "type_ref": "VGT_STRMOUT_BUFFER_CONFIG"
5601
  },
5602
  {
5603
   "chips": ["gfx9"],
5604
   "map": {"at": 166812, "to": "mm"},
5605
   "name": "VGT_DMA_EVENT_INITIATOR",
5606
   "type_ref": "VGT_EVENT_INITIATOR"
5607
  },
5608
  {
5609
   "chips": ["gfx9"],
5610
   "map": {"at": 166868, "to": "mm"},
5611
   "name": "PA_SC_CENTROID_PRIORITY_0",
5612
   "type_ref": "PA_SC_CENTROID_PRIORITY_0"
5613
  },
5614
  {
5615
   "chips": ["gfx9"],
5616
   "map": {"at": 166872, "to": "mm"},
5617
   "name": "PA_SC_CENTROID_PRIORITY_1",
5618
   "type_ref": "PA_SC_CENTROID_PRIORITY_1"
5619
  },
5620
  {
5621
   "chips": ["gfx9"],
5622
   "map": {"at": 166876, "to": "mm"},
5623
   "name": "PA_SC_LINE_CNTL",
5624
   "type_ref": "PA_SC_LINE_CNTL"
5625
  },
5626
  {
5627
   "chips": ["gfx9"],
5628
   "map": {"at": 166880, "to": "mm"},
5629
   "name": "PA_SC_AA_CONFIG",
5630
   "type_ref": "PA_SC_AA_CONFIG"
5631
  },
5632
  {
5633
   "chips": ["gfx9"],
5634
   "map": {"at": 166884, "to": "mm"},
5635
   "name": "PA_SU_VTX_CNTL",
5636
   "type_ref": "PA_SU_VTX_CNTL"
5637
  },
5638
  {
5639
   "chips": ["gfx9"],
5640
   "map": {"at": 166888, "to": "mm"},
5641
   "name": "PA_CL_GB_VERT_CLIP_ADJ"
5642
  },
5643
  {
5644
   "chips": ["gfx9"],
5645
   "map": {"at": 166892, "to": "mm"},
5646
   "name": "PA_CL_GB_VERT_DISC_ADJ"
5647
  },
5648
  {
5649
   "chips": ["gfx9"],
5650
   "map": {"at": 166896, "to": "mm"},
5651
   "name": "PA_CL_GB_HORZ_CLIP_ADJ"
5652
  },
5653
  {
5654
   "chips": ["gfx9"],
5655
   "map": {"at": 166900, "to": "mm"},
5656
   "name": "PA_CL_GB_HORZ_DISC_ADJ"
5657
  },
5658
  {
5659
   "chips": ["gfx9"],
5660
   "map": {"at": 166904, "to": "mm"},
5661
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",
5662
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5663
  },
5664
  {
5665
   "chips": ["gfx9"],
5666
   "map": {"at": 166908, "to": "mm"},
5667
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",
5668
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5669
  },
5670
  {
5671
   "chips": ["gfx9"],
5672
   "map": {"at": 166912, "to": "mm"},
5673
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",
5674
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5675
  },
5676
  {
5677
   "chips": ["gfx9"],
5678
   "map": {"at": 166916, "to": "mm"},
5679
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",
5680
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5681
  },
5682
  {
5683
   "chips": ["gfx9"],
5684
   "map": {"at": 166920, "to": "mm"},
5685
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",
5686
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5687
  },
5688
  {
5689
   "chips": ["gfx9"],
5690
   "map": {"at": 166924, "to": "mm"},
5691
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",
5692
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5693
  },
5694
  {
5695
   "chips": ["gfx9"],
5696
   "map": {"at": 166928, "to": "mm"},
5697
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",
5698
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5699
  },
5700
  {
5701
   "chips": ["gfx9"],
5702
   "map": {"at": 166932, "to": "mm"},
5703
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",
5704
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5705
  },
5706
  {
5707
   "chips": ["gfx9"],
5708
   "map": {"at": 166936, "to": "mm"},
5709
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",
5710
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5711
  },
5712
  {
5713
   "chips": ["gfx9"],
5714
   "map": {"at": 166940, "to": "mm"},
5715
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",
5716
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5717
  },
5718
  {
5719
   "chips": ["gfx9"],
5720
   "map": {"at": 166944, "to": "mm"},
5721
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",
5722
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5723
  },
5724
  {
5725
   "chips": ["gfx9"],
5726
   "map": {"at": 166948, "to": "mm"},
5727
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",
5728
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5729
  },
5730
  {
5731
   "chips": ["gfx9"],
5732
   "map": {"at": 166952, "to": "mm"},
5733
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",
5734
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5735
  },
5736
  {
5737
   "chips": ["gfx9"],
5738
   "map": {"at": 166956, "to": "mm"},
5739
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",
5740
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5741
  },
5742
  {
5743
   "chips": ["gfx9"],
5744
   "map": {"at": 166960, "to": "mm"},
5745
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",
5746
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5747
  },
5748
  {
5749
   "chips": ["gfx9"],
5750
   "map": {"at": 166964, "to": "mm"},
5751
   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",
5752
   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5753
  },
5754
  {
5755
   "chips": ["gfx9"],
5756
   "map": {"at": 166968, "to": "mm"},
5757
   "name": "PA_SC_AA_MASK_X0Y0_X1Y0",
5758
   "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0"
5759
  },
5760
  {
5761
   "chips": ["gfx9"],
5762
   "map": {"at": 166972, "to": "mm"},
5763
   "name": "PA_SC_AA_MASK_X0Y1_X1Y1",
5764
   "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1"
5765
  },
5766
  {
5767
   "chips": ["gfx9"],
5768
   "map": {"at": 166976, "to": "mm"},
5769
   "name": "PA_SC_SHADER_CONTROL",
5770
   "type_ref": "PA_SC_SHADER_CONTROL"
5771
  },
5772
  {
5773
   "chips": ["gfx9"],
5774
   "map": {"at": 166980, "to": "mm"},
5775
   "name": "PA_SC_BINNER_CNTL_0",
5776
   "type_ref": "PA_SC_BINNER_CNTL_0"
5777
  },
5778
  {
5779
   "chips": ["gfx9"],
5780
   "map": {"at": 166984, "to": "mm"},
5781
   "name": "PA_SC_BINNER_CNTL_1",
5782
   "type_ref": "PA_SC_BINNER_CNTL_1"
5783
  },
5784
  {
5785
   "chips": ["gfx9"],
5786
   "map": {"at": 166988, "to": "mm"},
5787
   "name": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL",
5788
   "type_ref": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"
5789
  },
5790
  {
5791
   "chips": ["gfx9"],
5792
   "map": {"at": 166992, "to": "mm"},
5793
   "name": "PA_SC_NGG_MODE_CNTL",
5794
   "type_ref": "PA_SC_NGG_MODE_CNTL"
5795
  },
5796
  {
5797
   "chips": ["gfx9"],
5798
   "map": {"at": 167000, "to": "mm"},
5799
   "name": "VGT_VERTEX_REUSE_BLOCK_CNTL",
5800
   "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL"
5801
  },
5802
  {
5803
   "chips": ["gfx9"],
5804
   "map": {"at": 167004, "to": "mm"},
5805
   "name": "VGT_OUT_DEALLOC_CNTL",
5806
   "type_ref": "VGT_OUT_DEALLOC_CNTL"
5807
  },
5808
  {
5809
   "chips": ["gfx9"],
5810
   "map": {"at": 167008, "to": "mm"},
5811
   "name": "CB_COLOR0_BASE"
5812
  },
5813
  {
5814
   "chips": ["gfx9"],
5815
   "map": {"at": 167012, "to": "mm"},
5816
   "name": "CB_COLOR0_BASE_EXT",
5817
   "type_ref": "CB_COLOR0_BASE_EXT"
5818
  },
5819
  {
5820
   "chips": ["gfx9"],
5821
   "map": {"at": 167016, "to": "mm"},
5822
   "name": "CB_COLOR0_ATTRIB2",
5823
   "type_ref": "CB_COLOR0_ATTRIB2"
5824
  },
5825
  {
5826
   "chips": ["gfx9"],
5827
   "map": {"at": 167020, "to": "mm"},
5828
   "name": "CB_COLOR0_VIEW",
5829
   "type_ref": "CB_COLOR0_VIEW"
5830
  },
5831
  {
5832
   "chips": ["gfx9"],
5833
   "map": {"at": 167024, "to": "mm"},
5834
   "name": "CB_COLOR0_INFO",
5835
   "type_ref": "CB_COLOR0_INFO"
5836
  },
5837
  {
5838
   "chips": ["gfx9"],
5839
   "map": {"at": 167028, "to": "mm"},
5840
   "name": "CB_COLOR0_ATTRIB",
5841
   "type_ref": "CB_COLOR0_ATTRIB"
5842
  },
5843
  {
5844
   "chips": ["gfx9"],
5845
   "map": {"at": 167032, "to": "mm"},
5846
   "name": "CB_COLOR0_DCC_CONTROL",
5847
   "type_ref": "CB_COLOR0_DCC_CONTROL"
5848
  },
5849
  {
5850
   "chips": ["gfx9"],
5851
   "map": {"at": 167036, "to": "mm"},
5852
   "name": "CB_COLOR0_CMASK"
5853
  },
5854
  {
5855
   "chips": ["gfx9"],
5856
   "map": {"at": 167040, "to": "mm"},
5857
   "name": "CB_COLOR0_CMASK_BASE_EXT",
5858
   "type_ref": "CB_COLOR0_BASE_EXT"
5859
  },
5860
  {
5861
   "chips": ["gfx9"],
5862
   "map": {"at": 167044, "to": "mm"},
5863
   "name": "CB_COLOR0_FMASK"
5864
  },
5865
  {
5866
   "chips": ["gfx9"],
5867
   "map": {"at": 167048, "to": "mm"},
5868
   "name": "CB_COLOR0_FMASK_BASE_EXT",
5869
   "type_ref": "CB_COLOR0_BASE_EXT"
5870
  },
5871
  {
5872
   "chips": ["gfx9"],
5873
   "map": {"at": 167052, "to": "mm"},
5874
   "name": "CB_COLOR0_CLEAR_WORD0"
5875
  },
5876
  {
5877
   "chips": ["gfx9"],
5878
   "map": {"at": 167056, "to": "mm"},
5879
   "name": "CB_COLOR0_CLEAR_WORD1"
5880
  },
5881
  {
5882
   "chips": ["gfx9"],
5883
   "map": {"at": 167060, "to": "mm"},
5884
   "name": "CB_COLOR0_DCC_BASE"
5885
  },
5886
  {
5887
   "chips": ["gfx9"],
5888
   "map": {"at": 167064, "to": "mm"},
5889
   "name": "CB_COLOR0_DCC_BASE_EXT",
5890
   "type_ref": "CB_COLOR0_BASE_EXT"
5891
  },
5892
  {
5893
   "chips": ["gfx9"],
5894
   "map": {"at": 167068, "to": "mm"},
5895
   "name": "CB_COLOR1_BASE"
5896
  },
5897
  {
5898
   "chips": ["gfx9"],
5899
   "map": {"at": 167072, "to": "mm"},
5900
   "name": "CB_COLOR1_BASE_EXT",
5901
   "type_ref": "CB_COLOR0_BASE_EXT"
5902
  },
5903
  {
5904
   "chips": ["gfx9"],
5905
   "map": {"at": 167076, "to": "mm"},
5906
   "name": "CB_COLOR1_ATTRIB2",
5907
   "type_ref": "CB_COLOR0_ATTRIB2"
5908
  },
5909
  {
5910
   "chips": ["gfx9"],
5911
   "map": {"at": 167080, "to": "mm"},
5912
   "name": "CB_COLOR1_VIEW",
5913
   "type_ref": "CB_COLOR0_VIEW"
5914
  },
5915
  {
5916
   "chips": ["gfx9"],
5917
   "map": {"at": 167084, "to": "mm"},
5918
   "name": "CB_COLOR1_INFO",
5919
   "type_ref": "CB_COLOR0_INFO"
5920
  },
5921
  {
5922
   "chips": ["gfx9"],
5923
   "map": {"at": 167088, "to": "mm"},
5924
   "name": "CB_COLOR1_ATTRIB",
5925
   "type_ref": "CB_COLOR0_ATTRIB"
5926
  },
5927
  {
5928
   "chips": ["gfx9"],
5929
   "map": {"at": 167092, "to": "mm"},
5930
   "name": "CB_COLOR1_DCC_CONTROL",
5931
   "type_ref": "CB_COLOR0_DCC_CONTROL"
5932
  },
5933
  {
5934
   "chips": ["gfx9"],
5935
   "map": {"at": 167096, "to": "mm"},
5936
   "name": "CB_COLOR1_CMASK"
5937
  },
5938
  {
5939
   "chips": ["gfx9"],
5940
   "map": {"at": 167100, "to": "mm"},
5941
   "name": "CB_COLOR1_CMASK_BASE_EXT",
5942
   "type_ref": "CB_COLOR0_BASE_EXT"
5943
  },
5944
  {
5945
   "chips": ["gfx9"],
5946
   "map": {"at": 167104, "to": "mm"},
5947
   "name": "CB_COLOR1_FMASK"
5948
  },
5949
  {
5950
   "chips": ["gfx9"],
5951
   "map": {"at": 167108, "to": "mm"},
5952
   "name": "CB_COLOR1_FMASK_BASE_EXT",
5953
   "type_ref": "CB_COLOR0_BASE_EXT"
5954
  },
5955
  {
5956
   "chips": ["gfx9"],
5957
   "map": {"at": 167112, "to": "mm"},
5958
   "name": "CB_COLOR1_CLEAR_WORD0"
5959
  },
5960
  {
5961
   "chips": ["gfx9"],
5962
   "map": {"at": 167116, "to": "mm"},
5963
   "name": "CB_COLOR1_CLEAR_WORD1"
5964
  },
5965
  {
5966
   "chips": ["gfx9"],
5967
   "map": {"at": 167120, "to": "mm"},
5968
   "name": "CB_COLOR1_DCC_BASE"
5969
  },
5970
  {
5971
   "chips": ["gfx9"],
5972
   "map": {"at": 167124, "to": "mm"},
5973
   "name": "CB_COLOR1_DCC_BASE_EXT",
5974
   "type_ref": "CB_COLOR0_BASE_EXT"
5975
  },
5976
  {
5977
   "chips": ["gfx9"],
5978
   "map": {"at": 167128, "to": "mm"},
5979
   "name": "CB_COLOR2_BASE"
5980
  },
5981
  {
5982
   "chips": ["gfx9"],
5983
   "map": {"at": 167132, "to": "mm"},
5984
   "name": "CB_COLOR2_BASE_EXT",
5985
   "type_ref": "CB_COLOR0_BASE_EXT"
5986
  },
5987
  {
5988
   "chips": ["gfx9"],
5989
   "map": {"at": 167136, "to": "mm"},
5990
   "name": "CB_COLOR2_ATTRIB2",
5991
   "type_ref": "CB_COLOR0_ATTRIB2"
5992
  },
5993
  {
5994
   "chips": ["gfx9"],
5995
   "map": {"at": 167140, "to": "mm"},
5996
   "name": "CB_COLOR2_VIEW",
5997
   "type_ref": "CB_COLOR0_VIEW"
5998
  },
5999
  {
6000
   "chips": ["gfx9"],
6001
   "map": {"at": 167144, "to": "mm"},
6002
   "name": "CB_COLOR2_INFO",
6003
   "type_ref": "CB_COLOR0_INFO"
6004
  },
6005
  {
6006
   "chips": ["gfx9"],
6007
   "map": {"at": 167148, "to": "mm"},
6008
   "name": "CB_COLOR2_ATTRIB",
6009
   "type_ref": "CB_COLOR0_ATTRIB"
6010
  },
6011
  {
6012
   "chips": ["gfx9"],
6013
   "map": {"at": 167152, "to": "mm"},
6014
   "name": "CB_COLOR2_DCC_CONTROL",
6015
   "type_ref": "CB_COLOR0_DCC_CONTROL"
6016
  },
6017
  {
6018
   "chips": ["gfx9"],
6019
   "map": {"at": 167156, "to": "mm"},
6020
   "name": "CB_COLOR2_CMASK"
6021
  },
6022
  {
6023
   "chips": ["gfx9"],
6024
   "map": {"at": 167160, "to": "mm"},
6025
   "name": "CB_COLOR2_CMASK_BASE_EXT",
6026
   "type_ref": "CB_COLOR0_BASE_EXT"
6027
  },
6028
  {
6029
   "chips": ["gfx9"],
6030
   "map": {"at": 167164, "to": "mm"},
6031
   "name": "CB_COLOR2_FMASK"
6032
  },
6033
  {
6034
   "chips": ["gfx9"],
6035
   "map": {"at": 167168, "to": "mm"},
6036
   "name": "CB_COLOR2_FMASK_BASE_EXT",
6037
   "type_ref": "CB_COLOR0_BASE_EXT"
6038
  },
6039
  {
6040
   "chips": ["gfx9"],
6041
   "map": {"at": 167172, "to": "mm"},
6042
   "name": "CB_COLOR2_CLEAR_WORD0"
6043
  },
6044
  {
6045
   "chips": ["gfx9"],
6046
   "map": {"at": 167176, "to": "mm"},
6047
   "name": "CB_COLOR2_CLEAR_WORD1"
6048
  },
6049
  {
6050
   "chips": ["gfx9"],
6051
   "map": {"at": 167180, "to": "mm"},
6052
   "name": "CB_COLOR2_DCC_BASE"
6053
  },
6054
  {
6055
   "chips": ["gfx9"],
6056
   "map": {"at": 167184, "to": "mm"},
6057
   "name": "CB_COLOR2_DCC_BASE_EXT",
6058
   "type_ref": "CB_COLOR0_BASE_EXT"
6059
  },
6060
  {
6061
   "chips": ["gfx9"],
6062
   "map": {"at": 167188, "to": "mm"},
6063
   "name": "CB_COLOR3_BASE"
6064
  },
6065
  {
6066
   "chips": ["gfx9"],
6067
   "map": {"at": 167192, "to": "mm"},
6068
   "name": "CB_COLOR3_BASE_EXT",
6069
   "type_ref": "CB_COLOR0_BASE_EXT"
6070
  },
6071
  {
6072
   "chips": ["gfx9"],
6073
   "map": {"at": 167196, "to": "mm"},
6074
   "name": "CB_COLOR3_ATTRIB2",
6075
   "type_ref": "CB_COLOR0_ATTRIB2"
6076
  },
6077
  {
6078
   "chips": ["gfx9"],
6079
   "map": {"at": 167200, "to": "mm"},
6080
   "name": "CB_COLOR3_VIEW",
6081
   "type_ref": "CB_COLOR0_VIEW"
6082
  },
6083
  {
6084
   "chips": ["gfx9"],
6085
   "map": {"at": 167204, "to": "mm"},
6086
   "name": "CB_COLOR3_INFO",
6087
   "type_ref": "CB_COLOR0_INFO"
6088
  },
6089
  {
6090
   "chips": ["gfx9"],
6091
   "map": {"at": 167208, "to": "mm"},
6092
   "name": "CB_COLOR3_ATTRIB",
6093
   "type_ref": "CB_COLOR0_ATTRIB"
6094
  },
6095
  {
6096
   "chips": ["gfx9"],
6097
   "map": {"at": 167212, "to": "mm"},
6098
   "name": "CB_COLOR3_DCC_CONTROL",
6099
   "type_ref": "CB_COLOR0_DCC_CONTROL"
6100
  },
6101
  {
6102
   "chips": ["gfx9"],
6103
   "map": {"at": 167216, "to": "mm"},
6104
   "name": "CB_COLOR3_CMASK"
6105
  },
6106
  {
6107
   "chips": ["gfx9"],
6108
   "map": {"at": 167220, "to": "mm"},
6109
   "name": "CB_COLOR3_CMASK_BASE_EXT",
6110
   "type_ref": "CB_COLOR0_BASE_EXT"
6111
  },
6112
  {
6113
   "chips": ["gfx9"],
6114
   "map": {"at": 167224, "to": "mm"},
6115
   "name": "CB_COLOR3_FMASK"
6116
  },
6117
  {
6118
   "chips": ["gfx9"],
6119
   "map": {"at": 167228, "to": "mm"},
6120
   "name": "CB_COLOR3_FMASK_BASE_EXT",
6121
   "type_ref": "CB_COLOR0_BASE_EXT"
6122
  },
6123
  {
6124
   "chips": ["gfx9"],
6125
   "map": {"at": 167232, "to": "mm"},
6126
   "name": "CB_COLOR3_CLEAR_WORD0"
6127
  },
6128
  {
6129
   "chips": ["gfx9"],
6130
   "map": {"at": 167236, "to": "mm"},
6131
   "name": "CB_COLOR3_CLEAR_WORD1"
6132
  },
6133
  {
6134
   "chips": ["gfx9"],
6135
   "map": {"at": 167240, "to": "mm"},
6136
   "name": "CB_COLOR3_DCC_BASE"
6137
  },
6138
  {
6139
   "chips": ["gfx9"],
6140
   "map": {"at": 167244, "to": "mm"},
6141
   "name": "CB_COLOR3_DCC_BASE_EXT",
6142
   "type_ref": "CB_COLOR0_BASE_EXT"
6143
  },
6144
  {
6145
   "chips": ["gfx9"],
6146
   "map": {"at": 167248, "to": "mm"},
6147
   "name": "CB_COLOR4_BASE"
6148
  },
6149
  {
6150
   "chips": ["gfx9"],
6151
   "map": {"at": 167252, "to": "mm"},
6152
   "name": "CB_COLOR4_BASE_EXT",
6153
   "type_ref": "CB_COLOR0_BASE_EXT"
6154
  },
6155
  {
6156
   "chips": ["gfx9"],
6157
   "map": {"at": 167256, "to": "mm"},
6158
   "name": "CB_COLOR4_ATTRIB2",
6159
   "type_ref": "CB_COLOR0_ATTRIB2"
6160
  },
6161
  {
6162
   "chips": ["gfx9"],
6163
   "map": {"at": 167260, "to": "mm"},
6164
   "name": "CB_COLOR4_VIEW",
6165
   "type_ref": "CB_COLOR0_VIEW"
6166
  },
6167
  {
6168
   "chips": ["gfx9"],
6169
   "map": {"at": 167264, "to": "mm"},
6170
   "name": "CB_COLOR4_INFO",
6171
   "type_ref": "CB_COLOR0_INFO"
6172
  },
6173
  {
6174
   "chips": ["gfx9"],
6175
   "map": {"at": 167268, "to": "mm"},
6176
   "name": "CB_COLOR4_ATTRIB",
6177
   "type_ref": "CB_COLOR0_ATTRIB"
6178
  },
6179
  {
6180
   "chips": ["gfx9"],
6181
   "map": {"at": 167272, "to": "mm"},
6182
   "name": "CB_COLOR4_DCC_CONTROL",
6183
   "type_ref": "CB_COLOR0_DCC_CONTROL"
6184
  },
6185
  {
6186
   "chips": ["gfx9"],
6187
   "map": {"at": 167276, "to": "mm"},
6188
   "name": "CB_COLOR4_CMASK"
6189
  },
6190
  {
6191
   "chips": ["gfx9"],
6192
   "map": {"at": 167280, "to": "mm"},
6193
   "name": "CB_COLOR4_CMASK_BASE_EXT",
6194
   "type_ref": "CB_COLOR0_BASE_EXT"
6195
  },
6196
  {
6197
   "chips": ["gfx9"],
6198
   "map": {"at": 167284, "to": "mm"},
6199
   "name": "CB_COLOR4_FMASK"
6200
  },
6201
  {
6202
   "chips": ["gfx9"],
6203
   "map": {"at": 167288, "to": "mm"},
6204
   "name": "CB_COLOR4_FMASK_BASE_EXT",
6205
   "type_ref": "CB_COLOR0_BASE_EXT"
6206
  },
6207
  {
6208
   "chips": ["gfx9"],
6209
   "map": {"at": 167292, "to": "mm"},
6210
   "name": "CB_COLOR4_CLEAR_WORD0"
6211
  },
6212
  {
6213
   "chips": ["gfx9"],
6214
   "map": {"at": 167296, "to": "mm"},
6215
   "name": "CB_COLOR4_CLEAR_WORD1"
6216
  },
6217
  {
6218
   "chips": ["gfx9"],
6219
   "map": {"at": 167300, "to": "mm"},
6220
   "name": "CB_COLOR4_DCC_BASE"
6221
  },
6222
  {
6223
   "chips": ["gfx9"],
6224
   "map": {"at": 167304, "to": "mm"},
6225
   "name": "CB_COLOR4_DCC_BASE_EXT",
6226
   "type_ref": "CB_COLOR0_BASE_EXT"
6227
  },
6228
  {
6229
   "chips": ["gfx9"],
6230
   "map": {"at": 167308, "to": "mm"},
6231
   "name": "CB_COLOR5_BASE"
6232
  },
6233
  {
6234
   "chips": ["gfx9"],
6235
   "map": {"at": 167312, "to": "mm"},
6236
   "name": "CB_COLOR5_BASE_EXT",
6237
   "type_ref": "CB_COLOR0_BASE_EXT"
6238
  },
6239
  {
6240
   "chips": ["gfx9"],
6241
   "map": {"at": 167316, "to": "mm"},
6242
   "name": "CB_COLOR5_ATTRIB2",
6243
   "type_ref": "CB_COLOR0_ATTRIB2"
6244
  },
6245
  {
6246
   "chips": ["gfx9"],
6247
   "map": {"at": 167320, "to": "mm"},
6248
   "name": "CB_COLOR5_VIEW",
6249
   "type_ref": "CB_COLOR0_VIEW"
6250
  },
6251
  {
6252
   "chips": ["gfx9"],
6253
   "map": {"at": 167324, "to": "mm"},
6254
   "name": "CB_COLOR5_INFO",
6255
   "type_ref": "CB_COLOR0_INFO"
6256
  },
6257
  {
6258
   "chips": ["gfx9"],
6259
   "map": {"at": 167328, "to": "mm"},
6260
   "name": "CB_COLOR5_ATTRIB",
6261
   "type_ref": "CB_COLOR0_ATTRIB"
6262
  },
6263
  {
6264
   "chips": ["gfx9"],
6265
   "map": {"at": 167332, "to": "mm"},
6266
   "name": "CB_COLOR5_DCC_CONTROL",
6267
   "type_ref": "CB_COLOR0_DCC_CONTROL"
6268
  },
6269
  {
6270
   "chips": ["gfx9"],
6271
   "map": {"at": 167336, "to": "mm"},
6272
   "name": "CB_COLOR5_CMASK"
6273
  },
6274
  {
6275
   "chips": ["gfx9"],
6276
   "map": {"at": 167340, "to": "mm"},
6277
   "name": "CB_COLOR5_CMASK_BASE_EXT",
6278
   "type_ref": "CB_COLOR0_BASE_EXT"
6279
  },
6280
  {
6281
   "chips": ["gfx9"],
6282
   "map": {"at": 167344, "to": "mm"},
6283
   "name": "CB_COLOR5_FMASK"
6284
  },
6285
  {
6286
   "chips": ["gfx9"],
6287
   "map": {"at": 167348, "to": "mm"},
6288
   "name": "CB_COLOR5_FMASK_BASE_EXT",
6289
   "type_ref": "CB_COLOR0_BASE_EXT"
6290
  },
6291
  {
6292
   "chips": ["gfx9"],
6293
   "map": {"at": 167352, "to": "mm"},
6294
   "name": "CB_COLOR5_CLEAR_WORD0"
6295
  },
6296
  {
6297
   "chips": ["gfx9"],
6298
   "map": {"at": 167356, "to": "mm"},
6299
   "name": "CB_COLOR5_CLEAR_WORD1"
6300
  },
6301
  {
6302
   "chips": ["gfx9"],
6303
   "map": {"at": 167360, "to": "mm"},
6304
   "name": "CB_COLOR5_DCC_BASE"
6305
  },
6306
  {
6307
   "chips": ["gfx9"],
6308
   "map": {"at": 167364, "to": "mm"},
6309
   "name": "CB_COLOR5_DCC_BASE_EXT",
6310
   "type_ref": "CB_COLOR0_BASE_EXT"
6311
  },
6312
  {
6313
   "chips": ["gfx9"],
6314
   "map": {"at": 167368, "to": "mm"},
6315
   "name": "CB_COLOR6_BASE"
6316
  },
6317
  {
6318
   "chips": ["gfx9"],
6319
   "map": {"at": 167372, "to": "mm"},
6320
   "name": "CB_COLOR6_BASE_EXT",
6321
   "type_ref": "CB_COLOR0_BASE_EXT"
6322
  },
6323
  {
6324
   "chips": ["gfx9"],
6325
   "map": {"at": 167376, "to": "mm"},
6326
   "name": "CB_COLOR6_ATTRIB2",
6327
   "type_ref": "CB_COLOR0_ATTRIB2"
6328
  },
6329
  {
6330
   "chips": ["gfx9"],
6331
   "map": {"at": 167380, "to": "mm"},
6332
   "name": "CB_COLOR6_VIEW",
6333
   "type_ref": "CB_COLOR0_VIEW"
6334
  },
6335
  {
6336
   "chips": ["gfx9"],
6337
   "map": {"at": 167384, "to": "mm"},
6338
   "name": "CB_COLOR6_INFO",
6339
   "type_ref": "CB_COLOR0_INFO"
6340
  },
6341
  {
6342
   "chips": ["gfx9"],
6343
   "map": {"at": 167388, "to": "mm"},
6344
   "name": "CB_COLOR6_ATTRIB",
6345
   "type_ref": "CB_COLOR0_ATTRIB"
6346
  },
6347
  {
6348
   "chips": ["gfx9"],
6349
   "map": {"at": 167392, "to": "mm"},
6350
   "name": "CB_COLOR6_DCC_CONTROL",
6351
   "type_ref": "CB_COLOR0_DCC_CONTROL"
6352
  },
6353
  {
6354
   "chips": ["gfx9"],
6355
   "map": {"at": 167396, "to": "mm"},
6356
   "name": "CB_COLOR6_CMASK"
6357
  },
6358
  {
6359
   "chips": ["gfx9"],
6360
   "map": {"at": 167400, "to": "mm"},
6361
   "name": "CB_COLOR6_CMASK_BASE_EXT",
6362
   "type_ref": "CB_COLOR0_BASE_EXT"
6363
  },
6364
  {
6365
   "chips": ["gfx9"],
6366
   "map": {"at": 167404, "to": "mm"},
6367
   "name": "CB_COLOR6_FMASK"
6368
  },
6369
  {
6370
   "chips": ["gfx9"],
6371
   "map": {"at": 167408, "to": "mm"},
6372
   "name": "CB_COLOR6_FMASK_BASE_EXT",
6373
   "type_ref": "CB_COLOR0_BASE_EXT"
6374
  },
6375
  {
6376
   "chips": ["gfx9"],
6377
   "map": {"at": 167412, "to": "mm"},
6378
   "name": "CB_COLOR6_CLEAR_WORD0"
6379
  },
6380
  {
6381
   "chips": ["gfx9"],
6382
   "map": {"at": 167416, "to": "mm"},
6383
   "name": "CB_COLOR6_CLEAR_WORD1"
6384
  },
6385
  {
6386
   "chips": ["gfx9"],
6387
   "map": {"at": 167420, "to": "mm"},
6388
   "name": "CB_COLOR6_DCC_BASE"
6389
  },
6390
  {
6391
   "chips": ["gfx9"],
6392
   "map": {"at": 167424, "to": "mm"},
6393
   "name": "CB_COLOR6_DCC_BASE_EXT",
6394
   "type_ref": "CB_COLOR0_BASE_EXT"
6395
  },
6396
  {
6397
   "chips": ["gfx9"],
6398
   "map": {"at": 167428, "to": "mm"},
6399
   "name": "CB_COLOR7_BASE"
6400
  },
6401
  {
6402
   "chips": ["gfx9"],
6403
   "map": {"at": 167432, "to": "mm"},
6404
   "name": "CB_COLOR7_BASE_EXT",
6405
   "type_ref": "CB_COLOR0_BASE_EXT"
6406
  },
6407
  {
6408
   "chips": ["gfx9"],
6409
   "map": {"at": 167436, "to": "mm"},
6410
   "name": "CB_COLOR7_ATTRIB2",
6411
   "type_ref": "CB_COLOR0_ATTRIB2"
6412
  },
6413
  {
6414
   "chips": ["gfx9"],
6415
   "map": {"at": 167440, "to": "mm"},
6416
   "name": "CB_COLOR7_VIEW",
6417
   "type_ref": "CB_COLOR0_VIEW"
6418
  },
6419
  {
6420
   "chips": ["gfx9"],
6421
   "map": {"at": 167444, "to": "mm"},
6422
   "name": "CB_COLOR7_INFO",
6423
   "type_ref": "CB_COLOR0_INFO"
6424
  },
6425
  {
6426
   "chips": ["gfx9"],
6427
   "map": {"at": 167448, "to": "mm"},
6428
   "name": "CB_COLOR7_ATTRIB",
6429
   "type_ref": "CB_COLOR0_ATTRIB"
6430
  },
6431
  {
6432
   "chips": ["gfx9"],
6433
   "map": {"at": 167452, "to": "mm"},
6434
   "name": "CB_COLOR7_DCC_CONTROL",
6435
   "type_ref": "CB_COLOR0_DCC_CONTROL"
6436
  },
6437
  {
6438
   "chips": ["gfx9"],
6439
   "map": {"at": 167456, "to": "mm"},
6440
   "name": "CB_COLOR7_CMASK"
6441
  },
6442
  {
6443
   "chips": ["gfx9"],
6444
   "map": {"at": 167460, "to": "mm"},
6445
   "name": "CB_COLOR7_CMASK_BASE_EXT",
6446
   "type_ref": "CB_COLOR0_BASE_EXT"
6447
  },
6448
  {
6449
   "chips": ["gfx9"],
6450
   "map": {"at": 167464, "to": "mm"},
6451
   "name": "CB_COLOR7_FMASK"
6452
  },
6453
  {
6454
   "chips": ["gfx9"],
6455
   "map": {"at": 167468, "to": "mm"},
6456
   "name": "CB_COLOR7_FMASK_BASE_EXT",
6457
   "type_ref": "CB_COLOR0_BASE_EXT"
6458
  },
6459
  {
6460
   "chips": ["gfx9"],
6461
   "map": {"at": 167472, "to": "mm"},
6462
   "name": "CB_COLOR7_CLEAR_WORD0"
6463
  },
6464
  {
6465
   "chips": ["gfx9"],
6466
   "map": {"at": 167476, "to": "mm"},
6467
   "name": "CB_COLOR7_CLEAR_WORD1"
6468
  },
6469
  {
6470
   "chips": ["gfx9"],
6471
   "map": {"at": 167480, "to": "mm"},
6472
   "name": "CB_COLOR7_DCC_BASE"
6473
  },
6474
  {
6475
   "chips": ["gfx9"],
6476
   "map": {"at": 167484, "to": "mm"},
6477
   "name": "CB_COLOR7_DCC_BASE_EXT",
6478
   "type_ref": "CB_COLOR0_BASE_EXT"
6479
  },
6480
  {
6481
   "chips": ["gfx9"],
6482
   "map": {"at": 196608, "to": "mm"},
6483
   "name": "CP_EOP_DONE_ADDR_LO",
6484
   "type_ref": "CP_EOP_DONE_ADDR_LO"
6485
  },
6486
  {
6487
   "chips": ["gfx9"],
6488
   "map": {"at": 196612, "to": "mm"},
6489
   "name": "CP_EOP_DONE_ADDR_HI",
6490
   "type_ref": "CP_EOP_DONE_ADDR_HI"
6491
  },
6492
  {
6493
   "chips": ["gfx9"],
6494
   "map": {"at": 196616, "to": "mm"},
6495
   "name": "CP_EOP_DONE_DATA_LO"
6496
  },
6497
  {
6498
   "chips": ["gfx9"],
6499
   "map": {"at": 196620, "to": "mm"},
6500
   "name": "CP_EOP_DONE_DATA_HI"
6501
  },
6502
  {
6503
   "chips": ["gfx9"],
6504
   "map": {"at": 196624, "to": "mm"},
6505
   "name": "CP_EOP_LAST_FENCE_LO"
6506
  },
6507
  {
6508
   "chips": ["gfx9"],
6509
   "map": {"at": 196628, "to": "mm"},
6510
   "name": "CP_EOP_LAST_FENCE_HI"
6511
  },
6512
  {
6513
   "chips": ["gfx9"],
6514
   "map": {"at": 196632, "to": "mm"},
6515
   "name": "CP_STREAM_OUT_ADDR_LO",
6516
   "type_ref": "CP_STREAM_OUT_ADDR_LO"
6517
  },
6518
  {
6519
   "chips": ["gfx9"],
6520
   "map": {"at": 196636, "to": "mm"},
6521
   "name": "CP_STREAM_OUT_ADDR_HI",
6522
   "type_ref": "CP_STREAM_OUT_ADDR_HI"
6523
  },
6524
  {
6525
   "chips": ["gfx9"],
6526
   "map": {"at": 196640, "to": "mm"},
6527
   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO"
6528
  },
6529
  {
6530
   "chips": ["gfx9"],
6531
   "map": {"at": 196644, "to": "mm"},
6532
   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI"
6533
  },
6534
  {
6535
   "chips": ["gfx9"],
6536
   "map": {"at": 196648, "to": "mm"},
6537
   "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO"
6538
  },
6539
  {
6540
   "chips": ["gfx9"],
6541
   "map": {"at": 196652, "to": "mm"},
6542
   "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI"
6543
  },
6544
  {
6545
   "chips": ["gfx9"],
6546
   "map": {"at": 196656, "to": "mm"},
6547
   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO"
6548
  },
6549
  {
6550
   "chips": ["gfx9"],
6551
   "map": {"at": 196660, "to": "mm"},
6552
   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI"
6553
  },
6554
  {
6555
   "chips": ["gfx9"],
6556
   "map": {"at": 196664, "to": "mm"},
6557
   "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO"
6558
  },
6559
  {
6560
   "chips": ["gfx9"],
6561
   "map": {"at": 196668, "to": "mm"},
6562
   "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI"
6563
  },
6564
  {
6565
   "chips": ["gfx9"],
6566
   "map": {"at": 196672, "to": "mm"},
6567
   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO"
6568
  },
6569
  {
6570
   "chips": ["gfx9"],
6571
   "map": {"at": 196676, "to": "mm"},
6572
   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI"
6573
  },
6574
  {
6575
   "chips": ["gfx9"],
6576
   "map": {"at": 196680, "to": "mm"},
6577
   "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO"
6578
  },
6579
  {
6580
   "chips": ["gfx9"],
6581
   "map": {"at": 196684, "to": "mm"},
6582
   "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI"
6583
  },
6584
  {
6585
   "chips": ["gfx9"],
6586
   "map": {"at": 196688, "to": "mm"},
6587
   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO"
6588
  },
6589
  {
6590
   "chips": ["gfx9"],
6591
   "map": {"at": 196692, "to": "mm"},
6592
   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI"
6593
  },
6594
  {
6595
   "chips": ["gfx9"],
6596
   "map": {"at": 196696, "to": "mm"},
6597
   "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO"
6598
  },
6599
  {
6600
   "chips": ["gfx9"],
6601
   "map": {"at": 196700, "to": "mm"},
6602
   "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI"
6603
  },
6604
  {
6605
   "chips": ["gfx9"],
6606
   "map": {"at": 196704, "to": "mm"},
6607
   "name": "CP_PIPE_STATS_ADDR_LO",
6608
   "type_ref": "CP_PIPE_STATS_ADDR_LO"
6609
  },
6610
  {
6611
   "chips": ["gfx9"],
6612
   "map": {"at": 196708, "to": "mm"},
6613
   "name": "CP_PIPE_STATS_ADDR_HI",
6614
   "type_ref": "CP_PIPE_STATS_ADDR_HI"
6615
  },
6616
  {
6617
   "chips": ["gfx9"],
6618
   "map": {"at": 196712, "to": "mm"},
6619
   "name": "CP_VGT_IAVERT_COUNT_LO"
6620
  },
6621
  {
6622
   "chips": ["gfx9"],
6623
   "map": {"at": 196716, "to": "mm"},
6624
   "name": "CP_VGT_IAVERT_COUNT_HI"
6625
  },
6626
  {
6627
   "chips": ["gfx9"],
6628
   "map": {"at": 196720, "to": "mm"},
6629
   "name": "CP_VGT_IAPRIM_COUNT_LO"
6630
  },
6631
  {
6632
   "chips": ["gfx9"],
6633
   "map": {"at": 196724, "to": "mm"},
6634
   "name": "CP_VGT_IAPRIM_COUNT_HI"
6635
  },
6636
  {
6637
   "chips": ["gfx9"],
6638
   "map": {"at": 196728, "to": "mm"},
6639
   "name": "CP_VGT_GSPRIM_COUNT_LO"
6640
  },
6641
  {
6642
   "chips": ["gfx9"],
6643
   "map": {"at": 196732, "to": "mm"},
6644
   "name": "CP_VGT_GSPRIM_COUNT_HI"
6645
  },
6646
  {
6647
   "chips": ["gfx9"],
6648
   "map": {"at": 196736, "to": "mm"},
6649
   "name": "CP_VGT_VSINVOC_COUNT_LO"
6650
  },
6651
  {
6652
   "chips": ["gfx9"],
6653
   "map": {"at": 196740, "to": "mm"},
6654
   "name": "CP_VGT_VSINVOC_COUNT_HI"
6655
  },
6656
  {
6657
   "chips": ["gfx9"],
6658
   "map": {"at": 196744, "to": "mm"},
6659
   "name": "CP_VGT_GSINVOC_COUNT_LO"
6660
  },
6661
  {
6662
   "chips": ["gfx9"],
6663
   "map": {"at": 196748, "to": "mm"},
6664
   "name": "CP_VGT_GSINVOC_COUNT_HI"
6665
  },
6666
  {
6667
   "chips": ["gfx9"],
6668
   "map": {"at": 196752, "to": "mm"},
6669
   "name": "CP_VGT_HSINVOC_COUNT_LO"
6670
  },
6671
  {
6672
   "chips": ["gfx9"],
6673
   "map": {"at": 196756, "to": "mm"},
6674
   "name": "CP_VGT_HSINVOC_COUNT_HI"
6675
  },
6676
  {
6677
   "chips": ["gfx9"],
6678
   "map": {"at": 196760, "to": "mm"},
6679
   "name": "CP_VGT_DSINVOC_COUNT_LO"
6680
  },
6681
  {
6682
   "chips": ["gfx9"],
6683
   "map": {"at": 196764, "to": "mm"},
6684
   "name": "CP_VGT_DSINVOC_COUNT_HI"
6685
  },
6686
  {
6687
   "chips": ["gfx9"],
6688
   "map": {"at": 196768, "to": "mm"},
6689
   "name": "CP_PA_CINVOC_COUNT_LO"
6690
  },
6691
  {
6692
   "chips": ["gfx9"],
6693
   "map": {"at": 196772, "to": "mm"},
6694
   "name": "CP_PA_CINVOC_COUNT_HI"
6695
  },
6696
  {
6697
   "chips": ["gfx9"],
6698
   "map": {"at": 196776, "to": "mm"},
6699
   "name": "CP_PA_CPRIM_COUNT_LO"
6700
  },
6701
  {
6702
   "chips": ["gfx9"],
6703
   "map": {"at": 196780, "to": "mm"},
6704
   "name": "CP_PA_CPRIM_COUNT_HI"
6705
  },
6706
  {
6707
   "chips": ["gfx9"],
6708
   "map": {"at": 196784, "to": "mm"},
6709
   "name": "CP_SC_PSINVOC_COUNT0_LO"
6710
  },
6711
  {
6712
   "chips": ["gfx9"],
6713
   "map": {"at": 196788, "to": "mm"},
6714
   "name": "CP_SC_PSINVOC_COUNT0_HI"
6715
  },
6716
  {
6717
   "chips": ["gfx9"],
6718
   "map": {"at": 196792, "to": "mm"},
6719
   "name": "CP_SC_PSINVOC_COUNT1_LO"
6720
  },
6721
  {
6722
   "chips": ["gfx9"],
6723
   "map": {"at": 196796, "to": "mm"},
6724
   "name": "CP_SC_PSINVOC_COUNT1_HI"
6725
  },
6726
  {
6727
   "chips": ["gfx9"],
6728
   "map": {"at": 196800, "to": "mm"},
6729
   "name": "CP_VGT_CSINVOC_COUNT_LO"
6730
  },
6731
  {
6732
   "chips": ["gfx9"],
6733
   "map": {"at": 196804, "to": "mm"},
6734
   "name": "CP_VGT_CSINVOC_COUNT_HI"
6735
  },
6736
  {
6737
   "chips": ["gfx9"],
6738
   "map": {"at": 196852, "to": "mm"},
6739
   "name": "CP_PIPE_STATS_CONTROL",
6740
   "type_ref": "CP_PIPE_STATS_CONTROL"
6741
  },
6742
  {
6743
   "chips": ["gfx9"],
6744
   "map": {"at": 196856, "to": "mm"},
6745
   "name": "CP_STREAM_OUT_CONTROL",
6746
   "type_ref": "CP_PIPE_STATS_CONTROL"
6747
  },
6748
  {
6749
   "chips": ["gfx9"],
6750
   "map": {"at": 196860, "to": "mm"},
6751
   "name": "CP_STRMOUT_CNTL",
6752
   "type_ref": "CP_STRMOUT_CNTL"
6753
  },
6754
  {
6755
   "chips": ["gfx9"],
6756
   "map": {"at": 196864, "to": "mm"},
6757
   "name": "SCRATCH_REG0"
6758
  },
6759
  {
6760
   "chips": ["gfx9"],
6761
   "map": {"at": 196868, "to": "mm"},
6762
   "name": "SCRATCH_REG1"
6763
  },
6764
  {
6765
   "chips": ["gfx9"],
6766
   "map": {"at": 196872, "to": "mm"},
6767
   "name": "SCRATCH_REG2"
6768
  },
6769
  {
6770
   "chips": ["gfx9"],
6771
   "map": {"at": 196876, "to": "mm"},
6772
   "name": "SCRATCH_REG3"
6773
  },
6774
  {
6775
   "chips": ["gfx9"],
6776
   "map": {"at": 196880, "to": "mm"},
6777
   "name": "SCRATCH_REG4"
6778
  },
6779
  {
6780
   "chips": ["gfx9"],
6781
   "map": {"at": 196884, "to": "mm"},
6782
   "name": "SCRATCH_REG5"
6783
  },
6784
  {
6785
   "chips": ["gfx9"],
6786
   "map": {"at": 196888, "to": "mm"},
6787
   "name": "SCRATCH_REG6"
6788
  },
6789
  {
6790
   "chips": ["gfx9"],
6791
   "map": {"at": 196892, "to": "mm"},
6792
   "name": "SCRATCH_REG7"
6793
  },
6794
  {
6795
   "chips": ["gfx9"],
6796
   "map": {"at": 196912, "to": "mm"},
6797
   "name": "CP_APPEND_DATA_HI"
6798
  },
6799
  {
6800
   "chips": ["gfx9"],
6801
   "map": {"at": 196916, "to": "mm"},
6802
   "name": "CP_APPEND_LAST_CS_FENCE_HI"
6803
  },
6804
  {
6805
   "chips": ["gfx9"],
6806
   "map": {"at": 196920, "to": "mm"},
6807
   "name": "CP_APPEND_LAST_PS_FENCE_HI"
6808
  },
6809
  {
6810
   "chips": ["gfx9"],
6811
   "map": {"at": 196928, "to": "mm"},
6812
   "name": "SCRATCH_UMSK",
6813
   "type_ref": "SCRATCH_UMSK"
6814
  },
6815
  {
6816
   "chips": ["gfx9"],
6817
   "map": {"at": 196932, "to": "mm"},
6818
   "name": "SCRATCH_ADDR"
6819
  },
6820
  {
6821
   "chips": ["gfx9"],
6822
   "map": {"at": 196936, "to": "mm"},
6823
   "name": "CP_PFP_ATOMIC_PREOP_LO"
6824
  },
6825
  {
6826
   "chips": ["gfx9"],
6827
   "map": {"at": 196940, "to": "mm"},
6828
   "name": "CP_PFP_ATOMIC_PREOP_HI"
6829
  },
6830
  {
6831
   "chips": ["gfx9"],
6832
   "map": {"at": 196944, "to": "mm"},
6833
   "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
6834
  },
6835
  {
6836
   "chips": ["gfx9"],
6837
   "map": {"at": 196948, "to": "mm"},
6838
   "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
6839
  },
6840
  {
6841
   "chips": ["gfx9"],
6842
   "map": {"at": 196952, "to": "mm"},
6843
   "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
6844
  },
6845
  {
6846
   "chips": ["gfx9"],
6847
   "map": {"at": 196956, "to": "mm"},
6848
   "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
6849
  },
6850
  {
6851
   "chips": ["gfx9"],
6852
   "map": {"at": 196960, "to": "mm"},
6853
   "name": "CP_APPEND_ADDR_LO",
6854
   "type_ref": "CP_APPEND_ADDR_LO"
6855
  },
6856
  {
6857
   "chips": ["gfx9"],
6858
   "map": {"at": 196964, "to": "mm"},
6859
   "name": "CP_APPEND_ADDR_HI",
6860
   "type_ref": "CP_APPEND_ADDR_HI"
6861
  },
6862
  {
6863
   "chips": ["gfx9"],
6864
   "map": {"at": 196968, "to": "mm"},
6865
   "name": "CP_APPEND_DATA_LO"
6866
  },
6867
  {
6868
   "chips": ["gfx9"],
6869
   "map": {"at": 196972, "to": "mm"},
6870
   "name": "CP_APPEND_LAST_CS_FENCE_LO"
6871
  },
6872
  {
6873
   "chips": ["gfx9"],
6874
   "map": {"at": 196976, "to": "mm"},
6875
   "name": "CP_APPEND_LAST_PS_FENCE_LO"
6876
  },
6877
  {
6878
   "chips": ["gfx9"],
6879
   "map": {"at": 196980, "to": "mm"},
6880
   "name": "CP_ATOMIC_PREOP_LO"
6881
  },
6882
  {
6883
   "chips": ["gfx9"],
6884
   "map": {"at": 196984, "to": "mm"},
6885
   "name": "CP_ATOMIC_PREOP_HI"
6886
  },
6887
  {
6888
   "chips": ["gfx9"],
6889
   "map": {"at": 196988, "to": "mm"},
6890
   "name": "CP_GDS_ATOMIC0_PREOP_LO"
6891
  },
6892
  {
6893
   "chips": ["gfx9"],
6894
   "map": {"at": 196992, "to": "mm"},
6895
   "name": "CP_GDS_ATOMIC0_PREOP_HI"
6896
  },
6897
  {
6898
   "chips": ["gfx9"],
6899
   "map": {"at": 196996, "to": "mm"},
6900
   "name": "CP_GDS_ATOMIC1_PREOP_LO"
6901
  },
6902
  {
6903
   "chips": ["gfx9"],
6904
   "map": {"at": 197000, "to": "mm"},
6905
   "name": "CP_GDS_ATOMIC1_PREOP_HI"
6906
  },
6907
  {
6908
   "chips": ["gfx9"],
6909
   "map": {"at": 197028, "to": "mm"},
6910
   "name": "CP_ME_MC_WADDR_LO",
6911
   "type_ref": "CP_ME_MC_WADDR_LO"
6912
  },
6913
  {
6914
   "chips": ["gfx9"],
6915
   "map": {"at": 197032, "to": "mm"},
6916
   "name": "CP_ME_MC_WADDR_HI",
6917
   "type_ref": "CP_ME_MC_WADDR_HI"
6918
  },
6919
  {
6920
   "chips": ["gfx9"],
6921
   "map": {"at": 197036, "to": "mm"},
6922
   "name": "CP_ME_MC_WDATA_LO"
6923
  },
6924
  {
6925
   "chips": ["gfx9"],
6926
   "map": {"at": 197040, "to": "mm"},
6927
   "name": "CP_ME_MC_WDATA_HI"
6928
  },
6929
  {
6930
   "chips": ["gfx9"],
6931
   "map": {"at": 197044, "to": "mm"},
6932
   "name": "CP_ME_MC_RADDR_LO",
6933
   "type_ref": "CP_ME_MC_RADDR_LO"
6934
  },
6935
  {
6936
   "chips": ["gfx9"],
6937
   "map": {"at": 197048, "to": "mm"},
6938
   "name": "CP_ME_MC_RADDR_HI",
6939
   "type_ref": "CP_ME_MC_RADDR_HI"
6940
  },
6941
  {
6942
   "chips": ["gfx9"],
6943
   "map": {"at": 197052, "to": "mm"},
6944
   "name": "CP_SEM_WAIT_TIMER"
6945
  },
6946
  {
6947
   "chips": ["gfx9"],
6948
   "map": {"at": 197056, "to": "mm"},
6949
   "name": "CP_SIG_SEM_ADDR_LO",
6950
   "type_ref": "CP_SIG_SEM_ADDR_LO"
6951
  },
6952
  {
6953
   "chips": ["gfx9"],
6954
   "map": {"at": 197060, "to": "mm"},
6955
   "name": "CP_SIG_SEM_ADDR_HI",
6956
   "type_ref": "CP_SIG_SEM_ADDR_HI"
6957
  },
6958
  {
6959
   "chips": ["gfx9"],
6960
   "map": {"at": 197072, "to": "mm"},
6961
   "name": "CP_WAIT_REG_MEM_TIMEOUT"
6962
  },
6963
  {
6964
   "chips": ["gfx9"],
6965
   "map": {"at": 197076, "to": "mm"},
6966
   "name": "CP_WAIT_SEM_ADDR_LO",
6967
   "type_ref": "CP_SIG_SEM_ADDR_LO"
6968
  },
6969
  {
6970
   "chips": ["gfx9"],
6971
   "map": {"at": 197080, "to": "mm"},
6972
   "name": "CP_WAIT_SEM_ADDR_HI",
6973
   "type_ref": "CP_SIG_SEM_ADDR_HI"
6974
  },
6975
  {
6976
   "chips": ["gfx9"],
6977
   "map": {"at": 197084, "to": "mm"},
6978
   "name": "CP_DMA_PFP_CONTROL",
6979
   "type_ref": "CP_DMA_PFP_CONTROL"
6980
  },
6981
  {
6982
   "chips": ["gfx9"],
6983
   "map": {"at": 197088, "to": "mm"},
6984
   "name": "CP_DMA_ME_CONTROL",
6985
   "type_ref": "CP_DMA_PFP_CONTROL"
6986
  },
6987
  {
6988
   "chips": ["gfx9"],
6989
   "map": {"at": 197092, "to": "mm"},
6990
   "name": "CP_COHER_BASE_HI",
6991
   "type_ref": "CP_COHER_BASE_HI"
6992
  },
6993
  {
6994
   "chips": ["gfx9"],
6995
   "map": {"at": 197100, "to": "mm"},
6996
   "name": "CP_COHER_START_DELAY",
6997
   "type_ref": "CP_COHER_START_DELAY"
6998
  },
6999
  {
7000
   "chips": ["gfx9"],
7001
   "map": {"at": 197104, "to": "mm"},
7002
   "name": "CP_COHER_CNTL",
7003
   "type_ref": "CP_COHER_CNTL"
7004
  },
7005
  {
7006
   "chips": ["gfx9"],
7007
   "map": {"at": 197108, "to": "mm"},
7008
   "name": "CP_COHER_SIZE"
7009
  },
7010
  {
7011
   "chips": ["gfx9"],
7012
   "map": {"at": 197112, "to": "mm"},
7013
   "name": "CP_COHER_BASE"
7014
  },
7015
  {
7016
   "chips": ["gfx9"],
7017
   "map": {"at": 197116, "to": "mm"},
7018
   "name": "CP_COHER_STATUS",
7019
   "type_ref": "CP_COHER_STATUS"
7020
  },
7021
  {
7022
   "chips": ["gfx9"],
7023
   "map": {"at": 197120, "to": "mm"},
7024
   "name": "CP_DMA_ME_SRC_ADDR"
7025
  },
7026
  {
7027
   "chips": ["gfx9"],
7028
   "map": {"at": 197124, "to": "mm"},
7029
   "name": "CP_DMA_ME_SRC_ADDR_HI",
7030
   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
7031
  },
7032
  {
7033
   "chips": ["gfx9"],
7034
   "map": {"at": 197128, "to": "mm"},
7035
   "name": "CP_DMA_ME_DST_ADDR"
7036
  },
7037
  {
7038
   "chips": ["gfx9"],
7039
   "map": {"at": 197132, "to": "mm"},
7040
   "name": "CP_DMA_ME_DST_ADDR_HI",
7041
   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
7042
  },
7043
  {
7044
   "chips": ["gfx9"],
7045
   "map": {"at": 197136, "to": "mm"},
7046
   "name": "CP_DMA_ME_COMMAND",
7047
   "type_ref": "CP_DMA_ME_COMMAND"
7048
  },
7049
  {
7050
   "chips": ["gfx9"],
7051
   "map": {"at": 197140, "to": "mm"},
7052
   "name": "CP_DMA_PFP_SRC_ADDR"
7053
  },
7054
  {
7055
   "chips": ["gfx9"],
7056
   "map": {"at": 197144, "to": "mm"},
7057
   "name": "CP_DMA_PFP_SRC_ADDR_HI",
7058
   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
7059
  },
7060
  {
7061
   "chips": ["gfx9"],
7062
   "map": {"at": 197148, "to": "mm"},
7063
   "name": "CP_DMA_PFP_DST_ADDR"
7064
  },
7065
  {
7066
   "chips": ["gfx9"],
7067
   "map": {"at": 197152, "to": "mm"},
7068
   "name": "CP_DMA_PFP_DST_ADDR_HI",
7069
   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
7070
  },
7071
  {
7072
   "chips": ["gfx9"],
7073
   "map": {"at": 197156, "to": "mm"},
7074
   "name": "CP_DMA_PFP_COMMAND",
7075
   "type_ref": "CP_DMA_ME_COMMAND"
7076
  },
7077
  {
7078
   "chips": ["gfx9"],
7079
   "map": {"at": 197160, "to": "mm"},
7080
   "name": "CP_DMA_CNTL",
7081
   "type_ref": "CP_DMA_CNTL"
7082
  },
7083
  {
7084
   "chips": ["gfx9"],
7085
   "map": {"at": 197164, "to": "mm"},
7086
   "name": "CP_DMA_READ_TAGS",
7087
   "type_ref": "CP_DMA_READ_TAGS"
7088
  },
7089
  {
7090
   "chips": ["gfx9"],
7091
   "map": {"at": 197168, "to": "mm"},
7092
   "name": "CP_COHER_SIZE_HI",
7093
   "type_ref": "CP_COHER_SIZE_HI"
7094
  },
7095
  {
7096
   "chips": ["gfx9"],
7097
   "map": {"at": 197172, "to": "mm"},
7098
   "name": "CP_PFP_IB_CONTROL",
7099
   "type_ref": "CP_PFP_IB_CONTROL"
7100
  },
7101
  {
7102
   "chips": ["gfx9"],
7103
   "map": {"at": 197176, "to": "mm"},
7104
   "name": "CP_PFP_LOAD_CONTROL",
7105
   "type_ref": "CP_PFP_LOAD_CONTROL"
7106
  },
7107
  {
7108
   "chips": ["gfx9"],
7109
   "map": {"at": 197180, "to": "mm"},
7110
   "name": "CP_SCRATCH_INDEX",
7111
   "type_ref": "CP_SCRATCH_INDEX"
7112
  },
7113
  {
7114
   "chips": ["gfx9"],
7115
   "map": {"at": 197184, "to": "mm"},
7116
   "name": "CP_SCRATCH_DATA"
7117
  },
7118
  {
7119
   "chips": ["gfx9"],
7120
   "map": {"at": 197188, "to": "mm"},
7121
   "name": "CP_RB_OFFSET",
7122
   "type_ref": "CP_RB_OFFSET"
7123
  },
7124
  {
7125
   "chips": ["gfx9"],
7126
   "map": {"at": 197192, "to": "mm"},
7127
   "name": "CP_IB1_OFFSET",
7128
   "type_ref": "CP_IB1_OFFSET"
7129
  },
7130
  {
7131
   "chips": ["gfx9"],
7132
   "map": {"at": 197196, "to": "mm"},
7133
   "name": "CP_IB2_OFFSET",
7134
   "type_ref": "CP_IB2_OFFSET"
7135
  },
7136
  {
7137
   "chips": ["gfx9"],
7138
   "map": {"at": 197200, "to": "mm"},
7139
   "name": "CP_IB1_PREAMBLE_BEGIN",
7140
   "type_ref": "CP_IB1_PREAMBLE_BEGIN"
7141
  },
7142
  {
7143
   "chips": ["gfx9"],
7144
   "map": {"at": 197204, "to": "mm"},
7145
   "name": "CP_IB1_PREAMBLE_END",
7146
   "type_ref": "CP_IB1_PREAMBLE_END"
7147
  },
7148
  {
7149
   "chips": ["gfx9"],
7150
   "map": {"at": 197208, "to": "mm"},
7151
   "name": "CP_IB2_PREAMBLE_BEGIN",
7152
   "type_ref": "CP_IB2_PREAMBLE_BEGIN"
7153
  },
7154
  {
7155
   "chips": ["gfx9"],
7156
   "map": {"at": 197212, "to": "mm"},
7157
   "name": "CP_IB2_PREAMBLE_END",
7158
   "type_ref": "CP_IB2_PREAMBLE_END"
7159
  },
7160
  {
7161
   "chips": ["gfx9"],
7162
   "map": {"at": 197216, "to": "mm"},
7163
   "name": "CP_CE_IB1_OFFSET",
7164
   "type_ref": "CP_IB1_OFFSET"
7165
  },
7166
  {
7167
   "chips": ["gfx9"],
7168
   "map": {"at": 197220, "to": "mm"},
7169
   "name": "CP_CE_IB2_OFFSET",
7170
   "type_ref": "CP_IB2_OFFSET"
7171
  },
7172
  {
7173
   "chips": ["gfx9"],
7174
   "map": {"at": 197224, "to": "mm"},
7175
   "name": "CP_CE_COUNTER"
7176
  },
7177
  {
7178
   "chips": ["gfx9"],
7179
   "map": {"at": 197228, "to": "mm"},
7180
   "name": "CP_CE_RB_OFFSET",
7181
   "type_ref": "CP_RB_OFFSET"
7182
  },
7183
  {
7184
   "chips": ["gfx9"],
7185
   "map": {"at": 197364, "to": "mm"},
7186
   "name": "CP_CE_INIT_CMD_BUFSZ",
7187
   "type_ref": "CP_CE_INIT_CMD_BUFSZ"
7188
  },
7189
  {
7190
   "chips": ["gfx9"],
7191
   "map": {"at": 197368, "to": "mm"},
7192
   "name": "CP_CE_IB1_CMD_BUFSZ",
7193
   "type_ref": "CP_CE_IB1_CMD_BUFSZ"
7194
  },
7195
  {
7196
   "chips": ["gfx9"],
7197
   "map": {"at": 197372, "to": "mm"},
7198
   "name": "CP_CE_IB2_CMD_BUFSZ",
7199
   "type_ref": "CP_CE_IB2_CMD_BUFSZ"
7200
  },
7201
  {
7202
   "chips": ["gfx9"],
7203
   "map": {"at": 197376, "to": "mm"},
7204
   "name": "CP_IB1_CMD_BUFSZ",
7205
   "type_ref": "CP_CE_IB1_CMD_BUFSZ"
7206
  },
7207
  {
7208
   "chips": ["gfx9"],
7209
   "map": {"at": 197380, "to": "mm"},
7210
   "name": "CP_IB2_CMD_BUFSZ",
7211
   "type_ref": "CP_CE_IB2_CMD_BUFSZ"
7212
  },
7213
  {
7214
   "chips": ["gfx9"],
7215
   "map": {"at": 197384, "to": "mm"},
7216
   "name": "CP_ST_CMD_BUFSZ",
7217
   "type_ref": "CP_ST_CMD_BUFSZ"
7218
  },
7219
  {
7220
   "chips": ["gfx9"],
7221
   "map": {"at": 197388, "to": "mm"},
7222
   "name": "CP_CE_INIT_BASE_LO",
7223
   "type_ref": "CP_CE_INIT_BASE_LO"
7224
  },
7225
  {
7226
   "chips": ["gfx9"],
7227
   "map": {"at": 197392, "to": "mm"},
7228
   "name": "CP_CE_INIT_BASE_HI",
7229
   "type_ref": "CP_CE_INIT_BASE_HI"
7230
  },
7231
  {
7232
   "chips": ["gfx9"],
7233
   "map": {"at": 197396, "to": "mm"},
7234
   "name": "CP_CE_INIT_BUFSZ",
7235
   "type_ref": "CP_CE_INIT_BUFSZ"
7236
  },
7237
  {
7238
   "chips": ["gfx9"],
7239
   "map": {"at": 197400, "to": "mm"},
7240
   "name": "CP_CE_IB1_BASE_LO",
7241
   "type_ref": "CP_CE_IB1_BASE_LO"
7242
  },
7243
  {
7244
   "chips": ["gfx9"],
7245
   "map": {"at": 197404, "to": "mm"},
7246
   "name": "CP_CE_IB1_BASE_HI",
7247
   "type_ref": "CP_CE_IB1_BASE_HI"
7248
  },
7249
  {
7250
   "chips": ["gfx9"],
7251
   "map": {"at": 197408, "to": "mm"},
7252
   "name": "CP_CE_IB1_BUFSZ",
7253
   "type_ref": "CP_CE_IB1_BUFSZ"
7254
  },
7255
  {
7256
   "chips": ["gfx9"],
7257
   "map": {"at": 197412, "to": "mm"},
7258
   "name": "CP_CE_IB2_BASE_LO",
7259
   "type_ref": "CP_CE_IB2_BASE_LO"
7260
  },
7261
  {
7262
   "chips": ["gfx9"],
7263
   "map": {"at": 197416, "to": "mm"},
7264
   "name": "CP_CE_IB2_BASE_HI",
7265
   "type_ref": "CP_CE_IB2_BASE_HI"
7266
  },
7267
  {
7268
   "chips": ["gfx9"],
7269
   "map": {"at": 197420, "to": "mm"},
7270
   "name": "CP_CE_IB2_BUFSZ",
7271
   "type_ref": "CP_CE_IB2_BUFSZ"
7272
  },
7273
  {
7274
   "chips": ["gfx9"],
7275
   "map": {"at": 197424, "to": "mm"},
7276
   "name": "CP_IB1_BASE_LO",
7277
   "type_ref": "CP_CE_IB1_BASE_LO"
7278
  },
7279
  {
7280
   "chips": ["gfx9"],
7281
   "map": {"at": 197428, "to": "mm"},
7282
   "name": "CP_IB1_BASE_HI",
7283
   "type_ref": "CP_CE_IB1_BASE_HI"
7284
  },
7285
  {
7286
   "chips": ["gfx9"],
7287
   "map": {"at": 197432, "to": "mm"},
7288
   "name": "CP_IB1_BUFSZ",
7289
   "type_ref": "CP_CE_IB1_BUFSZ"
7290
  },
7291
  {
7292
   "chips": ["gfx9"],
7293
   "map": {"at": 197436, "to": "mm"},
7294
   "name": "CP_IB2_BASE_LO",
7295
   "type_ref": "CP_CE_IB2_BASE_LO"
7296
  },
7297
  {
7298
   "chips": ["gfx9"],
7299
   "map": {"at": 197440, "to": "mm"},
7300
   "name": "CP_IB2_BASE_HI",
7301
   "type_ref": "CP_CE_IB2_BASE_HI"
7302
  },
7303
  {
7304
   "chips": ["gfx9"],
7305
   "map": {"at": 197444, "to": "mm"},
7306
   "name": "CP_IB2_BUFSZ",
7307
   "type_ref": "CP_CE_IB2_BUFSZ"
7308
  },
7309
  {
7310
   "chips": ["gfx9"],
7311
   "map": {"at": 197448, "to": "mm"},
7312
   "name": "CP_ST_BASE_LO",
7313
   "type_ref": "CP_ST_BASE_LO"
7314
  },
7315
  {
7316
   "chips": ["gfx9"],
7317
   "map": {"at": 197452, "to": "mm"},
7318
   "name": "CP_ST_BASE_HI",
7319
   "type_ref": "CP_ST_BASE_HI"
7320
  },
7321
  {
7322
   "chips": ["gfx9"],
7323
   "map": {"at": 197456, "to": "mm"},
7324
   "name": "CP_ST_BUFSZ",
7325
   "type_ref": "CP_ST_BUFSZ"
7326
  },
7327
  {
7328
   "chips": ["gfx9"],
7329
   "map": {"at": 197460, "to": "mm"},
7330
   "name": "CP_EOP_DONE_EVENT_CNTL",
7331
   "type_ref": "CP_EOP_DONE_EVENT_CNTL"
7332
  },
7333
  {
7334
   "chips": ["gfx9"],
7335
   "map": {"at": 197464, "to": "mm"},
7336
   "name": "CP_EOP_DONE_DATA_CNTL",
7337
   "type_ref": "CP_EOP_DONE_DATA_CNTL"
7338
  },
7339
  {
7340
   "chips": ["gfx9"],
7341
   "map": {"at": 197468, "to": "mm"},
7342
   "name": "CP_EOP_DONE_CNTX_ID"
7343
  },
7344
  {
7345
   "chips": ["gfx9"],
7346
   "map": {"at": 197552, "to": "mm"},
7347
   "name": "CP_PFP_COMPLETION_STATUS",
7348
   "type_ref": "CP_PFP_COMPLETION_STATUS"
7349
  },
7350
  {
7351
   "chips": ["gfx9"],
7352
   "map": {"at": 197556, "to": "mm"},
7353
   "name": "CP_CE_COMPLETION_STATUS",
7354
   "type_ref": "CP_PFP_COMPLETION_STATUS"
7355
  },
7356
  {
7357
   "chips": ["gfx9"],
7358
   "map": {"at": 197560, "to": "mm"},
7359
   "name": "CP_PRED_NOT_VISIBLE",
7360
   "type_ref": "CP_PRED_NOT_VISIBLE"
7361
  },
7362
  {
7363
   "chips": ["gfx9"],
7364
   "map": {"at": 197568, "to": "mm"},
7365
   "name": "CP_PFP_METADATA_BASE_ADDR"
7366
  },
7367
  {
7368
   "chips": ["gfx9"],
7369
   "map": {"at": 197572, "to": "mm"},
7370
   "name": "CP_PFP_METADATA_BASE_ADDR_HI",
7371
   "type_ref": "CP_EOP_DONE_ADDR_HI"
7372
  },
7373
  {
7374
   "chips": ["gfx9"],
7375
   "map": {"at": 197576, "to": "mm"},
7376
   "name": "CP_CE_METADATA_BASE_ADDR"
7377
  },
7378
  {
7379
   "chips": ["gfx9"],
7380
   "map": {"at": 197580, "to": "mm"},
7381
   "name": "CP_CE_METADATA_BASE_ADDR_HI",
7382
   "type_ref": "CP_EOP_DONE_ADDR_HI"
7383
  },
7384
  {
7385
   "chips": ["gfx9"],
7386
   "map": {"at": 197584, "to": "mm"},
7387
   "name": "CP_DRAW_INDX_INDR_ADDR"
7388
  },
7389
  {
7390
   "chips": ["gfx9"],
7391
   "map": {"at": 197588, "to": "mm"},
7392
   "name": "CP_DRAW_INDX_INDR_ADDR_HI",
7393
   "type_ref": "CP_EOP_DONE_ADDR_HI"
7394
  },
7395
  {
7396
   "chips": ["gfx9"],
7397
   "map": {"at": 197592, "to": "mm"},
7398
   "name": "CP_DISPATCH_INDR_ADDR"
7399
  },
7400
  {
7401
   "chips": ["gfx9"],
7402
   "map": {"at": 197596, "to": "mm"},
7403
   "name": "CP_DISPATCH_INDR_ADDR_HI",
7404
   "type_ref": "CP_EOP_DONE_ADDR_HI"
7405
  },
7406
  {
7407
   "chips": ["gfx9"],
7408
   "map": {"at": 197600, "to": "mm"},
7409
   "name": "CP_INDEX_BASE_ADDR"
7410
  },
7411
  {
7412
   "chips": ["gfx9"],
7413
   "map": {"at": 197604, "to": "mm"},
7414
   "name": "CP_INDEX_BASE_ADDR_HI",
7415
   "type_ref": "CP_EOP_DONE_ADDR_HI"
7416
  },
7417
  {
7418
   "chips": ["gfx9"],
7419
   "map": {"at": 197608, "to": "mm"},
7420
   "name": "CP_INDEX_TYPE",
7421
   "type_ref": "CP_INDEX_TYPE"
7422
  },
7423
  {
7424
   "chips": ["gfx9"],
7425
   "map": {"at": 197612, "to": "mm"},
7426
   "name": "CP_GDS_BKUP_ADDR"
7427
  },
7428
  {
7429
   "chips": ["gfx9"],
7430
   "map": {"at": 197616, "to": "mm"},
7431
   "name": "CP_GDS_BKUP_ADDR_HI",
7432
   "type_ref": "CP_EOP_DONE_ADDR_HI"
7433
  },
7434
  {
7435
   "chips": ["gfx9"],
7436
   "map": {"at": 197620, "to": "mm"},
7437
   "name": "CP_SAMPLE_STATUS",
7438
   "type_ref": "CP_SAMPLE_STATUS"
7439
  },
7440
  {
7441
   "chips": ["gfx9"],
7442
   "map": {"at": 197624, "to": "mm"},
7443
   "name": "CP_ME_COHER_CNTL",
7444
   "type_ref": "CP_ME_COHER_CNTL"
7445
  },
7446
  {
7447
   "chips": ["gfx9"],
7448
   "map": {"at": 197628, "to": "mm"},
7449
   "name": "CP_ME_COHER_SIZE"
7450
  },
7451
  {
7452
   "chips": ["gfx9"],
7453
   "map": {"at": 197632, "to": "mm"},
7454
   "name": "CP_ME_COHER_SIZE_HI",
7455
   "type_ref": "CP_COHER_SIZE_HI"
7456
  },
7457
  {
7458
   "chips": ["gfx9"],
7459
   "map": {"at": 197636, "to": "mm"},
7460
   "name": "CP_ME_COHER_BASE"
7461
  },
7462
  {
7463
   "chips": ["gfx9"],
7464
   "map": {"at": 197640, "to": "mm"},
7465
   "name": "CP_ME_COHER_BASE_HI",
7466
   "type_ref": "CP_COHER_BASE_HI"
7467
  },
7468
  {
7469
   "chips": ["gfx9"],
7470
   "map": {"at": 197644, "to": "mm"},
7471
   "name": "CP_ME_COHER_STATUS",
7472
   "type_ref": "CP_ME_COHER_STATUS"
7473
  },
7474
  {
7475
   "chips": ["gfx9"],
7476
   "map": {"at": 197888, "to": "mm"},
7477
   "name": "RLC_GPM_PERF_COUNT_0",
7478
   "type_ref": "RLC_GPM_PERF_COUNT_0"
7479
  },
7480
  {
7481
   "chips": ["gfx9"],
7482
   "map": {"at": 197892, "to": "mm"},
7483
   "name": "RLC_GPM_PERF_COUNT_1",
7484
   "type_ref": "RLC_GPM_PERF_COUNT_0"
7485
  },
7486
  {
7487
   "chips": ["gfx9"],
7488
   "map": {"at": 198656, "to": "mm"},
7489
   "name": "GRBM_GFX_INDEX",
7490
   "type_ref": "GRBM_GFX_INDEX"
7491
  },
7492
  {
7493
   "chips": ["gfx9"],
7494
   "map": {"at": 198916, "to": "mm"},
7495
   "name": "VGT_GSVS_RING_SIZE"
7496
  },
7497
  {
7498
   "chips": ["gfx9"],
7499
   "map": {"at": 198920, "to": "mm"},
7500
   "name": "VGT_PRIMITIVE_TYPE",
7501
   "type_ref": "VGT_PRIMITIVE_TYPE"
7502
  },
7503
  {
7504
   "chips": ["gfx9"],
7505
   "map": {"at": 198924, "to": "mm"},
7506
   "name": "VGT_INDEX_TYPE",
7507
   "type_ref": "VGT_INDEX_TYPE"
7508
  },
7509
  {
7510
   "chips": ["gfx9"],
7511
   "map": {"at": 198928, "to": "mm"},
7512
   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0"
7513
  },
7514
  {
7515
   "chips": ["gfx9"],
7516
   "map": {"at": 198932, "to": "mm"},
7517
   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1"
7518
  },
7519
  {
7520
   "chips": ["gfx9"],
7521
   "map": {"at": 198936, "to": "mm"},
7522
   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2"
7523
  },
7524
  {
7525
   "chips": ["gfx9"],
7526
   "map": {"at": 198940, "to": "mm"},
7527
   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3"
7528
  },
7529
  {
7530
   "chips": ["gfx9"],
7531
   "map": {"at": 198944, "to": "mm"},
7532
   "name": "VGT_MAX_VTX_INDX"
7533
  },
7534
  {
7535
   "chips": ["gfx9"],
7536
   "map": {"at": 198948, "to": "mm"},
7537
   "name": "VGT_MIN_VTX_INDX"
7538
  },
7539
  {
7540
   "chips": ["gfx9"],
7541
   "map": {"at": 198952, "to": "mm"},
7542
   "name": "VGT_INDX_OFFSET"
7543
  },
7544
  {
7545
   "chips": ["gfx9"],
7546
   "map": {"at": 198956, "to": "mm"},
7547
   "name": "VGT_MULTI_PRIM_IB_RESET_EN",
7548
   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
7549
  },
7550
  {
7551
   "chips": ["gfx9"],
7552
   "map": {"at": 198960, "to": "mm"},
7553
   "name": "VGT_NUM_INDICES"
7554
  },
7555
  {
7556
   "chips": ["gfx9"],
7557
   "map": {"at": 198964, "to": "mm"},
7558
   "name": "VGT_NUM_INSTANCES"
7559
  },
7560
  {
7561
   "chips": ["gfx9"],
7562
   "map": {"at": 198968, "to": "mm"},
7563
   "name": "VGT_TF_RING_SIZE",
7564
   "type_ref": "VGT_TF_RING_SIZE"
7565
  },
7566
  {
7567
   "chips": ["gfx9"],
7568
   "map": {"at": 198972, "to": "mm"},
7569
   "name": "VGT_HS_OFFCHIP_PARAM",
7570
   "type_ref": "VGT_HS_OFFCHIP_PARAM"
7571
  },
7572
  {
7573
   "chips": ["gfx9"],
7574
   "map": {"at": 198976, "to": "mm"},
7575
   "name": "VGT_TF_MEMORY_BASE"
7576
  },
7577
  {
7578
   "chips": ["gfx9"],
7579
   "map": {"at": 198980, "to": "mm"},
7580
   "name": "VGT_TF_MEMORY_BASE_HI",
7581
   "type_ref": "DB_HTILE_DATA_BASE_HI"
7582
  },
7583
  {
7584
   "chips": ["gfx9"],
7585
   "map": {"at": 198984, "to": "mm"},
7586
   "name": "WD_POS_BUF_BASE"
7587
  },
7588
  {
7589
   "chips": ["gfx9"],
7590
   "map": {"at": 198988, "to": "mm"},
7591
   "name": "WD_POS_BUF_BASE_HI",
7592
   "type_ref": "DB_HTILE_DATA_BASE_HI"
7593
  },
7594
  {
7595
   "chips": ["gfx9"],
7596
   "map": {"at": 198992, "to": "mm"},
7597
   "name": "WD_CNTL_SB_BUF_BASE"
7598
  },
7599
  {
7600
   "chips": ["gfx9"],
7601
   "map": {"at": 198996, "to": "mm"},
7602
   "name": "WD_CNTL_SB_BUF_BASE_HI",
7603
   "type_ref": "DB_HTILE_DATA_BASE_HI"
7604
  },
7605
  {
7606
   "chips": ["gfx9"],
7607
   "map": {"at": 199000, "to": "mm"},
7608
   "name": "WD_INDEX_BUF_BASE"
7609
  },
7610
  {
7611
   "chips": ["gfx9"],
7612
   "map": {"at": 199004, "to": "mm"},
7613
   "name": "WD_INDEX_BUF_BASE_HI",
7614
   "type_ref": "DB_HTILE_DATA_BASE_HI"
7615
  },
7616
  {
7617
   "chips": ["gfx9"],
7618
   "map": {"at": 199008, "to": "mm"},
7619
   "name": "IA_MULTI_VGT_PARAM",
7620
   "type_ref": "IA_MULTI_VGT_PARAM"
7621
  },
7622
  {
7623
   "chips": ["gfx9"],
7624
   "map": {"at": 199016, "to": "mm"},
7625
   "name": "VGT_INSTANCE_BASE_ID"
7626
  },
7627
  {
7628
   "chips": ["gfx9"],
7629
   "map": {"at": 199168, "to": "mm"},
7630
   "name": "PA_SU_LINE_STIPPLE_VALUE",
7631
   "type_ref": "PA_SU_LINE_STIPPLE_VALUE"
7632
  },
7633
  {
7634
   "chips": ["gfx9"],
7635
   "map": {"at": 199172, "to": "mm"},
7636
   "name": "PA_SC_LINE_STIPPLE_STATE",
7637
   "type_ref": "PA_SC_LINE_STIPPLE_STATE"
7638
  },
7639
  {
7640
   "chips": ["gfx9"],
7641
   "map": {"at": 199184, "to": "mm"},
7642
   "name": "PA_SC_SCREEN_EXTENT_MIN_0",
7643
   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7644
  },
7645
  {
7646
   "chips": ["gfx9"],
7647
   "map": {"at": 199188, "to": "mm"},
7648
   "name": "PA_SC_SCREEN_EXTENT_MAX_0",
7649
   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7650
  },
7651
  {
7652
   "chips": ["gfx9"],
7653
   "map": {"at": 199192, "to": "mm"},
7654
   "name": "PA_SC_SCREEN_EXTENT_MIN_1",
7655
   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7656
  },
7657
  {
7658
   "chips": ["gfx9"],
7659
   "map": {"at": 199212, "to": "mm"},
7660
   "name": "PA_SC_SCREEN_EXTENT_MAX_1",
7661
   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7662
  },
7663
  {
7664
   "chips": ["gfx9"],
7665
   "map": {"at": 199296, "to": "mm"},
7666
   "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN",
7667
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7668
  },
7669
  {
7670
   "chips": ["gfx9"],
7671
   "map": {"at": 199300, "to": "mm"},
7672
   "name": "PA_SC_P3D_TRAP_SCREEN_H",
7673
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7674
  },
7675
  {
7676
   "chips": ["gfx9"],
7677
   "map": {"at": 199304, "to": "mm"},
7678
   "name": "PA_SC_P3D_TRAP_SCREEN_V",
7679
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7680
  },
7681
  {
7682
   "chips": ["gfx9"],
7683
   "map": {"at": 199308, "to": "mm"},
7684
   "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE",
7685
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7686
  },
7687
  {
7688
   "chips": ["gfx9"],
7689
   "map": {"at": 199312, "to": "mm"},
7690
   "name": "PA_SC_P3D_TRAP_SCREEN_COUNT",
7691
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7692
  },
7693
  {
7694
   "chips": ["gfx9"],
7695
   "map": {"at": 199328, "to": "mm"},
7696
   "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN",
7697
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7698
  },
7699
  {
7700
   "chips": ["gfx9"],
7701
   "map": {"at": 199332, "to": "mm"},
7702
   "name": "PA_SC_HP3D_TRAP_SCREEN_H",
7703
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7704
  },
7705
  {
7706
   "chips": ["gfx9"],
7707
   "map": {"at": 199336, "to": "mm"},
7708
   "name": "PA_SC_HP3D_TRAP_SCREEN_V",
7709
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7710
  },
7711
  {
7712
   "chips": ["gfx9"],
7713
   "map": {"at": 199340, "to": "mm"},
7714
   "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE",
7715
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7716
  },
7717
  {
7718
   "chips": ["gfx9"],
7719
   "map": {"at": 199344, "to": "mm"},
7720
   "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT",
7721
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7722
  },
7723
  {
7724
   "chips": ["gfx9"],
7725
   "map": {"at": 199360, "to": "mm"},
7726
   "name": "PA_SC_TRAP_SCREEN_HV_EN",
7727
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7728
  },
7729
  {
7730
   "chips": ["gfx9"],
7731
   "map": {"at": 199364, "to": "mm"},
7732
   "name": "PA_SC_TRAP_SCREEN_H",
7733
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7734
  },
7735
  {
7736
   "chips": ["gfx9"],
7737
   "map": {"at": 199368, "to": "mm"},
7738
   "name": "PA_SC_TRAP_SCREEN_V",
7739
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7740
  },
7741
  {
7742
   "chips": ["gfx9"],
7743
   "map": {"at": 199372, "to": "mm"},
7744
   "name": "PA_SC_TRAP_SCREEN_OCCURRENCE",
7745
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7746
  },
7747
  {
7748
   "chips": ["gfx9"],
7749
   "map": {"at": 199376, "to": "mm"},
7750
   "name": "PA_SC_TRAP_SCREEN_COUNT",
7751
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7752
  },
7753
  {
7754
   "chips": ["gfx9"],
7755
   "map": {"at": 199380, "to": "mm"},
7756
   "name": "PA_STATE_STEREO_X"
7757
  },
7758
  {
7759
   "chips": ["gfx9"],
7760
   "map": {"at": 199872, "to": "mm"},
7761
   "name": "SQ_THREAD_TRACE_BASE"
7762
  },
7763
  {
7764
   "chips": ["gfx9"],
7765
   "map": {"at": 199876, "to": "mm"},
7766
   "name": "SQ_THREAD_TRACE_SIZE",
7767
   "type_ref": "SQ_THREAD_TRACE_SIZE"
7768
  },
7769
  {
7770
   "chips": ["gfx9"],
7771
   "map": {"at": 199880, "to": "mm"},
7772
   "name": "SQ_THREAD_TRACE_MASK",
7773
   "type_ref": "SQ_THREAD_TRACE_MASK"
7774
  },
7775
  {
7776
   "chips": ["gfx9"],
7777
   "map": {"at": 199884, "to": "mm"},
7778
   "name": "SQ_THREAD_TRACE_TOKEN_MASK",
7779
   "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK"
7780
  },
7781
  {
7782
   "chips": ["gfx9"],
7783
   "map": {"at": 199888, "to": "mm"},
7784
   "name": "SQ_THREAD_TRACE_PERF_MASK",
7785
   "type_ref": "SQ_THREAD_TRACE_PERF_MASK"
7786
  },
7787
  {
7788
   "chips": ["gfx9"],
7789
   "map": {"at": 199892, "to": "mm"},
7790
   "name": "SQ_THREAD_TRACE_CTRL",
7791
   "type_ref": "SQ_THREAD_TRACE_CTRL"
7792
  },
7793
  {
7794
   "chips": ["gfx9"],
7795
   "map": {"at": 199896, "to": "mm"},
7796
   "name": "SQ_THREAD_TRACE_MODE",
7797
   "type_ref": "SQ_THREAD_TRACE_MODE"
7798
  },
7799
  {
7800
   "chips": ["gfx9"],
7801
   "map": {"at": 199900, "to": "mm"},
7802
   "name": "SQ_THREAD_TRACE_BASE2",
7803
   "type_ref": "SQ_THREAD_TRACE_BASE2"
7804
  },
7805
  {
7806
   "chips": ["gfx9"],
7807
   "map": {"at": 199904, "to": "mm"},
7808
   "name": "SQ_THREAD_TRACE_TOKEN_MASK2"
7809
  },
7810
  {
7811
   "chips": ["gfx9"],
7812
   "map": {"at": 199908, "to": "mm"},
7813
   "name": "SQ_THREAD_TRACE_WPTR",
7814
   "type_ref": "SQ_THREAD_TRACE_WPTR"
7815
  },
7816
  {
7817
   "chips": ["gfx9"],
7818
   "map": {"at": 199912, "to": "mm"},
7819
   "name": "SQ_THREAD_TRACE_STATUS",
7820
   "type_ref": "SQ_THREAD_TRACE_STATUS"
7821
  },
7822
  {
7823
   "chips": ["gfx9"],
7824
   "map": {"at": 199916, "to": "mm"},
7825
   "name": "SQ_THREAD_TRACE_HIWATER",
7826
   "type_ref": "SQ_THREAD_TRACE_HIWATER"
7827
  },
7828
  {
7829
   "chips": ["gfx9"],
7830
   "map": {"at": 199920, "to": "mm"},
7831
   "name": "SQ_THREAD_TRACE_CNTR"
7832
  },
7833
  {
7834
   "chips": ["gfx9"],
7835
   "map": {"at": 199936, "to": "mm"},
7836
   "name": "SQ_THREAD_TRACE_USERDATA_0"
7837
  },
7838
  {
7839
   "chips": ["gfx9"],
7840
   "map": {"at": 199940, "to": "mm"},
7841
   "name": "SQ_THREAD_TRACE_USERDATA_1"
7842
  },
7843
  {
7844
   "chips": ["gfx9"],
7845
   "map": {"at": 199944, "to": "mm"},
7846
   "name": "SQ_THREAD_TRACE_USERDATA_2"
7847
  },
7848
  {
7849
   "chips": ["gfx9"],
7850
   "map": {"at": 199948, "to": "mm"},
7851
   "name": "SQ_THREAD_TRACE_USERDATA_3"
7852
  },
7853
  {
7854
   "chips": ["gfx9"],
7855
   "map": {"at": 199968, "to": "mm"},
7856
   "name": "SQC_CACHES",
7857
   "type_ref": "SQC_CACHES"
7858
  },
7859
  {
7860
   "chips": ["gfx9"],
7861
   "map": {"at": 199972, "to": "mm"},
7862
   "name": "SQC_WRITEBACK",
7863
   "type_ref": "SQC_WRITEBACK"
7864
  },
7865
  {
7866
   "chips": ["gfx9"],
7867
   "map": {"at": 200192, "to": "mm"},
7868
   "name": "TA_CS_BC_BASE_ADDR"
7869
  },
7870
  {
7871
   "chips": ["gfx9"],
7872
   "map": {"at": 200196, "to": "mm"},
7873
   "name": "TA_CS_BC_BASE_ADDR_HI",
7874
   "type_ref": "TA_BC_BASE_ADDR_HI"
7875
  },
7876
  {
7877
   "chips": ["gfx9"],
7878
   "map": {"at": 200448, "to": "mm"},
7879
   "name": "DB_OCCLUSION_COUNT0_LOW"
7880
  },
7881
  {
7882
   "chips": ["gfx9"],
7883
   "map": {"at": 200452, "to": "mm"},
7884
   "name": "DB_OCCLUSION_COUNT0_HI",
7885
   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7886
  },
7887
  {
7888
   "chips": ["gfx9"],
7889
   "map": {"at": 200456, "to": "mm"},
7890
   "name": "DB_OCCLUSION_COUNT1_LOW"
7891
  },
7892
  {
7893
   "chips": ["gfx9"],
7894
   "map": {"at": 200460, "to": "mm"},
7895
   "name": "DB_OCCLUSION_COUNT1_HI",
7896
   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7897
  },
7898
  {
7899
   "chips": ["gfx9"],
7900
   "map": {"at": 200464, "to": "mm"},
7901
   "name": "DB_OCCLUSION_COUNT2_LOW"
7902
  },
7903
  {
7904
   "chips": ["gfx9"],
7905
   "map": {"at": 200468, "to": "mm"},
7906
   "name": "DB_OCCLUSION_COUNT2_HI",
7907
   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7908
  },
7909
  {
7910
   "chips": ["gfx9"],
7911
   "map": {"at": 200472, "to": "mm"},
7912
   "name": "DB_OCCLUSION_COUNT3_LOW"
7913
  },
7914
  {
7915
   "chips": ["gfx9"],
7916
   "map": {"at": 200476, "to": "mm"},
7917
   "name": "DB_OCCLUSION_COUNT3_HI",
7918
   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7919
  },
7920
  {
7921
   "chips": ["gfx9"],
7922
   "map": {"at": 200696, "to": "mm"},
7923
   "name": "DB_ZPASS_COUNT_LOW"
7924
  },
7925
  {
7926
   "chips": ["gfx9"],
7927
   "map": {"at": 200700, "to": "mm"},
7928
   "name": "DB_ZPASS_COUNT_HI",
7929
   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7930
  },
7931
  {
7932
   "chips": ["gfx9"],
7933
   "map": {"at": 200704, "to": "mm"},
7934
   "name": "GDS_RD_ADDR"
7935
  },
7936
  {
7937
   "chips": ["gfx9"],
7938
   "map": {"at": 200708, "to": "mm"},
7939
   "name": "GDS_RD_DATA"
7940
  },
7941
  {
7942
   "chips": ["gfx9"],
7943
   "map": {"at": 200712, "to": "mm"},
7944
   "name": "GDS_RD_BURST_ADDR"
7945
  },
7946
  {
7947
   "chips": ["gfx9"],
7948
   "map": {"at": 200716, "to": "mm"},
7949
   "name": "GDS_RD_BURST_COUNT"
7950
  },
7951
  {
7952
   "chips": ["gfx9"],
7953
   "map": {"at": 200720, "to": "mm"},
7954
   "name": "GDS_RD_BURST_DATA"
7955
  },
7956
  {
7957
   "chips": ["gfx9"],
7958
   "map": {"at": 200724, "to": "mm"},
7959
   "name": "GDS_WR_ADDR"
7960
  },
7961
  {
7962
   "chips": ["gfx9"],
7963
   "map": {"at": 200728, "to": "mm"},
7964
   "name": "GDS_WR_DATA"
7965
  },
7966
  {
7967
   "chips": ["gfx9"],
7968
   "map": {"at": 200732, "to": "mm"},
7969
   "name": "GDS_WR_BURST_ADDR"
7970
  },
7971
  {
7972
   "chips": ["gfx9"],
7973
   "map": {"at": 200736, "to": "mm"},
7974
   "name": "GDS_WR_BURST_DATA"
7975
  },
7976
  {
7977
   "chips": ["gfx9"],
7978
   "map": {"at": 200740, "to": "mm"},
7979
   "name": "GDS_WRITE_COMPLETE"
7980
  },
7981
  {
7982
   "chips": ["gfx9"],
7983
   "map": {"at": 200744, "to": "mm"},
7984
   "name": "GDS_ATOM_CNTL",
7985
   "type_ref": "GDS_ATOM_CNTL"
7986
  },
7987
  {
7988
   "chips": ["gfx9"],
7989
   "map": {"at": 200748, "to": "mm"},
7990
   "name": "GDS_ATOM_COMPLETE",
7991
   "type_ref": "GDS_ATOM_COMPLETE"
7992
  },
7993
  {
7994
   "chips": ["gfx9"],
7995
   "map": {"at": 200752, "to": "mm"},
7996
   "name": "GDS_ATOM_BASE",
7997
   "type_ref": "GDS_ATOM_BASE"
7998
  },
7999
  {
8000
   "chips": ["gfx9"],
8001
   "map": {"at": 200756, "to": "mm"},
8002
   "name": "GDS_ATOM_SIZE",
8003
   "type_ref": "GDS_ATOM_SIZE"
8004
  },
8005
  {
8006
   "chips": ["gfx9"],
8007
   "map": {"at": 200760, "to": "mm"},
8008
   "name": "GDS_ATOM_OFFSET0",
8009
   "type_ref": "GDS_ATOM_OFFSET0"
8010
  },
8011
  {
8012
   "chips": ["gfx9"],
8013
   "map": {"at": 200764, "to": "mm"},
8014
   "name": "GDS_ATOM_OFFSET1",
8015
   "type_ref": "GDS_ATOM_OFFSET1"
8016
  },
8017
  {
8018
   "chips": ["gfx9"],
8019
   "map": {"at": 200768, "to": "mm"},
8020
   "name": "GDS_ATOM_DST"
8021
  },
8022
  {
8023
   "chips": ["gfx9"],
8024
   "map": {"at": 200772, "to": "mm"},
8025
   "name": "GDS_ATOM_OP",
8026
   "type_ref": "GDS_ATOM_OP"
8027
  },
8028
  {
8029
   "chips": ["gfx9"],
8030
   "map": {"at": 200776, "to": "mm"},
8031
   "name": "GDS_ATOM_SRC0"
8032
  },
8033
  {
8034
   "chips": ["gfx9"],
8035
   "map": {"at": 200780, "to": "mm"},
8036
   "name": "GDS_ATOM_SRC0_U"
8037
  },
8038
  {
8039
   "chips": ["gfx9"],
8040
   "map": {"at": 200784, "to": "mm"},
8041
   "name": "GDS_ATOM_SRC1"
8042
  },
8043
  {
8044
   "chips": ["gfx9"],
8045
   "map": {"at": 200788, "to": "mm"},
8046
   "name": "GDS_ATOM_SRC1_U"
8047
  },
8048
  {
8049
   "chips": ["gfx9"],
8050
   "map": {"at": 200792, "to": "mm"},
8051
   "name": "GDS_ATOM_READ0"
8052
  },
8053
  {
8054
   "chips": ["gfx9"],
8055
   "map": {"at": 200796, "to": "mm"},
8056
   "name": "GDS_ATOM_READ0_U"
8057
  },
8058
  {
8059
   "chips": ["gfx9"],
8060
   "map": {"at": 200800, "to": "mm"},
8061
   "name": "GDS_ATOM_READ1"
8062
  },
8063
  {
8064
   "chips": ["gfx9"],
8065
   "map": {"at": 200804, "to": "mm"},
8066
   "name": "GDS_ATOM_READ1_U"
8067
  },
8068
  {
8069
   "chips": ["gfx9"],
8070
   "map": {"at": 200808, "to": "mm"},
8071
   "name": "GDS_GWS_RESOURCE_CNTL",
8072
   "type_ref": "GDS_GWS_RESOURCE_CNTL"
8073
  },
8074
  {
8075
   "chips": ["gfx9"],
8076
   "map": {"at": 200812, "to": "mm"},
8077
   "name": "GDS_GWS_RESOURCE",
8078
   "type_ref": "GDS_GWS_RESOURCE"
8079
  },
8080
  {
8081
   "chips": ["gfx9"],
8082
   "map": {"at": 200816, "to": "mm"},
8083
   "name": "GDS_GWS_RESOURCE_CNT",
8084
   "type_ref": "GDS_GWS_RESOURCE_CNT"
8085
  },
8086
  {
8087
   "chips": ["gfx9"],
8088
   "map": {"at": 200820, "to": "mm"},
8089
   "name": "GDS_OA_CNTL",
8090
   "type_ref": "GDS_OA_CNTL"
8091
  },
8092
  {
8093
   "chips": ["gfx9"],
8094
   "map": {"at": 200824, "to": "mm"},
8095
   "name": "GDS_OA_COUNTER"
8096
  },
8097
  {
8098
   "chips": ["gfx9"],
8099
   "map": {"at": 200828, "to": "mm"},
8100
   "name": "GDS_OA_ADDRESS",
8101
   "type_ref": "GDS_OA_ADDRESS"
8102
  },
8103
  {
8104
   "chips": ["gfx9"],
8105
   "map": {"at": 200832, "to": "mm"},
8106
   "name": "GDS_OA_INCDEC",
8107
   "type_ref": "GDS_OA_INCDEC"
8108
  },
8109
  {
8110
   "chips": ["gfx9"],
8111
   "map": {"at": 200836, "to": "mm"},
8112
   "name": "GDS_OA_RING_SIZE"
8113
  },
8114
  {
8115
   "chips": ["gfx9"],
8116
   "map": {"at": 200960, "to": "mm"},
8117
   "name": "SPI_CONFIG_CNTL",
8118
   "type_ref": "SPI_CONFIG_CNTL"
8119
  },
8120
  {
8121
   "chips": ["gfx9"],
8122
   "map": {"at": 200964, "to": "mm"},
8123
   "name": "SPI_CONFIG_CNTL_1",
8124
   "type_ref": "SPI_CONFIG_CNTL_1"
8125
  },
8126
  {
8127
   "chips": ["gfx9"],
8128
   "map": {"at": 200968, "to": "mm"},
8129
   "name": "SPI_CONFIG_CNTL_2",
8130
   "type_ref": "SPI_CONFIG_CNTL_2"
8131
  },
8132
  {
8133
   "chips": ["gfx9"],
8134
   "map": {"at": 200972, "to": "mm"},
8135
   "name": "SPI_WAVE_LIMIT_CNTL",
8136
   "type_ref": "SPI_WAVE_LIMIT_CNTL"
8137
  },
8138
  {
8139
   "chips": ["gfx9"],
8140
   "map": {"at": 212992, "to": "mm"},
8141
   "name": "CPG_PERFCOUNTER1_LO"
8142
  },
8143
  {
8144
   "chips": ["gfx9"],
8145
   "map": {"at": 212996, "to": "mm"},
8146
   "name": "CPG_PERFCOUNTER1_HI"
8147
  },
8148
  {
8149
   "chips": ["gfx9"],
8150
   "map": {"at": 213000, "to": "mm"},
8151
   "name": "CPG_PERFCOUNTER0_LO"
8152
  },
8153
  {
8154
   "chips": ["gfx9"],
8155
   "map": {"at": 213004, "to": "mm"},
8156
   "name": "CPG_PERFCOUNTER0_HI"
8157
  },
8158
  {
8159
   "chips": ["gfx9"],
8160
   "map": {"at": 213008, "to": "mm"},
8161
   "name": "CPC_PERFCOUNTER1_LO"
8162
  },
8163
  {
8164
   "chips": ["gfx9"],
8165
   "map": {"at": 213012, "to": "mm"},
8166
   "name": "CPC_PERFCOUNTER1_HI"
8167
  },
8168
  {
8169
   "chips": ["gfx9"],
8170
   "map": {"at": 213016, "to": "mm"},
8171
   "name": "CPC_PERFCOUNTER0_LO"
8172
  },
8173
  {
8174
   "chips": ["gfx9"],
8175
   "map": {"at": 213020, "to": "mm"},
8176
   "name": "CPC_PERFCOUNTER0_HI"
8177
  },
8178
  {
8179
   "chips": ["gfx9"],
8180
   "map": {"at": 213024, "to": "mm"},
8181
   "name": "CPF_PERFCOUNTER1_LO"
8182
  },
8183
  {
8184
   "chips": ["gfx9"],
8185
   "map": {"at": 213028, "to": "mm"},
8186
   "name": "CPF_PERFCOUNTER1_HI"
8187
  },
8188
  {
8189
   "chips": ["gfx9"],
8190
   "map": {"at": 213032, "to": "mm"},
8191
   "name": "CPF_PERFCOUNTER0_LO"
8192
  },
8193
  {
8194
   "chips": ["gfx9"],
8195
   "map": {"at": 213036, "to": "mm"},
8196
   "name": "CPF_PERFCOUNTER0_HI"
8197
  },
8198
  {
8199
   "chips": ["gfx9"],
8200
   "map": {"at": 213040, "to": "mm"},
8201
   "name": "CPF_LATENCY_STATS_DATA"
8202
  },
8203
  {
8204
   "chips": ["gfx9"],
8205
   "map": {"at": 213044, "to": "mm"},
8206
   "name": "CPG_LATENCY_STATS_DATA"
8207
  },
8208
  {
8209
   "chips": ["gfx9"],
8210
   "map": {"at": 213048, "to": "mm"},
8211
   "name": "CPC_LATENCY_STATS_DATA"
8212
  },
8213
  {
8214
   "chips": ["gfx9"],
8215
   "map": {"at": 213248, "to": "mm"},
8216
   "name": "GRBM_PERFCOUNTER0_LO"
8217
  },
8218
  {
8219
   "chips": ["gfx9"],
8220
   "map": {"at": 213252, "to": "mm"},
8221
   "name": "GRBM_PERFCOUNTER0_HI"
8222
  },
8223
  {
8224
   "chips": ["gfx9"],
8225
   "map": {"at": 213260, "to": "mm"},
8226
   "name": "GRBM_PERFCOUNTER1_LO"
8227
  },
8228
  {
8229
   "chips": ["gfx9"],
8230
   "map": {"at": 213264, "to": "mm"},
8231
   "name": "GRBM_PERFCOUNTER1_HI"
8232
  },
8233
  {
8234
   "chips": ["gfx9"],
8235
   "map": {"at": 213268, "to": "mm"},
8236
   "name": "GRBM_SE0_PERFCOUNTER_LO"
8237
  },
8238
  {
8239
   "chips": ["gfx9"],
8240
   "map": {"at": 213272, "to": "mm"},
8241
   "name": "GRBM_SE0_PERFCOUNTER_HI"
8242
  },
8243
  {
8244
   "chips": ["gfx9"],
8245
   "map": {"at": 213276, "to": "mm"},
8246
   "name": "GRBM_SE1_PERFCOUNTER_LO"
8247
  },
8248
  {
8249
   "chips": ["gfx9"],
8250
   "map": {"at": 213280, "to": "mm"},
8251
   "name": "GRBM_SE1_PERFCOUNTER_HI"
8252
  },
8253
  {
8254
   "chips": ["gfx9"],
8255
   "map": {"at": 213284, "to": "mm"},
8256
   "name": "GRBM_SE2_PERFCOUNTER_LO"
8257
  },
8258
  {
8259
   "chips": ["gfx9"],
8260
   "map": {"at": 213288, "to": "mm"},
8261
   "name": "GRBM_SE2_PERFCOUNTER_HI"
8262
  },
8263
  {
8264
   "chips": ["gfx9"],
8265
   "map": {"at": 213292, "to": "mm"},
8266
   "name": "GRBM_SE3_PERFCOUNTER_LO"
8267
  },
8268
  {
8269
   "chips": ["gfx9"],
8270
   "map": {"at": 213296, "to": "mm"},
8271
   "name": "GRBM_SE3_PERFCOUNTER_HI"
8272
  },
8273
  {
8274
   "chips": ["gfx9"],
8275
   "map": {"at": 213504, "to": "mm"},
8276
   "name": "WD_PERFCOUNTER0_LO"
8277
  },
8278
  {
8279
   "chips": ["gfx9"],
8280
   "map": {"at": 213508, "to": "mm"},
8281
   "name": "WD_PERFCOUNTER0_HI"
8282
  },
8283
  {
8284
   "chips": ["gfx9"],
8285
   "map": {"at": 213512, "to": "mm"},
8286
   "name": "WD_PERFCOUNTER1_LO"
8287
  },
8288
  {
8289
   "chips": ["gfx9"],
8290
   "map": {"at": 213516, "to": "mm"},
8291
   "name": "WD_PERFCOUNTER1_HI"
8292
  },
8293
  {
8294
   "chips": ["gfx9"],
8295
   "map": {"at": 213520, "to": "mm"},
8296
   "name": "WD_PERFCOUNTER2_LO"
8297
  },
8298
  {
8299
   "chips": ["gfx9"],
8300
   "map": {"at": 213524, "to": "mm"},
8301
   "name": "WD_PERFCOUNTER2_HI"
8302
  },
8303
  {
8304
   "chips": ["gfx9"],
8305
   "map": {"at": 213528, "to": "mm"},
8306
   "name": "WD_PERFCOUNTER3_LO"
8307
  },
8308
  {
8309
   "chips": ["gfx9"],
8310
   "map": {"at": 213532, "to": "mm"},
8311
   "name": "WD_PERFCOUNTER3_HI"
8312
  },
8313
  {
8314
   "chips": ["gfx9"],
8315
   "map": {"at": 213536, "to": "mm"},
8316
   "name": "IA_PERFCOUNTER0_LO"
8317
  },
8318
  {
8319
   "chips": ["gfx9"],
8320
   "map": {"at": 213540, "to": "mm"},
8321
   "name": "IA_PERFCOUNTER0_HI"
8322
  },
8323
  {
8324
   "chips": ["gfx9"],
8325
   "map": {"at": 213544, "to": "mm"},
8326
   "name": "IA_PERFCOUNTER1_LO"
8327
  },
8328
  {
8329
   "chips": ["gfx9"],
8330
   "map": {"at": 213548, "to": "mm"},
8331
   "name": "IA_PERFCOUNTER1_HI"
8332
  },
8333
  {
8334
   "chips": ["gfx9"],
8335
   "map": {"at": 213552, "to": "mm"},
8336
   "name": "IA_PERFCOUNTER2_LO"
8337
  },
8338
  {
8339
   "chips": ["gfx9"],
8340
   "map": {"at": 213556, "to": "mm"},
8341
   "name": "IA_PERFCOUNTER2_HI"
8342
  },
8343
  {
8344
   "chips": ["gfx9"],
8345
   "map": {"at": 213560, "to": "mm"},
8346
   "name": "IA_PERFCOUNTER3_LO"
8347
  },
8348
  {
8349
   "chips": ["gfx9"],
8350
   "map": {"at": 213564, "to": "mm"},
8351
   "name": "IA_PERFCOUNTER3_HI"
8352
  },
8353
  {
8354
   "chips": ["gfx9"],
8355
   "map": {"at": 213568, "to": "mm"},
8356
   "name": "VGT_PERFCOUNTER0_LO"
8357
  },
8358
  {
8359
   "chips": ["gfx9"],
8360
   "map": {"at": 213572, "to": "mm"},
8361
   "name": "VGT_PERFCOUNTER0_HI"
8362
  },
8363
  {
8364
   "chips": ["gfx9"],
8365
   "map": {"at": 213576, "to": "mm"},
8366
   "name": "VGT_PERFCOUNTER1_LO"
8367
  },
8368
  {
8369
   "chips": ["gfx9"],
8370
   "map": {"at": 213580, "to": "mm"},
8371
   "name": "VGT_PERFCOUNTER1_HI"
8372
  },
8373
  {
8374
   "chips": ["gfx9"],
8375
   "map": {"at": 213584, "to": "mm"},
8376
   "name": "VGT_PERFCOUNTER2_LO"
8377
  },
8378
  {
8379
   "chips": ["gfx9"],
8380
   "map": {"at": 213588, "to": "mm"},
8381
   "name": "VGT_PERFCOUNTER2_HI"
8382
  },
8383
  {
8384
   "chips": ["gfx9"],
8385
   "map": {"at": 213592, "to": "mm"},
8386
   "name": "VGT_PERFCOUNTER3_LO"
8387
  },
8388
  {
8389
   "chips": ["gfx9"],
8390
   "map": {"at": 213596, "to": "mm"},
8391
   "name": "VGT_PERFCOUNTER3_HI"
8392
  },
8393
  {
8394
   "chips": ["gfx9"],
8395
   "map": {"at": 214016, "to": "mm"},
8396
   "name": "PA_SU_PERFCOUNTER0_LO"
8397
  },
8398
  {
8399
   "chips": ["gfx9"],
8400
   "map": {"at": 214020, "to": "mm"},
8401
   "name": "PA_SU_PERFCOUNTER0_HI",
8402
   "type_ref": "PA_SU_PERFCOUNTER0_HI"
8403
  },
8404
  {
8405
   "chips": ["gfx9"],
8406
   "map": {"at": 214024, "to": "mm"},
8407
   "name": "PA_SU_PERFCOUNTER1_LO"
8408
  },
8409
  {
8410
   "chips": ["gfx9"],
8411
   "map": {"at": 214028, "to": "mm"},
8412
   "name": "PA_SU_PERFCOUNTER1_HI",
8413
   "type_ref": "PA_SU_PERFCOUNTER0_HI"
8414
  },
8415
  {
8416
   "chips": ["gfx9"],
8417
   "map": {"at": 214032, "to": "mm"},
8418
   "name": "PA_SU_PERFCOUNTER2_LO"
8419
  },
8420
  {
8421
   "chips": ["gfx9"],
8422
   "map": {"at": 214036, "to": "mm"},
8423
   "name": "PA_SU_PERFCOUNTER2_HI",
8424
   "type_ref": "PA_SU_PERFCOUNTER0_HI"
8425
  },
8426
  {
8427
   "chips": ["gfx9"],
8428
   "map": {"at": 214040, "to": "mm"},
8429
   "name": "PA_SU_PERFCOUNTER3_LO"
8430
  },
8431
  {
8432
   "chips": ["gfx9"],
8433
   "map": {"at": 214044, "to": "mm"},
8434
   "name": "PA_SU_PERFCOUNTER3_HI",
8435
   "type_ref": "PA_SU_PERFCOUNTER0_HI"
8436
  },
8437
  {
8438
   "chips": ["gfx9"],
8439
   "map": {"at": 214272, "to": "mm"},
8440
   "name": "PA_SC_PERFCOUNTER0_LO"
8441
  },
8442
  {
8443
   "chips": ["gfx9"],
8444
   "map": {"at": 214276, "to": "mm"},
8445
   "name": "PA_SC_PERFCOUNTER0_HI"
8446
  },
8447
  {
8448
   "chips": ["gfx9"],
8449
   "map": {"at": 214280, "to": "mm"},
8450
   "name": "PA_SC_PERFCOUNTER1_LO"
8451
  },
8452
  {
8453
   "chips": ["gfx9"],
8454
   "map": {"at": 214284, "to": "mm"},
8455
   "name": "PA_SC_PERFCOUNTER1_HI"
8456
  },
8457
  {
8458
   "chips": ["gfx9"],
8459
   "map": {"at": 214288, "to": "mm"},
8460
   "name": "PA_SC_PERFCOUNTER2_LO"
8461
  },
8462
  {
8463
   "chips": ["gfx9"],
8464
   "map": {"at": 214292, "to": "mm"},
8465
   "name": "PA_SC_PERFCOUNTER2_HI"
8466
  },
8467
  {
8468
   "chips": ["gfx9"],
8469
   "map": {"at": 214296, "to": "mm"},
8470
   "name": "PA_SC_PERFCOUNTER3_LO"
8471
  },
8472
  {
8473
   "chips": ["gfx9"],
8474
   "map": {"at": 214300, "to": "mm"},
8475
   "name": "PA_SC_PERFCOUNTER3_HI"
8476
  },
8477
  {
8478
   "chips": ["gfx9"],
8479
   "map": {"at": 214304, "to": "mm"},
8480
   "name": "PA_SC_PERFCOUNTER4_LO"
8481
  },
8482
  {
8483
   "chips": ["gfx9"],
8484
   "map": {"at": 214308, "to": "mm"},
8485
   "name": "PA_SC_PERFCOUNTER4_HI"
8486
  },
8487
  {
8488
   "chips": ["gfx9"],
8489
   "map": {"at": 214312, "to": "mm"},
8490
   "name": "PA_SC_PERFCOUNTER5_LO"
8491
  },
8492
  {
8493
   "chips": ["gfx9"],
8494
   "map": {"at": 214316, "to": "mm"},
8495
   "name": "PA_SC_PERFCOUNTER5_HI"
8496
  },
8497
  {
8498
   "chips": ["gfx9"],
8499
   "map": {"at": 214320, "to": "mm"},
8500
   "name": "PA_SC_PERFCOUNTER6_LO"
8501
  },
8502
  {
8503
   "chips": ["gfx9"],
8504
   "map": {"at": 214324, "to": "mm"},
8505
   "name": "PA_SC_PERFCOUNTER6_HI"
8506
  },
8507
  {
8508
   "chips": ["gfx9"],
8509
   "map": {"at": 214328, "to": "mm"},
8510
   "name": "PA_SC_PERFCOUNTER7_LO"
8511
  },
8512
  {
8513
   "chips": ["gfx9"],
8514
   "map": {"at": 214332, "to": "mm"},
8515
   "name": "PA_SC_PERFCOUNTER7_HI"
8516
  },
8517
  {
8518
   "chips": ["gfx9"],
8519
   "map": {"at": 214528, "to": "mm"},
8520
   "name": "SPI_PERFCOUNTER0_HI"
8521
  },
8522
  {
8523
   "chips": ["gfx9"],
8524
   "map": {"at": 214532, "to": "mm"},
8525
   "name": "SPI_PERFCOUNTER0_LO"
8526
  },
8527
  {
8528
   "chips": ["gfx9"],
8529
   "map": {"at": 214536, "to": "mm"},
8530
   "name": "SPI_PERFCOUNTER1_HI"
8531
  },
8532
  {
8533
   "chips": ["gfx9"],
8534
   "map": {"at": 214540, "to": "mm"},
8535
   "name": "SPI_PERFCOUNTER1_LO"
8536
  },
8537
  {
8538
   "chips": ["gfx9"],
8539
   "map": {"at": 214544, "to": "mm"},
8540
   "name": "SPI_PERFCOUNTER2_HI"
8541
  },
8542
  {
8543
   "chips": ["gfx9"],
8544
   "map": {"at": 214548, "to": "mm"},
8545
   "name": "SPI_PERFCOUNTER2_LO"
8546
  },
8547
  {
8548
   "chips": ["gfx9"],
8549
   "map": {"at": 214552, "to": "mm"},
8550
   "name": "SPI_PERFCOUNTER3_HI"
8551
  },
8552
  {
8553
   "chips": ["gfx9"],
8554
   "map": {"at": 214556, "to": "mm"},
8555
   "name": "SPI_PERFCOUNTER3_LO"
8556
  },
8557
  {
8558
   "chips": ["gfx9"],
8559
   "map": {"at": 214560, "to": "mm"},
8560
   "name": "SPI_PERFCOUNTER4_HI"
8561
  },
8562
  {
8563
   "chips": ["gfx9"],
8564
   "map": {"at": 214564, "to": "mm"},
8565
   "name": "SPI_PERFCOUNTER4_LO"
8566
  },
8567
  {
8568
   "chips": ["gfx9"],
8569
   "map": {"at": 214568, "to": "mm"},
8570
   "name": "SPI_PERFCOUNTER5_HI"
8571
  },
8572
  {
8573
   "chips": ["gfx9"],
8574
   "map": {"at": 214572, "to": "mm"},
8575
   "name": "SPI_PERFCOUNTER5_LO"
8576
  },
8577
  {
8578
   "chips": ["gfx9"],
8579
   "map": {"at": 214784, "to": "mm"},
8580
   "name": "SQ_PERFCOUNTER0_LO"
8581
  },
8582
  {
8583
   "chips": ["gfx9"],
8584
   "map": {"at": 214788, "to": "mm"},
8585
   "name": "SQ_PERFCOUNTER0_HI"
8586
  },
8587
  {
8588
   "chips": ["gfx9"],
8589
   "map": {"at": 214792, "to": "mm"},
8590
   "name": "SQ_PERFCOUNTER1_LO"
8591
  },
8592
  {
8593
   "chips": ["gfx9"],
8594
   "map": {"at": 214796, "to": "mm"},
8595
   "name": "SQ_PERFCOUNTER1_HI"
8596
  },
8597
  {
8598
   "chips": ["gfx9"],
8599
   "map": {"at": 214800, "to": "mm"},
8600
   "name": "SQ_PERFCOUNTER2_LO"
8601
  },
8602
  {
8603
   "chips": ["gfx9"],
8604
   "map": {"at": 214804, "to": "mm"},
8605
   "name": "SQ_PERFCOUNTER2_HI"
8606
  },
8607
  {
8608
   "chips": ["gfx9"],
8609
   "map": {"at": 214808, "to": "mm"},
8610
   "name": "SQ_PERFCOUNTER3_LO"
8611
  },
8612
  {
8613
   "chips": ["gfx9"],
8614
   "map": {"at": 214812, "to": "mm"},
8615
   "name": "SQ_PERFCOUNTER3_HI"
8616
  },
8617
  {
8618
   "chips": ["gfx9"],
8619
   "map": {"at": 214816, "to": "mm"},
8620
   "name": "SQ_PERFCOUNTER4_LO"
8621
  },
8622
  {
8623
   "chips": ["gfx9"],
8624
   "map": {"at": 214820, "to": "mm"},
8625
   "name": "SQ_PERFCOUNTER4_HI"
8626
  },
8627
  {
8628
   "chips": ["gfx9"],
8629
   "map": {"at": 214824, "to": "mm"},
8630
   "name": "SQ_PERFCOUNTER5_LO"
8631
  },
8632
  {
8633
   "chips": ["gfx9"],
8634
   "map": {"at": 214828, "to": "mm"},
8635
   "name": "SQ_PERFCOUNTER5_HI"
8636
  },
8637
  {
8638
   "chips": ["gfx9"],
8639
   "map": {"at": 214832, "to": "mm"},
8640
   "name": "SQ_PERFCOUNTER6_LO"
8641
  },
8642
  {
8643
   "chips": ["gfx9"],
8644
   "map": {"at": 214836, "to": "mm"},
8645
   "name": "SQ_PERFCOUNTER6_HI"
8646
  },
8647
  {
8648
   "chips": ["gfx9"],
8649
   "map": {"at": 214840, "to": "mm"},
8650
   "name": "SQ_PERFCOUNTER7_LO"
8651
  },
8652
  {
8653
   "chips": ["gfx9"],
8654
   "map": {"at": 214844, "to": "mm"},
8655
   "name": "SQ_PERFCOUNTER7_HI"
8656
  },
8657
  {
8658
   "chips": ["gfx9"],
8659
   "map": {"at": 214848, "to": "mm"},
8660
   "name": "SQ_PERFCOUNTER8_LO"
8661
  },
8662
  {
8663
   "chips": ["gfx9"],
8664
   "map": {"at": 214852, "to": "mm"},
8665
   "name": "SQ_PERFCOUNTER8_HI"
8666
  },
8667
  {
8668
   "chips": ["gfx9"],
8669
   "map": {"at": 214856, "to": "mm"},
8670
   "name": "SQ_PERFCOUNTER9_LO"
8671
  },
8672
  {
8673
   "chips": ["gfx9"],
8674
   "map": {"at": 214860, "to": "mm"},
8675
   "name": "SQ_PERFCOUNTER9_HI"
8676
  },
8677
  {
8678
   "chips": ["gfx9"],
8679
   "map": {"at": 214864, "to": "mm"},
8680
   "name": "SQ_PERFCOUNTER10_LO"
8681
  },
8682
  {
8683
   "chips": ["gfx9"],
8684
   "map": {"at": 214868, "to": "mm"},
8685
   "name": "SQ_PERFCOUNTER10_HI"
8686
  },
8687
  {
8688
   "chips": ["gfx9"],
8689
   "map": {"at": 214872, "to": "mm"},
8690
   "name": "SQ_PERFCOUNTER11_LO"
8691
  },
8692
  {
8693
   "chips": ["gfx9"],
8694
   "map": {"at": 214876, "to": "mm"},
8695
   "name": "SQ_PERFCOUNTER11_HI"
8696
  },
8697
  {
8698
   "chips": ["gfx9"],
8699
   "map": {"at": 214880, "to": "mm"},
8700
   "name": "SQ_PERFCOUNTER12_LO"
8701
  },
8702
  {
8703
   "chips": ["gfx9"],
8704
   "map": {"at": 214884, "to": "mm"},
8705
   "name": "SQ_PERFCOUNTER12_HI"
8706
  },
8707
  {
8708
   "chips": ["gfx9"],
8709
   "map": {"at": 214888, "to": "mm"},
8710
   "name": "SQ_PERFCOUNTER13_LO"
8711
  },
8712
  {
8713
   "chips": ["gfx9"],
8714
   "map": {"at": 214892, "to": "mm"},
8715
   "name": "SQ_PERFCOUNTER13_HI"
8716
  },
8717
  {
8718
   "chips": ["gfx9"],
8719
   "map": {"at": 214896, "to": "mm"},
8720
   "name": "SQ_PERFCOUNTER14_LO"
8721
  },
8722
  {
8723
   "chips": ["gfx9"],
8724
   "map": {"at": 214900, "to": "mm"},
8725
   "name": "SQ_PERFCOUNTER14_HI"
8726
  },
8727
  {
8728
   "chips": ["gfx9"],
8729
   "map": {"at": 214904, "to": "mm"},
8730
   "name": "SQ_PERFCOUNTER15_LO"
8731
  },
8732
  {
8733
   "chips": ["gfx9"],
8734
   "map": {"at": 214908, "to": "mm"},
8735
   "name": "SQ_PERFCOUNTER15_HI"
8736
  },
8737
  {
8738
   "chips": ["gfx9"],
8739
   "map": {"at": 215296, "to": "mm"},
8740
   "name": "SX_PERFCOUNTER0_LO"
8741
  },
8742
  {
8743
   "chips": ["gfx9"],
8744
   "map": {"at": 215300, "to": "mm"},
8745
   "name": "SX_PERFCOUNTER0_HI"
8746
  },
8747
  {
8748
   "chips": ["gfx9"],
8749
   "map": {"at": 215304, "to": "mm"},
8750
   "name": "SX_PERFCOUNTER1_LO"
8751
  },
8752
  {
8753
   "chips": ["gfx9"],
8754
   "map": {"at": 215308, "to": "mm"},
8755
   "name": "SX_PERFCOUNTER1_HI"
8756
  },
8757
  {
8758
   "chips": ["gfx9"],
8759
   "map": {"at": 215312, "to": "mm"},
8760
   "name": "SX_PERFCOUNTER2_LO"
8761
  },
8762
  {
8763
   "chips": ["gfx9"],
8764
   "map": {"at": 215316, "to": "mm"},
8765
   "name": "SX_PERFCOUNTER2_HI"
8766
  },
8767
  {
8768
   "chips": ["gfx9"],
8769
   "map": {"at": 215320, "to": "mm"},
8770
   "name": "SX_PERFCOUNTER3_LO"
8771
  },
8772
  {
8773
   "chips": ["gfx9"],
8774
   "map": {"at": 215324, "to": "mm"},
8775
   "name": "SX_PERFCOUNTER3_HI"
8776
  },
8777
  {
8778
   "chips": ["gfx9"],
8779
   "map": {"at": 215552, "to": "mm"},
8780
   "name": "GDS_PERFCOUNTER0_LO"
8781
  },
8782
  {
8783
   "chips": ["gfx9"],
8784
   "map": {"at": 215556, "to": "mm"},
8785
   "name": "GDS_PERFCOUNTER0_HI"
8786
  },
8787
  {
8788
   "chips": ["gfx9"],
8789
   "map": {"at": 215560, "to": "mm"},
8790
   "name": "GDS_PERFCOUNTER1_LO"
8791
  },
8792
  {
8793
   "chips": ["gfx9"],
8794
   "map": {"at": 215564, "to": "mm"},
8795
   "name": "GDS_PERFCOUNTER1_HI"
8796
  },
8797
  {
8798
   "chips": ["gfx9"],
8799
   "map": {"at": 215568, "to": "mm"},
8800
   "name": "GDS_PERFCOUNTER2_LO"
8801
  },
8802
  {
8803
   "chips": ["gfx9"],
8804
   "map": {"at": 215572, "to": "mm"},
8805
   "name": "GDS_PERFCOUNTER2_HI"
8806
  },
8807
  {
8808
   "chips": ["gfx9"],
8809
   "map": {"at": 215576, "to": "mm"},
8810
   "name": "GDS_PERFCOUNTER3_LO"
8811
  },
8812
  {
8813
   "chips": ["gfx9"],
8814
   "map": {"at": 215580, "to": "mm"},
8815
   "name": "GDS_PERFCOUNTER3_HI"
8816
  },
8817
  {
8818
   "chips": ["gfx9"],
8819
   "map": {"at": 215808, "to": "mm"},
8820
   "name": "TA_PERFCOUNTER0_LO"
8821
  },
8822
  {
8823
   "chips": ["gfx9"],
8824
   "map": {"at": 215812, "to": "mm"},
8825
   "name": "TA_PERFCOUNTER0_HI"
8826
  },
8827
  {
8828
   "chips": ["gfx9"],
8829
   "map": {"at": 215816, "to": "mm"},
8830
   "name": "TA_PERFCOUNTER1_LO"
8831
  },
8832
  {
8833
   "chips": ["gfx9"],
8834
   "map": {"at": 215820, "to": "mm"},
8835
   "name": "TA_PERFCOUNTER1_HI"
8836
  },
8837
  {
8838
   "chips": ["gfx9"],
8839
   "map": {"at": 216064, "to": "mm"},
8840
   "name": "TD_PERFCOUNTER0_LO"
8841
  },
8842
  {
8843
   "chips": ["gfx9"],
8844
   "map": {"at": 216068, "to": "mm"},
8845
   "name": "TD_PERFCOUNTER0_HI"
8846
  },
8847
  {
8848
   "chips": ["gfx9"],
8849
   "map": {"at": 216072, "to": "mm"},
8850
   "name": "TD_PERFCOUNTER1_LO"
8851
  },
8852
  {
8853
   "chips": ["gfx9"],
8854
   "map": {"at": 216076, "to": "mm"},
8855
   "name": "TD_PERFCOUNTER1_HI"
8856
  },
8857
  {
8858
   "chips": ["gfx9"],
8859
   "map": {"at": 216320, "to": "mm"},
8860
   "name": "TCP_PERFCOUNTER0_LO"
8861
  },
8862
  {
8863
   "chips": ["gfx9"],
8864
   "map": {"at": 216324, "to": "mm"},
8865
   "name": "TCP_PERFCOUNTER0_HI"
8866
  },
8867
  {
8868
   "chips": ["gfx9"],
8869
   "map": {"at": 216328, "to": "mm"},
8870
   "name": "TCP_PERFCOUNTER1_LO"
8871
  },
8872
  {
8873
   "chips": ["gfx9"],
8874
   "map": {"at": 216332, "to": "mm"},
8875
   "name": "TCP_PERFCOUNTER1_HI"
8876
  },
8877
  {
8878
   "chips": ["gfx9"],
8879
   "map": {"at": 216336, "to": "mm"},
8880
   "name": "TCP_PERFCOUNTER2_LO"
8881
  },
8882
  {
8883
   "chips": ["gfx9"],
8884
   "map": {"at": 216340, "to": "mm"},
8885
   "name": "TCP_PERFCOUNTER2_HI"
8886
  },
8887
  {
8888
   "chips": ["gfx9"],
8889
   "map": {"at": 216344, "to": "mm"},
8890
   "name": "TCP_PERFCOUNTER3_LO"
8891
  },
8892
  {
8893
   "chips": ["gfx9"],
8894
   "map": {"at": 216348, "to": "mm"},
8895
   "name": "TCP_PERFCOUNTER3_HI"
8896
  },
8897
  {
8898
   "chips": ["gfx9"],
8899
   "map": {"at": 216576, "to": "mm"},
8900
   "name": "TCC_PERFCOUNTER0_LO"
8901
  },
8902
  {
8903
   "chips": ["gfx9"],
8904
   "map": {"at": 216580, "to": "mm"},
8905
   "name": "TCC_PERFCOUNTER0_HI"
8906
  },
8907
  {
8908
   "chips": ["gfx9"],
8909
   "map": {"at": 216584, "to": "mm"},
8910
   "name": "TCC_PERFCOUNTER1_LO"
8911
  },
8912
  {
8913
   "chips": ["gfx9"],
8914
   "map": {"at": 216588, "to": "mm"},
8915
   "name": "TCC_PERFCOUNTER1_HI"
8916
  },
8917
  {
8918
   "chips": ["gfx9"],
8919
   "map": {"at": 216592, "to": "mm"},
8920
   "name": "TCC_PERFCOUNTER2_LO"
8921
  },
8922
  {
8923
   "chips": ["gfx9"],
8924
   "map": {"at": 216596, "to": "mm"},
8925
   "name": "TCC_PERFCOUNTER2_HI"
8926
  },
8927
  {
8928
   "chips": ["gfx9"],
8929
   "map": {"at": 216600, "to": "mm"},
8930
   "name": "TCC_PERFCOUNTER3_LO"
8931
  },
8932
  {
8933
   "chips": ["gfx9"],
8934
   "map": {"at": 216604, "to": "mm"},
8935
   "name": "TCC_PERFCOUNTER3_HI"
8936
  },
8937
  {
8938
   "chips": ["gfx9"],
8939
   "map": {"at": 216640, "to": "mm"},
8940
   "name": "TCA_PERFCOUNTER0_LO"
8941
  },
8942
  {
8943
   "chips": ["gfx9"],
8944
   "map": {"at": 216644, "to": "mm"},
8945
   "name": "TCA_PERFCOUNTER0_HI"
8946
  },
8947
  {
8948
   "chips": ["gfx9"],
8949
   "map": {"at": 216648, "to": "mm"},
8950
   "name": "TCA_PERFCOUNTER1_LO"
8951
  },
8952
  {
8953
   "chips": ["gfx9"],
8954
   "map": {"at": 216652, "to": "mm"},
8955
   "name": "TCA_PERFCOUNTER1_HI"
8956
  },
8957
  {
8958
   "chips": ["gfx9"],
8959
   "map": {"at": 216656, "to": "mm"},
8960
   "name": "TCA_PERFCOUNTER2_LO"
8961
  },
8962
  {
8963
   "chips": ["gfx9"],
8964
   "map": {"at": 216660, "to": "mm"},
8965
   "name": "TCA_PERFCOUNTER2_HI"
8966
  },
8967
  {
8968
   "chips": ["gfx9"],
8969
   "map": {"at": 216664, "to": "mm"},
8970
   "name": "TCA_PERFCOUNTER3_LO"
8971
  },
8972
  {
8973
   "chips": ["gfx9"],
8974
   "map": {"at": 216668, "to": "mm"},
8975
   "name": "TCA_PERFCOUNTER3_HI"
8976
  },
8977
  {
8978
   "chips": ["gfx9"],
8979
   "map": {"at": 217112, "to": "mm"},
8980
   "name": "CB_PERFCOUNTER0_LO"
8981
  },
8982
  {
8983
   "chips": ["gfx9"],
8984
   "map": {"at": 217116, "to": "mm"},
8985
   "name": "CB_PERFCOUNTER0_HI"
8986
  },
8987
  {
8988
   "chips": ["gfx9"],
8989
   "map": {"at": 217120, "to": "mm"},
8990
   "name": "CB_PERFCOUNTER1_LO"
8991
  },
8992
  {
8993
   "chips": ["gfx9"],
8994
   "map": {"at": 217124, "to": "mm"},
8995
   "name": "CB_PERFCOUNTER1_HI"
8996
  },
8997
  {
8998
   "chips": ["gfx9"],
8999
   "map": {"at": 217128, "to": "mm"},
9000
   "name": "CB_PERFCOUNTER2_LO"
9001
  },
9002
  {
9003
   "chips": ["gfx9"],
9004
   "map": {"at": 217132, "to": "mm"},
9005
   "name": "CB_PERFCOUNTER2_HI"
9006
  },
9007
  {
9008
   "chips": ["gfx9"],
9009
   "map": {"at": 217136, "to": "mm"},
9010
   "name": "CB_PERFCOUNTER3_LO"
9011
  },
9012
  {
9013
   "chips": ["gfx9"],
9014
   "map": {"at": 217140, "to": "mm"},
9015
   "name": "CB_PERFCOUNTER3_HI"
9016
  },
9017
  {
9018
   "chips": ["gfx9"],
9019
   "map": {"at": 217344, "to": "mm"},
9020
   "name": "DB_PERFCOUNTER0_LO"
9021
  },
9022
  {
9023
   "chips": ["gfx9"],
9024
   "map": {"at": 217348, "to": "mm"},
9025
   "name": "DB_PERFCOUNTER0_HI"
9026
  },
9027
  {
9028
   "chips": ["gfx9"],
9029
   "map": {"at": 217352, "to": "mm"},
9030
   "name": "DB_PERFCOUNTER1_LO"
9031
  },
9032
  {
9033
   "chips": ["gfx9"],
9034
   "map": {"at": 217356, "to": "mm"},
9035
   "name": "DB_PERFCOUNTER1_HI"
9036
  },
9037
  {
9038
   "chips": ["gfx9"],
9039
   "map": {"at": 217360, "to": "mm"},
9040
   "name": "DB_PERFCOUNTER2_LO"
9041
  },
9042
  {
9043
   "chips": ["gfx9"],
9044
   "map": {"at": 217364, "to": "mm"},
9045
   "name": "DB_PERFCOUNTER2_HI"
9046
  },
9047
  {
9048
   "chips": ["gfx9"],
9049
   "map": {"at": 217368, "to": "mm"},
9050
   "name": "DB_PERFCOUNTER3_LO"
9051
  },
9052
  {
9053
   "chips": ["gfx9"],
9054
   "map": {"at": 217372, "to": "mm"},
9055
   "name": "DB_PERFCOUNTER3_HI"
9056
  },
9057
  {
9058
   "chips": ["gfx9"],
9059
   "map": {"at": 217600, "to": "mm"},
9060
   "name": "RLC_PERFCOUNTER0_LO"
9061
  },
9062
  {
9063
   "chips": ["gfx9"],
9064
   "map": {"at": 217604, "to": "mm"},
9065
   "name": "RLC_PERFCOUNTER0_HI"
9066
  },
9067
  {
9068
   "chips": ["gfx9"],
9069
   "map": {"at": 217608, "to": "mm"},
9070
   "name": "RLC_PERFCOUNTER1_LO"
9071
  },
9072
  {
9073
   "chips": ["gfx9"],
9074
   "map": {"at": 217612, "to": "mm"},
9075
   "name": "RLC_PERFCOUNTER1_HI"
9076
  },
9077
  {
9078
   "chips": ["gfx9"],
9079
   "map": {"at": 217856, "to": "mm"},
9080
   "name": "RMI_PERFCOUNTER0_LO"
9081
  },
9082
  {
9083
   "chips": ["gfx9"],
9084
   "map": {"at": 217860, "to": "mm"},
9085
   "name": "RMI_PERFCOUNTER0_HI"
9086
  },
9087
  {
9088
   "chips": ["gfx9"],
9089
   "map": {"at": 217864, "to": "mm"},
9090
   "name": "RMI_PERFCOUNTER1_LO"
9091
  },
9092
  {
9093
   "chips": ["gfx9"],
9094
   "map": {"at": 217868, "to": "mm"},
9095
   "name": "RMI_PERFCOUNTER1_HI"
9096
  },
9097
  {
9098
   "chips": ["gfx9"],
9099
   "map": {"at": 217872, "to": "mm"},
9100
   "name": "RMI_PERFCOUNTER2_LO"
9101
  },
9102
  {
9103
   "chips": ["gfx9"],
9104
   "map": {"at": 217876, "to": "mm"},
9105
   "name": "RMI_PERFCOUNTER2_HI"
9106
  },
9107
  {
9108
   "chips": ["gfx9"],
9109
   "map": {"at": 217880, "to": "mm"},
9110
   "name": "RMI_PERFCOUNTER3_LO"
9111
  },
9112
  {
9113
   "chips": ["gfx9"],
9114
   "map": {"at": 217884, "to": "mm"},
9115
   "name": "RMI_PERFCOUNTER3_HI"
9116
  },
9117
  {
9118
   "chips": ["gfx9"],
9119
   "map": {"at": 218112, "to": "mm"},
9120
   "name": "ATC_L2_PERFCOUNTER_LO"
9121
  },
9122
  {
9123
   "chips": ["gfx9"],
9124
   "map": {"at": 218116, "to": "mm"},
9125
   "name": "ATC_L2_PERFCOUNTER_HI",
9126
   "type_ref": "ATC_L2_PERFCOUNTER_HI"
9127
  },
9128
  {
9129
   "chips": ["gfx9"],
9130
   "map": {"at": 218144, "to": "mm"},
9131
   "name": "MC_VM_L2_PERFCOUNTER_LO"
9132
  },
9133
  {
9134
   "chips": ["gfx9"],
9135
   "map": {"at": 218148, "to": "mm"},
9136
   "name": "MC_VM_L2_PERFCOUNTER_HI",
9137
   "type_ref": "ATC_L2_PERFCOUNTER_HI"
9138
  },
9139
  {
9140
   "chips": ["gfx9"],
9141
   "map": {"at": 221184, "to": "mm"},
9142
   "name": "CPG_PERFCOUNTER1_SELECT",
9143
   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9144
  },
9145
  {
9146
   "chips": ["gfx9"],
9147
   "map": {"at": 221188, "to": "mm"},
9148
   "name": "CPG_PERFCOUNTER0_SELECT1",
9149
   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
9150
  },
9151
  {
9152
   "chips": ["gfx9"],
9153
   "map": {"at": 221192, "to": "mm"},
9154
   "name": "CPG_PERFCOUNTER0_SELECT",
9155
   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9156
  },
9157
  {
9158
   "chips": ["gfx9"],
9159
   "map": {"at": 221196, "to": "mm"},
9160
   "name": "CPC_PERFCOUNTER1_SELECT",
9161
   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9162
  },
9163
  {
9164
   "chips": ["gfx9"],
9165
   "map": {"at": 221200, "to": "mm"},
9166
   "name": "CPC_PERFCOUNTER0_SELECT1",
9167
   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
9168
  },
9169
  {
9170
   "chips": ["gfx9"],
9171
   "map": {"at": 221204, "to": "mm"},
9172
   "name": "CPF_PERFCOUNTER1_SELECT",
9173
   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9174
  },
9175
  {
9176
   "chips": ["gfx9"],
9177
   "map": {"at": 221208, "to": "mm"},
9178
   "name": "CPF_PERFCOUNTER0_SELECT1",
9179
   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
9180
  },
9181
  {
9182
   "chips": ["gfx9"],
9183
   "map": {"at": 221212, "to": "mm"},
9184
   "name": "CPF_PERFCOUNTER0_SELECT",
9185
   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9186
  },
9187
  {
9188
   "chips": ["gfx9"],
9189
   "map": {"at": 221216, "to": "mm"},
9190
   "name": "CP_PERFMON_CNTL",
9191
   "type_ref": "CP_PERFMON_CNTL"
9192
  },
9193
  {
9194
   "chips": ["gfx9"],
9195
   "map": {"at": 221220, "to": "mm"},
9196
   "name": "CPC_PERFCOUNTER0_SELECT",
9197
   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9198
  },
9199
  {
9200
   "chips": ["gfx9"],
9201
   "map": {"at": 221224, "to": "mm"},
9202
   "name": "CPF_TC_PERF_COUNTER_WINDOW_SELECT",
9203
   "type_ref": "CPF_TC_PERF_COUNTER_WINDOW_SELECT"
9204
  },
9205
  {
9206
   "chips": ["gfx9"],
9207
   "map": {"at": 221228, "to": "mm"},
9208
   "name": "CPG_TC_PERF_COUNTER_WINDOW_SELECT",
9209
   "type_ref": "CPG_TC_PERF_COUNTER_WINDOW_SELECT"
9210
  },
9211
  {
9212
   "chips": ["gfx9"],
9213
   "map": {"at": 221232, "to": "mm"},
9214
   "name": "CPF_LATENCY_STATS_SELECT",
9215
   "type_ref": "CPF_LATENCY_STATS_SELECT"
9216
  },
9217
  {
9218
   "chips": ["gfx9"],
9219
   "map": {"at": 221236, "to": "mm"},
9220
   "name": "CPG_LATENCY_STATS_SELECT",
9221
   "type_ref": "CPG_LATENCY_STATS_SELECT"
9222
  },
9223
  {
9224
   "chips": ["gfx9"],
9225
   "map": {"at": 221240, "to": "mm"},
9226
   "name": "CPC_LATENCY_STATS_SELECT",
9227
   "type_ref": "CPC_LATENCY_STATS_SELECT"
9228
  },
9229
  {
9230
   "chips": ["gfx9"],
9231
   "map": {"at": 221248, "to": "mm"},
9232
   "name": "CP_DRAW_OBJECT"
9233
  },
9234
  {
9235
   "chips": ["gfx9"],
9236
   "map": {"at": 221252, "to": "mm"},
9237
   "name": "CP_DRAW_OBJECT_COUNTER",
9238
   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
9239
  },
9240
  {
9241
   "chips": ["gfx9"],
9242
   "map": {"at": 221256, "to": "mm"},
9243
   "name": "CP_DRAW_WINDOW_MASK_HI"
9244
  },
9245
  {
9246
   "chips": ["gfx9"],
9247
   "map": {"at": 221260, "to": "mm"},
9248
   "name": "CP_DRAW_WINDOW_HI"
9249
  },
9250
  {
9251
   "chips": ["gfx9"],
9252
   "map": {"at": 221264, "to": "mm"},
9253
   "name": "CP_DRAW_WINDOW_LO",
9254
   "type_ref": "CP_DRAW_WINDOW_LO"
9255
  },
9256
  {
9257
   "chips": ["gfx9"],
9258
   "map": {"at": 221268, "to": "mm"},
9259
   "name": "CP_DRAW_WINDOW_CNTL",
9260
   "type_ref": "CP_DRAW_WINDOW_CNTL"
9261
  },
9262
  {
9263
   "chips": ["gfx9"],
9264
   "map": {"at": 221440, "to": "mm"},
9265
   "name": "GRBM_PERFCOUNTER0_SELECT",
9266
   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
9267
  },
9268
  {
9269
   "chips": ["gfx9"],
9270
   "map": {"at": 221444, "to": "mm"},
9271
   "name": "GRBM_PERFCOUNTER1_SELECT",
9272
   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
9273
  },
9274
  {
9275
   "chips": ["gfx9"],
9276
   "map": {"at": 221448, "to": "mm"},
9277
   "name": "GRBM_SE0_PERFCOUNTER_SELECT",
9278
   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9279
  },
9280
  {
9281
   "chips": ["gfx9"],
9282
   "map": {"at": 221452, "to": "mm"},
9283
   "name": "GRBM_SE1_PERFCOUNTER_SELECT",
9284
   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9285
  },
9286
  {
9287
   "chips": ["gfx9"],
9288
   "map": {"at": 221456, "to": "mm"},
9289
   "name": "GRBM_SE2_PERFCOUNTER_SELECT",
9290
   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9291
  },
9292
  {
9293
   "chips": ["gfx9"],
9294
   "map": {"at": 221460, "to": "mm"},
9295
   "name": "GRBM_SE3_PERFCOUNTER_SELECT",
9296
   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9297
  },
9298
  {
9299
   "chips": ["gfx9"],
9300
   "map": {"at": 221696, "to": "mm"},
9301
   "name": "WD_PERFCOUNTER0_SELECT",
9302
   "type_ref": "WD_PERFCOUNTER0_SELECT"
9303
  },
9304
  {
9305
   "chips": ["gfx9"],
9306
   "map": {"at": 221700, "to": "mm"},
9307
   "name": "WD_PERFCOUNTER1_SELECT",
9308
   "type_ref": "WD_PERFCOUNTER0_SELECT"
9309
  },
9310
  {
9311
   "chips": ["gfx9"],
9312
   "map": {"at": 221704, "to": "mm"},
9313
   "name": "WD_PERFCOUNTER2_SELECT",
9314
   "type_ref": "WD_PERFCOUNTER0_SELECT"
9315
  },
9316
  {
9317
   "chips": ["gfx9"],
9318
   "map": {"at": 221708, "to": "mm"},
9319
   "name": "WD_PERFCOUNTER3_SELECT",
9320
   "type_ref": "WD_PERFCOUNTER0_SELECT"
9321
  },
9322
  {
9323
   "chips": ["gfx9"],
9324
   "map": {"at": 221712, "to": "mm"},
9325
   "name": "IA_PERFCOUNTER0_SELECT",
9326
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9327
  },
9328
  {
9329
   "chips": ["gfx9"],
9330
   "map": {"at": 221716, "to": "mm"},
9331
   "name": "IA_PERFCOUNTER1_SELECT",
9332
   "type_ref": "WD_PERFCOUNTER0_SELECT"
9333
  },
9334
  {
9335
   "chips": ["gfx9"],
9336
   "map": {"at": 221720, "to": "mm"},
9337
   "name": "IA_PERFCOUNTER2_SELECT",
9338
   "type_ref": "WD_PERFCOUNTER0_SELECT"
9339
  },
9340
  {
9341
   "chips": ["gfx9"],
9342
   "map": {"at": 221724, "to": "mm"},
9343
   "name": "IA_PERFCOUNTER3_SELECT",
9344
   "type_ref": "WD_PERFCOUNTER0_SELECT"
9345
  },
9346
  {
9347
   "chips": ["gfx9"],
9348
   "map": {"at": 221728, "to": "mm"},
9349
   "name": "IA_PERFCOUNTER0_SELECT1",
9350
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9351
  },
9352
  {
9353
   "chips": ["gfx9"],
9354
   "map": {"at": 221744, "to": "mm"},
9355
   "name": "VGT_PERFCOUNTER0_SELECT",
9356
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9357
  },
9358
  {
9359
   "chips": ["gfx9"],
9360
   "map": {"at": 221748, "to": "mm"},
9361
   "name": "VGT_PERFCOUNTER1_SELECT",
9362
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9363
  },
9364
  {
9365
   "chips": ["gfx9"],
9366
   "map": {"at": 221752, "to": "mm"},
9367
   "name": "VGT_PERFCOUNTER2_SELECT",
9368
   "type_ref": "WD_PERFCOUNTER0_SELECT"
9369
  },
9370
  {
9371
   "chips": ["gfx9"],
9372
   "map": {"at": 221756, "to": "mm"},
9373
   "name": "VGT_PERFCOUNTER3_SELECT",
9374
   "type_ref": "WD_PERFCOUNTER0_SELECT"
9375
  },
9376
  {
9377
   "chips": ["gfx9"],
9378
   "map": {"at": 221760, "to": "mm"},
9379
   "name": "VGT_PERFCOUNTER0_SELECT1",
9380
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9381
  },
9382
  {
9383
   "chips": ["gfx9"],
9384
   "map": {"at": 221764, "to": "mm"},
9385
   "name": "VGT_PERFCOUNTER1_SELECT1",
9386
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9387
  },
9388
  {
9389
   "chips": ["gfx9"],
9390
   "map": {"at": 221776, "to": "mm"},
9391
   "name": "VGT_PERFCOUNTER_SEID_MASK",
9392
   "type_ref": "VGT_PERFCOUNTER_SEID_MASK"
9393
  },
9394
  {
9395
   "chips": ["gfx9"],
9396
   "map": {"at": 222208, "to": "mm"},
9397
   "name": "PA_SU_PERFCOUNTER0_SELECT",
9398
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9399
  },
9400
  {
9401
   "chips": ["gfx9"],
9402
   "map": {"at": 222212, "to": "mm"},
9403
   "name": "PA_SU_PERFCOUNTER0_SELECT1",
9404
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9405
  },
9406
  {
9407
   "chips": ["gfx9"],
9408
   "map": {"at": 222216, "to": "mm"},
9409
   "name": "PA_SU_PERFCOUNTER1_SELECT",
9410
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9411
  },
9412
  {
9413
   "chips": ["gfx9"],
9414
   "map": {"at": 222220, "to": "mm"},
9415
   "name": "PA_SU_PERFCOUNTER1_SELECT1",
9416
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9417
  },
9418
  {
9419
   "chips": ["gfx9"],
9420
   "map": {"at": 222224, "to": "mm"},
9421
   "name": "PA_SU_PERFCOUNTER2_SELECT",
9422
   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
9423
  },
9424
  {
9425
   "chips": ["gfx9"],
9426
   "map": {"at": 222228, "to": "mm"},
9427
   "name": "PA_SU_PERFCOUNTER3_SELECT",
9428
   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
9429
  },
9430
  {
9431
   "chips": ["gfx9"],
9432
   "map": {"at": 222464, "to": "mm"},
9433
   "name": "PA_SC_PERFCOUNTER0_SELECT",
9434
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9435
  },
9436
  {
9437
   "chips": ["gfx9"],
9438
   "map": {"at": 222468, "to": "mm"},
9439
   "name": "PA_SC_PERFCOUNTER0_SELECT1",
9440
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9441
  },
9442
  {
9443
   "chips": ["gfx9"],
9444
   "map": {"at": 222472, "to": "mm"},
9445
   "name": "PA_SC_PERFCOUNTER1_SELECT",
9446
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9447
  },
9448
  {
9449
   "chips": ["gfx9"],
9450
   "map": {"at": 222476, "to": "mm"},
9451
   "name": "PA_SC_PERFCOUNTER2_SELECT",
9452
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9453
  },
9454
  {
9455
   "chips": ["gfx9"],
9456
   "map": {"at": 222480, "to": "mm"},
9457
   "name": "PA_SC_PERFCOUNTER3_SELECT",
9458
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9459
  },
9460
  {
9461
   "chips": ["gfx9"],
9462
   "map": {"at": 222484, "to": "mm"},
9463
   "name": "PA_SC_PERFCOUNTER4_SELECT",
9464
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9465
  },
9466
  {
9467
   "chips": ["gfx9"],
9468
   "map": {"at": 222488, "to": "mm"},
9469
   "name": "PA_SC_PERFCOUNTER5_SELECT",
9470
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9471
  },
9472
  {
9473
   "chips": ["gfx9"],
9474
   "map": {"at": 222492, "to": "mm"},
9475
   "name": "PA_SC_PERFCOUNTER6_SELECT",
9476
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9477
  },
9478
  {
9479
   "chips": ["gfx9"],
9480
   "map": {"at": 222496, "to": "mm"},
9481
   "name": "PA_SC_PERFCOUNTER7_SELECT",
9482
   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9483
  },
9484
  {
9485
   "chips": ["gfx9"],
9486
   "map": {"at": 222720, "to": "mm"},
9487
   "name": "SPI_PERFCOUNTER0_SELECT",
9488
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9489
  },
9490
  {
9491
   "chips": ["gfx9"],
9492
   "map": {"at": 222724, "to": "mm"},
9493
   "name": "SPI_PERFCOUNTER1_SELECT",
9494
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9495
  },
9496
  {
9497
   "chips": ["gfx9"],
9498
   "map": {"at": 222728, "to": "mm"},
9499
   "name": "SPI_PERFCOUNTER2_SELECT",
9500
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9501
  },
9502
  {
9503
   "chips": ["gfx9"],
9504
   "map": {"at": 222732, "to": "mm"},
9505
   "name": "SPI_PERFCOUNTER3_SELECT",
9506
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9507
  },
9508
  {
9509
   "chips": ["gfx9"],
9510
   "map": {"at": 222736, "to": "mm"},
9511
   "name": "SPI_PERFCOUNTER0_SELECT1",
9512
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9513
  },
9514
  {
9515
   "chips": ["gfx9"],
9516
   "map": {"at": 222740, "to": "mm"},
9517
   "name": "SPI_PERFCOUNTER1_SELECT1",
9518
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9519
  },
9520
  {
9521
   "chips": ["gfx9"],
9522
   "map": {"at": 222744, "to": "mm"},
9523
   "name": "SPI_PERFCOUNTER2_SELECT1",
9524
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9525
  },
9526
  {
9527
   "chips": ["gfx9"],
9528
   "map": {"at": 222748, "to": "mm"},
9529
   "name": "SPI_PERFCOUNTER3_SELECT1",
9530
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9531
  },
9532
  {
9533
   "chips": ["gfx9"],
9534
   "map": {"at": 222752, "to": "mm"},
9535
   "name": "SPI_PERFCOUNTER4_SELECT",
9536
   "type_ref": "SPI_PERFCOUNTER4_SELECT"
9537
  },
9538
  {
9539
   "chips": ["gfx9"],
9540
   "map": {"at": 222756, "to": "mm"},
9541
   "name": "SPI_PERFCOUNTER5_SELECT",
9542
   "type_ref": "SPI_PERFCOUNTER4_SELECT"
9543
  },
9544
  {
9545
   "chips": ["gfx9"],
9546
   "map": {"at": 222760, "to": "mm"},
9547
   "name": "SPI_PERFCOUNTER_BINS",
9548
   "type_ref": "SPI_PERFCOUNTER_BINS"
9549
  },
9550
  {
9551
   "chips": ["gfx9"],
9552
   "map": {"at": 222976, "to": "mm"},
9553
   "name": "SQ_PERFCOUNTER0_SELECT",
9554
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9555
  },
9556
  {
9557
   "chips": ["gfx9"],
9558
   "map": {"at": 222980, "to": "mm"},
9559
   "name": "SQ_PERFCOUNTER1_SELECT",
9560
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9561
  },
9562
  {
9563
   "chips": ["gfx9"],
9564
   "map": {"at": 222984, "to": "mm"},
9565
   "name": "SQ_PERFCOUNTER2_SELECT",
9566
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9567
  },
9568
  {
9569
   "chips": ["gfx9"],
9570
   "map": {"at": 222988, "to": "mm"},
9571
   "name": "SQ_PERFCOUNTER3_SELECT",
9572
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9573
  },
9574
  {
9575
   "chips": ["gfx9"],
9576
   "map": {"at": 222992, "to": "mm"},
9577
   "name": "SQ_PERFCOUNTER4_SELECT",
9578
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9579
  },
9580
  {
9581
   "chips": ["gfx9"],
9582
   "map": {"at": 222996, "to": "mm"},
9583
   "name": "SQ_PERFCOUNTER5_SELECT",
9584
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9585
  },
9586
  {
9587
   "chips": ["gfx9"],
9588
   "map": {"at": 223000, "to": "mm"},
9589
   "name": "SQ_PERFCOUNTER6_SELECT",
9590
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9591
  },
9592
  {
9593
   "chips": ["gfx9"],
9594
   "map": {"at": 223004, "to": "mm"},
9595
   "name": "SQ_PERFCOUNTER7_SELECT",
9596
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9597
  },
9598
  {
9599
   "chips": ["gfx9"],
9600
   "map": {"at": 223008, "to": "mm"},
9601
   "name": "SQ_PERFCOUNTER8_SELECT",
9602
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9603
  },
9604
  {
9605
   "chips": ["gfx9"],
9606
   "map": {"at": 223012, "to": "mm"},
9607
   "name": "SQ_PERFCOUNTER9_SELECT",
9608
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9609
  },
9610
  {
9611
   "chips": ["gfx9"],
9612
   "map": {"at": 223016, "to": "mm"},
9613
   "name": "SQ_PERFCOUNTER10_SELECT",
9614
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9615
  },
9616
  {
9617
   "chips": ["gfx9"],
9618
   "map": {"at": 223020, "to": "mm"},
9619
   "name": "SQ_PERFCOUNTER11_SELECT",
9620
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9621
  },
9622
  {
9623
   "chips": ["gfx9"],
9624
   "map": {"at": 223024, "to": "mm"},
9625
   "name": "SQ_PERFCOUNTER12_SELECT",
9626
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9627
  },
9628
  {
9629
   "chips": ["gfx9"],
9630
   "map": {"at": 223028, "to": "mm"},
9631
   "name": "SQ_PERFCOUNTER13_SELECT",
9632
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9633
  },
9634
  {
9635
   "chips": ["gfx9"],
9636
   "map": {"at": 223032, "to": "mm"},
9637
   "name": "SQ_PERFCOUNTER14_SELECT",
9638
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9639
  },
9640
  {
9641
   "chips": ["gfx9"],
9642
   "map": {"at": 223036, "to": "mm"},
9643
   "name": "SQ_PERFCOUNTER15_SELECT",
9644
   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9645
  },
9646
  {
9647
   "chips": ["gfx9"],
9648
   "map": {"at": 223104, "to": "mm"},
9649
   "name": "SQ_PERFCOUNTER_CTRL",
9650
   "type_ref": "SQ_PERFCOUNTER_CTRL"
9651
  },
9652
  {
9653
   "chips": ["gfx9"],
9654
   "map": {"at": 223108, "to": "mm"},
9655
   "name": "SQ_PERFCOUNTER_MASK",
9656
   "type_ref": "SQ_THREAD_TRACE_PERF_MASK"
9657
  },
9658
  {
9659
   "chips": ["gfx9"],
9660
   "map": {"at": 223112, "to": "mm"},
9661
   "name": "SQ_PERFCOUNTER_CTRL2",
9662
   "type_ref": "SQ_PERFCOUNTER_CTRL2"
9663
  },
9664
  {
9665
   "chips": ["gfx9"],
9666
   "map": {"at": 223488, "to": "mm"},
9667
   "name": "SX_PERFCOUNTER0_SELECT",
9668
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9669
  },
9670
  {
9671
   "chips": ["gfx9"],
9672
   "map": {"at": 223492, "to": "mm"},
9673
   "name": "SX_PERFCOUNTER1_SELECT",
9674
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9675
  },
9676
  {
9677
   "chips": ["gfx9"],
9678
   "map": {"at": 223496, "to": "mm"},
9679
   "name": "SX_PERFCOUNTER2_SELECT",
9680
   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
9681
  },
9682
  {
9683
   "chips": ["gfx9"],
9684
   "map": {"at": 223500, "to": "mm"},
9685
   "name": "SX_PERFCOUNTER3_SELECT",
9686
   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
9687
  },
9688
  {
9689
   "chips": ["gfx9"],
9690
   "map": {"at": 223504, "to": "mm"},
9691
   "name": "SX_PERFCOUNTER0_SELECT1",
9692
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9693
  },
9694
  {
9695
   "chips": ["gfx9"],
9696
   "map": {"at": 223508, "to": "mm"},
9697
   "name": "SX_PERFCOUNTER1_SELECT1",
9698
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9699
  },
9700
  {
9701
   "chips": ["gfx9"],
9702
   "map": {"at": 223744, "to": "mm"},
9703
   "name": "GDS_PERFCOUNTER0_SELECT",
9704
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9705
  },
9706
  {
9707
   "chips": ["gfx9"],
9708
   "map": {"at": 223748, "to": "mm"},
9709
   "name": "GDS_PERFCOUNTER1_SELECT",
9710
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9711
  },
9712
  {
9713
   "chips": ["gfx9"],
9714
   "map": {"at": 223752, "to": "mm"},
9715
   "name": "GDS_PERFCOUNTER2_SELECT",
9716
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9717
  },
9718
  {
9719
   "chips": ["gfx9"],
9720
   "map": {"at": 223756, "to": "mm"},
9721
   "name": "GDS_PERFCOUNTER3_SELECT",
9722
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9723
  },
9724
  {
9725
   "chips": ["gfx9"],
9726
   "map": {"at": 223760, "to": "mm"},
9727
   "name": "GDS_PERFCOUNTER0_SELECT1",
9728
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9729
  },
9730
  {
9731
   "chips": ["gfx9"],
9732
   "map": {"at": 224000, "to": "mm"},
9733
   "name": "TA_PERFCOUNTER0_SELECT",
9734
   "type_ref": "TA_PERFCOUNTER0_SELECT"
9735
  },
9736
  {
9737
   "chips": ["gfx9"],
9738
   "map": {"at": 224004, "to": "mm"},
9739
   "name": "TA_PERFCOUNTER0_SELECT1",
9740
   "type_ref": "TA_PERFCOUNTER0_SELECT1"
9741
  },
9742
  {
9743
   "chips": ["gfx9"],
9744
   "map": {"at": 224008, "to": "mm"},
9745
   "name": "TA_PERFCOUNTER1_SELECT",
9746
   "type_ref": "TA_PERFCOUNTER1_SELECT"
9747
  },
9748
  {
9749
   "chips": ["gfx9"],
9750
   "map": {"at": 224256, "to": "mm"},
9751
   "name": "TD_PERFCOUNTER0_SELECT",
9752
   "type_ref": "TA_PERFCOUNTER0_SELECT"
9753
  },
9754
  {
9755
   "chips": ["gfx9"],
9756
   "map": {"at": 224260, "to": "mm"},
9757
   "name": "TD_PERFCOUNTER0_SELECT1",
9758
   "type_ref": "TA_PERFCOUNTER0_SELECT1"
9759
  },
9760
  {
9761
   "chips": ["gfx9"],
9762
   "map": {"at": 224264, "to": "mm"},
9763
   "name": "TD_PERFCOUNTER1_SELECT",
9764
   "type_ref": "TA_PERFCOUNTER1_SELECT"
9765
  },
9766
  {
9767
   "chips": ["gfx9"],
9768
   "map": {"at": 224512, "to": "mm"},
9769
   "name": "TCP_PERFCOUNTER0_SELECT",
9770
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9771
  },
9772
  {
9773
   "chips": ["gfx9"],
9774
   "map": {"at": 224516, "to": "mm"},
9775
   "name": "TCP_PERFCOUNTER0_SELECT1",
9776
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9777
  },
9778
  {
9779
   "chips": ["gfx9"],
9780
   "map": {"at": 224520, "to": "mm"},
9781
   "name": "TCP_PERFCOUNTER1_SELECT",
9782
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9783
  },
9784
  {
9785
   "chips": ["gfx9"],
9786
   "map": {"at": 224524, "to": "mm"},
9787
   "name": "TCP_PERFCOUNTER1_SELECT1",
9788
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9789
  },
9790
  {
9791
   "chips": ["gfx9"],
9792
   "map": {"at": 224528, "to": "mm"},
9793
   "name": "TCP_PERFCOUNTER2_SELECT",
9794
   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
9795
  },
9796
  {
9797
   "chips": ["gfx9"],
9798
   "map": {"at": 224532, "to": "mm"},
9799
   "name": "TCP_PERFCOUNTER3_SELECT",
9800
   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
9801
  },
9802
  {
9803
   "chips": ["gfx9"],
9804
   "map": {"at": 224768, "to": "mm"},
9805
   "name": "TCC_PERFCOUNTER0_SELECT",
9806
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9807
  },
9808
  {
9809
   "chips": ["gfx9"],
9810
   "map": {"at": 224772, "to": "mm"},
9811
   "name": "TCC_PERFCOUNTER0_SELECT1",
9812
   "type_ref": "TCC_PERFCOUNTER0_SELECT1"
9813
  },
9814
  {
9815
   "chips": ["gfx9"],
9816
   "map": {"at": 224776, "to": "mm"},
9817
   "name": "TCC_PERFCOUNTER1_SELECT",
9818
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9819
  },
9820
  {
9821
   "chips": ["gfx9"],
9822
   "map": {"at": 224780, "to": "mm"},
9823
   "name": "TCC_PERFCOUNTER1_SELECT1",
9824
   "type_ref": "TCC_PERFCOUNTER0_SELECT1"
9825
  },
9826
  {
9827
   "chips": ["gfx9"],
9828
   "map": {"at": 224784, "to": "mm"},
9829
   "name": "TCC_PERFCOUNTER2_SELECT",
9830
   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
9831
  },
9832
  {
9833
   "chips": ["gfx9"],
9834
   "map": {"at": 224788, "to": "mm"},
9835
   "name": "TCC_PERFCOUNTER3_SELECT",
9836
   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
9837
  },
9838
  {
9839
   "chips": ["gfx9"],
9840
   "map": {"at": 224832, "to": "mm"},
9841
   "name": "TCA_PERFCOUNTER0_SELECT",
9842
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9843
  },
9844
  {
9845
   "chips": ["gfx9"],
9846
   "map": {"at": 224836, "to": "mm"},
9847
   "name": "TCA_PERFCOUNTER0_SELECT1",
9848
   "type_ref": "TCC_PERFCOUNTER0_SELECT1"
9849
  },
9850
  {
9851
   "chips": ["gfx9"],
9852
   "map": {"at": 224840, "to": "mm"},
9853
   "name": "TCA_PERFCOUNTER1_SELECT",
9854
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9855
  },
9856
  {
9857
   "chips": ["gfx9"],
9858
   "map": {"at": 224844, "to": "mm"},
9859
   "name": "TCA_PERFCOUNTER1_SELECT1",
9860
   "type_ref": "TCC_PERFCOUNTER0_SELECT1"
9861
  },
9862
  {
9863
   "chips": ["gfx9"],
9864
   "map": {"at": 224848, "to": "mm"},
9865
   "name": "TCA_PERFCOUNTER2_SELECT",
9866
   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
9867
  },
9868
  {
9869
   "chips": ["gfx9"],
9870
   "map": {"at": 224852, "to": "mm"},
9871
   "name": "TCA_PERFCOUNTER3_SELECT",
9872
   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
9873
  },
9874
  {
9875
   "chips": ["gfx9"],
9876
   "map": {"at": 225280, "to": "mm"},
9877
   "name": "CB_PERFCOUNTER_FILTER",
9878
   "type_ref": "CB_PERFCOUNTER_FILTER"
9879
  },
9880
  {
9881
   "chips": ["gfx9"],
9882
   "map": {"at": 225284, "to": "mm"},
9883
   "name": "CB_PERFCOUNTER0_SELECT",
9884
   "type_ref": "CB_PERFCOUNTER0_SELECT"
9885
  },
9886
  {
9887
   "chips": ["gfx9"],
9888
   "map": {"at": 225288, "to": "mm"},
9889
   "name": "CB_PERFCOUNTER0_SELECT1",
9890
   "type_ref": "CB_PERFCOUNTER0_SELECT1"
9891
  },
9892
  {
9893
   "chips": ["gfx9"],
9894
   "map": {"at": 225292, "to": "mm"},
9895
   "name": "CB_PERFCOUNTER1_SELECT",
9896
   "type_ref": "CB_PERFCOUNTER1_SELECT"
9897
  },
9898
  {
9899
   "chips": ["gfx9"],
9900
   "map": {"at": 225296, "to": "mm"},
9901
   "name": "CB_PERFCOUNTER2_SELECT",
9902
   "type_ref": "CB_PERFCOUNTER1_SELECT"
9903
  },
9904
  {
9905
   "chips": ["gfx9"],
9906
   "map": {"at": 225300, "to": "mm"},
9907
   "name": "CB_PERFCOUNTER3_SELECT",
9908
   "type_ref": "CB_PERFCOUNTER1_SELECT"
9909
  },
9910
  {
9911
   "chips": ["gfx9"],
9912
   "map": {"at": 225536, "to": "mm"},
9913
   "name": "DB_PERFCOUNTER0_SELECT",
9914
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9915
  },
9916
  {
9917
   "chips": ["gfx9"],
9918
   "map": {"at": 225540, "to": "mm"},
9919
   "name": "DB_PERFCOUNTER0_SELECT1",
9920
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9921
  },
9922
  {
9923
   "chips": ["gfx9"],
9924
   "map": {"at": 225544, "to": "mm"},
9925
   "name": "DB_PERFCOUNTER1_SELECT",
9926
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9927
  },
9928
  {
9929
   "chips": ["gfx9"],
9930
   "map": {"at": 225548, "to": "mm"},
9931
   "name": "DB_PERFCOUNTER1_SELECT1",
9932
   "type_ref": "IA_PERFCOUNTER0_SELECT1"
9933
  },
9934
  {
9935
   "chips": ["gfx9"],
9936
   "map": {"at": 225552, "to": "mm"},
9937
   "name": "DB_PERFCOUNTER2_SELECT",
9938
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9939
  },
9940
  {
9941
   "chips": ["gfx9"],
9942
   "map": {"at": 225560, "to": "mm"},
9943
   "name": "DB_PERFCOUNTER3_SELECT",
9944
   "type_ref": "IA_PERFCOUNTER0_SELECT"
9945
  },
9946
  {
9947
   "chips": ["gfx9"],
9948
   "map": {"at": 225792, "to": "mm"},
9949
   "name": "RLC_SPM_PERFMON_CNTL",
9950
   "type_ref": "RLC_SPM_PERFMON_CNTL"
9951
  },
9952
  {
9953
   "chips": ["gfx9"],
9954
   "map": {"at": 225796, "to": "mm"},
9955
   "name": "RLC_SPM_PERFMON_RING_BASE_LO"
9956
  },
9957
  {
9958
   "chips": ["gfx9"],
9959
   "map": {"at": 225800, "to": "mm"},
9960
   "name": "RLC_SPM_PERFMON_RING_BASE_HI",
9961
   "type_ref": "RLC_SPM_PERFMON_RING_BASE_HI"
9962
  },
9963
  {
9964
   "chips": ["gfx9"],
9965
   "map": {"at": 225804, "to": "mm"},
9966
   "name": "RLC_SPM_PERFMON_RING_SIZE"
9967
  },
9968
  {
9969
   "chips": ["gfx9"],
9970
   "map": {"at": 225808, "to": "mm"},
9971
   "name": "RLC_SPM_PERFMON_SEGMENT_SIZE",
9972
   "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"
9973
  },
9974
  {
9975
   "chips": ["gfx9"],
9976
   "map": {"at": 225812, "to": "mm"},
9977
   "name": "RLC_SPM_SE_MUXSEL_ADDR"
9978
  },
9979
  {
9980
   "chips": ["gfx9"],
9981
   "map": {"at": 225816, "to": "mm"},
9982
   "name": "RLC_SPM_SE_MUXSEL_DATA"
9983
  },
9984
  {
9985
   "chips": ["gfx9"],
9986
   "map": {"at": 225820, "to": "mm"},
9987
   "name": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY",
9988
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9989
  },
9990
  {
9991
   "chips": ["gfx9"],
9992
   "map": {"at": 225824, "to": "mm"},
9993
   "name": "RLC_SPM_CPC_PERFMON_SAMPLE_DELAY",
9994
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9995
  },
9996
  {
9997
   "chips": ["gfx9"],
9998
   "map": {"at": 225828, "to": "mm"},
9999
   "name": "RLC_SPM_CPF_PERFMON_SAMPLE_DELAY",
10000
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10001
  },
10002
  {
10003
   "chips": ["gfx9"],
10004
   "map": {"at": 225832, "to": "mm"},
10005
   "name": "RLC_SPM_CB_PERFMON_SAMPLE_DELAY",
10006
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10007
  },
10008
  {
10009
   "chips": ["gfx9"],
10010
   "map": {"at": 225836, "to": "mm"},
10011
   "name": "RLC_SPM_DB_PERFMON_SAMPLE_DELAY",
10012
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10013
  },
10014
  {
10015
   "chips": ["gfx9"],
10016
   "map": {"at": 225840, "to": "mm"},
10017
   "name": "RLC_SPM_PA_PERFMON_SAMPLE_DELAY",
10018
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10019
  },
10020
  {
10021
   "chips": ["gfx9"],
10022
   "map": {"at": 225844, "to": "mm"},
10023
   "name": "RLC_SPM_GDS_PERFMON_SAMPLE_DELAY",
10024
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10025
  },
10026
  {
10027
   "chips": ["gfx9"],
10028
   "map": {"at": 225848, "to": "mm"},
10029
   "name": "RLC_SPM_IA_PERFMON_SAMPLE_DELAY",
10030
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10031
  },
10032
  {
10033
   "chips": ["gfx9"],
10034
   "map": {"at": 225856, "to": "mm"},
10035
   "name": "RLC_SPM_SC_PERFMON_SAMPLE_DELAY",
10036
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10037
  },
10038
  {
10039
   "chips": ["gfx9"],
10040
   "map": {"at": 225860, "to": "mm"},
10041
   "name": "RLC_SPM_TCC_PERFMON_SAMPLE_DELAY",
10042
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10043
  },
10044
  {
10045
   "chips": ["gfx9"],
10046
   "map": {"at": 225864, "to": "mm"},
10047
   "name": "RLC_SPM_TCA_PERFMON_SAMPLE_DELAY",
10048
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10049
  },
10050
  {
10051
   "chips": ["gfx9"],
10052
   "map": {"at": 225868, "to": "mm"},
10053
   "name": "RLC_SPM_TCP_PERFMON_SAMPLE_DELAY",
10054
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10055
  },
10056
  {
10057
   "chips": ["gfx9"],
10058
   "map": {"at": 225872, "to": "mm"},
10059
   "name": "RLC_SPM_TA_PERFMON_SAMPLE_DELAY",
10060
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10061
  },
10062
  {
10063
   "chips": ["gfx9"],
10064
   "map": {"at": 225876, "to": "mm"},
10065
   "name": "RLC_SPM_TD_PERFMON_SAMPLE_DELAY",
10066
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10067
  },
10068
  {
10069
   "chips": ["gfx9"],
10070
   "map": {"at": 225880, "to": "mm"},
10071
   "name": "RLC_SPM_VGT_PERFMON_SAMPLE_DELAY",
10072
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10073
  },
10074
  {
10075
   "chips": ["gfx9"],
10076
   "map": {"at": 225884, "to": "mm"},
10077
   "name": "RLC_SPM_SPI_PERFMON_SAMPLE_DELAY",
10078
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10079
  },
10080
  {
10081
   "chips": ["gfx9"],
10082
   "map": {"at": 225888, "to": "mm"},
10083
   "name": "RLC_SPM_SQG_PERFMON_SAMPLE_DELAY",
10084
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10085
  },
10086
  {
10087
   "chips": ["gfx9"],
10088
   "map": {"at": 225896, "to": "mm"},
10089
   "name": "RLC_SPM_SX_PERFMON_SAMPLE_DELAY",
10090
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10091
  },
10092
  {
10093
   "chips": ["gfx9"],
10094
   "map": {"at": 225900, "to": "mm"},
10095
   "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR"
10096
  },
10097
  {
10098
   "chips": ["gfx9"],
10099
   "map": {"at": 225904, "to": "mm"},
10100
   "name": "RLC_SPM_GLOBAL_MUXSEL_DATA"
10101
  },
10102
  {
10103
   "chips": ["gfx9"],
10104
   "map": {"at": 225908, "to": "mm"},
10105
   "name": "RLC_SPM_RING_RDPTR"
10106
  },
10107
  {
10108
   "chips": ["gfx9"],
10109
   "map": {"at": 225912, "to": "mm"},
10110
   "name": "RLC_SPM_SEGMENT_THRESHOLD"
10111
  },
10112
  {
10113
   "chips": ["gfx9"],
10114
   "map": {"at": 225932, "to": "mm"},
10115
   "name": "RLC_SPM_RMI_PERFMON_SAMPLE_DELAY",
10116
   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10117
  },
10118
  {
10119
   "chips": ["gfx9"],
10120
   "map": {"at": 225936, "to": "mm"},
10121
   "name": "RLC_SPM_PERFMON_SAMPLE_DELAY_MAX",
10122
   "type_ref": "RLC_SPM_PERFMON_SAMPLE_DELAY_MAX"
10123
  },
10124
  {
10125
   "chips": ["gfx9"],
10126
   "map": {"at": 226040, "to": "mm"},
10127
   "name": "RLC_PERFMON_CLK_CNTL_UCODE",
10128
   "type_ref": "RLC_PERFMON_CLK_CNTL_UCODE"
10129
  },
10130
  {
10131
   "chips": ["gfx9"],
10132
   "map": {"at": 226044, "to": "mm"},
10133
   "name": "RLC_PERFMON_CLK_CNTL",
10134
   "type_ref": "RLC_PERFMON_CLK_CNTL_UCODE"
10135
  },
10136
  {
10137
   "chips": ["gfx9"],
10138
   "map": {"at": 226048, "to": "mm"},
10139
   "name": "RLC_PERFMON_CNTL",
10140
   "type_ref": "RLC_PERFMON_CNTL"
10141
  },
10142
  {
10143
   "chips": ["gfx9"],
10144
   "map": {"at": 226052, "to": "mm"},
10145
   "name": "RLC_PERFCOUNTER0_SELECT",
10146
   "type_ref": "RLC_PERFCOUNTER0_SELECT"
10147
  },
10148
  {
10149
   "chips": ["gfx9"],
10150
   "map": {"at": 226056, "to": "mm"},
10151
   "name": "RLC_PERFCOUNTER1_SELECT",
10152
   "type_ref": "RLC_PERFCOUNTER0_SELECT"
10153
  },
10154
  {
10155
   "chips": ["gfx9"],
10156
   "map": {"at": 226060, "to": "mm"},
10157
   "name": "RLC_GPU_IOV_PERF_CNT_CNTL",
10158
   "type_ref": "RLC_GPU_IOV_PERF_CNT_CNTL"
10159
  },
10160
  {
10161
   "chips": ["gfx9"],
10162
   "map": {"at": 226064, "to": "mm"},
10163
   "name": "RLC_GPU_IOV_PERF_CNT_WR_ADDR",
10164
   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
10165
  },
10166
  {
10167
   "chips": ["gfx9"],
10168
   "map": {"at": 226068, "to": "mm"},
10169
   "name": "RLC_GPU_IOV_PERF_CNT_WR_DATA",
10170
   "type_ref": "COMPUTE_VMID"
10171
  },
10172
  {
10173
   "chips": ["gfx9"],
10174
   "map": {"at": 226072, "to": "mm"},
10175
   "name": "RLC_GPU_IOV_PERF_CNT_RD_ADDR",
10176
   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
10177
  },
10178
  {
10179
   "chips": ["gfx9"],
10180
   "map": {"at": 226076, "to": "mm"},
10181
   "name": "RLC_GPU_IOV_PERF_CNT_RD_DATA",
10182
   "type_ref": "COMPUTE_VMID"
10183
  },
10184
  {
10185
   "chips": ["gfx9"],
10186
   "map": {"at": 226304, "to": "mm"},
10187
   "name": "RMI_PERFCOUNTER0_SELECT",
10188
   "type_ref": "CB_PERFCOUNTER0_SELECT"
10189
  },
10190
  {
10191
   "chips": ["gfx9"],
10192
   "map": {"at": 226308, "to": "mm"},
10193
   "name": "RMI_PERFCOUNTER0_SELECT1",
10194
   "type_ref": "CB_PERFCOUNTER0_SELECT1"
10195
  },
10196
  {
10197
   "chips": ["gfx9"],
10198
   "map": {"at": 226312, "to": "mm"},
10199
   "name": "RMI_PERFCOUNTER1_SELECT",
10200
   "type_ref": "CB_PERFCOUNTER1_SELECT"
10201
  },
10202
  {
10203
   "chips": ["gfx9"],
10204
   "map": {"at": 226316, "to": "mm"},
10205
   "name": "RMI_PERFCOUNTER2_SELECT",
10206
   "type_ref": "CB_PERFCOUNTER0_SELECT"
10207
  },
10208
  {
10209
   "chips": ["gfx9"],
10210
   "map": {"at": 226320, "to": "mm"},
10211
   "name": "RMI_PERFCOUNTER2_SELECT1",
10212
   "type_ref": "CB_PERFCOUNTER0_SELECT1"
10213
  },
10214
  {
10215
   "chips": ["gfx9"],
10216
   "map": {"at": 226324, "to": "mm"},
10217
   "name": "RMI_PERFCOUNTER3_SELECT",
10218
   "type_ref": "CB_PERFCOUNTER1_SELECT"
10219
  },
10220
  {
10221
   "chips": ["gfx9"],
10222
   "map": {"at": 226328, "to": "mm"},
10223
   "name": "RMI_PERF_COUNTER_CNTL",
10224
   "type_ref": "RMI_PERF_COUNTER_CNTL"
10225
  },
10226
  {
10227
   "chips": ["gfx9"],
10228
   "map": {"at": 226560, "to": "mm"},
10229
   "name": "ATC_L2_PERFCOUNTER0_CFG",
10230
   "type_ref": "ATC_L2_PERFCOUNTER0_CFG"
10231
  },
10232
  {
10233
   "chips": ["gfx9"],
10234
   "map": {"at": 226564, "to": "mm"},
10235
   "name": "ATC_L2_PERFCOUNTER1_CFG",
10236
   "type_ref": "ATC_L2_PERFCOUNTER0_CFG"
10237
  },
10238
  {
10239
   "chips": ["gfx9"],
10240
   "map": {"at": 226568, "to": "mm"},
10241
   "name": "ATC_L2_PERFCOUNTER_RSLT_CNTL",
10242
   "type_ref": "ATC_L2_PERFCOUNTER_RSLT_CNTL"
10243
  },
10244
  {
10245
   "chips": ["gfx9"],
10246
   "map": {"at": 226608, "to": "mm"},
10247
   "name": "MC_VM_L2_PERFCOUNTER0_CFG",
10248
   "type_ref": "ATC_L2_PERFCOUNTER0_CFG"
10249
  },
10250
  {
10251
   "chips": ["gfx9"],
10252
   "map": {"at": 226612, "to": "mm"},
10253
   "name": "MC_VM_L2_PERFCOUNTER1_CFG",
10254
   "type_ref": "ATC_L2_PERFCOUNTER0_CFG"
10255
  },
10256
  {
10257
   "chips": ["gfx9"],
10258
   "map": {"at": 226616, "to": "mm"},
10259
   "name": "MC_VM_L2_PERFCOUNTER2_CFG",
10260
   "type_ref": "ATC_L2_PERFCOUNTER0_CFG"
10261
  },
10262
  {
10263
   "chips": ["gfx9"],
10264
   "map": {"at": 226620, "to": "mm"},
10265
   "name": "MC_VM_L2_PERFCOUNTER3_CFG",
10266
   "type_ref": "ATC_L2_PERFCOUNTER0_CFG"
10267
  },
10268
  {
10269
   "chips": ["gfx9"],
10270
   "map": {"at": 226624, "to": "mm"},
10271
   "name": "MC_VM_L2_PERFCOUNTER4_CFG",
10272
   "type_ref": "ATC_L2_PERFCOUNTER0_CFG"
10273
  },
10274
  {
10275
   "chips": ["gfx9"],
10276
   "map": {"at": 226628, "to": "mm"},
10277
   "name": "MC_VM_L2_PERFCOUNTER5_CFG",
10278
   "type_ref": "ATC_L2_PERFCOUNTER0_CFG"
10279
  },
10280
  {
10281
   "chips": ["gfx9"],
10282
   "map": {"at": 226632, "to": "mm"},
10283
   "name": "MC_VM_L2_PERFCOUNTER6_CFG",
10284
   "type_ref": "ATC_L2_PERFCOUNTER0_CFG"
10285
  },
10286
  {
10287
   "chips": ["gfx9"],
10288
   "map": {"at": 226636, "to": "mm"},
10289
   "name": "MC_VM_L2_PERFCOUNTER7_CFG",
10290
   "type_ref": "ATC_L2_PERFCOUNTER0_CFG"
10291
  },
10292
  {
10293
   "chips": ["gfx9"],
10294
   "map": {"at": 226640, "to": "mm"},
10295
   "name": "MC_VM_L2_PERFCOUNTER_RSLT_CNTL",
10296
   "type_ref": "ATC_L2_PERFCOUNTER_RSLT_CNTL"
10297
  }
10298
 ],
10299
 "register_types": {
10300
  "ATC_L2_PERFCOUNTER0_CFG": {
10301
   "fields": [
10302
    {"bits": [0, 7], "name": "PERF_SEL"},
10303
    {"bits": [8, 15], "name": "PERF_SEL_END"},
10304
    {"bits": [24, 27], "name": "PERF_MODE"},
10305
    {"bits": [28, 28], "name": "ENABLE"},
10306
    {"bits": [29, 29], "name": "CLEAR"}
10307
   ]
10308
  },
10309
  "ATC_L2_PERFCOUNTER_HI": {
10310
   "fields": [
10311
    {"bits": [0, 15], "name": "COUNTER_HI"},
10312
    {"bits": [16, 31], "name": "COMPARE_VALUE"}
10313
   ]
10314
  },
10315
  "ATC_L2_PERFCOUNTER_RSLT_CNTL": {
10316
   "fields": [
10317
    {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"},
10318
    {"bits": [8, 15], "name": "START_TRIGGER"},
10319
    {"bits": [16, 23], "name": "STOP_TRIGGER"},
10320
    {"bits": [24, 24], "name": "ENABLE_ANY"},
10321
    {"bits": [25, 25], "name": "CLEAR_ALL"},
10322
    {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"}
10323
   ]
10324
  },
10325
  "CB_BLEND0_CONTROL": {
10326
   "fields": [
10327
    {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
10328
    {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
10329
    {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
10330
    {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
10331
    {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
10332
    {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
10333
    {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
10334
    {"bits": [30, 30], "name": "ENABLE"},
10335
    {"bits": [31, 31], "name": "DISABLE_ROP3"}
10336
   ]
10337
  },
10338
  "CB_COLOR0_ATTRIB": {
10339
   "fields": [
10340
    {"bits": [0, 10], "name": "MIP0_DEPTH"},
10341
    {"bits": [11, 11], "name": "META_LINEAR"},
10342
    {"bits": [12, 14], "name": "NUM_SAMPLES"},
10343
    {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
10344
    {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"},
10345
    {"bits": [18, 22], "name": "COLOR_SW_MODE"},
10346
    {"bits": [23, 27], "name": "FMASK_SW_MODE"},
10347
    {"bits": [28, 29], "name": "RESOURCE_TYPE"},
10348
    {"bits": [30, 30], "name": "RB_ALIGNED"},
10349
    {"bits": [31, 31], "name": "PIPE_ALIGNED"}
10350
   ]
10351
  },
10352
  "CB_COLOR0_ATTRIB2": {
10353
   "fields": [
10354
    {"bits": [0, 13], "name": "MIP0_HEIGHT"},
10355
    {"bits": [14, 27], "name": "MIP0_WIDTH"},
10356
    {"bits": [28, 31], "name": "MAX_MIP"}
10357
   ]
10358
  },
10359
  "CB_COLOR0_BASE_EXT": {
10360
   "fields": [
10361
    {"bits": [0, 7], "name": "BASE_256B"}
10362
   ]
10363
  },
10364
  "CB_COLOR0_DCC_CONTROL": {
10365
   "fields": [
10366
    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
10367
    {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"},
10368
    {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
10369
    {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
10370
    {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
10371
    {"bits": [7, 8], "name": "COLOR_TRANSFORM"},
10372
    {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},
10373
    {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"},
10374
    {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"},
10375
    {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"},
10376
    {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"}
10377
   ]
10378
  },
10379
  "CB_COLOR0_INFO": {
10380
   "fields": [
10381
    {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
10382
    {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
10383
    {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
10384
    {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
10385
    {"bits": [13, 13], "name": "FAST_CLEAR"},
10386
    {"bits": [14, 14], "name": "COMPRESSION"},
10387
    {"bits": [15, 15], "name": "BLEND_CLAMP"},
10388
    {"bits": [16, 16], "name": "BLEND_BYPASS"},
10389
    {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
10390
    {"bits": [18, 18], "name": "ROUND_MODE"},
10391
    {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
10392
    {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
10393
    {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"},
10394
    {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"},
10395
    {"bits": [28, 28], "name": "DCC_ENABLE"},
10396
    {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"}
10397
   ]
10398
  },
10399
  "CB_COLOR0_VIEW": {
10400
   "fields": [
10401
    {"bits": [0, 10], "name": "SLICE_START"},
10402
    {"bits": [13, 23], "name": "SLICE_MAX"},
10403
    {"bits": [24, 27], "name": "MIP_LEVEL"}
10404
   ]
10405
  },
10406
  "CB_COLOR_CONTROL": {
10407
   "fields": [
10408
    {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},
10409
    {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
10410
    {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
10411
    {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
10412
   ]
10413
  },
10414
  "CB_DCC_CONTROL": {
10415
   "fields": [
10416
    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
10417
    {"bits": [1, 1], "name": "OVERWRITE_COMBINER_MRT_SHARING_DISABLE"},
10418
    {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"},
10419
    {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"},
10420
    {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"},
10421
    {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"},
10422
    {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"},
10423
    {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"},
10424
    {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"}
10425
   ]
10426
  },
10427
  "CB_PERFCOUNTER0_SELECT": {
10428
   "fields": [
10429
    {"bits": [0, 8], "name": "PERF_SEL"},
10430
    {"bits": [10, 18], "name": "PERF_SEL1"},
10431
    {"bits": [20, 23], "name": "CNTR_MODE"},
10432
    {"bits": [24, 27], "name": "PERF_MODE1"},
10433
    {"bits": [28, 31], "name": "PERF_MODE"}
10434
   ]
10435
  },
10436
  "CB_PERFCOUNTER0_SELECT1": {
10437
   "fields": [
10438
    {"bits": [0, 8], "name": "PERF_SEL2"},
10439
    {"bits": [10, 18], "name": "PERF_SEL3"},
10440
    {"bits": [24, 27], "name": "PERF_MODE3"},
10441
    {"bits": [28, 31], "name": "PERF_MODE2"}
10442
   ]
10443
  },
10444
  "CB_PERFCOUNTER1_SELECT": {
10445
   "fields": [
10446
    {"bits": [0, 8], "name": "PERF_SEL"},
10447
    {"bits": [28, 31], "name": "PERF_MODE"}
10448
   ]
10449
  },
10450
  "CB_PERFCOUNTER_FILTER": {
10451
   "fields": [
10452
    {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},
10453
    {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
10454
    {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},
10455
    {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},
10456
    {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},
10457
    {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
10458
    {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},
10459
    {"bits": [13, 15], "name": "MRT_FILTER_SEL"},
10460
    {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},
10461
    {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},
10462
    {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},
10463
    {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}
10464
   ]
10465
  },
10466
  "CB_SHADER_MASK": {
10467
   "fields": [
10468
    {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
10469
    {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
10470
    {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
10471
    {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
10472
    {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
10473
    {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
10474
    {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
10475
    {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
10476
   ]
10477
  },
10478
  "CB_TARGET_MASK": {
10479
   "fields": [
10480
    {"bits": [0, 3], "name": "TARGET0_ENABLE"},
10481
    {"bits": [4, 7], "name": "TARGET1_ENABLE"},
10482
    {"bits": [8, 11], "name": "TARGET2_ENABLE"},
10483
    {"bits": [12, 15], "name": "TARGET3_ENABLE"},
10484
    {"bits": [16, 19], "name": "TARGET4_ENABLE"},
10485
    {"bits": [20, 23], "name": "TARGET5_ENABLE"},
10486
    {"bits": [24, 27], "name": "TARGET6_ENABLE"},
10487
    {"bits": [28, 31], "name": "TARGET7_ENABLE"}
10488
   ]
10489
  },
10490
  "COHER_DEST_BASE_HI_0": {
10491
   "fields": [
10492
    {"bits": [0, 7], "name": "DEST_BASE_HI_256B"}
10493
   ]
10494
  },
10495
  "COMPUTE_DISPATCH_INITIATOR": {
10496
   "fields": [
10497
    {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
10498
    {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
10499
    {"bits": [2, 2], "name": "FORCE_START_AT_000"},
10500
    {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
10501
    {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
10502
    {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
10503
    {"bits": [6, 6], "name": "ORDER_MODE"},
10504
    {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
10505
    {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
10506
    {"bits": [12, 12], "name": "RESERVED"},
10507
    {"bits": [14, 14], "name": "RESTORE"}
10508
   ]
10509
  },
10510
  "COMPUTE_MISC_RESERVED": {
10511
   "fields": [
10512
    {"bits": [0, 1], "name": "SEND_SEID"},
10513
    {"bits": [2, 2], "name": "RESERVED2"},
10514
    {"bits": [3, 3], "name": "RESERVED3"},
10515
    {"bits": [4, 4], "name": "RESERVED4"},
10516
    {"bits": [5, 16], "name": "WAVE_ID_BASE"}
10517
   ]
10518
  },
10519
  "COMPUTE_NUM_THREAD_X": {
10520
   "fields": [
10521
    {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
10522
    {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
10523
   ]
10524
  },
10525
  "COMPUTE_PERFCOUNT_ENABLE": {
10526
   "fields": [
10527
    {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}
10528
   ]
10529
  },
10530
  "COMPUTE_PGM_HI": {
10531
   "fields": [
10532
    {"bits": [0, 7], "name": "DATA"}
10533
   ]
10534
  },
10535
  "COMPUTE_PGM_RSRC1": {
10536
   "fields": [
10537
    {"bits": [0, 5], "name": "VGPRS"},
10538
    {"bits": [6, 9], "name": "SGPRS"},
10539
    {"bits": [10, 11], "name": "PRIORITY"},
10540
    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
10541
    {"bits": [20, 20], "name": "PRIV"},
10542
    {"bits": [21, 21], "name": "DX10_CLAMP"},
10543
    {"bits": [22, 22], "name": "DEBUG_MODE"},
10544
    {"bits": [23, 23], "name": "IEEE_MODE"},
10545
    {"bits": [24, 24], "name": "BULKY"},
10546
    {"bits": [25, 25], "name": "CDBG_USER"},
10547
    {"bits": [26, 26], "name": "FP16_OVFL"}
10548
   ]
10549
  },
10550
  "COMPUTE_PGM_RSRC2": {
10551
   "fields": [
10552
    {"bits": [0, 0], "name": "SCRATCH_EN"},
10553
    {"bits": [1, 5], "name": "USER_SGPR"},
10554
    {"bits": [6, 6], "name": "TRAP_PRESENT"},
10555
    {"bits": [7, 7], "name": "TGID_X_EN"},
10556
    {"bits": [8, 8], "name": "TGID_Y_EN"},
10557
    {"bits": [9, 9], "name": "TGID_Z_EN"},
10558
    {"bits": [10, 10], "name": "TG_SIZE_EN"},
10559
    {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
10560
    {"bits": [13, 14], "name": "EXCP_EN_MSB"},
10561
    {"bits": [15, 23], "name": "LDS_SIZE"},
10562
    {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
10563
    {"bits": [31, 31], "name": "SKIP_USGPR0"}
10564
   ]
10565
  },
10566
  "COMPUTE_PIPELINESTAT_ENABLE": {
10567
   "fields": [
10568
    {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
10569
   ]
10570
  },
10571
  "COMPUTE_RELAUNCH": {
10572
   "fields": [
10573
    {"bits": [0, 29], "name": "PAYLOAD"},
10574
    {"bits": [30, 30], "name": "IS_EVENT"},
10575
    {"bits": [31, 31], "name": "IS_STATE"}
10576
   ]
10577
  },
10578
  "COMPUTE_RESOURCE_LIMITS": {
10579
   "fields": [
10580
    {"bits": [0, 9], "name": "WAVES_PER_SH"},
10581
    {"bits": [12, 15], "name": "TG_PER_CU"},
10582
    {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
10583
    {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
10584
    {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
10585
    {"bits": [24, 26], "name": "CU_GROUP_COUNT"},
10586
    {"bits": [27, 30], "name": "SIMD_DISABLE"}
10587
   ]
10588
  },
10589
  "COMPUTE_STATIC_THREAD_MGMT_SE0": {
10590
   "fields": [
10591
    {"bits": [0, 15], "name": "SH0_CU_EN"},
10592
    {"bits": [16, 31], "name": "SH1_CU_EN"}
10593
   ]
10594
  },
10595
  "COMPUTE_THREAD_TRACE_ENABLE": {
10596
   "fields": [
10597
    {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}
10598
   ]
10599
  },
10600
  "COMPUTE_TMPRING_SIZE": {
10601
   "fields": [
10602
    {"bits": [0, 11], "name": "WAVES"},
10603
    {"bits": [12, 24], "name": "WAVESIZE"}
10604
   ]
10605
  },
10606
  "COMPUTE_VMID": {
10607
   "fields": [
10608
    {"bits": [0, 3], "name": "DATA"}
10609
   ]
10610
  },
10611
  "COMPUTE_WAVE_RESTORE_ADDR_HI": {
10612
   "fields": [
10613
    {"bits": [0, 15], "name": "ADDR"}
10614
   ]
10615
  },
10616
  "CPC_LATENCY_STATS_SELECT": {
10617
   "fields": [
10618
    {"bits": [0, 2], "name": "INDEX"},
10619
    {"bits": [30, 30], "name": "CLEAR"},
10620
    {"bits": [31, 31], "name": "ENABLE"}
10621
   ]
10622
  },
10623
  "CPF_LATENCY_STATS_SELECT": {
10624
   "fields": [
10625
    {"bits": [0, 3], "name": "INDEX"},
10626
    {"bits": [30, 30], "name": "CLEAR"},
10627
    {"bits": [31, 31], "name": "ENABLE"}
10628
   ]
10629
  },
10630
  "CPF_TC_PERF_COUNTER_WINDOW_SELECT": {
10631
   "fields": [
10632
    {"bits": [0, 2], "name": "INDEX"},
10633
    {"bits": [30, 30], "name": "ALWAYS"},
10634
    {"bits": [31, 31], "name": "ENABLE"}
10635
   ]
10636
  },
10637
  "CPG_LATENCY_STATS_SELECT": {
10638
   "fields": [
10639
    {"bits": [0, 4], "name": "INDEX"},
10640
    {"bits": [30, 30], "name": "CLEAR"},
10641
    {"bits": [31, 31], "name": "ENABLE"}
10642
   ]
10643
  },
10644
  "CPG_PERFCOUNTER0_SELECT1": {
10645
   "fields": [
10646
    {"bits": [0, 9], "name": "CNTR_SEL2"},
10647
    {"bits": [10, 19], "name": "CNTR_SEL3"},
10648
    {"bits": [24, 27], "name": "CNTR_MODE3"},
10649
    {"bits": [28, 31], "name": "CNTR_MODE2"}
10650
   ]
10651
  },
10652
  "CPG_PERFCOUNTER1_SELECT": {
10653
   "fields": [
10654
    {"bits": [0, 9], "name": "CNTR_SEL0"},
10655
    {"bits": [10, 19], "name": "CNTR_SEL1"},
10656
    {"bits": [20, 23], "name": "SPM_MODE"},
10657
    {"bits": [24, 27], "name": "CNTR_MODE1"},
10658
    {"bits": [28, 31], "name": "CNTR_MODE0"}
10659
   ]
10660
  },
10661
  "CPG_TC_PERF_COUNTER_WINDOW_SELECT": {
10662
   "fields": [
10663
    {"bits": [0, 4], "name": "INDEX"},
10664
    {"bits": [30, 30], "name": "ALWAYS"},
10665
    {"bits": [31, 31], "name": "ENABLE"}
10666
   ]
10667
  },
10668
  "CP_APPEND_ADDR_HI": {
10669
   "fields": [
10670
    {"bits": [0, 15], "name": "MEM_ADDR_HI"},
10671
    {"bits": [16, 16], "name": "CS_PS_SEL"},
10672
    {"bits": [25, 25], "name": "CACHE_POLICY"},
10673
    {"bits": [29, 31], "name": "COMMAND"}
10674
   ]
10675
  },
10676
  "CP_APPEND_ADDR_LO": {
10677
   "fields": [
10678
    {"bits": [2, 31], "name": "MEM_ADDR_LO"}
10679
   ]
10680
  },
10681
  "CP_CE_IB1_BASE_HI": {
10682
   "fields": [
10683
    {"bits": [0, 15], "name": "IB1_BASE_HI"}
10684
   ]
10685
  },
10686
  "CP_CE_IB1_BASE_LO": {
10687
   "fields": [
10688
    {"bits": [2, 31], "name": "IB1_BASE_LO"}
10689
   ]
10690
  },
10691
  "CP_CE_IB1_BUFSZ": {
10692
   "fields": [
10693
    {"bits": [0, 19], "name": "IB1_BUFSZ"}
10694
   ]
10695
  },
10696
  "CP_CE_IB1_CMD_BUFSZ": {
10697
   "fields": [
10698
    {"bits": [0, 19], "name": "IB1_CMD_REQSZ"}
10699
   ]
10700
  },
10701
  "CP_CE_IB2_BASE_HI": {
10702
   "fields": [
10703
    {"bits": [0, 15], "name": "IB2_BASE_HI"}
10704
   ]
10705
  },
10706
  "CP_CE_IB2_BASE_LO": {
10707
   "fields": [
10708
    {"bits": [2, 31], "name": "IB2_BASE_LO"}
10709
   ]
10710
  },
10711
  "CP_CE_IB2_BUFSZ": {
10712
   "fields": [
10713
    {"bits": [0, 19], "name": "IB2_BUFSZ"}
10714
   ]
10715
  },
10716
  "CP_CE_IB2_CMD_BUFSZ": {
10717
   "fields": [
10718
    {"bits": [0, 19], "name": "IB2_CMD_REQSZ"}
10719
   ]
10720
  },
10721
  "CP_CE_INIT_BASE_HI": {
10722
   "fields": [
10723
    {"bits": [0, 15], "name": "INIT_BASE_HI"}
10724
   ]
10725
  },
10726
  "CP_CE_INIT_BASE_LO": {
10727
   "fields": [
10728
    {"bits": [5, 31], "name": "INIT_BASE_LO"}
10729
   ]
10730
  },
10731
  "CP_CE_INIT_BUFSZ": {
10732
   "fields": [
10733
    {"bits": [0, 11], "name": "INIT_BUFSZ"}
10734
   ]
10735
  },
10736
  "CP_CE_INIT_CMD_BUFSZ": {
10737
   "fields": [
10738
    {"bits": [0, 11], "name": "INIT_CMD_REQSZ"}
10739
   ]
10740
  },
10741
  "CP_COHER_BASE_HI": {
10742
   "fields": [
10743
    {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}
10744
   ]
10745
  },
10746
  "CP_COHER_CNTL": {
10747
   "fields": [
10748
    {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"},
10749
    {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"},
10750
    {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"},
10751
    {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
10752
    {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
10753
    {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
10754
    {"bits": [23, 23], "name": "TC_ACTION_ENA"},
10755
    {"bits": [25, 25], "name": "CB_ACTION_ENA"},
10756
    {"bits": [26, 26], "name": "DB_ACTION_ENA"},
10757
    {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
10758
    {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
10759
    {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"},
10760
    {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"}
10761
   ]
10762
  },
10763
  "CP_COHER_SIZE_HI": {
10764
   "fields": [
10765
    {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}
10766
   ]
10767
  },
10768
  "CP_COHER_START_DELAY": {
10769
   "fields": [
10770
    {"bits": [0, 5], "name": "START_DELAY_COUNT"}
10771
   ]
10772
  },
10773
  "CP_COHER_STATUS": {
10774
   "fields": [
10775
    {"bits": [24, 25], "name": "MEID"},
10776
    {"bits": [31, 31], "name": "STATUS"}
10777
   ]
10778
  },
10779
  "CP_CPC_BUSY_STAT": {
10780
   "fields": [
10781
    {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},
10782
    {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"},
10783
    {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},
10784
    {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},
10785
    {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},
10786
    {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},
10787
    {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},
10788
    {"bits": [7, 7], "name": "MEC1_TC_BUSY"},
10789
    {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},
10790
    {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},
10791
    {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},
10792
    {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},
10793
    {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},
10794
    {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},
10795
    {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},
10796
    {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"},
10797
    {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},
10798
    {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},
10799
    {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},
10800
    {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},
10801
    {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},
10802
    {"bits": [23, 23], "name": "MEC2_TC_BUSY"},
10803
    {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},
10804
    {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},
10805
    {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},
10806
    {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},
10807
    {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},
10808
    {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}
10809
   ]
10810
  },
10811
  "CP_CPC_GRBM_FREE_COUNT": {
10812
   "fields": [
10813
    {"bits": [0, 5], "name": "FREE_COUNT"}
10814
   ]
10815
  },
10816
  "CP_CPC_HALT_HYST_COUNT": {
10817
   "fields": [
10818
    {"bits": [0, 3], "name": "COUNT"}
10819
   ]
10820
  },
10821
  "CP_CPC_SCRATCH_INDEX": {
10822
   "fields": [
10823
    {"bits": [0, 8], "name": "SCRATCH_INDEX"}
10824
   ]
10825
  },
10826
  "CP_CPC_STALLED_STAT1": {
10827
   "fields": [
10828
    {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},
10829
    {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},
10830
    {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},
10831
    {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},
10832
    {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},
10833
    {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},
10834
    {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},
10835
    {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},
10836
    {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},
10837
    {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},
10838
    {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},
10839
    {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"},
10840
    {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"},
10841
    {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"}
10842
   ]
10843
  },
10844
  "CP_CPC_STATUS": {
10845
   "fields": [
10846
    {"bits": [0, 0], "name": "MEC1_BUSY"},
10847
    {"bits": [1, 1], "name": "MEC2_BUSY"},
10848
    {"bits": [2, 2], "name": "DC0_BUSY"},
10849
    {"bits": [3, 3], "name": "DC1_BUSY"},
10850
    {"bits": [4, 4], "name": "RCIU1_BUSY"},
10851
    {"bits": [5, 5], "name": "RCIU2_BUSY"},
10852
    {"bits": [6, 6], "name": "ROQ1_BUSY"},
10853
    {"bits": [7, 7], "name": "ROQ2_BUSY"},
10854
    {"bits": [10, 10], "name": "TCIU_BUSY"},
10855
    {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},
10856
    {"bits": [12, 12], "name": "QU_BUSY"},
10857
    {"bits": [13, 13], "name": "UTCL2IU_BUSY"},
10858
    {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"},
10859
    {"bits": [29, 29], "name": "CPG_CPC_BUSY"},
10860
    {"bits": [30, 30], "name": "CPF_CPC_BUSY"},
10861
    {"bits": [31, 31], "name": "CPC_BUSY"}
10862
   ]
10863
  },
10864
  "CP_CPF_BUSY_STAT": {
10865
   "fields": [
10866
    {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
10867
    {"bits": [1, 1], "name": "CSF_RING_BUSY"},
10868
    {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},
10869
    {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},
10870
    {"bits": [4, 4], "name": "CSF_STATE_BUSY"},
10871
    {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},
10872
    {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},
10873
    {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},
10874
    {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},
10875
    {"bits": [9, 9], "name": "OUTSTANDING_READ_TAGS"},
10876
    {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},
10877
    {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},
10878
    {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},
10879
    {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},
10880
    {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},
10881
    {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},
10882
    {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},
10883
    {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},
10884
    {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},
10885
    {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},
10886
    {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},
10887
    {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},
10888
    {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},
10889
    {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},
10890
    {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},
10891
    {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},
10892
    {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},
10893
    {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},
10894
    {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},
10895
    {"bits": [30, 30], "name": "HQD_PQ_BUSY"},
10896
    {"bits": [31, 31], "name": "HQD_IB_BUSY"}
10897
   ]
10898
  },
10899
  "CP_CPF_GRBM_FREE_COUNT": {
10900
   "fields": [
10901
    {"bits": [0, 2], "name": "FREE_COUNT"}
10902
   ]
10903
  },
10904
  "CP_CPF_STALLED_STAT1": {
10905
   "fields": [
10906
    {"bits": [0, 0], "name": "RING_FETCHING_DATA"},
10907
    {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},
10908
    {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},
10909
    {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},
10910
    {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},
10911
    {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},
10912
    {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"},
10913
    {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"},
10914
    {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"},
10915
    {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"},
10916
    {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"}
10917
   ]
10918
  },
10919
  "CP_CPF_STATUS": {
10920
   "fields": [
10921
    {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},
10922
    {"bits": [1, 1], "name": "CSF_BUSY"},
10923
    {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},
10924
    {"bits": [5, 5], "name": "ROQ_RING_BUSY"},
10925
    {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},
10926
    {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},
10927
    {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},
10928
    {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},
10929
    {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},
10930
    {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},
10931
    {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},
10932
    {"bits": [13, 13], "name": "INTERRUPT_BUSY"},
10933
    {"bits": [14, 14], "name": "TCIU_BUSY"},
10934
    {"bits": [15, 15], "name": "HQD_BUSY"},
10935
    {"bits": [16, 16], "name": "PRT_BUSY"},
10936
    {"bits": [17, 17], "name": "UTCL2IU_BUSY"},
10937
    {"bits": [26, 26], "name": "CPF_GFX_BUSY"},
10938
    {"bits": [27, 27], "name": "CPF_CMP_BUSY"},
10939
    {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},
10940
    {"bits": [30, 30], "name": "CPC_CPF_BUSY"},
10941
    {"bits": [31, 31], "name": "CPF_BUSY"}
10942
   ]
10943
  },
10944
  "CP_DMA_CNTL": {
10945
   "fields": [
10946
    {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"},
10947
    {"bits": [4, 5], "name": "MIN_AVAILSZ"},
10948
    {"bits": [16, 19], "name": "BUFFER_DEPTH"},
10949
    {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
10950
    {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
10951
    {"bits": [30, 31], "name": "PIO_COUNT"}
10952
   ]
10953
  },
10954
  "CP_DMA_ME_COMMAND": {
10955
   "fields": [
10956
    {"bits": [0, 25], "name": "BYTE_COUNT"},
10957
    {"bits": [26, 26], "name": "SAS"},
10958
    {"bits": [27, 27], "name": "DAS"},
10959
    {"bits": [28, 28], "name": "SAIC"},
10960
    {"bits": [29, 29], "name": "DAIC"},
10961
    {"bits": [30, 30], "name": "RAW_WAIT"},
10962
    {"bits": [31, 31], "name": "DIS_WC"}
10963
   ]
10964
  },
10965
  "CP_DMA_ME_DST_ADDR_HI": {
10966
   "fields": [
10967
    {"bits": [0, 15], "name": "DST_ADDR_HI"}
10968
   ]
10969
  },
10970
  "CP_DMA_ME_SRC_ADDR_HI": {
10971
   "fields": [
10972
    {"bits": [0, 15], "name": "SRC_ADDR_HI"}
10973
   ]
10974
  },
10975
  "CP_DMA_PFP_CONTROL": {
10976
   "fields": [
10977
    {"bits": [10, 10], "name": "MEMLOG_CLEAR"},
10978
    {"bits": [13, 13], "name": "SRC_CACHE_POLICY"},
10979
    {"bits": [20, 21], "name": "DST_SELECT"},
10980
    {"bits": [25, 25], "name": "DST_CACHE_POLICY"},
10981
    {"bits": [29, 30], "name": "SRC_SELECT"}
10982
   ]
10983
  },
10984
  "CP_DMA_READ_TAGS": {
10985
   "fields": [
10986
    {"bits": [0, 25], "name": "DMA_READ_TAG"},
10987
    {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
10988
   ]
10989
  },
10990
  "CP_DRAW_WINDOW_CNTL": {
10991
   "fields": [
10992
    {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},
10993
    {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},
10994
    {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},
10995
    {"bits": [8, 8], "name": "MODE"}
10996
   ]
10997
  },
10998
  "CP_DRAW_WINDOW_LO": {
10999
   "fields": [
11000
    {"bits": [0, 15], "name": "MIN"},
11001
    {"bits": [16, 31], "name": "MAX"}
11002
   ]
11003
  },
11004
  "CP_EOP_DONE_ADDR_HI": {
11005
   "fields": [
11006
    {"bits": [0, 15], "name": "ADDR_HI"}
11007
   ]
11008
  },
11009
  "CP_EOP_DONE_ADDR_LO": {
11010
   "fields": [
11011
    {"bits": [2, 31], "name": "ADDR_LO"}
11012
   ]
11013
  },
11014
  "CP_EOP_DONE_DATA_CNTL": {
11015
   "fields": [
11016
    {"bits": [16, 17], "name": "DST_SEL"},
11017
    {"bits": [24, 26], "name": "INT_SEL"},
11018
    {"bits": [29, 31], "name": "DATA_SEL"}
11019
   ]
11020
  },
11021
  "CP_EOP_DONE_EVENT_CNTL": {
11022
   "fields": [
11023
    {"bits": [0, 6], "name": "WBINV_TC_OP"},
11024
    {"bits": [12, 17], "name": "WBINV_ACTION_ENA"},
11025
    {"bits": [25, 25], "name": "CACHE_POLICY"},
11026
    {"bits": [28, 28], "name": "EXECUTE"}
11027
   ]
11028
  },
11029
  "CP_IB1_OFFSET": {
11030
   "fields": [
11031
    {"bits": [0, 19], "name": "IB1_OFFSET"}
11032
   ]
11033
  },
11034
  "CP_IB1_PREAMBLE_BEGIN": {
11035
   "fields": [
11036
    {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"}
11037
   ]
11038
  },
11039
  "CP_IB1_PREAMBLE_END": {
11040
   "fields": [
11041
    {"bits": [0, 19], "name": "IB1_PREAMBLE_END"}
11042
   ]
11043
  },
11044
  "CP_IB2_OFFSET": {
11045
   "fields": [
11046
    {"bits": [0, 19], "name": "IB2_OFFSET"}
11047
   ]
11048
  },
11049
  "CP_IB2_PREAMBLE_BEGIN": {
11050
   "fields": [
11051
    {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
11052
   ]
11053
  },
11054
  "CP_IB2_PREAMBLE_END": {
11055
   "fields": [
11056
    {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
11057
   ]
11058
  },
11059
  "CP_INDEX_TYPE": {
11060
   "fields": [
11061
    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
11062
   ]
11063
  },
11064
  "CP_ME_COHER_CNTL": {
11065
   "fields": [
11066
    {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
11067
    {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
11068
    {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
11069
    {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
11070
    {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
11071
    {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
11072
    {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
11073
    {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
11074
    {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
11075
    {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
11076
    {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
11077
    {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
11078
    {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}
11079
   ]
11080
  },
11081
  "CP_ME_COHER_STATUS": {
11082
   "fields": [
11083
    {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
11084
    {"bits": [31, 31], "name": "STATUS"}
11085
   ]
11086
  },
11087
  "CP_ME_MC_RADDR_HI": {
11088
   "fields": [
11089
    {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},
11090
    {"bits": [22, 22], "name": "CACHE_POLICY"}
11091
   ]
11092
  },
11093
  "CP_ME_MC_RADDR_LO": {
11094
   "fields": [
11095
    {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
11096
   ]
11097
  },
11098
  "CP_ME_MC_WADDR_HI": {
11099
   "fields": [
11100
    {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},
11101
    {"bits": [22, 22], "name": "CACHE_POLICY"}
11102
   ]
11103
  },
11104
  "CP_ME_MC_WADDR_LO": {
11105
   "fields": [
11106
    {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
11107
   ]
11108
  },
11109
  "CP_PERFMON_CNTL": {
11110
   "fields": [
11111
    {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
11112
    {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
11113
    {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
11114
    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
11115
   ]
11116
  },
11117
  "CP_PERFMON_CNTX_CNTL": {
11118
   "fields": [
11119
    {"bits": [31, 31], "name": "PERFMON_ENABLE"}
11120
   ]
11121
  },
11122
  "CP_PFP_COMPLETION_STATUS": {
11123
   "fields": [
11124
    {"bits": [0, 1], "name": "STATUS"}
11125
   ]
11126
  },
11127
  "CP_PFP_IB_CONTROL": {
11128
   "fields": [
11129
    {"bits": [0, 7], "name": "IB_EN"}
11130
   ]
11131
  },
11132
  "CP_PFP_LOAD_CONTROL": {
11133
   "fields": [
11134
    {"bits": [0, 0], "name": "CONFIG_REG_EN"},
11135
    {"bits": [1, 1], "name": "CNTX_REG_EN"},
11136
    {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
11137
    {"bits": [24, 24], "name": "SH_CS_REG_EN"}
11138
   ]
11139
  },
11140
  "CP_PIPEID": {
11141
   "fields": [
11142
    {"bits": [0, 1], "name": "PIPE_ID"}
11143
   ]
11144
  },
11145
  "CP_PIPE_STATS_ADDR_HI": {
11146
   "fields": [
11147
    {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}
11148
   ]
11149
  },
11150
  "CP_PIPE_STATS_ADDR_LO": {
11151
   "fields": [
11152
    {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
11153
   ]
11154
  },
11155
  "CP_PIPE_STATS_CONTROL": {
11156
   "fields": [
11157
    {"bits": [25, 25], "name": "CACHE_POLICY"}
11158
   ]
11159
  },
11160
  "CP_PRED_NOT_VISIBLE": {
11161
   "fields": [
11162
    {"bits": [0, 0], "name": "NOT_VISIBLE"}
11163
   ]
11164
  },
11165
  "CP_RB_OFFSET": {
11166
   "fields": [
11167
    {"bits": [0, 19], "name": "RB_OFFSET"}
11168
   ]
11169
  },
11170
  "CP_SAMPLE_STATUS": {
11171
   "fields": [
11172
    {"bits": [0, 0], "name": "Z_PASS_ACITVE"},
11173
    {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},
11174
    {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},
11175
    {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},
11176
    {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},
11177
    {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},
11178
    {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},
11179
    {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}
11180
   ]
11181
  },
11182
  "CP_SCRATCH_INDEX": {
11183
   "fields": [
11184
    {"bits": [0, 7], "name": "SCRATCH_INDEX"}
11185
   ]
11186
  },
11187
  "CP_SIG_SEM_ADDR_HI": {
11188
   "fields": [
11189
    {"bits": [0, 15], "name": "SEM_ADDR_HI"},
11190
    {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
11191
    {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
11192
    {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
11193
    {"bits": [29, 31], "name": "SEM_SELECT"}
11194
   ]
11195
  },
11196
  "CP_SIG_SEM_ADDR_LO": {
11197
   "fields": [
11198
    {"bits": [0, 1], "name": "SEM_ADDR_SWAP"},
11199
    {"bits": [3, 31], "name": "SEM_ADDR_LO"}
11200
   ]
11201
  },
11202
  "CP_STREAM_OUT_ADDR_HI": {
11203
   "fields": [
11204
    {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"}
11205
   ]
11206
  },
11207
  "CP_STREAM_OUT_ADDR_LO": {
11208
   "fields": [
11209
    {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
11210
   ]
11211
  },
11212
  "CP_STRMOUT_CNTL": {
11213
   "fields": [
11214
    {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
11215
   ]
11216
  },
11217
  "CP_ST_BASE_HI": {
11218
   "fields": [
11219
    {"bits": [0, 15], "name": "ST_BASE_HI"}
11220
   ]
11221
  },
11222
  "CP_ST_BASE_LO": {
11223
   "fields": [
11224
    {"bits": [2, 31], "name": "ST_BASE_LO"}
11225
   ]
11226
  },
11227
  "CP_ST_BUFSZ": {
11228
   "fields": [
11229
    {"bits": [0, 19], "name": "ST_BUFSZ"}
11230
   ]
11231
  },
11232
  "CP_ST_CMD_BUFSZ": {
11233
   "fields": [
11234
    {"bits": [0, 19], "name": "ST_CMD_REQSZ"}
11235
   ]
11236
  },
11237
  "CP_VMID": {
11238
   "fields": [
11239
    {"bits": [0, 3], "name": "VMID"}
11240
   ]
11241
  },
11242
  "CS_COPY_STATE": {
11243
   "fields": [
11244
    {"bits": [0, 2], "name": "SRC_STATE_ID"}
11245
   ]
11246
  },
11247
  "DB_ALPHA_TO_MASK": {
11248
   "fields": [
11249
    {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
11250
    {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
11251
    {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
11252
    {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
11253
    {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
11254
    {"bits": [16, 16], "name": "OFFSET_ROUND"}
11255
   ]
11256
  },
11257
  "DB_COUNT_CONTROL": {
11258
   "fields": [
11259
    {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
11260
    {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
11261
    {"bits": [4, 6], "name": "SAMPLE_RATE"},
11262
    {"bits": [8, 11], "name": "ZPASS_ENABLE"},
11263
    {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
11264
    {"bits": [16, 19], "name": "SFAIL_ENABLE"},
11265
    {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
11266
    {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
11267
    {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
11268
   ]
11269
  },
11270
  "DB_DEPTH_CONTROL": {
11271
   "fields": [
11272
    {"bits": [0, 0], "name": "STENCIL_ENABLE"},
11273
    {"bits": [1, 1], "name": "Z_ENABLE"},
11274
    {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
11275
    {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
11276
    {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
11277
    {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
11278
    {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
11279
    {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
11280
    {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
11281
    {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
11282
   ]
11283
  },
11284
  "DB_DEPTH_SIZE": {
11285
   "fields": [
11286
    {"bits": [0, 13], "name": "X_MAX"},
11287
    {"bits": [16, 29], "name": "Y_MAX"}
11288
   ]
11289
  },
11290
  "DB_DEPTH_VIEW": {
11291
   "fields": [
11292
    {"bits": [0, 10], "name": "SLICE_START"},
11293
    {"bits": [13, 23], "name": "SLICE_MAX"},
11294
    {"bits": [24, 24], "name": "Z_READ_ONLY"},
11295
    {"bits": [25, 25], "name": "STENCIL_READ_ONLY"},
11296
    {"bits": [26, 29], "name": "MIPID"}
11297
   ]
11298
  },
11299
  "DB_DFSM_CONTROL": {
11300
   "fields": [
11301
    {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"},
11302
    {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"},
11303
    {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"}
11304
   ]
11305
  },
11306
  "DB_EQAA": {
11307
   "fields": [
11308
    {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
11309
    {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
11310
    {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
11311
    {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
11312
    {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
11313
    {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
11314
    {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
11315
    {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
11316
    {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
11317
    {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
11318
    {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
11319
    {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
11320
   ]
11321
  },
11322
  "DB_HTILE_DATA_BASE_HI": {
11323
   "fields": [
11324
    {"bits": [0, 7], "name": "BASE_HI"}
11325
   ]
11326
  },
11327
  "DB_HTILE_SURFACE": {
11328
   "fields": [
11329
    {"bits": [1, 1], "name": "FULL_CACHE"},
11330
    {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"},
11331
    {"bits": [3, 3], "name": "PRELOAD"},
11332
    {"bits": [4, 9], "name": "PREFETCH_WIDTH"},
11333
    {"bits": [10, 15], "name": "PREFETCH_HEIGHT"},
11334
    {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},
11335
    {"bits": [18, 18], "name": "PIPE_ALIGNED"},
11336
    {"bits": [19, 19], "name": "RB_ALIGNED"}
11337
   ]
11338
  },
11339
  "DB_OCCLUSION_COUNT0_HI": {
11340
   "fields": [
11341
    {"bits": [0, 30], "name": "COUNT_HI"}
11342
   ]
11343
  },
11344
  "DB_PRELOAD_CONTROL": {
11345
   "fields": [
11346
    {"bits": [0, 7], "name": "START_X"},
11347
    {"bits": [8, 15], "name": "START_Y"},
11348
    {"bits": [16, 23], "name": "MAX_X"},
11349
    {"bits": [24, 31], "name": "MAX_Y"}
11350
   ]
11351
  },
11352
  "DB_RENDER_CONTROL": {
11353
   "fields": [
11354
    {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
11355
    {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
11356
    {"bits": [2, 2], "name": "DEPTH_COPY"},
11357
    {"bits": [3, 3], "name": "STENCIL_COPY"},
11358
    {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
11359
    {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
11360
    {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
11361
    {"bits": [7, 7], "name": "COPY_CENTROID"},
11362
    {"bits": [8, 11], "name": "COPY_SAMPLE"},
11363
    {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"}
11364
   ]
11365
  },
11366
  "DB_RENDER_OVERRIDE": {
11367
   "fields": [
11368
    {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
11369
    {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
11370
    {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
11371
    {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
11372
    {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
11373
    {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
11374
    {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
11375
    {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
11376
    {"bits": [11, 11], "name": "FORCE_Z_READ"},
11377
    {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
11378
    {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
11379
    {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
11380
    {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
11381
    {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
11382
    {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
11383
    {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
11384
    {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
11385
    {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
11386
    {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
11387
    {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
11388
    {"bits": [29, 29], "name": "FORCE_Z_VALID"},
11389
    {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
11390
    {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
11391
   ]
11392
  },
11393
  "DB_RENDER_OVERRIDE2": {
11394
   "fields": [
11395
    {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
11396
    {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
11397
    {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
11398
    {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
11399
    {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
11400
    {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
11401
    {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
11402
    {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
11403
    {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
11404
    {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
11405
    {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
11406
    {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
11407
    {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
11408
    {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
11409
    {"bits": [23, 23], "name": "DISABLE_FAST_PASS"},
11410
    {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"}
11411
   ]
11412
  },
11413
  "DB_SHADER_CONTROL": {
11414
   "fields": [
11415
    {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
11416
    {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
11417
    {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
11418
    {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
11419
    {"bits": [6, 6], "name": "KILL_ENABLE"},
11420
    {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
11421
    {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
11422
    {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
11423
    {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
11424
    {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
11425
    {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
11426
    {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
11427
    {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"},
11428
    {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"},
11429
    {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"},
11430
    {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"}
11431
   ]
11432
  },
11433
  "DB_SRESULTS_COMPARE_STATE0": {
11434
   "fields": [
11435
    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
11436
    {"bits": [4, 11], "name": "COMPAREVALUE0"},
11437
    {"bits": [12, 19], "name": "COMPAREMASK0"},
11438
    {"bits": [24, 24], "name": "ENABLE0"}
11439
   ]
11440
  },
11441
  "DB_SRESULTS_COMPARE_STATE1": {
11442
   "fields": [
11443
    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
11444
    {"bits": [4, 11], "name": "COMPAREVALUE1"},
11445
    {"bits": [12, 19], "name": "COMPAREMASK1"},
11446
    {"bits": [24, 24], "name": "ENABLE1"}
11447
   ]
11448
  },
11449
  "DB_STENCILREFMASK": {
11450
   "fields": [
11451
    {"bits": [0, 7], "name": "STENCILTESTVAL"},
11452
    {"bits": [8, 15], "name": "STENCILMASK"},
11453
    {"bits": [16, 23], "name": "STENCILWRITEMASK"},
11454
    {"bits": [24, 31], "name": "STENCILOPVAL"}
11455
   ]
11456
  },
11457
  "DB_STENCILREFMASK_BF": {
11458
   "fields": [
11459
    {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
11460
    {"bits": [8, 15], "name": "STENCILMASK_BF"},
11461
    {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
11462
    {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
11463
   ]
11464
  },
11465
  "DB_STENCIL_CLEAR": {
11466
   "fields": [
11467
    {"bits": [0, 7], "name": "CLEAR"}
11468
   ]
11469
  },
11470
  "DB_STENCIL_CONTROL": {
11471
   "fields": [
11472
    {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
11473
    {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
11474
    {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
11475
    {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
11476
    {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
11477
    {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
11478
   ]
11479
  },
11480
  "DB_STENCIL_INFO": {
11481
   "fields": [
11482
    {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
11483
    {"bits": [4, 8], "name": "SW_MODE"},
11484
    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
11485
    {"bits": [13, 14], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
11486
    {"bits": [15, 15], "name": "ITERATE_FLUSH"},
11487
    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
11488
    {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"},
11489
    {"bits": [30, 30], "name": "CLEAR_DISALLOWED"}
11490
   ]
11491
  },
11492
  "DB_Z_INFO": {
11493
   "fields": [
11494
    {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
11495
    {"bits": [2, 3], "name": "NUM_SAMPLES"},
11496
    {"bits": [4, 8], "name": "SW_MODE"},
11497
    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
11498
    {"bits": [13, 14], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
11499
    {"bits": [15, 15], "name": "ITERATE_FLUSH"},
11500
    {"bits": [16, 19], "name": "MAXMIP"},
11501
    {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},
11502
    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
11503
    {"bits": [28, 28], "name": "READ_SIZE"},
11504
    {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
11505
    {"bits": [30, 30], "name": "CLEAR_DISALLOWED"},
11506
    {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
11507
   ]
11508
  },
11509
  "DB_Z_INFO2": {
11510
   "fields": [
11511
    {"bits": [0, 15], "name": "EPITCH"}
11512
   ]
11513
  },
11514
  "GB_ADDR_CONFIG": {
11515
   "fields": [
11516
    {"bits": [0, 2], "name": "NUM_PIPES"},
11517
    {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"},
11518
    {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"},
11519
    {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"},
11520
    {"bits": [12, 14], "enum_ref": "NumBanks", "name": "NUM_BANKS"},
11521
    {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"},
11522
    {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"},
11523
    {"bits": [21, 23], "name": "NUM_GPUS"},
11524
    {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"},
11525
    {"bits": [26, 27], "name": "NUM_RB_PER_SE"},
11526
    {"bits": [28, 29], "name": "ROW_SIZE"},
11527
    {"bits": [30, 30], "name": "NUM_LOWER_PIPES"},
11528
    {"bits": [31, 31], "name": "SE_ENABLE"}
11529
   ]
11530
  },
11531
  "GB_MACROTILE_MODE0": {
11532
   "fields": [
11533
    {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
11534
    {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
11535
    {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
11536
    {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
11537
   ]
11538
  },
11539
  "GB_TILE_MODE0": {
11540
   "fields": [
11541
    {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
11542
    {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
11543
    {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
11544
    {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},
11545
    {"bits": [25, 26], "name": "SAMPLE_SPLIT"}
11546
   ]
11547
  },
11548
  "GDS_ATOM_BASE": {
11549
   "fields": [
11550
    {"bits": [0, 15], "name": "BASE"},
11551
    {"bits": [16, 31], "name": "UNUSED"}
11552
   ]
11553
  },
11554
  "GDS_ATOM_CNTL": {
11555
   "fields": [
11556
    {"bits": [0, 5], "name": "AINC"},
11557
    {"bits": [6, 7], "name": "UNUSED1"},
11558
    {"bits": [8, 9], "name": "DMODE"},
11559
    {"bits": [10, 31], "name": "UNUSED2"}
11560
   ]
11561
  },
11562
  "GDS_ATOM_COMPLETE": {
11563
   "fields": [
11564
    {"bits": [0, 0], "name": "COMPLETE"},
11565
    {"bits": [1, 31], "name": "UNUSED"}
11566
   ]
11567
  },
11568
  "GDS_ATOM_OFFSET0": {
11569
   "fields": [
11570
    {"bits": [0, 7], "name": "OFFSET0"},
11571
    {"bits": [8, 31], "name": "UNUSED"}
11572
   ]
11573
  },
11574
  "GDS_ATOM_OFFSET1": {
11575
   "fields": [
11576
    {"bits": [0, 7], "name": "OFFSET1"},
11577
    {"bits": [8, 31], "name": "UNUSED"}
11578
   ]
11579
  },
11580
  "GDS_ATOM_OP": {
11581
   "fields": [
11582
    {"bits": [0, 7], "name": "OP"},
11583
    {"bits": [8, 31], "name": "UNUSED"}
11584
   ]
11585
  },
11586
  "GDS_ATOM_SIZE": {
11587
   "fields": [
11588
    {"bits": [0, 15], "name": "SIZE"},
11589
    {"bits": [16, 31], "name": "UNUSED"}
11590
   ]
11591
  },
11592
  "GDS_GWS_RESOURCE": {
11593
   "fields": [
11594
    {"bits": [0, 0], "name": "FLAG"},
11595
    {"bits": [1, 12], "name": "COUNTER"},
11596
    {"bits": [13, 13], "name": "TYPE"},
11597
    {"bits": [14, 14], "name": "DED"},
11598
    {"bits": [15, 15], "name": "RELEASE_ALL"},
11599
    {"bits": [16, 27], "name": "HEAD_QUEUE"},
11600
    {"bits": [28, 28], "name": "HEAD_VALID"},
11601
    {"bits": [29, 29], "name": "HEAD_FLAG"},
11602
    {"bits": [30, 30], "name": "HALTED"},
11603
    {"bits": [31, 31], "name": "UNUSED1"}
11604
   ]
11605
  },
11606
  "GDS_GWS_RESOURCE_CNT": {
11607
   "fields": [
11608
    {"bits": [0, 15], "name": "RESOURCE_CNT"},
11609
    {"bits": [16, 31], "name": "UNUSED"}
11610
   ]
11611
  },
11612
  "GDS_GWS_RESOURCE_CNTL": {
11613
   "fields": [
11614
    {"bits": [0, 5], "name": "INDEX"},
11615
    {"bits": [6, 31], "name": "UNUSED"}
11616
   ]
11617
  },
11618
  "GDS_OA_ADDRESS": {
11619
   "fields": [
11620
    {"bits": [0, 15], "name": "DS_ADDRESS"},
11621
    {"bits": [16, 19], "name": "CRAWLER"},
11622
    {"bits": [20, 21], "name": "CRAWLER_TYPE"},
11623
    {"bits": [22, 29], "name": "UNUSED"},
11624
    {"bits": [30, 30], "name": "NO_ALLOC"},
11625
    {"bits": [31, 31], "name": "ENABLE"}
11626
   ]
11627
  },
11628
  "GDS_OA_CNTL": {
11629
   "fields": [
11630
    {"bits": [0, 3], "name": "INDEX"},
11631
    {"bits": [4, 31], "name": "UNUSED"}
11632
   ]
11633
  },
11634
  "GDS_OA_INCDEC": {
11635
   "fields": [
11636
    {"bits": [0, 30], "name": "VALUE"},
11637
    {"bits": [31, 31], "name": "INCDEC"}
11638
   ]
11639
  },
11640
  "GRBM_GFX_INDEX": {
11641
   "fields": [
11642
    {"bits": [0, 7], "name": "INSTANCE_INDEX"},
11643
    {"bits": [8, 15], "name": "SH_INDEX"},
11644
    {"bits": [16, 23], "name": "SE_INDEX"},
11645
    {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"},
11646
    {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
11647
    {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
11648
   ]
11649
  },
11650
  "GRBM_PERFCOUNTER0_SELECT": {
11651
   "fields": [
11652
    {"bits": [0, 5], "name": "PERF_SEL"},
11653
    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
11654
    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
11655
    {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"},
11656
    {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
11657
    {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
11658
    {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
11659
    {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
11660
    {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
11661
    {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
11662
    {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
11663
    {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
11664
    {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
11665
    {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"},
11666
    {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
11667
    {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
11668
    {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
11669
    {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"},
11670
    {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"},
11671
    {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"},
11672
    {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"},
11673
    {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"}
11674
   ]
11675
  },
11676
  "GRBM_SE0_PERFCOUNTER_SELECT": {
11677
   "fields": [
11678
    {"bits": [0, 5], "name": "PERF_SEL"},
11679
    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
11680
    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
11681
    {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
11682
    {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
11683
    {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
11684
    {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
11685
    {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
11686
    {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
11687
    {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"},
11688
    {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
11689
    {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"},
11690
    {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"}
11691
   ]
11692
  },
11693
  "GRBM_STATUS": {
11694
   "fields": [
11695
    {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
11696
    {"bits": [5, 5], "name": "RSMU_RQ_PENDING"},
11697
    {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
11698
    {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
11699
    {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
11700
    {"bits": [12, 12], "name": "DB_CLEAN"},
11701
    {"bits": [13, 13], "name": "CB_CLEAN"},
11702
    {"bits": [14, 14], "name": "TA_BUSY"},
11703
    {"bits": [15, 15], "name": "GDS_BUSY"},
11704
    {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"},
11705
    {"bits": [17, 17], "name": "VGT_BUSY"},
11706
    {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"},
11707
    {"bits": [19, 19], "name": "IA_BUSY"},
11708
    {"bits": [20, 20], "name": "SX_BUSY"},
11709
    {"bits": [21, 21], "name": "WD_BUSY"},
11710
    {"bits": [22, 22], "name": "SPI_BUSY"},
11711
    {"bits": [23, 23], "name": "BCI_BUSY"},
11712
    {"bits": [24, 24], "name": "SC_BUSY"},
11713
    {"bits": [25, 25], "name": "PA_BUSY"},
11714
    {"bits": [26, 26], "name": "DB_BUSY"},
11715
    {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
11716
    {"bits": [29, 29], "name": "CP_BUSY"},
11717
    {"bits": [30, 30], "name": "CB_BUSY"},
11718
    {"bits": [31, 31], "name": "GUI_ACTIVE"}
11719
   ]
11720
  },
11721
  "GRBM_STATUS2": {
11722
   "fields": [
11723
    {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
11724
    {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
11725
    {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
11726
    {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
11727
    {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
11728
    {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
11729
    {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
11730
    {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
11731
    {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
11732
    {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
11733
    {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
11734
    {"bits": [14, 14], "name": "RLC_RQ_PENDING"},
11735
    {"bits": [15, 15], "name": "UTCL2_BUSY"},
11736
    {"bits": [16, 16], "name": "EA_BUSY"},
11737
    {"bits": [17, 17], "name": "RMI_BUSY"},
11738
    {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"},
11739
    {"bits": [19, 19], "name": "CPF_RQ_PENDING"},
11740
    {"bits": [20, 20], "name": "EA_LINK_BUSY"},
11741
    {"bits": [24, 24], "name": "RLC_BUSY"},
11742
    {"bits": [25, 25], "name": "TC_BUSY"},
11743
    {"bits": [26, 26], "name": "TCC_CC_RESIDENT"},
11744
    {"bits": [28, 28], "name": "CPF_BUSY"},
11745
    {"bits": [29, 29], "name": "CPC_BUSY"},
11746
    {"bits": [30, 30], "name": "CPG_BUSY"},
11747
    {"bits": [31, 31], "name": "CPAXI_BUSY"}
11748
   ]
11749
  },
11750
  "GRBM_STATUS_SE0": {
11751
   "fields": [
11752
    {"bits": [1, 1], "name": "DB_CLEAN"},
11753
    {"bits": [2, 2], "name": "CB_CLEAN"},
11754
    {"bits": [21, 21], "name": "RMI_BUSY"},
11755
    {"bits": [22, 22], "name": "BCI_BUSY"},
11756
    {"bits": [23, 23], "name": "VGT_BUSY"},
11757
    {"bits": [24, 24], "name": "PA_BUSY"},
11758
    {"bits": [25, 25], "name": "TA_BUSY"},
11759
    {"bits": [26, 26], "name": "SX_BUSY"},
11760
    {"bits": [27, 27], "name": "SPI_BUSY"},
11761
    {"bits": [29, 29], "name": "SC_BUSY"},
11762
    {"bits": [30, 30], "name": "DB_BUSY"},
11763
    {"bits": [31, 31], "name": "CB_BUSY"}
11764
   ]
11765
  },
11766
  "IA_MULTI_VGT_PARAM": {
11767
   "fields": [
11768
    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
11769
    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
11770
    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
11771
    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
11772
    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
11773
    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"},
11774
    {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"},
11775
    {"bits": [22, 22], "name": "EN_INST_OPT_ADV"},
11776
    {"bits": [23, 23], "name": "HW_USE_ONLY"}
11777
   ]
11778
  },
11779
  "IA_PERFCOUNTER0_SELECT": {
11780
   "fields": [
11781
    {"bits": [0, 9], "name": "PERF_SEL"},
11782
    {"bits": [10, 19], "name": "PERF_SEL1"},
11783
    {"bits": [20, 23], "name": "CNTR_MODE"},
11784
    {"bits": [24, 27], "name": "PERF_MODE1"},
11785
    {"bits": [28, 31], "name": "PERF_MODE"}
11786
   ]
11787
  },
11788
  "IA_PERFCOUNTER0_SELECT1": {
11789
   "fields": [
11790
    {"bits": [0, 9], "name": "PERF_SEL2"},
11791
    {"bits": [10, 19], "name": "PERF_SEL3"},
11792
    {"bits": [24, 27], "name": "PERF_MODE3"},
11793
    {"bits": [28, 31], "name": "PERF_MODE2"}
11794
   ]
11795
  },
11796
  "PA_CL_CLIP_CNTL": {
11797
   "fields": [
11798
    {"bits": [0, 0], "name": "UCP_ENA_0"},
11799
    {"bits": [1, 1], "name": "UCP_ENA_1"},
11800
    {"bits": [2, 2], "name": "UCP_ENA_2"},
11801
    {"bits": [3, 3], "name": "UCP_ENA_3"},
11802
    {"bits": [4, 4], "name": "UCP_ENA_4"},
11803
    {"bits": [5, 5], "name": "UCP_ENA_5"},
11804
    {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
11805
    {"bits": [14, 15], "name": "PS_UCP_MODE"},
11806
    {"bits": [16, 16], "name": "CLIP_DISABLE"},
11807
    {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
11808
    {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
11809
    {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
11810
    {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
11811
    {"bits": [21, 21], "name": "VTX_KILL_OR"},
11812
    {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
11813
    {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
11814
    {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
11815
    {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
11816
    {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"},
11817
    {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"}
11818
   ]
11819
  },
11820
  "PA_CL_NANINF_CNTL": {
11821
   "fields": [
11822
    {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
11823
    {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
11824
    {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
11825
    {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
11826
    {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
11827
    {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
11828
    {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
11829
    {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
11830
    {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
11831
    {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
11832
    {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
11833
    {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
11834
    {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
11835
    {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
11836
    {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
11837
    {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
11838
   ]
11839
  },
11840
  "PA_CL_NGG_CNTL": {
11841
   "fields": [
11842
    {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"},
11843
    {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"}
11844
   ]
11845
  },
11846
  "PA_CL_OBJPRIM_ID_CNTL": {
11847
   "fields": [
11848
    {"bits": [0, 0], "name": "OBJ_ID_SEL"},
11849
    {"bits": [1, 1], "name": "ADD_PIPED_PRIM_ID"},
11850
    {"bits": [2, 2], "name": "EN_32BIT_OBJPRIMID"}
11851
   ]
11852
  },
11853
  "PA_CL_VS_OUT_CNTL": {
11854
   "fields": [
11855
    {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
11856
    {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
11857
    {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
11858
    {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
11859
    {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
11860
    {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
11861
    {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
11862
    {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
11863
    {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
11864
    {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
11865
    {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
11866
    {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
11867
    {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
11868
    {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
11869
    {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
11870
    {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
11871
    {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
11872
    {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
11873
    {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
11874
    {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
11875
    {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
11876
    {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
11877
    {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
11878
    {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
11879
    {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
11880
    {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},
11881
    {"bits": [26, 26], "name": "USE_VTX_LINE_WIDTH"},
11882
    {"bits": [27, 27], "name": "USE_VTX_SHD_OBJPRIM_ID"}
11883
   ]
11884
  },
11885
  "PA_CL_VTE_CNTL": {
11886
   "fields": [
11887
    {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
11888
    {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
11889
    {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
11890
    {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
11891
    {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
11892
    {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
11893
    {"bits": [8, 8], "name": "VTX_XY_FMT"},
11894
    {"bits": [9, 9], "name": "VTX_Z_FMT"},
11895
    {"bits": [10, 10], "name": "VTX_W0_FMT"},
11896
    {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
11897
   ]
11898
  },
11899
  "PA_SC_AA_CONFIG": {
11900
   "fields": [
11901
    {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
11902
    {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
11903
    {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
11904
    {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
11905
    {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"},
11906
    {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"}
11907
   ]
11908
  },
11909
  "PA_SC_AA_MASK_X0Y0_X1Y0": {
11910
   "fields": [
11911
    {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
11912
    {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
11913
   ]
11914
  },
11915
  "PA_SC_AA_MASK_X0Y1_X1Y1": {
11916
   "fields": [
11917
    {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
11918
    {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
11919
   ]
11920
  },
11921
  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": {
11922
   "fields": [
11923
    {"bits": [0, 3], "name": "S0_X"},
11924
    {"bits": [4, 7], "name": "S0_Y"},
11925
    {"bits": [8, 11], "name": "S1_X"},
11926
    {"bits": [12, 15], "name": "S1_Y"},
11927
    {"bits": [16, 19], "name": "S2_X"},
11928
    {"bits": [20, 23], "name": "S2_Y"},
11929
    {"bits": [24, 27], "name": "S3_X"},
11930
    {"bits": [28, 31], "name": "S3_Y"}
11931
   ]
11932
  },
11933
  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": {
11934
   "fields": [
11935
    {"bits": [0, 3], "name": "S4_X"},
11936
    {"bits": [4, 7], "name": "S4_Y"},
11937
    {"bits": [8, 11], "name": "S5_X"},
11938
    {"bits": [12, 15], "name": "S5_Y"},
11939
    {"bits": [16, 19], "name": "S6_X"},
11940
    {"bits": [20, 23], "name": "S6_Y"},
11941
    {"bits": [24, 27], "name": "S7_X"},
11942
    {"bits": [28, 31], "name": "S7_Y"}
11943
   ]
11944
  },
11945
  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": {
11946
   "fields": [
11947
    {"bits": [0, 3], "name": "S8_X"},
11948
    {"bits": [4, 7], "name": "S8_Y"},
11949
    {"bits": [8, 11], "name": "S9_X"},
11950
    {"bits": [12, 15], "name": "S9_Y"},
11951
    {"bits": [16, 19], "name": "S10_X"},
11952
    {"bits": [20, 23], "name": "S10_Y"},
11953
    {"bits": [24, 27], "name": "S11_X"},
11954
    {"bits": [28, 31], "name": "S11_Y"}
11955
   ]
11956
  },
11957
  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": {
11958
   "fields": [
11959
    {"bits": [0, 3], "name": "S12_X"},
11960
    {"bits": [4, 7], "name": "S12_Y"},
11961
    {"bits": [8, 11], "name": "S13_X"},
11962
    {"bits": [12, 15], "name": "S13_Y"},
11963
    {"bits": [16, 19], "name": "S14_X"},
11964
    {"bits": [20, 23], "name": "S14_Y"},
11965
    {"bits": [24, 27], "name": "S15_X"},
11966
    {"bits": [28, 31], "name": "S15_Y"}
11967
   ]
11968
  },
11969
  "PA_SC_BINNER_CNTL_0": {
11970
   "fields": [
11971
    {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"},
11972
    {"bits": [2, 2], "name": "BIN_SIZE_X"},
11973
    {"bits": [3, 3], "name": "BIN_SIZE_Y"},
11974
    {"bits": [4, 6], "name": "BIN_SIZE_X_EXTEND"},
11975
    {"bits": [7, 9], "name": "BIN_SIZE_Y_EXTEND"},
11976
    {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"},
11977
    {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"},
11978
    {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"},
11979
    {"bits": [19, 26], "name": "FPOVS_PER_BATCH"},
11980
    {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"},
11981
    {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"}
11982
   ]
11983
  },
11984
  "PA_SC_BINNER_CNTL_1": {
11985
   "fields": [
11986
    {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"},
11987
    {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"}
11988
   ]
11989
  },
11990
  "PA_SC_CENTROID_PRIORITY_0": {
11991
   "fields": [
11992
    {"bits": [0, 3], "name": "DISTANCE_0"},
11993
    {"bits": [4, 7], "name": "DISTANCE_1"},
11994
    {"bits": [8, 11], "name": "DISTANCE_2"},
11995
    {"bits": [12, 15], "name": "DISTANCE_3"},
11996
    {"bits": [16, 19], "name": "DISTANCE_4"},
11997
    {"bits": [20, 23], "name": "DISTANCE_5"},
11998
    {"bits": [24, 27], "name": "DISTANCE_6"},
11999
    {"bits": [28, 31], "name": "DISTANCE_7"}
12000
   ]
12001
  },
12002
  "PA_SC_CENTROID_PRIORITY_1": {
12003
   "fields": [
12004
    {"bits": [0, 3], "name": "DISTANCE_8"},
12005
    {"bits": [4, 7], "name": "DISTANCE_9"},
12006
    {"bits": [8, 11], "name": "DISTANCE_10"},
12007
    {"bits": [12, 15], "name": "DISTANCE_11"},
12008
    {"bits": [16, 19], "name": "DISTANCE_12"},
12009
    {"bits": [20, 23], "name": "DISTANCE_13"},
12010
    {"bits": [24, 27], "name": "DISTANCE_14"},
12011
    {"bits": [28, 31], "name": "DISTANCE_15"}
12012
   ]
12013
  },
12014
  "PA_SC_CLIPRECT_0_TL": {
12015
   "fields": [
12016
    {"bits": [0, 14], "name": "TL_X"},
12017
    {"bits": [16, 30], "name": "TL_Y"}
12018
   ]
12019
  },
12020
  "PA_SC_CLIPRECT_RULE": {
12021
   "fields": [
12022
    {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
12023
   ]
12024
  },
12025
  "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL": {
12026
   "fields": [
12027
    {"bits": [0, 0], "name": "OVER_RAST_ENABLE"},
12028
    {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"},
12029
    {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"},
12030
    {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"},
12031
    {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"},
12032
    {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"},
12033
    {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"},
12034
    {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"},
12035
    {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"},
12036
    {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"},
12037
    {"bits": [16, 17], "name": "UNCERTAINTY_REGION_MODE"},
12038
    {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"},
12039
    {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"},
12040
    {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"},
12041
    {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"},
12042
    {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"},
12043
    {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"},
12044
    {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"}
12045
   ]
12046
  },
12047
  "PA_SC_EDGERULE": {
12048
   "fields": [
12049
    {"bits": [0, 3], "name": "ER_TRI"},
12050
    {"bits": [4, 7], "name": "ER_POINT"},
12051
    {"bits": [8, 11], "name": "ER_RECT"},
12052
    {"bits": [12, 17], "name": "ER_LINE_LR"},
12053
    {"bits": [18, 23], "name": "ER_LINE_RL"},
12054
    {"bits": [24, 27], "name": "ER_LINE_TB"},
12055
    {"bits": [28, 31], "name": "ER_LINE_BT"}
12056
   ]
12057
  },
12058
  "PA_SC_HORIZ_GRID": {
12059
   "fields": [
12060
    {"bits": [0, 7], "name": "TOP_QTR"},
12061
    {"bits": [8, 15], "name": "TOP_HALF"},
12062
    {"bits": [16, 23], "name": "BOT_HALF"},
12063
    {"bits": [24, 31], "name": "BOT_QTR"}
12064
   ]
12065
  },
12066
  "PA_SC_LINE_CNTL": {
12067
   "fields": [
12068
    {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
12069
    {"bits": [10, 10], "name": "LAST_PIXEL"},
12070
    {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
12071
    {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"},
12072
    {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"}
12073
   ]
12074
  },
12075
  "PA_SC_LINE_STIPPLE": {
12076
   "fields": [
12077
    {"bits": [0, 15], "name": "LINE_PATTERN"},
12078
    {"bits": [16, 23], "name": "REPEAT_COUNT"},
12079
    {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
12080
    {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
12081
   ]
12082
  },
12083
  "PA_SC_LINE_STIPPLE_STATE": {
12084
   "fields": [
12085
    {"bits": [0, 3], "name": "CURRENT_PTR"},
12086
    {"bits": [8, 15], "name": "CURRENT_COUNT"}
12087
   ]
12088
  },
12089
  "PA_SC_MODE_CNTL_0": {
12090
   "fields": [
12091
    {"bits": [0, 0], "name": "MSAA_ENABLE"},
12092
    {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
12093
    {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
12094
    {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"},
12095
    {"bits": [4, 4], "name": "SCALE_LINE_WIDTH_PAD"},
12096
    {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"},
12097
    {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"}
12098
   ]
12099
  },
12100
  "PA_SC_MODE_CNTL_1": {
12101
   "fields": [
12102
    {"bits": [0, 0], "name": "WALK_SIZE"},
12103
    {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
12104
    {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
12105
    {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
12106
    {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
12107
    {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
12108
    {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
12109
    {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
12110
    {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
12111
    {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
12112
    {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
12113
    {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
12114
    {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
12115
    {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
12116
    {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
12117
    {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
12118
    {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
12119
    {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
12120
    {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
12121
    {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
12122
    {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
12123
    {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
12124
    {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
12125
    {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
12126
   ]
12127
  },
12128
  "PA_SC_NGG_MODE_CNTL": {
12129
   "fields": [
12130
    {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"}
12131
   ]
12132
  },
12133
  "PA_SC_P3D_TRAP_SCREEN_H": {
12134
   "fields": [
12135
    {"bits": [0, 13], "name": "X_COORD"}
12136
   ]
12137
  },
12138
  "PA_SC_P3D_TRAP_SCREEN_HV_EN": {
12139
   "fields": [
12140
    {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},
12141
    {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}
12142
   ]
12143
  },
12144
  "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE": {
12145
   "fields": [
12146
    {"bits": [0, 15], "name": "COUNT"}
12147
   ]
12148
  },
12149
  "PA_SC_P3D_TRAP_SCREEN_V": {
12150
   "fields": [
12151
    {"bits": [0, 13], "name": "Y_COORD"}
12152
   ]
12153
  },
12154
  "PA_SC_PERFCOUNTER1_SELECT": {
12155
   "fields": [
12156
    {"bits": [0, 9], "name": "PERF_SEL"}
12157
   ]
12158
  },
12159
  "PA_SC_RASTER_CONFIG": {
12160
   "fields": [
12161
    {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
12162
    {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
12163
    {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
12164
    {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
12165
    {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
12166
    {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
12167
    {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
12168
    {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
12169
    {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
12170
    {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
12171
    {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
12172
    {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
12173
    {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
12174
    {"bits": [26, 28], "enum_ref": "SeXsel", "name": "SE_XSEL"},
12175
    {"bits": [29, 31], "enum_ref": "SeYsel", "name": "SE_YSEL"}
12176
   ]
12177
  },
12178
  "PA_SC_RASTER_CONFIG_1": {
12179
   "fields": [
12180
    {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
12181
    {"bits": [2, 4], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
12182
    {"bits": [5, 7], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
12183
   ]
12184
  },
12185
  "PA_SC_RIGHT_VERT_GRID": {
12186
   "fields": [
12187
    {"bits": [0, 7], "name": "LEFT_QTR"},
12188
    {"bits": [8, 15], "name": "LEFT_HALF"},
12189
    {"bits": [16, 23], "name": "RIGHT_HALF"},
12190
    {"bits": [24, 31], "name": "RIGHT_QTR"}
12191
   ]
12192
  },
12193
  "PA_SC_SCREEN_EXTENT_CONTROL": {
12194
   "fields": [
12195
    {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},
12196
    {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}
12197
   ]
12198
  },
12199
  "PA_SC_SCREEN_EXTENT_MIN_0": {
12200
   "fields": [
12201
    {"bits": [0, 15], "name": "X"},
12202
    {"bits": [16, 31], "name": "Y"}
12203
   ]
12204
  },
12205
  "PA_SC_SCREEN_SCISSOR_BR": {
12206
   "fields": [
12207
    {"bits": [0, 15], "name": "BR_X"},
12208
    {"bits": [16, 31], "name": "BR_Y"}
12209
   ]
12210
  },
12211
  "PA_SC_SCREEN_SCISSOR_TL": {
12212
   "fields": [
12213
    {"bits": [0, 15], "name": "TL_X"},
12214
    {"bits": [16, 31], "name": "TL_Y"}
12215
   ]
12216
  },
12217
  "PA_SC_SHADER_CONTROL": {
12218
   "fields": [
12219
    {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"},
12220
    {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"},
12221
    {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"}
12222
   ]
12223
  },
12224
  "PA_SC_TILE_STEERING_OVERRIDE": {
12225
   "fields": [
12226
    {"bits": [0, 0], "name": "ENABLE"},
12227
    {"bits": [1, 2], "name": "NUM_SE"},
12228
    {"bits": [5, 6], "name": "NUM_RB_PER_SE"}
12229
   ]
12230
  },
12231
  "PA_SC_WINDOW_OFFSET": {
12232
   "fields": [
12233
    {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
12234
    {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
12235
   ]
12236
  },
12237
  "PA_SC_WINDOW_SCISSOR_BR": {
12238
   "fields": [
12239
    {"bits": [0, 14], "name": "BR_X"},
12240
    {"bits": [16, 30], "name": "BR_Y"}
12241
   ]
12242
  },
12243
  "PA_SC_WINDOW_SCISSOR_TL": {
12244
   "fields": [
12245
    {"bits": [0, 14], "name": "TL_X"},
12246
    {"bits": [16, 30], "name": "TL_Y"},
12247
    {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
12248
   ]
12249
  },
12250
  "PA_STEREO_CNTL": {
12251
   "fields": [
12252
    {"bits": [0, 0], "name": "EN_STEREO"},
12253
    {"bits": [1, 4], "name": "STEREO_MODE"},
12254
    {"bits": [5, 7], "name": "RT_SLICE_MODE"},
12255
    {"bits": [8, 9], "name": "RT_SLICE_OFFSET"},
12256
    {"bits": [10, 12], "name": "VP_ID_MODE"},
12257
    {"bits": [13, 16], "name": "VP_ID_OFFSET"}
12258
   ]
12259
  },
12260
  "PA_SU_HARDWARE_SCREEN_OFFSET": {
12261
   "fields": [
12262
    {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
12263
    {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
12264
   ]
12265
  },
12266
  "PA_SU_LINE_CNTL": {
12267
   "fields": [
12268
    {"bits": [0, 15], "name": "WIDTH"}
12269
   ]
12270
  },
12271
  "PA_SU_LINE_STIPPLE_CNTL": {
12272
   "fields": [
12273
    {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
12274
    {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
12275
    {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
12276
    {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
12277
   ]
12278
  },
12279
  "PA_SU_LINE_STIPPLE_VALUE": {
12280
   "fields": [
12281
    {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
12282
   ]
12283
  },
12284
  "PA_SU_OVER_RASTERIZATION_CNTL": {
12285
   "fields": [
12286
    {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"},
12287
    {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"},
12288
    {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"},
12289
    {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"},
12290
    {"bits": [4, 4], "name": "USE_PROVOKING_ZW"}
12291
   ]
12292
  },
12293
  "PA_SU_PERFCOUNTER0_HI": {
12294
   "fields": [
12295
    {"bits": [0, 15], "name": "PERFCOUNTER_HI"}
12296
   ]
12297
  },
12298
  "PA_SU_PERFCOUNTER2_SELECT": {
12299
   "fields": [
12300
    {"bits": [0, 9], "name": "PERF_SEL"},
12301
    {"bits": [20, 23], "name": "CNTR_MODE"},
12302
    {"bits": [28, 31], "name": "PERF_MODE"}
12303
   ]
12304
  },
12305
  "PA_SU_POINT_MINMAX": {
12306
   "fields": [
12307
    {"bits": [0, 15], "name": "MIN_SIZE"},
12308
    {"bits": [16, 31], "name": "MAX_SIZE"}
12309
   ]
12310
  },
12311
  "PA_SU_POINT_SIZE": {
12312
   "fields": [
12313
    {"bits": [0, 15], "name": "HEIGHT"},
12314
    {"bits": [16, 31], "name": "WIDTH"}
12315
   ]
12316
  },
12317
  "PA_SU_POLY_OFFSET_DB_FMT_CNTL": {
12318
   "fields": [
12319
    {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
12320
    {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
12321
   ]
12322
  },
12323
  "PA_SU_PRIM_FILTER_CNTL": {
12324
   "fields": [
12325
    {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
12326
    {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
12327
    {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
12328
    {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
12329
    {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
12330
    {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
12331
    {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
12332
    {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
12333
    {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
12334
    {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
12335
    {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
12336
   ]
12337
  },
12338
  "PA_SU_SC_MODE_CNTL": {
12339
   "fields": [
12340
    {"bits": [0, 0], "name": "CULL_FRONT"},
12341
    {"bits": [1, 1], "name": "CULL_BACK"},
12342
    {"bits": [2, 2], "name": "FACE"},
12343
    {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
12344
    {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
12345
    {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
12346
    {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
12347
    {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
12348
    {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
12349
    {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
12350
    {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
12351
    {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
12352
    {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"},
12353
    {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"},
12354
    {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"}
12355
   ]
12356
  },
12357
  "PA_SU_SMALL_PRIM_FILTER_CNTL": {
12358
   "fields": [
12359
    {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"},
12360
    {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"},
12361
    {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"},
12362
    {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"},
12363
    {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"},
12364
    {"bits": [6, 6], "name": "SC_1XMSAA_COMPATIBLE_DISABLE"}
12365
   ]
12366
  },
12367
  "PA_SU_VTX_CNTL": {
12368
   "fields": [
12369
    {"bits": [0, 0], "name": "PIX_CENTER"},
12370
    {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
12371
    {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
12372
   ]
12373
  },
12374
  "RLC_GPM_PERF_COUNT_0": {
12375
   "fields": [
12376
    {"bits": [0, 3], "name": "FEATURE_SEL"},
12377
    {"bits": [4, 7], "name": "SE_INDEX"},
12378
    {"bits": [8, 11], "name": "SH_INDEX"},
12379
    {"bits": [12, 15], "name": "CU_INDEX"},
12380
    {"bits": [16, 17], "name": "EVENT_SEL"},
12381
    {"bits": [18, 19], "name": "UNUSED"},
12382
    {"bits": [20, 20], "name": "ENABLE"},
12383
    {"bits": [21, 31], "name": "RESERVED"}
12384
   ]
12385
  },
12386
  "RLC_GPU_IOV_PERF_CNT_CNTL": {
12387
   "fields": [
12388
    {"bits": [0, 0], "name": "ENABLE"},
12389
    {"bits": [1, 1], "name": "MODE_SELECT"},
12390
    {"bits": [2, 2], "name": "RESET"},
12391
    {"bits": [3, 31], "name": "RESERVED"}
12392
   ]
12393
  },
12394
  "RLC_GPU_IOV_PERF_CNT_WR_ADDR": {
12395
   "fields": [
12396
    {"bits": [0, 3], "name": "VFID"},
12397
    {"bits": [4, 5], "name": "CNT_ID"},
12398
    {"bits": [6, 31], "name": "RESERVED"}
12399
   ]
12400
  },
12401
  "RLC_PERFCOUNTER0_SELECT": {
12402
   "fields": [
12403
    {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}
12404
   ]
12405
  },
12406
  "RLC_PERFMON_CLK_CNTL_UCODE": {
12407
   "fields": [
12408
    {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"}
12409
   ]
12410
  },
12411
  "RLC_PERFMON_CNTL": {
12412
   "fields": [
12413
    {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
12414
    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
12415
   ]
12416
  },
12417
  "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY": {
12418
   "fields": [
12419
    {"bits": [0, 7], "name": "PERFMON_SAMPLE_DELAY"},
12420
    {"bits": [8, 31], "name": "RESERVED"}
12421
   ]
12422
  },
12423
  "RLC_SPM_PERFMON_CNTL": {
12424
   "fields": [
12425
    {"bits": [0, 11], "name": "RESERVED1"},
12426
    {"bits": [12, 13], "name": "PERFMON_RING_MODE"},
12427
    {"bits": [14, 15], "name": "RESERVED"},
12428
    {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}
12429
   ]
12430
  },
12431
  "RLC_SPM_PERFMON_RING_BASE_HI": {
12432
   "fields": [
12433
    {"bits": [0, 15], "name": "RING_BASE_HI"},
12434
    {"bits": [16, 31], "name": "RESERVED"}
12435
   ]
12436
  },
12437
  "RLC_SPM_PERFMON_SAMPLE_DELAY_MAX": {
12438
   "fields": [
12439
    {"bits": [0, 7], "name": "PERFMON_MAX_SAMPLE_DELAY"},
12440
    {"bits": [8, 31], "name": "RESERVED"}
12441
   ]
12442
  },
12443
  "RLC_SPM_PERFMON_SEGMENT_SIZE": {
12444
   "fields": [
12445
    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
12446
    {"bits": [8, 10], "name": "RESERVED1"},
12447
    {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"},
12448
    {"bits": [16, 20], "name": "SE0_NUM_LINE"},
12449
    {"bits": [21, 25], "name": "SE1_NUM_LINE"},
12450
    {"bits": [26, 30], "name": "SE2_NUM_LINE"},
12451
    {"bits": [31, 31], "name": "RESERVED"}
12452
   ]
12453
  },
12454
  "RMI_PERF_COUNTER_CNTL": {
12455
   "fields": [
12456
    {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"},
12457
    {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"},
12458
    {"bits": [4, 5], "name": "TC_PERF_EN_SEL"},
12459
    {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"},
12460
    {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"},
12461
    {"bits": [10, 13], "name": "PERF_COUNTER_CID"},
12462
    {"bits": [14, 18], "name": "PERF_COUNTER_VMID"},
12463
    {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"},
12464
    {"bits": [25, 25], "name": "PERF_SOFT_RESET"},
12465
    {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"}
12466
   ]
12467
  },
12468
  "SCRATCH_UMSK": {
12469
   "fields": [
12470
    {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
12471
    {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
12472
   ]
12473
  },
12474
  "SPI_BARYC_CNTL": {
12475
   "fields": [
12476
    {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
12477
    {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
12478
    {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
12479
    {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
12480
    {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
12481
    {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
12482
    {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
12483
   ]
12484
  },
12485
  "SPI_CONFIG_CNTL": {
12486
   "fields": [
12487
    {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
12488
    {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
12489
    {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
12490
    {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
12491
    {"bits": [26, 26], "name": "RSRC_MGMT_RESET"},
12492
    {"bits": [27, 27], "name": "TTRACE_STALL_ALL"},
12493
    {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"},
12494
    {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"},
12495
    {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"}
12496
   ]
12497
  },
12498
  "SPI_CONFIG_CNTL_1": {
12499
   "fields": [
12500
    {"bits": [0, 3], "name": "VTX_DONE_DELAY"},
12501
    {"bits": [4, 4], "name": "INTERP_ONE_PRIM_PER_ROW"},
12502
    {"bits": [5, 5], "name": "BATON_RESET_DISABLE"},
12503
    {"bits": [6, 6], "name": "PC_LIMIT_ENABLE"},
12504
    {"bits": [7, 7], "name": "PC_LIMIT_STRICT"},
12505
    {"bits": [8, 8], "name": "CRC_SIMD_ID_WADDR_DISABLE"},
12506
    {"bits": [9, 9], "name": "LBPW_CU_CHK_MODE"},
12507
    {"bits": [10, 13], "name": "LBPW_CU_CHK_CNT"},
12508
    {"bits": [14, 14], "name": "CSC_PWR_SAVE_DISABLE"},
12509
    {"bits": [15, 15], "name": "CSG_PWR_SAVE_DISABLE"},
12510
    {"bits": [16, 31], "name": "PC_LIMIT_SIZE"}
12511
   ]
12512
  },
12513
  "SPI_CONFIG_CNTL_2": {
12514
   "fields": [
12515
    {"bits": [0, 3], "name": "CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD"},
12516
    {"bits": [4, 7], "name": "CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD"}
12517
   ]
12518
  },
12519
  "SPI_INTERP_CONTROL_0": {
12520
   "fields": [
12521
    {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
12522
    {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
12523
    {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
12524
    {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
12525
    {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
12526
    {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
12527
    {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
12528
   ]
12529
  },
12530
  "SPI_PERFCOUNTER4_SELECT": {
12531
   "fields": [
12532
    {"bits": [0, 7], "name": "PERF_SEL"}
12533
   ]
12534
  },
12535
  "SPI_PERFCOUNTER_BINS": {
12536
   "fields": [
12537
    {"bits": [0, 3], "name": "BIN0_MIN"},
12538
    {"bits": [4, 7], "name": "BIN0_MAX"},
12539
    {"bits": [8, 11], "name": "BIN1_MIN"},
12540
    {"bits": [12, 15], "name": "BIN1_MAX"},
12541
    {"bits": [16, 19], "name": "BIN2_MIN"},
12542
    {"bits": [20, 23], "name": "BIN2_MAX"},
12543
    {"bits": [24, 27], "name": "BIN3_MIN"},
12544
    {"bits": [28, 31], "name": "BIN3_MAX"}
12545
   ]
12546
  },
12547
  "SPI_PS_INPUT_CNTL_0": {
12548
   "fields": [
12549
    {"bits": [0, 5], "name": "OFFSET"},
12550
    {"bits": [8, 9], "name": "DEFAULT_VAL"},
12551
    {"bits": [10, 10], "name": "FLAT_SHADE"},
12552
    {"bits": [13, 16], "name": "CYL_WRAP"},
12553
    {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
12554
    {"bits": [18, 18], "name": "DUP"},
12555
    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
12556
    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
12557
    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
12558
    {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},
12559
    {"bits": [24, 24], "name": "ATTR0_VALID"},
12560
    {"bits": [25, 25], "name": "ATTR1_VALID"}
12561
   ]
12562
  },
12563
  "SPI_PS_INPUT_CNTL_20": {
12564
   "fields": [
12565
    {"bits": [0, 5], "name": "OFFSET"},
12566
    {"bits": [8, 9], "name": "DEFAULT_VAL"},
12567
    {"bits": [10, 10], "name": "FLAT_SHADE"},
12568
    {"bits": [18, 18], "name": "DUP"},
12569
    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
12570
    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
12571
    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
12572
    {"bits": [24, 24], "name": "ATTR0_VALID"},
12573
    {"bits": [25, 25], "name": "ATTR1_VALID"}
12574
   ]
12575
  },
12576
  "SPI_PS_INPUT_ENA": {
12577
   "fields": [
12578
    {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
12579
    {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
12580
    {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
12581
    {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
12582
    {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
12583
    {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
12584
    {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
12585
    {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
12586
    {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
12587
    {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
12588
    {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
12589
    {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
12590
    {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
12591
    {"bits": [13, 13], "name": "ANCILLARY_ENA"},
12592
    {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
12593
    {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
12594
   ]
12595
  },
12596
  "SPI_PS_IN_CONTROL": {
12597
   "fields": [
12598
    {"bits": [0, 5], "name": "NUM_INTERP"},
12599
    {"bits": [6, 6], "name": "PARAM_GEN"},
12600
    {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"},
12601
    {"bits": [8, 8], "name": "LATE_PC_DEALLOC"},
12602
    {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"}
12603
   ]
12604
  },
12605
  "SPI_SHADER_COL_FORMAT": {
12606
   "fields": [
12607
    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
12608
    {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
12609
    {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
12610
    {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
12611
    {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
12612
    {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
12613
    {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
12614
    {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
12615
   ]
12616
  },
12617
  "SPI_SHADER_LATE_ALLOC_VS": {
12618
   "fields": [
12619
    {"bits": [0, 5], "name": "LIMIT"}
12620
   ]
12621
  },
12622
  "SPI_SHADER_PGM_HI_PS": {
12623
   "fields": [
12624
    {"bits": [0, 7], "name": "MEM_BASE"}
12625
   ]
12626
  },
12627
  "SPI_SHADER_PGM_RSRC1_GS": {
12628
   "fields": [
12629
    {"bits": [0, 5], "name": "VGPRS"},
12630
    {"bits": [6, 9], "name": "SGPRS"},
12631
    {"bits": [10, 11], "name": "PRIORITY"},
12632
    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
12633
    {"bits": [20, 20], "name": "PRIV"},
12634
    {"bits": [21, 21], "name": "DX10_CLAMP"},
12635
    {"bits": [22, 22], "name": "DEBUG_MODE"},
12636
    {"bits": [23, 23], "name": "IEEE_MODE"},
12637
    {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
12638
    {"bits": [28, 28], "name": "CDBG_USER"},
12639
    {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"},
12640
    {"bits": [31, 31], "name": "FP16_OVFL"}
12641
   ]
12642
  },
12643
  "SPI_SHADER_PGM_RSRC1_HS": {
12644
   "fields": [
12645
    {"bits": [0, 5], "name": "VGPRS"},
12646
    {"bits": [6, 9], "name": "SGPRS"},
12647
    {"bits": [10, 11], "name": "PRIORITY"},
12648
    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
12649
    {"bits": [20, 20], "name": "PRIV"},
12650
    {"bits": [21, 21], "name": "DX10_CLAMP"},
12651
    {"bits": [22, 22], "name": "DEBUG_MODE"},
12652
    {"bits": [23, 23], "name": "IEEE_MODE"},
12653
    {"bits": [27, 27], "name": "CDBG_USER"},
12654
    {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"},
12655
    {"bits": [30, 30], "name": "FP16_OVFL"}
12656
   ]
12657
  },
12658
  "SPI_SHADER_PGM_RSRC1_PS": {
12659
   "fields": [
12660
    {"bits": [0, 5], "name": "VGPRS"},
12661
    {"bits": [6, 9], "name": "SGPRS"},
12662
    {"bits": [10, 11], "name": "PRIORITY"},
12663
    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
12664
    {"bits": [20, 20], "name": "PRIV"},
12665
    {"bits": [21, 21], "name": "DX10_CLAMP"},
12666
    {"bits": [22, 22], "name": "DEBUG_MODE"},
12667
    {"bits": [23, 23], "name": "IEEE_MODE"},
12668
    {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
12669
    {"bits": [28, 28], "name": "CDBG_USER"},
12670
    {"bits": [29, 29], "name": "FP16_OVFL"}
12671
   ]
12672
  },
12673
  "SPI_SHADER_PGM_RSRC1_VS": {
12674
   "fields": [
12675
    {"bits": [0, 5], "name": "VGPRS"},
12676
    {"bits": [6, 9], "name": "SGPRS"},
12677
    {"bits": [10, 11], "name": "PRIORITY"},
12678
    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
12679
    {"bits": [20, 20], "name": "PRIV"},
12680
    {"bits": [21, 21], "name": "DX10_CLAMP"},
12681
    {"bits": [22, 22], "name": "DEBUG_MODE"},
12682
    {"bits": [23, 23], "name": "IEEE_MODE"},
12683
    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
12684
    {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
12685
    {"bits": [30, 30], "name": "CDBG_USER"},
12686
    {"bits": [31, 31], "name": "FP16_OVFL"}
12687
   ]
12688
  },
12689
  "SPI_SHADER_PGM_RSRC2_GS": {
12690
   "fields": [
12691
    {"bits": [0, 0], "name": "SCRATCH_EN"},
12692
    {"bits": [1, 5], "name": "USER_SGPR"},
12693
    {"bits": [6, 6], "name": "TRAP_PRESENT"},
12694
    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
12695
    {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"},
12696
    {"bits": [18, 18], "name": "OC_LDS_EN"},
12697
    {"bits": [19, 26], "name": "LDS_SIZE"},
12698
    {"bits": [27, 27], "name": "SKIP_USGPR0"},
12699
    {"bits": [28, 28], "name": "USER_SGPR_MSB"}
12700
   ]
12701
  },
12702
  "SPI_SHADER_PGM_RSRC2_GS_VS": {
12703
   "fields": [
12704
    {"bits": [0, 0], "name": "SCRATCH_EN"},
12705
    {"bits": [1, 5], "name": "USER_SGPR"},
12706
    {"bits": [6, 6], "name": "TRAP_PRESENT"},
12707
    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
12708
    {"bits": [16, 17], "name": "VGPR_COMP_CNT"},
12709
    {"bits": [18, 18], "name": "OC_LDS_EN"},
12710
    {"bits": [19, 26], "name": "LDS_SIZE"},
12711
    {"bits": [27, 27], "name": "SKIP_USGPR0"},
12712
    {"bits": [28, 28], "name": "USER_SGPR_MSB"}
12713
   ]
12714
  },
12715
  "SPI_SHADER_PGM_RSRC2_HS": {
12716
   "fields": [
12717
    {"bits": [0, 0], "name": "SCRATCH_EN"},
12718
    {"bits": [1, 5], "name": "USER_SGPR"},
12719
    {"bits": [6, 6], "name": "TRAP_PRESENT"},
12720
    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
12721
    {"bits": [16, 24], "name": "LDS_SIZE"},
12722
    {"bits": [27, 27], "name": "SKIP_USGPR0"},
12723
    {"bits": [28, 28], "name": "USER_SGPR_MSB"}
12724
   ]
12725
  },
12726
  "SPI_SHADER_PGM_RSRC2_PS": {
12727
   "fields": [
12728
    {"bits": [0, 0], "name": "SCRATCH_EN"},
12729
    {"bits": [1, 5], "name": "USER_SGPR"},
12730
    {"bits": [6, 6], "name": "TRAP_PRESENT"},
12731
    {"bits": [7, 7], "name": "WAVE_CNT_EN"},
12732
    {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
12733
    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
12734
    {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"},
12735
    {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"},
12736
    {"bits": [27, 27], "name": "SKIP_USGPR0"},
12737
    {"bits": [28, 28], "name": "USER_SGPR_MSB"}
12738
   ]
12739
  },
12740
  "SPI_SHADER_PGM_RSRC2_VS": {
12741
   "fields": [
12742
    {"bits": [0, 0], "name": "SCRATCH_EN"},
12743
    {"bits": [1, 5], "name": "USER_SGPR"},
12744
    {"bits": [6, 6], "name": "TRAP_PRESENT"},
12745
    {"bits": [7, 7], "name": "OC_LDS_EN"},
12746
    {"bits": [8, 8], "name": "SO_BASE0_EN"},
12747
    {"bits": [9, 9], "name": "SO_BASE1_EN"},
12748
    {"bits": [10, 10], "name": "SO_BASE2_EN"},
12749
    {"bits": [11, 11], "name": "SO_BASE3_EN"},
12750
    {"bits": [12, 12], "name": "SO_EN"},
12751
    {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
12752
    {"bits": [22, 22], "name": "PC_BASE_EN"},
12753
    {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"},
12754
    {"bits": [27, 27], "name": "SKIP_USGPR0"},
12755
    {"bits": [28, 28], "name": "USER_SGPR_MSB"}
12756
   ]
12757
  },
12758
  "SPI_SHADER_PGM_RSRC3_HS": {
12759
   "fields": [
12760
    {"bits": [0, 5], "name": "WAVE_LIMIT"},
12761
    {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},
12762
    {"bits": [10, 13], "name": "SIMD_DISABLE"},
12763
    {"bits": [16, 31], "name": "CU_EN"}
12764
   ]
12765
  },
12766
  "SPI_SHADER_PGM_RSRC3_PS": {
12767
   "fields": [
12768
    {"bits": [0, 15], "name": "CU_EN"},
12769
    {"bits": [16, 21], "name": "WAVE_LIMIT"},
12770
    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},
12771
    {"bits": [26, 29], "name": "SIMD_DISABLE"}
12772
   ]
12773
  },
12774
  "SPI_SHADER_PGM_RSRC4_GS": {
12775
   "fields": [
12776
    {"bits": [0, 6], "name": "GROUP_FIFO_DEPTH"},
12777
    {"bits": [7, 13], "name": "SPI_SHADER_LATE_ALLOC_GS"}
12778
   ]
12779
  },
12780
  "SPI_SHADER_PGM_RSRC4_HS": {
12781
   "fields": [
12782
    {"bits": [0, 6], "name": "GROUP_FIFO_DEPTH"}
12783
   ]
12784
  },
12785
  "SPI_SHADER_POS_FORMAT": {
12786
   "fields": [
12787
    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
12788
    {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
12789
    {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
12790
    {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"}
12791
   ]
12792
  },
12793
  "SPI_SHADER_Z_FORMAT": {
12794
   "fields": [
12795
    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
12796
   ]
12797
  },
12798
  "SPI_VS_OUT_CONFIG": {
12799
   "fields": [
12800
    {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
12801
    {"bits": [6, 6], "name": "VS_HALF_PACK"}
12802
   ]
12803
  },
12804
  "SPI_WAVE_LIMIT_CNTL": {
12805
   "fields": [
12806
    {"bits": [0, 1], "name": "PS_WAVE_GRAN"},
12807
    {"bits": [2, 3], "name": "VS_WAVE_GRAN"},
12808
    {"bits": [4, 5], "name": "GS_WAVE_GRAN"},
12809
    {"bits": [6, 7], "name": "HS_WAVE_GRAN"}
12810
   ]
12811
  },
12812
  "SQC_CACHES": {
12813
   "fields": [
12814
    {"bits": [0, 0], "name": "TARGET_INST"},
12815
    {"bits": [1, 1], "name": "TARGET_DATA"},
12816
    {"bits": [2, 2], "name": "INVALIDATE"},
12817
    {"bits": [3, 3], "name": "WRITEBACK"},
12818
    {"bits": [4, 4], "name": "VOL"},
12819
    {"bits": [16, 16], "name": "COMPLETE"}
12820
   ]
12821
  },
12822
  "SQC_WRITEBACK": {
12823
   "fields": [
12824
    {"bits": [0, 0], "name": "DWB"},
12825
    {"bits": [1, 1], "name": "DIRTY"}
12826
   ]
12827
  },
12828
  "SQ_BUF_RSRC_WORD1": {
12829
   "fields": [
12830
    {"bits": [0, 15], "name": "BASE_ADDRESS_HI"},
12831
    {"bits": [16, 29], "name": "STRIDE"},
12832
    {"bits": [30, 30], "name": "CACHE_SWIZZLE"},
12833
    {"bits": [31, 31], "name": "SWIZZLE_ENABLE"}
12834
   ]
12835
  },
12836
  "SQ_BUF_RSRC_WORD3": {
12837
   "fields": [
12838
    {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},
12839
    {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},
12840
    {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},
12841
    {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},
12842
    {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"},
12843
    {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"},
12844
    {"bits": [19, 19], "name": "USER_VM_ENABLE"},
12845
    {"bits": [20, 20], "name": "USER_VM_MODE"},
12846
    {"bits": [21, 22], "name": "INDEX_STRIDE"},
12847
    {"bits": [23, 23], "name": "ADD_TID_ENABLE"},
12848
    {"bits": [27, 27], "name": "NV"},
12849
    {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"}
12850
   ]
12851
  },
12852
  "SQ_IMG_RSRC_WORD1": {
12853
   "fields": [
12854
    {"bits": [0, 7], "name": "BASE_ADDRESS_HI"},
12855
    {"bits": [8, 19], "name": "MIN_LOD"},
12856
    {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"},
12857
    {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT_STENCIL", "name": "DATA_FORMAT_STENCIL"},
12858
    {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"},
12859
    {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT_FMASK", "name": "NUM_FORMAT_FMASK"},
12860
    {"bits": [30, 30], "name": "NV"},
12861
    {"bits": [31, 31], "name": "META_DIRECT"}
12862
   ]
12863
  },
12864
  "SQ_IMG_RSRC_WORD2": {
12865
   "fields": [
12866
    {"bits": [0, 13], "name": "WIDTH"},
12867
    {"bits": [14, 27], "name": "HEIGHT"},
12868
    {"bits": [28, 30], "name": "PERF_MOD"}
12869
   ]
12870
  },
12871
  "SQ_IMG_RSRC_WORD3": {
12872
   "fields": [
12873
    {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},
12874
    {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},
12875
    {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},
12876
    {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},
12877
    {"bits": [12, 15], "name": "BASE_LEVEL"},
12878
    {"bits": [16, 19], "name": "LAST_LEVEL"},
12879
    {"bits": [20, 24], "name": "SW_MODE"},
12880
    {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"}
12881
   ]
12882
  },
12883
  "SQ_IMG_RSRC_WORD4": {
12884
   "fields": [
12885
    {"bits": [0, 12], "name": "DEPTH"},
12886
    {"bits": [13, 28], "name": "PITCH"},
12887
    {"bits": [29, 31], "enum_ref": "SQ_IMG_RSRC_WORD4__BC_SWIZZLE", "name": "BC_SWIZZLE"}
12888
   ]
12889
  },
12890
  "SQ_IMG_RSRC_WORD5": {
12891
   "fields": [
12892
    {"bits": [0, 12], "name": "BASE_ARRAY"},
12893
    {"bits": [13, 16], "name": "ARRAY_PITCH"},
12894
    {"bits": [17, 24], "name": "META_DATA_ADDRESS"},
12895
    {"bits": [25, 25], "name": "META_LINEAR"},
12896
    {"bits": [26, 26], "name": "META_PIPE_ALIGNED"},
12897
    {"bits": [27, 27], "name": "META_RB_ALIGNED"},
12898
    {"bits": [28, 31], "name": "MAX_MIP"}
12899
   ]
12900
  },
12901
  "SQ_IMG_RSRC_WORD6": {
12902
   "fields": [
12903
    {"bits": [0, 11], "name": "MIN_LOD_WARN"},
12904
    {"bits": [12, 19], "name": "COUNTER_BANK_ID"},
12905
    {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"},
12906
    {"bits": [21, 21], "name": "COMPRESSION_EN"},
12907
    {"bits": [22, 22], "name": "ALPHA_IS_ON_MSB"},
12908
    {"bits": [23, 23], "name": "COLOR_TRANSFORM"},
12909
    {"bits": [24, 27], "name": "LOST_ALPHA_BITS"},
12910
    {"bits": [28, 31], "name": "LOST_COLOR_BITS"}
12911
   ]
12912
  },
12913
  "SQ_IMG_SAMP_WORD0": {
12914
   "fields": [
12915
    {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"},
12916
    {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"},
12917
    {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"},
12918
    {"bits": [9, 11], "name": "MAX_ANISO_RATIO"},
12919
    {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"},
12920
    {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"},
12921
    {"bits": [16, 18], "name": "ANISO_THRESHOLD"},
12922
    {"bits": [19, 19], "name": "MC_COORD_TRUNC"},
12923
    {"bits": [20, 20], "name": "FORCE_DEGAMMA"},
12924
    {"bits": [21, 26], "name": "ANISO_BIAS"},
12925
    {"bits": [27, 27], "name": "TRUNC_COORD"},
12926
    {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"},
12927
    {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"},
12928
    {"bits": [31, 31], "name": "COMPAT_MODE"}
12929
   ]
12930
  },
12931
  "SQ_IMG_SAMP_WORD1": {
12932
   "fields": [
12933
    {"bits": [0, 11], "name": "MIN_LOD"},
12934
    {"bits": [12, 23], "name": "MAX_LOD"},
12935
    {"bits": [24, 27], "name": "PERF_MIP"},
12936
    {"bits": [28, 31], "name": "PERF_Z"}
12937
   ]
12938
  },
12939
  "SQ_IMG_SAMP_WORD2": {
12940
   "fields": [
12941
    {"bits": [0, 13], "name": "LOD_BIAS"},
12942
    {"bits": [14, 19], "name": "LOD_BIAS_SEC"},
12943
    {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"},
12944
    {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"},
12945
    {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"},
12946
    {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"},
12947
    {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"},
12948
    {"bits": [29, 29], "name": "BLEND_ZERO_PRT"},
12949
    {"bits": [30, 30], "name": "FILTER_PREC_FIX"},
12950
    {"bits": [31, 31], "name": "ANISO_OVERRIDE"}
12951
   ]
12952
  },
12953
  "SQ_IMG_SAMP_WORD3": {
12954
   "fields": [
12955
    {"bits": [0, 11], "name": "BORDER_COLOR_PTR"},
12956
    {"bits": [12, 12], "name": "SKIP_DEGAMMA"},
12957
    {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"}
12958
   ]
12959
  },
12960
  "SQ_PERFCOUNTER0_SELECT": {
12961
   "fields": [
12962
    {"bits": [0, 8], "name": "PERF_SEL"},
12963
    {"bits": [12, 15], "name": "SQC_BANK_MASK"},
12964
    {"bits": [16, 19], "name": "SQC_CLIENT_MASK"},
12965
    {"bits": [20, 23], "name": "SPM_MODE"},
12966
    {"bits": [24, 27], "name": "SIMD_MASK"},
12967
    {"bits": [28, 31], "name": "PERF_MODE"}
12968
   ]
12969
  },
12970
  "SQ_PERFCOUNTER_CTRL": {
12971
   "fields": [
12972
    {"bits": [0, 0], "name": "PS_EN"},
12973
    {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
12974
    {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
12975
    {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
12976
    {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
12977
    {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
12978
    {"bits": [6, 6], "name": "CS_EN"},
12979
    {"bits": [8, 12], "name": "CNTR_RATE"},
12980
    {"bits": [13, 13], "name": "DISABLE_FLUSH"}
12981
   ]
12982
  },
12983
  "SQ_PERFCOUNTER_CTRL2": {
12984
   "fields": [
12985
    {"bits": [0, 0], "name": "FORCE_EN"}
12986
   ]
12987
  },
12988
  "SQ_THREAD_TRACE_BASE2": {
12989
   "fields": [
12990
    {"bits": [0, 3], "name": "ADDR_HI"}
12991
   ]
12992
  },
12993
  "SQ_THREAD_TRACE_CTRL": {
12994
   "fields": [
12995
    {"bits": [31, 31], "name": "RESET_BUFFER"}
12996
   ]
12997
  },
12998
  "SQ_THREAD_TRACE_HIWATER": {
12999
   "fields": [
13000
    {"bits": [0, 2], "name": "HIWATER"}
13001
   ]
13002
  },
13003
  "SQ_THREAD_TRACE_MASK": {
13004
   "fields": [
13005
    {"bits": [0, 4], "name": "CU_SEL"},
13006
    {"bits": [5, 5], "name": "SH_SEL"},
13007
    {"bits": [7, 7], "name": "REG_STALL_EN"},
13008
    {"bits": [8, 11], "name": "SIMD_EN"},
13009
    {"bits": [12, 13], "name": "VM_ID_MASK"},
13010
    {"bits": [14, 14], "name": "SPI_STALL_EN"},
13011
    {"bits": [15, 15], "name": "SQ_STALL_EN"}
13012
   ]
13013
  },
13014
  "SQ_THREAD_TRACE_MODE": {
13015
   "fields": [
13016
    {"bits": [0, 2], "name": "MASK_PS"},
13017
    {"bits": [3, 5], "name": "MASK_VS"},
13018
    {"bits": [6, 8], "name": "MASK_GS"},
13019
    {"bits": [9, 11], "name": "MASK_ES"},
13020
    {"bits": [12, 14], "name": "MASK_HS"},
13021
    {"bits": [15, 17], "name": "MASK_LS"},
13022
    {"bits": [18, 20], "name": "MASK_CS"},
13023
    {"bits": [21, 22], "name": "MODE"},
13024
    {"bits": [23, 24], "name": "CAPTURE_MODE"},
13025
    {"bits": [25, 25], "name": "AUTOFLUSH_EN"},
13026
    {"bits": [26, 26], "name": "TC_PERF_EN"},
13027
    {"bits": [27, 28], "name": "ISSUE_MASK"},
13028
    {"bits": [29, 29], "name": "TEST_MODE"},
13029
    {"bits": [30, 30], "name": "INTERRUPT_EN"},
13030
    {"bits": [31, 31], "name": "WRAP"}
13031
   ]
13032
  },
13033
  "SQ_THREAD_TRACE_PERF_MASK": {
13034
   "fields": [
13035
    {"bits": [0, 15], "name": "SH0_MASK"},
13036
    {"bits": [16, 31], "name": "SH1_MASK"}
13037
   ]
13038
  },
13039
  "SQ_THREAD_TRACE_SIZE": {
13040
   "fields": [
13041
    {"bits": [0, 21], "name": "SIZE"}
13042
   ]
13043
  },
13044
  "SQ_THREAD_TRACE_STATUS": {
13045
   "fields": [
13046
    {"bits": [0, 9], "name": "FINISH_PENDING"},
13047
    {"bits": [16, 25], "name": "FINISH_DONE"},
13048
    {"bits": [28, 28], "name": "UTC_ERROR"},
13049
    {"bits": [29, 29], "name": "NEW_BUF"},
13050
    {"bits": [30, 30], "name": "BUSY"},
13051
    {"bits": [31, 31], "name": "FULL"}
13052
   ]
13053
  },
13054
  "SQ_THREAD_TRACE_TOKEN_MASK": {
13055
   "fields": [
13056
    {"bits": [0, 15], "name": "TOKEN_MASK"},
13057
    {"bits": [16, 23], "name": "REG_MASK"},
13058
    {"bits": [24, 24], "name": "REG_DROP_ON_STALL"}
13059
   ]
13060
  },
13061
  "SQ_THREAD_TRACE_WPTR": {
13062
   "fields": [
13063
    {"bits": [0, 29], "name": "WPTR"},
13064
    {"bits": [30, 31], "name": "READ_OFFSET"}
13065
   ]
13066
  },
13067
  "SQ_WAVE_GPR_ALLOC": {
13068
   "fields": [
13069
    {"bits": [0, 5], "name": "VGPR_BASE"},
13070
    {"bits": [8, 13], "name": "VGPR_SIZE"},
13071
    {"bits": [16, 21], "name": "SGPR_BASE"},
13072
    {"bits": [24, 27], "name": "SGPR_SIZE"}
13073
   ]
13074
  },
13075
  "SQ_WAVE_HW_ID": {
13076
   "fields": [
13077
    {"bits": [0, 3], "name": "WAVE_ID"},
13078
    {"bits": [4, 5], "name": "SIMD_ID"},
13079
    {"bits": [6, 7], "name": "PIPE_ID"},
13080
    {"bits": [8, 11], "name": "CU_ID"},
13081
    {"bits": [12, 12], "name": "SH_ID"},
13082
    {"bits": [13, 14], "name": "SE_ID"},
13083
    {"bits": [16, 19], "name": "TG_ID"},
13084
    {"bits": [20, 23], "name": "VM_ID"},
13085
    {"bits": [24, 26], "name": "QUEUE_ID"},
13086
    {"bits": [27, 29], "name": "STATE_ID"},
13087
    {"bits": [30, 31], "name": "ME_ID"}
13088
   ]
13089
  },
13090
  "SQ_WAVE_IB_DBG0": {
13091
   "fields": [
13092
    {"bits": [0, 2], "name": "IBUF_ST"},
13093
    {"bits": [3, 3], "name": "PC_INVALID"},
13094
    {"bits": [4, 4], "name": "NEED_NEXT_DW"},
13095
    {"bits": [5, 7], "name": "NO_PREFETCH_CNT"},
13096
    {"bits": [8, 9], "name": "IBUF_RPTR"},
13097
    {"bits": [10, 11], "name": "IBUF_WPTR"},
13098
    {"bits": [16, 19], "name": "INST_STR_ST"},
13099
    {"bits": [24, 25], "name": "ECC_ST"},
13100
    {"bits": [26, 26], "name": "IS_HYB"},
13101
    {"bits": [27, 28], "name": "HYB_CNT"},
13102
    {"bits": [29, 29], "name": "KILL"},
13103
    {"bits": [30, 30], "name": "NEED_KILL_IFETCH"},
13104
    {"bits": [31, 31], "name": "NO_PREFETCH_CNT_HI"}
13105
   ]
13106
  },
13107
  "SQ_WAVE_IB_DBG1": {
13108
   "fields": [
13109
    {"bits": [0, 0], "name": "IXNACK"},
13110
    {"bits": [1, 1], "name": "XNACK"},
13111
    {"bits": [2, 2], "name": "TA_NEED_RESET"},
13112
    {"bits": [4, 8], "name": "XCNT"},
13113
    {"bits": [11, 15], "name": "QCNT"},
13114
    {"bits": [18, 22], "name": "RCNT"},
13115
    {"bits": [25, 31], "name": "MISC_CNT"}
13116
   ]
13117
  },
13118
  "SQ_WAVE_IB_STS": {
13119
   "fields": [
13120
    {"bits": [0, 3], "name": "VM_CNT"},
13121
    {"bits": [4, 6], "name": "EXP_CNT"},
13122
    {"bits": [8, 11], "name": "LGKM_CNT"},
13123
    {"bits": [12, 14], "name": "VALU_CNT"},
13124
    {"bits": [15, 15], "name": "FIRST_REPLAY"},
13125
    {"bits": [16, 20], "name": "RCNT"},
13126
    {"bits": [22, 23], "name": "VM_CNT_HI"}
13127
   ]
13128
  },
13129
  "SQ_WAVE_LDS_ALLOC": {
13130
   "fields": [
13131
    {"bits": [0, 7], "name": "LDS_BASE"},
13132
    {"bits": [12, 20], "name": "LDS_SIZE"}
13133
   ]
13134
  },
13135
  "SQ_WAVE_MODE": {
13136
   "fields": [
13137
    {"bits": [0, 3], "name": "FP_ROUND"},
13138
    {"bits": [4, 7], "name": "FP_DENORM"},
13139
    {"bits": [8, 8], "name": "DX10_CLAMP"},
13140
    {"bits": [9, 9], "name": "IEEE"},
13141
    {"bits": [10, 10], "name": "LOD_CLAMPED"},
13142
    {"bits": [11, 11], "name": "DEBUG_EN"},
13143
    {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
13144
    {"bits": [23, 23], "name": "FP16_OVFL"},
13145
    {"bits": [24, 24], "name": "POPS_PACKER0"},
13146
    {"bits": [25, 25], "name": "POPS_PACKER1"},
13147
    {"bits": [26, 26], "name": "DISABLE_PERF"},
13148
    {"bits": [27, 27], "name": "GPR_IDX_EN"},
13149
    {"bits": [28, 28], "name": "VSKIP"},
13150
    {"bits": [29, 31], "name": "CSP"}
13151
   ]
13152
  },
13153
  "SQ_WAVE_PC_HI": {
13154
   "fields": [
13155
    {"bits": [0, 15], "name": "PC_HI"}
13156
   ]
13157
  },
13158
  "SQ_WAVE_STATUS": {
13159
   "fields": [
13160
    {"bits": [0, 0], "name": "SCC"},
13161
    {"bits": [1, 2], "name": "SPI_PRIO"},
13162
    {"bits": [3, 4], "name": "USER_PRIO"},
13163
    {"bits": [5, 5], "name": "PRIV"},
13164
    {"bits": [6, 6], "name": "TRAP_EN"},
13165
    {"bits": [7, 7], "name": "TTRACE_EN"},
13166
    {"bits": [8, 8], "name": "EXPORT_RDY"},
13167
    {"bits": [9, 9], "name": "EXECZ"},
13168
    {"bits": [10, 10], "name": "VCCZ"},
13169
    {"bits": [11, 11], "name": "IN_TG"},
13170
    {"bits": [12, 12], "name": "IN_BARRIER"},
13171
    {"bits": [13, 13], "name": "HALT"},
13172
    {"bits": [14, 14], "name": "TRAP"},
13173
    {"bits": [15, 15], "name": "TTRACE_CU_EN"},
13174
    {"bits": [16, 16], "name": "VALID"},
13175
    {"bits": [17, 17], "name": "ECC_ERR"},
13176
    {"bits": [18, 18], "name": "SKIP_EXPORT"},
13177
    {"bits": [19, 19], "name": "PERF_EN"},
13178
    {"bits": [20, 20], "name": "COND_DBG_USER"},
13179
    {"bits": [21, 21], "name": "COND_DBG_SYS"},
13180
    {"bits": [22, 22], "name": "ALLOW_REPLAY"},
13181
    {"bits": [23, 23], "name": "FATAL_HALT"},
13182
    {"bits": [27, 27], "name": "MUST_EXPORT"}
13183
   ]
13184
  },
13185
  "SQ_WAVE_TRAPSTS": {
13186
   "fields": [
13187
    {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
13188
    {"bits": [10, 10], "name": "SAVECTX"},
13189
    {"bits": [11, 11], "name": "ILLEGAL_INST"},
13190
    {"bits": [12, 14], "name": "EXCP_HI"},
13191
    {"bits": [16, 21], "name": "EXCP_CYCLE"},
13192
    {"bits": [28, 28], "name": "XNACK_ERROR"},
13193
    {"bits": [29, 31], "name": "DP_RATE"}
13194
   ]
13195
  },
13196
  "SX_BLEND_OPT_CONTROL": {
13197
   "fields": [
13198
    {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
13199
    {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},
13200
    {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},
13201
    {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},
13202
    {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},
13203
    {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},
13204
    {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},
13205
    {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},
13206
    {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},
13207
    {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},
13208
    {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},
13209
    {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},
13210
    {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},
13211
    {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},
13212
    {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},
13213
    {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},
13214
    {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}
13215
   ]
13216
  },
13217
  "SX_BLEND_OPT_EPSILON": {
13218
   "fields": [
13219
    {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
13220
    {"bits": [4, 7], "name": "MRT1_EPSILON"},
13221
    {"bits": [8, 11], "name": "MRT2_EPSILON"},
13222
    {"bits": [12, 15], "name": "MRT3_EPSILON"},
13223
    {"bits": [16, 19], "name": "MRT4_EPSILON"},
13224
    {"bits": [20, 23], "name": "MRT5_EPSILON"},
13225
    {"bits": [24, 27], "name": "MRT6_EPSILON"},
13226
    {"bits": [28, 31], "name": "MRT7_EPSILON"}
13227
   ]
13228
  },
13229
  "SX_MRT0_BLEND_OPT": {
13230
   "fields": [
13231
    {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
13232
    {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
13233
    {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
13234
    {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
13235
    {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
13236
    {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
13237
   ]
13238
  },
13239
  "SX_PS_DOWNCONVERT": {
13240
   "fields": [
13241
    {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
13242
    {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
13243
    {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
13244
    {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
13245
    {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
13246
    {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
13247
    {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
13248
    {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
13249
   ]
13250
  },
13251
  "TA_BC_BASE_ADDR_HI": {
13252
   "fields": [
13253
    {"bits": [0, 7], "name": "ADDRESS"}
13254
   ]
13255
  },
13256
  "TA_PERFCOUNTER0_SELECT": {
13257
   "fields": [
13258
    {"bits": [0, 7], "name": "PERF_SEL"},
13259
    {"bits": [10, 17], "name": "PERF_SEL1"},
13260
    {"bits": [20, 23], "name": "CNTR_MODE"},
13261
    {"bits": [24, 27], "name": "PERF_MODE1"},
13262
    {"bits": [28, 31], "name": "PERF_MODE"}
13263
   ]
13264
  },
13265
  "TA_PERFCOUNTER0_SELECT1": {
13266
   "fields": [
13267
    {"bits": [0, 7], "name": "PERF_SEL2"},
13268
    {"bits": [10, 17], "name": "PERF_SEL3"},
13269
    {"bits": [24, 27], "name": "PERF_MODE3"},
13270
    {"bits": [28, 31], "name": "PERF_MODE2"}
13271
   ]
13272
  },
13273
  "TA_PERFCOUNTER1_SELECT": {
13274
   "fields": [
13275
    {"bits": [0, 7], "name": "PERF_SEL"},
13276
    {"bits": [20, 23], "name": "CNTR_MODE"},
13277
    {"bits": [28, 31], "name": "PERF_MODE"}
13278
   ]
13279
  },
13280
  "TCC_PERFCOUNTER0_SELECT1": {
13281
   "fields": [
13282
    {"bits": [0, 9], "name": "PERF_SEL2"},
13283
    {"bits": [10, 19], "name": "PERF_SEL3"},
13284
    {"bits": [24, 27], "name": "PERF_MODE2"},
13285
    {"bits": [28, 31], "name": "PERF_MODE3"}
13286
   ]
13287
  },
13288
  "VGT_DMA_BASE_HI": {
13289
   "fields": [
13290
    {"bits": [0, 15], "name": "BASE_ADDR"}
13291
   ]
13292
  },
13293
  "VGT_DMA_INDEX_TYPE": {
13294
   "fields": [
13295
    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
13296
    {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
13297
    {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
13298
    {"bits": [6, 6], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
13299
    {"bits": [8, 8], "name": "PRIMGEN_EN"},
13300
    {"bits": [9, 9], "name": "NOT_EOP"},
13301
    {"bits": [10, 10], "name": "REQ_PATH"}
13302
   ]
13303
  },
13304
  "VGT_DRAW_INITIATOR": {
13305
   "fields": [
13306
    {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
13307
    {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
13308
    {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
13309
    {"bits": [5, 5], "name": "NOT_EOP"},
13310
    {"bits": [6, 6], "name": "USE_OPAQUE"},
13311
    {"bits": [7, 7], "name": "UNROLLED_INST"},
13312
    {"bits": [8, 8], "name": "GRBM_SKEW_NO_DEC"},
13313
    {"bits": [29, 31], "name": "REG_RT_INDEX"}
13314
   ]
13315
  },
13316
  "VGT_DRAW_PAYLOAD_CNTL": {
13317
   "fields": [
13318
    {"bits": [0, 0], "name": "OBJPRIM_ID_EN"},
13319
    {"bits": [1, 1], "name": "EN_REG_RT_INDEX"},
13320
    {"bits": [2, 2], "name": "EN_PIPELINE_PRIMID"},
13321
    {"bits": [3, 3], "name": "OBJECT_ID_INST_EN"}
13322
   ]
13323
  },
13324
  "VGT_ESGS_RING_ITEMSIZE": {
13325
   "fields": [
13326
    {"bits": [0, 14], "name": "ITEMSIZE"}
13327
   ]
13328
  },
13329
  "VGT_ES_PER_GS": {
13330
   "fields": [
13331
    {"bits": [0, 10], "name": "ES_PER_GS"}
13332
   ]
13333
  },
13334
  "VGT_EVENT_ADDRESS_REG": {
13335
   "fields": [
13336
    {"bits": [0, 27], "name": "ADDRESS_LOW"}
13337
   ]
13338
  },
13339
  "VGT_EVENT_INITIATOR": {
13340
   "fields": [
13341
    {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
13342
    {"bits": [10, 26], "name": "ADDRESS_HI"},
13343
    {"bits": [27, 27], "name": "EXTENDED_EVENT"}
13344
   ]
13345
  },
13346
  "VGT_GROUP_DECR": {
13347
   "fields": [
13348
    {"bits": [0, 3], "name": "DECR"}
13349
   ]
13350
  },
13351
  "VGT_GROUP_FIRST_DECR": {
13352
   "fields": [
13353
    {"bits": [0, 3], "name": "FIRST_DECR"}
13354
   ]
13355
  },
13356
  "VGT_GROUP_PRIM_TYPE": {
13357
   "fields": [
13358
    {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
13359
    {"bits": [14, 14], "name": "RETAIN_ORDER"},
13360
    {"bits": [15, 15], "name": "RETAIN_QUADS"},
13361
    {"bits": [16, 18], "name": "PRIM_ORDER"}
13362
   ]
13363
  },
13364
  "VGT_GROUP_VECT_0_CNTL": {
13365
   "fields": [
13366
    {"bits": [0, 0], "name": "COMP_X_EN"},
13367
    {"bits": [1, 1], "name": "COMP_Y_EN"},
13368
    {"bits": [2, 2], "name": "COMP_Z_EN"},
13369
    {"bits": [3, 3], "name": "COMP_W_EN"},
13370
    {"bits": [8, 15], "name": "STRIDE"},
13371
    {"bits": [16, 23], "name": "SHIFT"}
13372
   ]
13373
  },
13374
  "VGT_GROUP_VECT_0_FMT_CNTL": {
13375
   "fields": [
13376
    {"bits": [0, 3], "name": "X_CONV"},
13377
    {"bits": [4, 7], "name": "X_OFFSET"},
13378
    {"bits": [8, 11], "name": "Y_CONV"},
13379
    {"bits": [12, 15], "name": "Y_OFFSET"},
13380
    {"bits": [16, 19], "name": "Z_CONV"},
13381
    {"bits": [20, 23], "name": "Z_OFFSET"},
13382
    {"bits": [24, 27], "name": "W_CONV"},
13383
    {"bits": [28, 31], "name": "W_OFFSET"}
13384
   ]
13385
  },
13386
  "VGT_GSVS_RING_OFFSET_1": {
13387
   "fields": [
13388
    {"bits": [0, 14], "name": "OFFSET"}
13389
   ]
13390
  },
13391
  "VGT_GS_INSTANCE_CNT": {
13392
   "fields": [
13393
    {"bits": [0, 0], "name": "ENABLE"},
13394
    {"bits": [2, 8], "name": "CNT"}
13395
   ]
13396
  },
13397
  "VGT_GS_MAX_PRIMS_PER_SUBGROUP": {
13398
   "fields": [
13399
    {"bits": [0, 15], "name": "MAX_PRIMS_PER_SUBGROUP"}
13400
   ]
13401
  },
13402
  "VGT_GS_MAX_VERT_OUT": {
13403
   "fields": [
13404
    {"bits": [0, 10], "name": "MAX_VERT_OUT"}
13405
   ]
13406
  },
13407
  "VGT_GS_MODE": {
13408
   "fields": [
13409
    {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
13410
    {"bits": [3, 3], "name": "RESERVED_0"},
13411
    {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
13412
    {"bits": [6, 10], "name": "RESERVED_1"},
13413
    {"bits": [11, 11], "name": "GS_C_PACK_EN"},
13414
    {"bits": [12, 12], "name": "RESERVED_2"},
13415
    {"bits": [13, 13], "name": "ES_PASSTHRU"},
13416
    {"bits": [14, 14], "name": "RESERVED_3"},
13417
    {"bits": [15, 15], "name": "RESERVED_4"},
13418
    {"bits": [16, 16], "name": "RESERVED_5"},
13419
    {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
13420
    {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
13421
    {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
13422
    {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
13423
    {"bits": [21, 22], "name": "ONCHIP"}
13424
   ]
13425
  },
13426
  "VGT_GS_ONCHIP_CNTL": {
13427
   "fields": [
13428
    {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"},
13429
    {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"},
13430
    {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"}
13431
   ]
13432
  },
13433
  "VGT_GS_OUT_PRIM_TYPE": {
13434
   "fields": [
13435
    {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
13436
    {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
13437
    {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
13438
    {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
13439
    {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
13440
   ]
13441
  },
13442
  "VGT_GS_PER_ES": {
13443
   "fields": [
13444
    {"bits": [0, 10], "name": "GS_PER_ES"}
13445
   ]
13446
  },
13447
  "VGT_GS_PER_VS": {
13448
   "fields": [
13449
    {"bits": [0, 3], "name": "GS_PER_VS"}
13450
   ]
13451
  },
13452
  "VGT_HOS_CNTL": {
13453
   "fields": [
13454
    {"bits": [0, 1], "name": "TESS_MODE"}
13455
   ]
13456
  },
13457
  "VGT_HOS_REUSE_DEPTH": {
13458
   "fields": [
13459
    {"bits": [0, 7], "name": "REUSE_DEPTH"}
13460
   ]
13461
  },
13462
  "VGT_HS_OFFCHIP_PARAM": {
13463
   "fields": [
13464
    {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"},
13465
    {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
13466
   ]
13467
  },
13468
  "VGT_INDEX_TYPE": {
13469
   "fields": [
13470
    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
13471
    {"bits": [8, 8], "name": "PRIMGEN_EN"}
13472
   ]
13473
  },
13474
  "VGT_LS_HS_CONFIG": {
13475
   "fields": [
13476
    {"bits": [0, 7], "name": "NUM_PATCHES"},
13477
    {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
13478
    {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
13479
   ]
13480
  },
13481
  "VGT_MULTI_PRIM_IB_RESET_EN": {
13482
   "fields": [
13483
    {"bits": [0, 0], "name": "RESET_EN"},
13484
    {"bits": [1, 1], "name": "MATCH_ALL_BITS"}
13485
   ]
13486
  },
13487
  "VGT_OUTPUT_PATH_CNTL": {
13488
   "fields": [
13489
    {"bits": [0, 2], "name": "PATH_SELECT"}
13490
   ]
13491
  },
13492
  "VGT_OUT_DEALLOC_CNTL": {
13493
   "fields": [
13494
    {"bits": [0, 6], "name": "DEALLOC_DIST"}
13495
   ]
13496
  },
13497
  "VGT_PERFCOUNTER_SEID_MASK": {
13498
   "fields": [
13499
    {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"}
13500
   ]
13501
  },
13502
  "VGT_PRIMITIVEID_EN": {
13503
   "fields": [
13504
    {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
13505
    {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"},
13506
    {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"}
13507
   ]
13508
  },
13509
  "VGT_PRIMITIVE_TYPE": {
13510
   "fields": [
13511
    {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
13512
   ]
13513
  },
13514
  "VGT_REUSE_OFF": {
13515
   "fields": [
13516
    {"bits": [0, 0], "name": "REUSE_OFF"}
13517
   ]
13518
  },
13519
  "VGT_SHADER_STAGES_EN": {
13520
   "fields": [
13521
    {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
13522
    {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
13523
    {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
13524
    {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
13525
    {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
13526
    {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"},
13527
    {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"},
13528
    {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"},
13529
    {"bits": [12, 12], "name": "VS_WAVE_ID_EN"},
13530
    {"bits": [13, 13], "name": "PRIMGEN_EN"},
13531
    {"bits": [14, 14], "name": "ORDERED_ID_MODE"},
13532
    {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"},
13533
    {"bits": [19, 20], "name": "GS_FAST_LAUNCH"}
13534
   ]
13535
  },
13536
  "VGT_STRMOUT_BUFFER_CONFIG": {
13537
   "fields": [
13538
    {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
13539
    {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
13540
    {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
13541
    {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
13542
   ]
13543
  },
13544
  "VGT_STRMOUT_CONFIG": {
13545
   "fields": [
13546
    {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
13547
    {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
13548
    {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
13549
    {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
13550
    {"bits": [4, 6], "name": "RAST_STREAM"},
13551
    {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"},
13552
    {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
13553
    {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
13554
   ]
13555
  },
13556
  "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": {
13557
   "fields": [
13558
    {"bits": [0, 8], "name": "VERTEX_STRIDE"}
13559
   ]
13560
  },
13561
  "VGT_STRMOUT_VTX_STRIDE_0": {
13562
   "fields": [
13563
    {"bits": [0, 9], "name": "STRIDE"}
13564
   ]
13565
  },
13566
  "VGT_TESS_DISTRIBUTION": {
13567
   "fields": [
13568
    {"bits": [0, 7], "name": "ACCUM_ISOLINE"},
13569
    {"bits": [8, 15], "name": "ACCUM_TRI"},
13570
    {"bits": [16, 23], "name": "ACCUM_QUAD"},
13571
    {"bits": [24, 28], "name": "DONUT_SPLIT"},
13572
    {"bits": [29, 31], "name": "TRAP_SPLIT"}
13573
   ]
13574
  },
13575
  "VGT_TF_PARAM": {
13576
   "fields": [
13577
    {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
13578
    {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
13579
    {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
13580
    {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
13581
    {"bits": [9, 9], "name": "DEPRECATED"},
13582
    {"bits": [14, 14], "name": "DISABLE_DONUTS"},
13583
    {"bits": [15, 15], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
13584
    {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"}
13585
   ]
13586
  },
13587
  "VGT_TF_RING_SIZE": {
13588
   "fields": [
13589
    {"bits": [0, 15], "name": "SIZE"}
13590
   ]
13591
  },
13592
  "VGT_VERTEX_REUSE_BLOCK_CNTL": {
13593
   "fields": [
13594
    {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
13595
   ]
13596
  },
13597
  "VGT_VTX_CNT_EN": {
13598
   "fields": [
13599
    {"bits": [0, 0], "name": "VTX_CNT_EN"}
13600
   ]
13601
  },
13602
  "WD_PERFCOUNTER0_SELECT": {
13603
   "fields": [
13604
    {"bits": [0, 7], "name": "PERF_SEL"},
13605
    {"bits": [28, 31], "name": "PERF_MODE"}
13606
   ]
13607
  }
13608
 }
13609
}
13610

13611
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