CoCalc -- parse_kernel

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/amd/registers/parse_kernel_headers.py
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#!/usr/bin/env python3
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import sys, io, re, json
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from canonicalize import json_canonicalize
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######### BEGIN HARDCODED CONFIGURATION
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gfx_versions = {
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    'gfx6': [
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        None,
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        'asic_reg/gca/gfx_6_0_d.h',
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        'asic_reg/gca/gfx_6_0_sh_mask.h',
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        'asic_reg/gca/gfx_7_2_enum.h' # the file for gfx6 doesn't exist
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    ],
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    'gfx7': [
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        None,
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        'asic_reg/gca/gfx_7_2_d.h',
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        'asic_reg/gca/gfx_7_2_sh_mask.h',
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        'asic_reg/gca/gfx_7_2_enum.h'
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    ],
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    'gfx8': [
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        None,
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        'asic_reg/gca/gfx_8_0_d.h',
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        'asic_reg/gca/gfx_8_0_sh_mask.h',
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        'asic_reg/gca/gfx_8_0_enum.h',
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    ],
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    'gfx81': [
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        None,
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        'asic_reg/gca/gfx_8_1_d.h',
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        'asic_reg/gca/gfx_8_1_sh_mask.h',
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        'asic_reg/gca/gfx_8_1_enum.h',
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    ],
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    'gfx9': [
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        'vega10_ip_offset.h',
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        'asic_reg/gc/gc_9_2_1_offset.h',
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        'asic_reg/gc/gc_9_2_1_sh_mask.h',
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        'vega10_enum.h',
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    ],
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    'gfx10': [
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        'navi14_ip_offset.h',
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        'asic_reg/gc/gc_10_1_0_offset.h',
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        'asic_reg/gc/gc_10_1_0_sh_mask.h',
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        'navi10_enum.h',
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    ],
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    'gfx103': [
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        'sienna_cichlid_ip_offset.h',
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        'asic_reg/gc/gc_10_3_0_offset.h',
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        'asic_reg/gc/gc_10_3_0_sh_mask.h',
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        'navi10_enum.h', # the file for gfx10.3 doesn't exist
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    ],
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}
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# match: static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
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re_base = re.compile(r'^static const struct IP_BASE.*GC_BASE\s*=\s*{ { { { (\w+), (\w+), (\w+), (\w+), (\w+).*} },\n')
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# match: #define mmSDMA0_DEC_START                              0x0000
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# match: #define ixSDMA0_DEC_START                              0x0000
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# match: #define regSDMA0_DEC_START                              0x0000
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re_offset = re.compile(r'^#define (?P<mm>(mm|ix|reg))(?P<name>\w+)\s+(?P<value>\w+)\n')
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# match: #define SDMA0_DEC_START__START__SHIFT                  0x0
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re_shift = re.compile(r'^#define (?P<name>\w+)__(?P<field>\w+)__SHIFT\s+(?P<value>\w+)\n')
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# match: #define SDMA0_DEC_START__START_MASK                    0xFFFFFFFFL
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# match: #define SDMA0_DEC_START__START_MASK                    0xFFFFFFFF
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re_mask = re.compile(r'^#define (?P<name>\w+)__(?P<field>\w+)_MASK\s+(?P<value>[0-9a-fA-Fx]+)L?\n')
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def register_filter(gfx_version, name, offset, already_added):
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    # Only accept writeable registers and debug registers
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    return ((offset // 0x1000 in [0xB, 0x28, 0x30, 0x31, 0x34, 0x35, 0x36, 0x37] or
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             # Add SQ_WAVE registers for trap handlers
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             name.startswith('SQ_WAVE_') or
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             # Add registers in the 0x8000 range used by all generations
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             (offset // 0x1000 == 0x8 and
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              (name.startswith('SQ_IMG_') or
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               name.startswith('SQ_BUF_') or
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               name.startswith('SQ_THREAD') or
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               name.startswith('GRBM_STATUS') or
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               name.startswith('CP_CP'))) or
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             # Add all registers in the 0x8000 range for gfx6
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             (gfx_version == 'gfx6' and offset // 0x1000 == 0x8) or
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             # Add registers in the 0x9000 range
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             (offset // 0x1000 == 0x9 and
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              (name in ['TA_CS_BC_BASE_ADDR', 'GB_ADDR_CONFIG', 'SPI_CONFIG_CNTL'] or
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               (name.startswith('GB') and 'TILE_MODE' in name)))) and
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            # Remove SQ compiler definitions
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            offset // 4 not in (0x23B0, 0x23B1, 0x237F) and
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            # Remove conflicts (multiple definitions for the same offset)
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            not already_added and
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            'PREF_PRI_ACCUM' not in name)
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# Mapping from field names to enum types
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enum_map = {
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    # Format:
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    #    field: [type1]                          - all registers use the same enum
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    # OR:
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    #    field: [type1, reg1, type2, reg2, ...]  - apply different enums to different registers
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    "ALPHA_COMB_FCN": ["CombFunc", "CB_BLEND0_CONTROL", "SX_OPT_COMB_FCN", "SX_MRT0_BLEND_OPT"],
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    "ALPHA_DESTBLEND": ["BlendOp"],
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    "ALPHA_DST_OPT": ["SX_BLEND_OPT"],
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    "ALPHA_SRCBLEND": ["BlendOp"],
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    "ALPHA_SRC_OPT": ["SX_BLEND_OPT"],
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    "ARRAY_MODE": ["ArrayMode"],
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    "BANK_HEIGHT": ["BankHeight"],
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    "BANK_WIDTH": ["BankWidth"],
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    "BC_SWIZZLE": ["SQ_IMG_RSRC_WORD4__BC_SWIZZLE"],
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    "BIN_MAPPING_MODE": ["BinMapMode"],
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    "BINNING_MODE": ["BinningMode"],
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    "BIN_SIZE_X_EXTEND": ["BinSizeExtend"],
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    "BIN_SIZE_Y_EXTEND": ["BinSizeExtend"],
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    "BLEND_OPT_DISCARD_PIXEL": ["BlendOpt"],
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    "BLEND_OPT_DONT_RD_DST": ["BlendOpt"],
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    "BORDER_COLOR_TYPE": ["SQ_TEX_BORDER_COLOR"],
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    "BUF_TYPE": ["VGT_DMA_BUF_TYPE"],
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    "CLAMP_X": ["SQ_TEX_CLAMP"],
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    "CLAMP_Y": ["SQ_TEX_CLAMP"],
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    "CLAMP_Z": ["SQ_TEX_CLAMP"],
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    "CLEAR_FILTER_SEL": ["CBPerfClearFilterSel"],
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    "CLIP_RULE": ["CLIP_RULE"],
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    "CMASK_ADDR_TYPE": ["CmaskAddr"],
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    "CMASK_RD_POLICY": ["ReadPolicy"],
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    "CMASK_WR_POLICY": ["WritePolicy"],
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    "COL0_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"],
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    "COL1_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"],
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    "COL2_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"],
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    "COL3_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"],
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    "COL4_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"],
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    "COL5_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"],
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    "COL6_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"],
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    "COL7_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"],
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    "COLOR_COMB_FCN": ["CombFunc", "CB_BLEND0_CONTROL", "SX_OPT_COMB_FCN", "SX_MRT0_BLEND_OPT"],
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    "COLOR_DESTBLEND": ["BlendOp"],
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    "COLOR_DST_OPT": ["SX_BLEND_OPT"],
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    "COLOR_RD_POLICY": ["ReadPolicy"],
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    "COLOR_SRCBLEND": ["BlendOp"],
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    "COLOR_SRC_OPT": ["SX_BLEND_OPT"],
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    "COLOR_WR_POLICY": ["WritePolicy"],
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    "COMPAREFUNC0": ["CompareFrag"],
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    "COMPAREFUNC1": ["CompareFrag"],
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    "COMP_SWAP": ["SurfaceSwap"],
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    "CONSERVATIVE_Z_EXPORT": ["ConservativeZExport"],
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    "COVERAGE_TO_SHADER_SELECT": ["CovToShaderSel"],
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    "CUT_MODE": ["VGT_GS_CUT_MODE"],
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    "DATA_FORMAT": ["BUF_DATA_FORMAT", "SQ_BUF_RSRC_WORD3", "IMG_DATA_FORMAT", "SQ_IMG_RSRC_WORD1"],
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    "DCC_RD_POLICY": ["ReadPolicy"],
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    "DCC_WR_POLICY": ["WritePolicy"],
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    "DEPTH_COMPARE_FUNC": ["SQ_TEX_DEPTH_COMPARE"],
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    "DETECT_ONE": ["VGT_DETECT_ONE"],
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    "DETECT_ZERO": ["VGT_DETECT_ZERO"],
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    "DISTRIBUTION_MODE": ["VGT_DIST_MODE"],
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    "DST_SEL_W": ["SQ_SEL_XYZW01"],
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    "DST_SEL_X": ["SQ_SEL_XYZW01"],
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    "DST_SEL_Y": ["SQ_SEL_XYZW01"],
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    "DST_SEL_Z": ["SQ_SEL_XYZW01"],
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    "ENDIAN": ["SurfaceEndian"],
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    "ES_EN": ["VGT_STAGES_ES_EN"],
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    "EVENT_TYPE": ["VGT_EVENT_TYPE"],
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    "EXCP": ["EXCP_EN"],
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    "EXCP_EN": ["EXCP_EN"],
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    "FAULT_BEHAVIOR": ["DbPRTFaultBehavior"],
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    "FILTER_MODE": ["SQ_IMG_FILTER_TYPE"],
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    "FLOAT_MODE": ["FLOAT_MODE"],
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    "FMASK_RD_POLICY": ["ReadPolicy"],
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    "FMASK_WR_POLICY": ["WritePolicy"],
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    "FORCE_FULL_Z_RANGE": ["ForceControl"],
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    "FORCE_HIS_ENABLE0": ["ForceControl"],
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    "FORCE_HIS_ENABLE1": ["ForceControl"],
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    "FORCE_HIZ_ENABLE": ["ForceControl"],
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    "FORCE_Z_LIMIT_SUMM": ["ZLimitSumm"],
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    "FORMAT": ["ColorFormat", "CB_COLOR0_INFO", "StencilFormat", "DB_STENCIL_INFO", "ZFormat", "DB_Z_INFO"],
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    "GS_EN": ["VGT_STAGES_GS_EN"],
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    "HIZ_ZFUNC": ["CompareFrag"],
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    "HS_EN": ["VGT_STAGES_HS_EN"],
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    "HTILE_RD_POLICY": ["ReadPolicy"],
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    "HTILE_WR_POLICY": ["WritePolicy"],
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    "IDX0_EXPORT_FORMAT": ["SPI_SHADER_FORMAT"],
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    "INDEX_TYPE": ["VGT_INDEX_TYPE_MODE"],
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    "LS_EN": ["VGT_STAGES_LS_EN"],
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    "MACRO_TILE_ASPECT": ["MacroTileAspect"],
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    "MAJOR_MODE": ["VGT_DI_MAJOR_MODE_SELECT"],
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    "MAX_UNCOMPRESSED_BLOCK_SIZE": ["CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE"],
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    "MICRO_TILE_MODE": ["GB_TILE_MODE0__MICRO_TILE_MODE"],
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    "MICRO_TILE_MODE_NEW": ["MicroTileMode"],
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    "MIN_COMPRESSED_BLOCK_SIZE": ["CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE"],
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    "MIP_FILTER": ["SQ_TEX_MIP_FILTER"],
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    "MODE": ["CBMode", "CB_COLOR_CONTROL", "VGT_GS_MODE_TYPE", "VGT_GS_MODE"],
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    "MRT0_EPSILON": ["SX_BLEND_OPT_EPSILON__MRT0_EPSILON"],
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    "MRT0": ["SX_DOWNCONVERT_FORMAT"],
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    "MRT1": ["SX_DOWNCONVERT_FORMAT"],
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    "MRT2": ["SX_DOWNCONVERT_FORMAT"],
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    "MRT3": ["SX_DOWNCONVERT_FORMAT"],
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    "MRT4": ["SX_DOWNCONVERT_FORMAT"],
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    "MRT5": ["SX_DOWNCONVERT_FORMAT"],
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    "MRT6": ["SX_DOWNCONVERT_FORMAT"],
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    "MRT7": ["SX_DOWNCONVERT_FORMAT"],
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    "NUM_BANKS": ["NumBanks"],
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    "NUM_FORMAT": ["BUF_NUM_FORMAT", "SQ_BUF_RSRC_WORD3", "IMG_NUM_FORMAT", "SQ_IMG_RSRC_WORD1"],
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    "NUMBER_TYPE": ["SurfaceNumber"],
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    "OFFCHIP_GRANULARITY": ["VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY"],
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    "OP_FILTER_SEL": ["CBPerfOpFilterSel"],
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    "OUTPRIM_TYPE_1": ["VGT_GS_OUTPRIM_TYPE"],
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    "OUTPRIM_TYPE_2": ["VGT_GS_OUTPRIM_TYPE"],
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    "OUTPRIM_TYPE_3": ["VGT_GS_OUTPRIM_TYPE"],
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    "OUTPRIM_TYPE": ["VGT_GS_OUTPRIM_TYPE"],
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    "PARTIAL_SQUAD_LAUNCH_CONTROL": ["DbPSLControl"],
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    "PARTITIONING": ["VGT_TESS_PARTITION"],
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    "PERFMON_ENABLE_MODE": ["CP_PERFMON_ENABLE_MODE"],
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    "PERFMON_STATE": ["CP_PERFMON_STATE"],
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    "PIPE_CONFIG": ["PipeConfig"],
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    "PKR_MAP": ["PkrMap"],
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    "PKR_XSEL2": ["PkrXsel2"],
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    "PKR_XSEL": ["PkrXsel"],
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    "PKR_YSEL": ["PkrYsel"],
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    "PNT_SPRITE_OVRD_W": ["SPI_PNT_SPRITE_OVERRIDE"],
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    "PNT_SPRITE_OVRD_X": ["SPI_PNT_SPRITE_OVERRIDE"],
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    "PNT_SPRITE_OVRD_Y": ["SPI_PNT_SPRITE_OVERRIDE"],
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    "PNT_SPRITE_OVRD_Z": ["SPI_PNT_SPRITE_OVERRIDE"],
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    "POLYMODE_BACK_PTYPE": ["PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE"],
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    "POLYMODE_FRONT_PTYPE": ["PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE"],
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    "POLY_MODE": ["PA_SU_SC_MODE_CNTL__POLY_MODE"],
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    "POS0_EXPORT_FORMAT": ["SPI_SHADER_FORMAT"],
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    "POS1_EXPORT_FORMAT": ["SPI_SHADER_FORMAT"],
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    "POS2_EXPORT_FORMAT": ["SPI_SHADER_FORMAT"],
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    "POS3_EXPORT_FORMAT": ["SPI_SHADER_FORMAT"],
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    "POS4_EXPORT_FORMAT": ["SPI_SHADER_FORMAT"],
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    "PRIM_TYPE": ["VGT_DI_PRIM_TYPE"],
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    "PUNCHOUT_MODE": ["DB_DFSM_CONTROL__PUNCHOUT_MODE"],
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    "QUANT_MODE": ["QUANT_MODE"],
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    "RB_MAP_PKR0": ["RbMap"],
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    "RB_MAP_PKR1": ["RbMap"],
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    "RB_XSEL2": ["RbXsel2"],
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    "RB_XSEL": ["RbXsel"],
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    "RB_YSEL": ["RbYsel"],
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    "ROP3": ["ROP3"],
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    "RDREQ_POLICY": ["VGT_RDREQ_POLICY"],
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    "REG_INCLUDE": ["ThreadTraceRegInclude"],
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    "ROUND_MODE": ["PA_SU_VTX_CNTL__ROUND_MODE", "PA_SU_VTX_CNTL"],
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    "SC_MAP": ["ScMap"],
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    "SC_XSEL": ["ScXsel"],
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    "SC_YSEL": ["ScYsel"],
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    "SE_MAP": ["SeMap"],
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    "SE_PAIR_MAP": ["SePairMap"],
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    "SE_PAIR_XSEL": ["SePairXsel"],
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    "SE_PAIR_YSEL": ["SePairYsel"],
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    "SE_XSEL": ["SeXsel"],
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    "SE_YSEL": ["SeYsel"],
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    "SOURCE_SELECT": ["VGT_DI_SOURCE_SELECT"],
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    "SPM_PERFMON_STATE": ["SPM_PERFMON_STATE"],
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    "S_RD_POLICY": ["ReadPolicy"],
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    "STENCILFAIL_BF": ["StencilOp"],
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    "STENCILFAIL": ["StencilOp"],
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    "STENCILFUNC_BF": ["CompareFrag"],
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    "STENCILFUNC": ["CompareFrag"],
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    "STENCILZFAIL_BF": ["StencilOp"],
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    "STENCILZFAIL": ["StencilOp"],
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    "STENCILZPASS_BF": ["StencilOp"],
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    "STENCILZPASS": ["StencilOp"],
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    "SWAP_MODE": ["VGT_DMA_SWAP_MODE"],
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    "S_WR_POLICY": ["WritePolicy"],
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    "TILE_SPLIT": ["TileSplit"],
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    "TOKEN_EXCLUDE": ["ThreadTraceTokenExclude"],
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    "TOPOLOGY": ["VGT_TESS_TOPOLOGY"],
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    "TYPE": ["SQ_RSRC_BUF_TYPE", "SQ_BUF_RSRC_WORD3", "SQ_RSRC_IMG_TYPE", "SQ_IMG_RSRC_WORD3", "VGT_TESS_TYPE", "VGT_TF_PARAM"],
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    "UNCERTAINTY_REGION_MODE": ["ScUncertaintyRegionMode"],
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    "VRS_HTILE_ENCODING": ["VRSHtileEncoding"],
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    "VS_EN": ["VGT_STAGES_VS_EN"],
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    "XY_MAG_FILTER": ["SQ_TEX_XY_FILTER"],
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    "XY_MIN_FILTER": ["SQ_TEX_XY_FILTER"],
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    "Z_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"],
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    "Z_FILTER": ["SQ_TEX_Z_FILTER"],
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    "ZFUNC": ["CompareFrag"],
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    "Z_ORDER": ["ZOrder"],
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    "ZPCPSD_WR_POLICY": ["WritePolicy"],
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    "Z_RD_POLICY": ["ReadPolicy"],
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    "Z_WR_POLICY": ["WritePolicy"],
276

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    "VERTEX_RATE_COMBINER_MODE": ["VRSCombinerMode"],
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    "PRIMITIVE_RATE_COMBINER_MODE": ["VRSCombinerMode"],
279
    "HTILE_RATE_COMBINER_MODE": ["VRSCombinerMode"],
280
    "SAMPLE_ITER_COMBINER_MODE": ["VRSCombinerMode"],
281
    "VRS_OVERRIDE_RATE_COMBINER_MODE": ["VRSCombinerMode"],
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}
283

284
# Enum definitions that are incomplete or missing in kernel headers
285
DB_DFSM_CONTROL__PUNCHOUT_MODE = {
286
 "entries": [
287
  {"name": "AUTO", "value": 0},
288
  {"name": "FORCE_ON", "value": 1},
289
  {"name": "FORCE_OFF", "value": 2},
290
  {"name": "RESERVED", "value": 3}
291
 ]
292
}
293

294
ColorFormat = {
295
 "entries": [
296
  {"name": "COLOR_INVALID", "value": 0},
297
  {"name": "COLOR_8", "value": 1},
298
  {"name": "COLOR_16", "value": 2},
299
  {"name": "COLOR_8_8", "value": 3},
300
  {"name": "COLOR_32", "value": 4},
301
  {"name": "COLOR_16_16", "value": 5},
302
  {"name": "COLOR_10_11_11", "value": 6},
303
  {"name": "COLOR_11_11_10", "value": 7},
304
  {"name": "COLOR_10_10_10_2", "value": 8},
305
  {"name": "COLOR_2_10_10_10", "value": 9},
306
  {"name": "COLOR_8_8_8_8", "value": 10},
307
  {"name": "COLOR_32_32", "value": 11},
308
  {"name": "COLOR_16_16_16_16", "value": 12},
309
  {"name": "COLOR_32_32_32_32", "value": 14},
310
  {"name": "COLOR_5_6_5", "value": 16},
311
  {"name": "COLOR_1_5_5_5", "value": 17},
312
  {"name": "COLOR_5_5_5_1", "value": 18},
313
  {"name": "COLOR_4_4_4_4", "value": 19},
314
  {"name": "COLOR_8_24", "value": 20},
315
  {"name": "COLOR_24_8", "value": 21},
316
  {"name": "COLOR_X24_8_32_FLOAT", "value": 22},
317
  {"name": "COLOR_5_9_9_9", "value": 24}
318
 ]
319
}
320

321
SQ_IMG_RSRC_WORD4__BC_SWIZZLE = {
322
 "entries": [
323
  {"name": "BC_SWIZZLE_XYZW", "value": 0},
324
  {"name": "BC_SWIZZLE_XWYZ", "value": 1},
325
  {"name": "BC_SWIZZLE_WZYX", "value": 2},
326
  {"name": "BC_SWIZZLE_WXYZ", "value": 3},
327
  {"name": "BC_SWIZZLE_ZYXW", "value": 4},
328
  {"name": "BC_SWIZZLE_YXWZ", "value": 5}
329
 ]
330
}
331

332
SX_DOWNCONVERT_FORMAT = {
333
 "entries": [
334
  {"name": "SX_RT_EXPORT_NO_CONVERSION", "value": 0},
335
  {"name": "SX_RT_EXPORT_32_R", "value": 1},
336
  {"name": "SX_RT_EXPORT_32_A", "value": 2},
337
  {"name": "SX_RT_EXPORT_10_11_11", "value": 3},
338
  {"name": "SX_RT_EXPORT_2_10_10_10", "value": 4},
339
  {"name": "SX_RT_EXPORT_8_8_8_8", "value": 5},
340
  {"name": "SX_RT_EXPORT_5_6_5", "value": 6},
341
  {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7},
342
  {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8},
343
  {"name": "SX_RT_EXPORT_16_16_GR", "value": 9},
344
  {"name": "SX_RT_EXPORT_16_16_AR", "value": 10},
345
  {"name": "SX_RT_EXPORT_9_9_9_E5", "value": 11}
346
 ]
347
}
348

349
ThreadTraceRegInclude = {
350
  "entries": [
351
   {"name": "REG_INCLUDE_SQDEC", "value": 1},
352
   {"name": "REG_INCLUDE_SHDEC", "value": 2},
353
   {"name": "REG_INCLUDE_GFXUDEC", "value": 4},
354
   {"name": "REG_INCLUDE_COMP", "value": 8},
355
   {"name": "REG_INCLUDE_CONTEXT", "value": 16},
356
   {"name": "REG_INCLUDE_CONFIG", "value": 32},
357
   {"name": "REG_INCLUDE_OTHER", "value": 64},
358
   {"name": "REG_INCLUDE_READS", "value": 128}
359
  ]
360
}
361

362
ThreadTraceTokenExclude = {
363
  "entries": [
364
   {"name": "TOKEN_EXCLUDE_VMEMEXEC", "value": 1},
365
   {"name": "TOKEN_EXCLUDE_ALUEXEC", "value": 2},
366
   {"name": "TOKEN_EXCLUDE_VALUINST", "value": 4},
367
   {"name": "TOKEN_EXCLUDE_WAVERDY", "value": 8},
368
   {"name": "TOKEN_EXCLUDE_IMMED1", "value": 16},
369
   {"name": "TOKEN_EXCLUDE_IMMEDIATE", "value": 32},
370
   {"name": "TOKEN_EXCLUDE_REG", "value": 64},
371
   {"name": "TOKEN_EXCLUDE_EVENT", "value": 128},
372
   {"name": "TOKEN_EXCLUDE_INST", "value": 256},
373
   {"name": "TOKEN_EXCLUDE_UTILCTR", "value": 512},
374
   {"name": "TOKEN_EXCLUDE_WAVEALLOC", "value": 1024},
375
   {"name": "TOKEN_EXCLUDE_PERF", "value": 2048}
376
  ]
377
}
378

379
GB_TILE_MODE0__MICRO_TILE_MODE = {
380
 "entries": [
381
  {"name": "ADDR_SURF_DISPLAY_MICRO_TILING", "value": 0},
382
  {"name": "ADDR_SURF_THIN_MICRO_TILING", "value": 1},
383
  {"name": "ADDR_SURF_DEPTH_MICRO_TILING", "value": 2},
384
  {"name": "ADDR_SURF_THICK_MICRO_TILING_GFX6", "value": 3}
385
 ]
386
}
387

388
IMG_DATA_FORMAT_STENCIL = {
389
 "entries": [
390
  {"name": "IMG_DATA_FORMAT_S8_16", "value": 59},
391
  {"name": "IMG_DATA_FORMAT_S8_32", "value": 60},
392
 ]
393
}
394

395
VRSCombinerMode = {
396
 "entries": [
397
  {"name": "VRS_COMB_MODE_PASSTHRU", "value": 0},
398
  {"name": "VRS_COMB_MODE_OVERRIDE", "value": 1},
399
  {"name": "VRS_COMB_MODE_MIN", "value": 2},
400
  {"name": "VRS_COMB_MODE_MAX", "value": 3},
401
  {"name": "VRS_COMB_MODE_SATURATE", "value": 4},
402
 ]
403
}
404

405
VRSHtileEncoding = {
406
 "entries": [
407
  {"name": "VRS_HTILE_DISABLE", "value": 0},
408
  {"name": "VRS_HTILE_2BIT_ENCODING", "value": 1},
409
  {"name": "VRS_HTILE_4BIT_ENCODING", "value": 2},
410
 ]
411
}
412

413
missing_enums_all = {
414
  'FLOAT_MODE': {
415
    "entries": [
416
      {"name": "FP_32_DENORMS", "value": 48},
417
      {"name": "FP_64_DENORMS", "value": 192},
418
      {"name": "FP_ALL_DENORMS", "value": 240}
419
    ]
420
  },
421
  'QUANT_MODE': {
422
    "entries": [
423
      {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},
424
      {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
425
      {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
426
      {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
427
      {"name": "X_16_8_FIXED_POINT_1", "value": 4},
428
      {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
429
      {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
430
      {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
431
    ]
432
  },
433
  "CLIP_RULE": {
434
   "entries": [
435
    {"name": "OUT", "value": 1},
436
    {"name": "IN_0", "value": 2},
437
    {"name": "IN_1", "value": 4},
438
    {"name": "IN_10", "value": 8},
439
    {"name": "IN_2", "value": 16},
440
    {"name": "IN_20", "value": 32},
441
    {"name": "IN_21", "value": 64},
442
    {"name": "IN_210", "value": 128},
443
    {"name": "IN_3", "value": 256},
444
    {"name": "IN_30", "value": 512},
445
    {"name": "IN_31", "value": 1024},
446
    {"name": "IN_310", "value": 2048},
447
    {"name": "IN_32", "value": 4096},
448
    {"name": "IN_320", "value": 8192},
449
    {"name": "IN_321", "value": 16384},
450
    {"name": "IN_3210", "value": 32768}
451
   ]
452
  },
453
  'PA_SU_VTX_CNTL__ROUND_MODE': {
454
    "entries": [
455
      {"name": "X_TRUNCATE", "value": 0},
456
      {"name": "X_ROUND", "value": 1},
457
      {"name": "X_ROUND_TO_EVEN", "value": 2},
458
      {"name": "X_ROUND_TO_ODD", "value": 3}
459
    ]
460
  },
461
  "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE": {
462
   "entries": [
463
    {"name": "X_DRAW_POINTS", "value": 0},
464
    {"name": "X_DRAW_LINES", "value": 1},
465
    {"name": "X_DRAW_TRIANGLES", "value": 2}
466
   ]
467
  },
468
  "PA_SU_SC_MODE_CNTL__POLY_MODE": {
469
   "entries": [
470
    {"name": "X_DISABLE_POLY_MODE", "value": 0},
471
    {"name": "X_DUAL_MODE", "value": 1}
472
   ]
473
  },
474
  'VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY': {
475
    "entries": [
476
      {"name": "X_8K_DWORDS", "value": 0},
477
      {"name": "X_4K_DWORDS", "value": 1},
478
      {"name": "X_2K_DWORDS", "value": 2},
479
      {"name": "X_1K_DWORDS", "value": 3}
480
    ]
481
  },
482
  "ROP3": {
483
   "entries": [
484
    {"name": "ROP3_CLEAR", "value": 0},
485
    {"name": "X_0X05", "value": 5},
486
    {"name": "X_0X0A", "value": 10},
487
    {"name": "X_0X0F", "value": 15},
488
    {"name": "ROP3_NOR", "value": 17},
489
    {"name": "ROP3_AND_INVERTED", "value": 34},
490
    {"name": "ROP3_COPY_INVERTED", "value": 51},
491
    {"name": "ROP3_AND_REVERSE", "value": 68},
492
    {"name": "X_0X50", "value": 80},
493
    {"name": "ROP3_INVERT", "value": 85},
494
    {"name": "X_0X5A", "value": 90},
495
    {"name": "X_0X5F", "value": 95},
496
    {"name": "ROP3_XOR", "value": 102},
497
    {"name": "ROP3_NAND", "value": 119},
498
    {"name": "ROP3_AND", "value": 136},
499
    {"name": "ROP3_EQUIVALENT", "value": 153},
500
    {"name": "X_0XA0", "value": 160},
501
    {"name": "X_0XA5", "value": 165},
502
    {"name": "ROP3_NO_OP", "value": 170},
503
    {"name": "X_0XAF", "value": 175},
504
    {"name": "ROP3_OR_INVERTED", "value": 187},
505
    {"name": "ROP3_COPY", "value": 204},
506
    {"name": "ROP3_OR_REVERSE", "value": 221},
507
    {"name": "ROP3_OR", "value": 238},
508
    {"name": "X_0XF0", "value": 240},
509
    {"name": "X_0XF5", "value": 245},
510
    {"name": "X_0XFA", "value": 250},
511
    {"name": "ROP3_SET", "value": 255}
512
   ]
513
  },
514
  "EXCP_EN": {
515
   "entries": [
516
    {"name": "INVALID", "value": 1},
517
    {"name": "INPUT_DENORMAL", "value": 2},
518
    {"name": "DIVIDE_BY_ZERO", "value": 4},
519
    {"name": "OVERFLOW", "value": 8},
520
    {"name": "UNDERFLOW", "value": 16},
521
    {"name": "INEXACT", "value": 32},
522
    {"name": "INT_DIVIDE_BY_ZERO", "value": 64},
523
    {"name": "ADDRESS_WATCH", "value": 128},
524
    {"name": "MEMORY_VIOLATION", "value": 256}
525
   ]
526
  }
527
}
528

529
missing_enums_gfx8plus = {
530
  **missing_enums_all,
531
  'CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE': {
532
    "entries": [
533
      {"name": "MAX_BLOCK_SIZE_64B", "value": 0},
534
      {"name": "MAX_BLOCK_SIZE_128B", "value": 1},
535
      {"name": "MAX_BLOCK_SIZE_256B", "value": 2}
536
    ]
537
  },
538
  'CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE': {
539
    "entries": [
540
      {"name": "MIN_BLOCK_SIZE_32B", "value": 0},
541
      {"name": "MIN_BLOCK_SIZE_64B", "value": 1}
542
    ]
543
  },
544
}
545

546
missing_enums_gfx81plus = {
547
  **missing_enums_gfx8plus,
548
  "SX_BLEND_OPT_EPSILON__MRT0_EPSILON": {
549
    "entries": [
550
      {"name": "EXACT", "value": 0},
551
      {"name": "11BIT_FORMAT", "value": 1},
552
      {"name": "10BIT_FORMAT", "value": 3},
553
      {"name": "8BIT_FORMAT", "value": 6},
554
      {"name": "6BIT_FORMAT", "value": 11},
555
      {"name": "5BIT_FORMAT", "value": 13},
556
      {"name": "4BIT_FORMAT", "value": 15}
557
    ]
558
  },
559
}
560

561
enums_missing = {
562
  'gfx6': {
563
    **missing_enums_all,
564
   "GB_TILE_MODE0__MICRO_TILE_MODE": GB_TILE_MODE0__MICRO_TILE_MODE,
565
  },
566
  'gfx7': {
567
    **missing_enums_all,
568
  },
569
  'gfx8': {
570
    **missing_enums_gfx8plus,
571
  },
572
  'gfx81': {
573
    **missing_enums_gfx81plus,
574
  },
575
  'gfx9': {
576
    **missing_enums_gfx81plus,
577
    "DB_DFSM_CONTROL__PUNCHOUT_MODE": DB_DFSM_CONTROL__PUNCHOUT_MODE,
578
    "IMG_DATA_FORMAT_STENCIL": IMG_DATA_FORMAT_STENCIL,
579
    "SQ_IMG_RSRC_WORD4__BC_SWIZZLE": SQ_IMG_RSRC_WORD4__BC_SWIZZLE,
580
  },
581
  'gfx10': {
582
    **missing_enums_gfx81plus,
583
    "DB_DFSM_CONTROL__PUNCHOUT_MODE": DB_DFSM_CONTROL__PUNCHOUT_MODE,
584
    "ThreadTraceRegInclude": ThreadTraceRegInclude,
585
    "ThreadTraceTokenExclude": ThreadTraceTokenExclude,
586
  },
587
  'gfx103': {
588
    **missing_enums_gfx81plus,
589
    "ColorFormat": ColorFormat,
590
    "SX_DOWNCONVERT_FORMAT": SX_DOWNCONVERT_FORMAT,
591
    "DB_DFSM_CONTROL__PUNCHOUT_MODE": DB_DFSM_CONTROL__PUNCHOUT_MODE,
592
    "ThreadTraceRegInclude": ThreadTraceRegInclude,
593
    "ThreadTraceTokenExclude": ThreadTraceTokenExclude,
594
    "VRSCombinerMode": VRSCombinerMode,
595
    "VRSHtileEncoding": VRSHtileEncoding,
596
  },
597
}
598

599
# Register field definitions that are missing in kernel headers
600
fields_missing = {
601
  # Format:
602
  #   Register: [[Field, StartBit, EndBit, EnumType(optional), ReplaceField=True/False(optional)], ...]
603
  'gfx6': {
604
    "COMPUTE_RESOURCE_LIMITS": [["WAVES_PER_SH_GFX6", 0, 5]],
605
    "GB_TILE_MODE0": [["MICRO_TILE_MODE", 0, 1, "GB_TILE_MODE0__MICRO_TILE_MODE"]],
606
    "SQ_IMG_SAMP_WORD3": [["UPGRADED_DEPTH", 29, 29]],
607
    "SQ_THREAD_TRACE_MASK": [["RANDOM_SEED", 16, 31]],
608
  },
609
  'gfx7': {
610
    "SQ_IMG_SAMP_WORD3": [["UPGRADED_DEPTH", 29, 29]],
611
    "SQ_THREAD_TRACE_MASK": [["RANDOM_SEED", 16, 31]],
612
  },
613
  'gfx8': {
614
    "SQ_IMG_SAMP_WORD3": [["UPGRADED_DEPTH", 29, 29]],
615
    "SQ_THREAD_TRACE_MASK": [["RANDOM_SEED", 16, 31]],
616
  },
617
  'gfx81': {
618
    "SQ_IMG_SAMP_WORD3": [["UPGRADED_DEPTH", 29, 29]],
619
    "SQ_THREAD_TRACE_MASK": [["RANDOM_SEED", 16, 31]],
620
  },
621
  'gfx9': {
622
    "SQ_IMG_RSRC_WORD1": [
623
      ["DATA_FORMAT_STENCIL", 20, 25, "IMG_DATA_FORMAT_STENCIL"],
624
      ["NUM_FORMAT_FMASK", 26, 29, "IMG_NUM_FORMAT_FMASK"]
625
    ],
626
  },
627
  'gfx10': {
628
    "DB_RESERVED_REG_2": [["RESOURCE_LEVEL", 28, 31, None, True]],
629
  },
630
  'gfx103': {
631
    "DB_RESERVED_REG_2": [["RESOURCE_LEVEL", 28, 31, None, True]],
632
    "VGT_DRAW_PAYLOAD_CNTL": [["EN_VRS_RATE", 6, 6]],
633
    "VGT_SHADER_STAGES_EN": [["PRIMGEN_PASSTHRU_NO_MSG", 26, 26]],
634
  },
635
}
636

637
######### END HARDCODED CONFIGURATION
638

639
def bitcount(n):
640
    return bin(n).count('1')
641

642
def generate_json(gfx_version, amd_headers_path):
643
    # Add the path to the filenames
644
    filenames = [amd_headers_path + '/' + a if a is not None else None for a in gfx_versions[gfx_version]]
645
    old_gen = filenames[0] is None
646

647
    # Open the files
648
    files = [open(a, 'r').readlines() if a is not None else None for a in filenames]
649

650
    # Parse the ip_offset.h file
651
    base_offsets = None
652
    if not old_gen:
653
        for line in files[0]:
654
            r = re_base.match(line)
655
            if r is not None:
656
                base_offsets = r.groups()
657

658
        if base_offsets is None:
659
            print('Can\'t parse: ' + filenames[0], file=sys.stderr)
660
            sys.exit(1)
661

662

663
    # Parse the offset.h file
664
    name = None
665
    offset = None
666
    added_offsets = set()
667
    regs = {}
668
    for line in files[1]:
669
        r = re_offset.match(line)
670
        if r is None:
671
            continue
672

673
        if '_BASE_IDX' not in r.group('name'):
674
            name = r.group('name')
675
            offset = int(r.group('value'), 0) * 4
676
            if not old_gen and r.group('mm') == 'mm':
677
                continue
678
        else:
679
            assert name == r.group('name')[:-9]
680
            idx = int(r.group('value'))
681
            assert idx < len(base_offsets)
682
            offset += int(base_offsets[idx], 0) * 4
683

684
        # Only accept writeable registers and debug registers
685
        if register_filter(gfx_version, name, offset, offset in added_offsets):
686
            regs[name] = {
687
                'chips': [gfx_version],
688
                'map': {'at': offset, 'to': 'mm'},
689
                'name': name,
690
            }
691
            added_offsets.add(offset)
692

693

694
    # Parse the sh_mask.h file
695
    shifts = {}
696
    masks = {}
697
    for line in files[2]:
698
        r = re_shift.match(line)
699
        is_shift = r is not None
700
        r = re_mask.match(line) if r is None else r
701
        if r is None:
702
            continue
703

704
        name = r.group('name')
705
        if name not in regs.keys():
706
            continue
707

708
        field = r.group('field')
709
        value = int(r.group('value'), 0)
710
        assert not is_shift or value < 32
711

712
        d = shifts if is_shift else masks
713
        if name not in d:
714
            d[name] = {}
715
        d[name][field] = value
716

717

718
    # Parse the enum.h file
719
    re_enum_begin = re.compile(r'^typedef enum (?P<name>\w+) {\n')
720
    re_enum_entry = re.compile(r'\s*(?P<name>\w+)\s*=\s*(?P<value>\w+),?\n')
721
    re_enum_end = re.compile(r'^} \w+;\n')
722
    inside_enum = False
723
    name = None
724
    enums = enums_missing[gfx_version] if gfx_version in enums_missing else {}
725

726
    for line in files[3]:
727
        r = re_enum_begin.match(line)
728
        if r is not None:
729
            name = r.group('name')
730
            if name in enums:
731
                continue
732
            enums[name] = {'entries': []}
733
            inside_enum = True
734
            continue
735

736
        r = re_enum_end.match(line)
737
        if r is not None:
738
            inside_enum = False
739
            name = None
740
            continue
741

742
        if inside_enum:
743
            r = re_enum_entry.match(line)
744
            assert r
745
            enums[name]['entries'].append({
746
                'name': r.group('name'),
747
                'value': int(r.group('value'), 0),
748
            })
749

750

751
    # Assemble everything
752
    reg_types = {}
753
    reg_mappings = []
754
    missing_fields = fields_missing[gfx_version] if gfx_version in fields_missing else {}
755

756
    for (name, reg) in regs.items():
757
        type = {'fields': []}
758

759
        if name in shifts and name in masks:
760
            for (field, shift) in shifts[name].items():
761
                if field not in masks[name]:
762
                    continue
763

764
                new = {
765
                    'bits': [shift, shift + bitcount(masks[name][field]) - 1],
766
                    'name': field,
767
                }
768
                if field in enum_map:
769
                    type_map = enum_map[field]
770
                    type_name = None
771

772
                    if len(type_map) == 1:
773
                        type_name = type_map[0];
774
                    else:
775
                        reg_index = type_map.index(name) if name in type_map else -1
776
                        if reg_index >= 1 and reg_index % 2 == 1:
777
                            type_name = type_map[reg_index - 1]
778

779
                    if type_name is not None:
780
                        if type_name not in enums:
781
                            print('{0}: {1} type not found for {2}.{3}'
782
                                  .format(gfx_version, type_name, name, field), file=sys.stderr)
783
                        else:
784
                            new['enum_ref'] = type_name
785

786
                type['fields'].append(new)
787

788
        if name in missing_fields:
789
            fields = missing_fields[name]
790
            for f in fields:
791
                field = {
792
                    'bits': [f[1], f[2]],
793
                    'name': f[0],
794
                }
795
                if len(f) >= 4 and f[3] is not None and f[3] in enums:
796
                    field['enum_ref'] = f[3]
797
                # missing_fields should replace overlapping fields if requested
798
                if len(f) >= 5 and f[4]:
799
                    for f2 in type['fields']:
800
                        if f2['bits'] == field['bits']:
801
                            type['fields'].remove(f2)
802

803
                type['fields'].append(field)
804

805
        if len(type['fields']) > 0:
806
            reg_types[name] = type
807

808
            # Don't define types that have only one field covering all bits
809
            field0_bits = type['fields'][0]['bits'];
810
            if len(type['fields']) > 1 or field0_bits[0] != 0 or field0_bits[1] != 31:
811
                reg['type_ref'] = name
812

813
            reg_mappings.append(reg)
814

815

816
    # Generate and canonicalize json
817
    all = {
818
        'enums': enums,
819
        'register_mappings': reg_mappings,
820
        'register_types': reg_types,
821
    }
822

823
    return json_canonicalize(io.StringIO(json.dumps(all, indent=1)))
824

825

826
if __name__ == '__main__':
827
    if len(sys.argv) <= 1 or (sys.argv[1] not in gfx_versions and sys.argv[1] != 'all'):
828
        print('First parameter should be one of: all, ' + ', '.join(gfx_versions.keys()), file=sys.stderr)
829
        sys.exit(1)
830

831
    if len(sys.argv) <= 2:
832
        print('Second parameter should be the path to the amd/include directory.', file=sys.stderr)
833
        sys.exit(1)
834

835
    if sys.argv[1] == 'all':
836
        for gfx_version in gfx_versions.keys():
837
            print(generate_json(gfx_version, sys.argv[2]), file=open(gfx_version + '.json', 'w'))
838
        sys.exit(0)
839

840
    print(generate_json(sys.argv[1], sys.argv[2]))
841

842
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