CoCalc -- pkt3.json

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/amd/registers/pkt3.json
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{
2
 "enums": {
3
  "COMMAND__SAIC": {
4
   "entries": [
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    {"name": "INCREMENT", "value": 0},
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    {"name": "NO_INCREMENT", "value": 1}
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   ]
8
  },
9
  "COMMAND__SAS": {
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   "entries": [
11
    {"name": "MEMORY", "value": 0},
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    {"name": "REGISTER", "value": 1}
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   ]
14
  },
15
  "COMMAND__SRC_SWAP": {
16
   "entries": [
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    {"name": "NONE", "value": 0},
18
    {"name": "8_IN_16", "value": 1},
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    {"name": "8_IN_32", "value": 2},
20
    {"name": "8_IN_64", "value": 3}
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   ]
22
  },
23
  "CONTROL__DST_SEL": {
24
   "entries": [
25
    {"name": "MEM_MAPPED_REGISTER", "value": 0},
26
    {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
27
    {"name": "TC_L2", "value": 2},
28
    {"name": "GDS", "value": 3},
29
    {"name": "RESERVED", "value": 4}
30
   ]
31
  },
32
  "CONTROL__DST_SEL_cik": {
33
   "entries": [
34
    {"name": "MEM_MAPPED_REGISTER", "value": 0},
35
    {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
36
    {"name": "TC_L2", "value": 2},
37
    {"name": "GDS", "value": 3},
38
    {"name": "RESERVED", "value": 4},
39
    {"name": "MEM", "value": 5}
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   ]
41
  },
42
  "CONTROL__ENGINE_SEL": {
43
   "entries": [
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    {"name": "ME", "value": 0},
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    {"name": "PFP", "value": 1},
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    {"name": "CE", "value": 2},
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    {"name": "DE", "value": 3}
48
   ]
49
  },
50
  "CP_DMA_WORD1__DST_SEL": {
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   "entries": [
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    {"name": "DST_ADDR", "value": 0},
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    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1}
54
   ]
55
  },
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  "CP_DMA_WORD1__DST_SEL_cik": {
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   "entries": [
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    {"name": "DST_ADDR", "value": 0},
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    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
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    {"name": "DST_ADDR_TC_L2", "value": 3}
61
   ]
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  },
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  "CP_DMA_WORD1__DST_SEL_gfx9": {
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   "entries": [
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    {"name": "DST_ADDR", "value": 0},
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    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
67
    {"name": "NOWHERE", "value": 2},
68
    {"name": "DST_ADDR_TC_L2", "value": 3}
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   ]
70
  },
71
  "CP_DMA_WORD1__ENGINE": {
72
   "entries": [
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    {"name": "ME", "value": 0},
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    {"name": "PFP", "value": 1}
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   ]
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  },
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  "CP_DMA_WORD1__SRC_SEL": {
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   "entries": [
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    {"name": "SRC_ADDR", "value": 0},
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    {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
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    {"name": "DATA", "value": 2}
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   ]
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  },
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  "CP_DMA_WORD1__SRC_SEL_cik": {
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   "entries": [
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    {"name": "SRC_ADDR", "value": 0},
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    {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
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    {"name": "DATA", "value": 2},
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    {"name": "SRC_ADDR_TC_L2", "value": 3}
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   ]
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  },
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  "GCR_GL1_RANGE": {
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   "entries": [
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    {"name": "GL1_ALL", "value": 0},
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    {"name": "GL1_RANGE", "value": 2},
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    {"name": "GL1_FIRST_LAST", "value": 3}
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   ]
98
  },
99
  "GCR_GL2_RANGE": {
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   "entries": [
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    {"name": "GL2_ALL", "value": 0},
102
    {"name": "GL2_VOL", "value": 1},
103
    {"name": "GL2_RANGE", "value": 2},
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    {"name": "GL2_FIRST_LAST", "value": 3}
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   ]
106
  },
107
  "GCR_GLI_INV": {
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   "entries": [
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    {"name": "GLI_NOP", "value": 0},
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    {"name": "GLI_ALL", "value": 1},
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    {"name": "GLI_RANGE", "value": 2},
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    {"name": "GLI_FIRST_LAST", "value": 3}
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   ]
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  },
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  "GCR_SEQ": {
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   "entries": [
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    {"name": "SEQ_PARALLEL", "value": 0},
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    {"name": "SEQ_FORWARD", "value": 1},
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    {"name": "SEQ_REVERSE", "value": 2}
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   ]
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  }
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 },
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 "register_mappings": [
124
  {
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   "comment": "This is at offset 0x415 instead of 0x414 due to a conflict with SQ_WAVE_GPR_ALLOC",
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   "chips": ["gfx6", "gfx7", "gfx8", "gfx81"],
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   "map": {"at": 1045, "to": "pkt3"},
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   "name": "COMMAND",
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   "type_ref": "COMMAND"
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  },
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  {
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   "chips": ["gfx9", "gfx10", "gfx103"],
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   "map": {"at": 1045, "to": "pkt3"},
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   "name": "COMMAND",
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   "type_ref": "COMMAND_gfx9"
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  },
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  {
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   "chips": ["gfx6"],
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   "map": {"at": 880, "to": "pkt3"},
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   "name": "CONTROL",
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   "type_ref": "CONTROL"
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  },
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  {
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   "chips": ["gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
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   "map": {"at": 880, "to": "pkt3"},
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   "name": "CONTROL",
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   "type_ref": "CONTROL_cik"
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  },
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  {
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   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
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   "map": {"at": 1040, "to": "pkt3"},
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   "name": "CP_DMA_WORD0",
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   "type_ref": "CP_DMA_WORD0"
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  },
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  {
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   "chips": ["gfx6"],
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   "map": {"at": 1041, "to": "pkt3"},
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   "name": "CP_DMA_WORD1",
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   "type_ref": "CP_DMA_WORD1"
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  },
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  {
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   "chips": ["gfx7", "gfx8", "gfx81"],
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   "map": {"at": 1041, "to": "pkt3"},
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   "name": "CP_DMA_WORD1",
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   "type_ref": "CP_DMA_WORD1_cik"
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  },
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  {
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   "chips": ["gfx9", "gfx10", "gfx103"],
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   "map": {"at": 1041, "to": "pkt3"},
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   "name": "CP_DMA_WORD1",
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   "type_ref": "CP_DMA_WORD1_gfx9"
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  },
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  {
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   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
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   "map": {"at": 1042, "to": "pkt3"},
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   "name": "CP_DMA_WORD2",
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   "type_ref": "CP_DMA_WORD2"
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  },
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  {
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   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
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   "map": {"at": 1043, "to": "pkt3"},
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   "name": "CP_DMA_WORD3",
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   "type_ref": "CP_DMA_WORD3"
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  },
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  {
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   "chips": ["gfx6"],
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   "map": {"at": 1280, "to": "pkt3"},
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   "name": "DMA_DATA_WORD0",
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   "type_ref": "DMA_DATA_WORD0"
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  },
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  {
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   "chips": ["gfx7", "gfx8", "gfx81"],
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   "map": {"at": 1280, "to": "pkt3"},
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   "name": "DMA_DATA_WORD0",
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   "type_ref": "DMA_DATA_WORD0_cik"
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  },
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  {
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   "chips": ["gfx9", "gfx10", "gfx103"],
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   "map": {"at": 1280, "to": "pkt3"},
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   "name": "DMA_DATA_WORD0",
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   "type_ref": "DMA_DATA_WORD0_gfx9"
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  },
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  {
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   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
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   "map": {"at": 882, "to": "pkt3"},
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   "name": "DST_ADDR_HI"
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  },
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  {
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   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
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   "map": {"at": 1284, "to": "pkt3"},
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   "name": "DST_ADDR_HI"
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  },
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  {
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   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
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   "map": {"at": 881, "to": "pkt3"},
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   "name": "DST_ADDR_LO"
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  },
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  {
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   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
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   "map": {"at": 1283, "to": "pkt3"},
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   "name": "DST_ADDR_LO"
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  },
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  {
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   "chips": ["gfx10", "gfx103"],
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   "map": {"at": 1414, "to": "pkt3"},
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   "name": "GCR_CNTL",
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   "type_ref": "GCR_CNTL"
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  },
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  {
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   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
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   "map": {"at": 1009, "to": "pkt3"},
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   "name": "IB_BASE_HI"
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  },
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  {
235
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
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   "map": {"at": 1008, "to": "pkt3"},
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   "name": "IB_BASE_LO"
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  },
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  {
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   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
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   "map": {"at": 1010, "to": "pkt3"},
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   "name": "IB_CONTROL",
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   "type_ref": "IB_CONTROL"
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  },
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  {
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   "chips": ["gfx10", "gfx103"],
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   "map": {"at": 1168, "to": "pkt3"},
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   "name": "RELEASE_MEM_OP",
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   "type_ref": "RELEASE_MEM_OP"
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  },
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  {
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   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
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   "map": {"at": 1282, "to": "pkt3"},
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   "name": "SRC_ADDR_HI"
255
  },
256
  {
257
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
258
   "map": {"at": 1281, "to": "pkt3"},
259
   "name": "SRC_ADDR_LO"
260
  }
261
 ],
262
 "register_types": {
263
  "COMMAND": {
264
   "fields": [
265
    {"bits": [0, 20], "name": "BYTE_COUNT"},
266
    {"bits": [21, 21], "name": "DISABLE_WR_CONFIRM"},
267
    {"bits": [22, 23], "enum_ref": "COMMAND__SRC_SWAP", "name": "SRC_SWAP"},
268
    {"bits": [24, 25], "enum_ref": "COMMAND__SRC_SWAP", "name": "DST_SWAP"},
269
    {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
270
    {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
271
    {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
272
    {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
273
    {"bits": [30, 30], "name": "RAW_WAIT"}
274
   ]
275
  },
276
  "COMMAND_gfx9": {
277
   "fields": [
278
    {"bits": [0, 25], "name": "BYTE_COUNT"},
279
    {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
280
    {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
281
    {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
282
    {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
283
    {"bits": [30, 30], "name": "RAW_WAIT"},
284
    {"bits": [31, 31], "name": "DISABLE_WR_CONFIRM"}
285
   ]
286
  },
287
  "CONTROL": {
288
   "fields": [
289
    {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL", "name": "DST_SEL"},
290
    {"bits": [16, 16], "name": "WR_ONE_ADDR"},
291
    {"bits": [20, 20], "name": "WR_CONFIRM"},
292
    {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
293
   ]
294
  },
295
  "CONTROL_cik": {
296
   "fields": [
297
    {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL_cik", "name": "DST_SEL"},
298
    {"bits": [16, 16], "name": "WR_ONE_ADDR"},
299
    {"bits": [20, 20], "name": "WR_CONFIRM"},
300
    {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
301
   ]
302
  },
303
  "CP_DMA_WORD0": {
304
   "fields": [
305
    {"bits": [0, 31], "name": "SRC_ADDR_LO"}
306
   ]
307
  },
308
  "CP_DMA_WORD1": {
309
   "fields": [
310
    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
311
    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
312
    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
313
    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
314
    {"bits": [31, 31], "name": "CP_SYNC"}
315
   ]
316
  },
317
  "CP_DMA_WORD1_cik": {
318
   "fields": [
319
    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
320
    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
321
    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
322
    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
323
    {"bits": [31, 31], "name": "CP_SYNC"}
324
   ]
325
  },
326
  "CP_DMA_WORD1_gfx9": {
327
   "fields": [
328
    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
329
    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
330
    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
331
    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
332
    {"bits": [31, 31], "name": "CP_SYNC"}
333
   ]
334
  },
335
  "CP_DMA_WORD2": {
336
   "fields": [
337
    {"bits": [0, 31], "name": "DST_ADDR_LO"}
338
   ]
339
  },
340
  "CP_DMA_WORD3": {
341
   "fields": [
342
    {"bits": [0, 15], "name": "DST_ADDR_HI"}
343
   ]
344
  },
345
  "DMA_DATA_WORD0": {
346
   "fields": [
347
    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
348
    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
349
    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
350
    {"bits": [31, 31], "name": "CP_SYNC"}
351
   ]
352
  },
353
  "DMA_DATA_WORD0_cik": {
354
   "fields": [
355
    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
356
    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
357
    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
358
    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
359
    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
360
    {"bits": [31, 31], "name": "CP_SYNC"}
361
   ]
362
  },
363
  "DMA_DATA_WORD0_gfx9": {
364
   "fields": [
365
    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
366
    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
367
    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
368
    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
369
    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
370
    {"bits": [31, 31], "name": "CP_SYNC"}
371
   ]
372
  },
373
  "GCR_CNTL": {
374
   "fields": [
375
    {"bits": [0, 1], "enum_ref": "GCR_GLI_INV", "name": "GLI_INV"},
376
    {"bits": [2, 3], "enum_ref": "GCR_GL1_RANGE", "name": "GL1_RANGE"},
377
    {"bits": [4, 4], "name": "GLM_WB"},
378
    {"bits": [5, 5], "name": "GLM_INV"},
379
    {"bits": [6, 6], "name": "GLK_WB"},
380
    {"bits": [7, 7], "name": "GLK_INV"},
381
    {"bits": [8, 8], "name": "GLV_INV"},
382
    {"bits": [9, 9], "name": "GL1_INV"},
383
    {"bits": [10, 10], "name": "GL2_US"},
384
    {"bits": [11, 12], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
385
    {"bits": [13, 13], "name": "GL2_DISCARD"},
386
    {"bits": [14, 14], "name": "GL2_INV"},
387
    {"bits": [15, 15], "name": "GL2_WB"},
388
    {"bits": [16, 17], "enum_ref": "GCR_SEQ", "name": "SEQ"},
389
    {"bits": [18, 18], "name": "RANGE_IS_PA"}
390
   ]
391
  },
392
  "IB_CONTROL": {
393
   "fields": [
394
    {"bits": [0, 19], "name": "IB_SIZE"},
395
    {"bits": [20, 20], "name": "CHAIN"},
396
    {"bits": [23, 23], "name": "VALID"}
397
   ]
398
  },
399
  "RELEASE_MEM_OP": {
400
   "fields": [
401
    {"bits": [0, 5], "name": "EVENT_TYPE"},
402
    {"bits": [8, 11], "name": "EVENT_INDEX"},
403
    {"bits": [12, 12], "name": "GLM_WB"},
404
    {"bits": [13, 13], "name": "GLM_INV"},
405
    {"bits": [14, 14], "name": "GLV_INV"},
406
    {"bits": [15, 15], "name": "GL1_INV"},
407
    {"bits": [16, 16], "name": "GL2_US"},
408
    {"bits": [17, 18], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
409
    {"bits": [19, 19], "name": "GL2_DISCARD"},
410
    {"bits": [20, 20], "name": "GL2_INV"},
411
    {"bits": [21, 21], "name": "GL2_WB"},
412
    {"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"}
413
   ]
414
  }
415
 }
416
}
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