Path: blob/21.2-virgl/src/amd/vulkan/radv_constants.h
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/*1* Copyright © 2016 Red Hat.2* Copyright © 2016 Bas Nieuwenhuizen3*4* based in part on anv driver which is:5* Copyright © 2015 Intel Corporation6*7* Permission is hereby granted, free of charge, to any person obtaining a8* copy of this software and associated documentation files (the "Software"),9* to deal in the Software without restriction, including without limitation10* the rights to use, copy, modify, merge, publish, distribute, sublicense,11* and/or sell copies of the Software, and to permit persons to whom the12* Software is furnished to do so, subject to the following conditions:13*14* The above copyright notice and this permission notice (including the next15* paragraph) shall be included in all copies or substantial portions of the16* Software.17*18* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR19* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,20* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL21* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER22* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING23* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS24* IN THE SOFTWARE.25*/2627#ifndef RADV_CONSTANTS_H28#define RADV_CONSTANTS_H2930#define ATI_VENDOR_ID 0x10023132#define MAX_VBS 3233#define MAX_VERTEX_ATTRIBS 3234#define MAX_RTS 835#define MAX_VIEWPORTS 1636#define MAX_SCISSORS 1637#define MAX_DISCARD_RECTANGLES 438#define MAX_SAMPLE_LOCATIONS 3239#define MAX_PUSH_CONSTANTS_SIZE 12840#define MAX_PUSH_DESCRIPTORS 3241#define MAX_DYNAMIC_UNIFORM_BUFFERS 1642#define MAX_DYNAMIC_STORAGE_BUFFERS 843#define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)44#define MAX_SAMPLES_LOG2 445#define NUM_META_FS_KEYS 1246#define RADV_MAX_DRM_DEVICES 847#define MAX_VIEWS 848#define MAX_SO_STREAMS 449#define MAX_SO_BUFFERS 450#define MAX_SO_OUTPUTS 6451#define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)52#define MAX_INLINE_UNIFORM_BLOCK_COUNT 6453#define MAX_BIND_POINTS 3 /* compute + graphics + raytracing */5455#define NUM_DEPTH_CLEAR_PIPELINES 356#define NUM_DEPTH_DECOMPRESS_PIPELINES 35758/*59* This is the point we switch from using CP to compute shader60* for certain buffer operations.61*/62#define RADV_BUFFER_OPS_CS_THRESHOLD 40966364#define RADV_BUFFER_UPDATE_THRESHOLD 10246566/* descriptor index into scratch ring offsets */67#define RING_SCRATCH 068#define RING_ESGS_VS 169#define RING_ESGS_GS 270#define RING_GSVS_VS 371#define RING_GSVS_GS 472#define RING_HS_TESS_FACTOR 573#define RING_HS_TESS_OFFCHIP 674#define RING_PS_SAMPLE_POSITIONS 77576/* max number of descriptor sets */77#define MAX_SETS 327879/* Make sure everything is addressable by a signed 32-bit int, and80* our largest descriptors are 96 bytes.81*/82#define RADV_MAX_PER_SET_DESCRIPTORS ((1ull << 31) / 96)8384/* Our buffer size fields allow only 2**32 - 1. We round that down to a multiple85* of 4 bytes so we can align buffer sizes up.86*/87#define RADV_MAX_MEMORY_ALLOCATION_SIZE 0xFFFFFFFCull8889/* Number of invocations in each subgroup. */90#define RADV_SUBGROUP_SIZE 649192#endif /* RADV_CONSTANTS_H */939495