Path: blob/21.2-virgl/src/amd/vulkan/radv_meta.h
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/*1* Copyright © 2016 Red Hat2* based on intel anv code:3* Copyright © 2015 Intel Corporation4*5* Permission is hereby granted, free of charge, to any person obtaining a6* copy of this software and associated documentation files (the "Software"),7* to deal in the Software without restriction, including without limitation8* the rights to use, copy, modify, merge, publish, distribute, sublicense,9* and/or sell copies of the Software, and to permit persons to whom the10* Software is furnished to do so, subject to the following conditions:11*12* The above copyright notice and this permission notice (including the next13* paragraph) shall be included in all copies or substantial portions of the14* Software.15*16* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER20* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING21* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS22* IN THE SOFTWARE.23*/2425#ifndef RADV_META_H26#define RADV_META_H2728#include "radv_private.h"29#include "radv_shader.h"3031#ifdef __cplusplus32extern "C" {33#endif3435enum radv_meta_save_flags {36RADV_META_SAVE_PASS = (1 << 0),37RADV_META_SAVE_CONSTANTS = (1 << 1),38RADV_META_SAVE_DESCRIPTORS = (1 << 2),39RADV_META_SAVE_GRAPHICS_PIPELINE = (1 << 3),40RADV_META_SAVE_COMPUTE_PIPELINE = (1 << 4),41RADV_META_SAVE_SAMPLE_LOCATIONS = (1 << 5),42};4344struct radv_meta_saved_state {45uint32_t flags;4647struct radv_descriptor_set *old_descriptor_set0;48struct radv_pipeline *old_pipeline;49struct radv_viewport_state viewport;50struct radv_scissor_state scissor;51struct radv_sample_locations_state sample_location;5253char push_constants[128];5455struct radv_render_pass *pass;56const struct radv_subpass *subpass;57struct radv_attachment_state *attachments;58struct radv_framebuffer *framebuffer;59VkRect2D render_area;6061VkCullModeFlags cull_mode;62VkFrontFace front_face;6364unsigned primitive_topology;6566bool depth_test_enable;67bool depth_write_enable;68unsigned depth_compare_op;69bool depth_bounds_test_enable;70bool stencil_test_enable;7172struct {73struct {74VkStencilOp fail_op;75VkStencilOp pass_op;76VkStencilOp depth_fail_op;77VkCompareOp compare_op;78} front;7980struct {81VkStencilOp fail_op;82VkStencilOp pass_op;83VkStencilOp depth_fail_op;84VkCompareOp compare_op;85} back;86} stencil_op;8788struct {89VkExtent2D size;90VkFragmentShadingRateCombinerOpKHR combiner_ops[2];91} fragment_shading_rate;9293bool depth_bias_enable;94bool primitive_restart_enable;95bool rasterizer_discard_enable;9697unsigned logic_op;9899uint32_t color_write_enable;100};101102VkResult radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand);103void radv_device_finish_meta_clear_state(struct radv_device *device);104105VkResult radv_device_init_meta_resolve_state(struct radv_device *device, bool on_demand);106void radv_device_finish_meta_resolve_state(struct radv_device *device);107108VkResult radv_device_init_meta_depth_decomp_state(struct radv_device *device, bool on_demand);109void radv_device_finish_meta_depth_decomp_state(struct radv_device *device);110111VkResult radv_device_init_meta_fast_clear_flush_state(struct radv_device *device, bool on_demand);112void radv_device_finish_meta_fast_clear_flush_state(struct radv_device *device);113114VkResult radv_device_init_meta_blit_state(struct radv_device *device, bool on_demand);115void radv_device_finish_meta_blit_state(struct radv_device *device);116117VkResult radv_device_init_meta_blit2d_state(struct radv_device *device, bool on_demand);118void radv_device_finish_meta_blit2d_state(struct radv_device *device);119120VkResult radv_device_init_meta_buffer_state(struct radv_device *device);121void radv_device_finish_meta_buffer_state(struct radv_device *device);122123VkResult radv_device_init_meta_query_state(struct radv_device *device, bool on_demand);124void radv_device_finish_meta_query_state(struct radv_device *device);125126VkResult radv_device_init_meta_resolve_compute_state(struct radv_device *device, bool on_demand);127void radv_device_finish_meta_resolve_compute_state(struct radv_device *device);128129VkResult radv_device_init_meta_resolve_fragment_state(struct radv_device *device, bool on_demand);130void radv_device_finish_meta_resolve_fragment_state(struct radv_device *device);131132VkResult radv_device_init_meta_fmask_expand_state(struct radv_device *device);133void radv_device_finish_meta_fmask_expand_state(struct radv_device *device);134135void radv_device_finish_meta_dcc_retile_state(struct radv_device *device);136137void radv_device_finish_meta_copy_vrs_htile_state(struct radv_device *device);138139VkResult radv_device_init_accel_struct_build_state(struct radv_device *device);140void radv_device_finish_accel_struct_build_state(struct radv_device *device);141142void radv_meta_save(struct radv_meta_saved_state *saved_state, struct radv_cmd_buffer *cmd_buffer,143uint32_t flags);144145void radv_meta_restore(const struct radv_meta_saved_state *state,146struct radv_cmd_buffer *cmd_buffer);147148VkImageViewType radv_meta_get_view_type(const struct radv_image *image);149150uint32_t radv_meta_get_iview_layer(const struct radv_image *dest_image,151const VkImageSubresourceLayers *dest_subresource,152const VkOffset3D *dest_offset);153154struct radv_meta_blit2d_surf {155/** The size of an element in bytes. */156uint8_t bs;157VkFormat format;158159struct radv_image *image;160unsigned level;161unsigned layer;162VkImageAspectFlags aspect_mask;163VkImageLayout current_layout;164bool disable_compression;165};166167struct radv_meta_blit2d_buffer {168struct radv_buffer *buffer;169uint32_t offset;170uint32_t pitch;171uint8_t bs;172VkFormat format;173};174175struct radv_meta_blit2d_rect {176uint32_t src_x, src_y;177uint32_t dst_x, dst_y;178uint32_t width, height;179};180181void radv_meta_begin_blit2d(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_saved_state *save);182183void radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src_img,184struct radv_meta_blit2d_buffer *src_buf, struct radv_meta_blit2d_surf *dst,185unsigned num_rects, struct radv_meta_blit2d_rect *rects);186187void radv_meta_end_blit2d(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_saved_state *save);188189VkResult radv_device_init_meta_bufimage_state(struct radv_device *device);190void radv_device_finish_meta_bufimage_state(struct radv_device *device);191void radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,192struct radv_meta_blit2d_surf *src,193struct radv_meta_blit2d_buffer *dst, unsigned num_rects,194struct radv_meta_blit2d_rect *rects);195196void radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer,197struct radv_meta_blit2d_buffer *src,198struct radv_meta_blit2d_surf *dst, unsigned num_rects,199struct radv_meta_blit2d_rect *rects);200void radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer,201struct radv_meta_blit2d_surf *src,202struct radv_meta_blit2d_surf *dst, unsigned num_rects,203struct radv_meta_blit2d_rect *rects);204void radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *dst,205const VkClearColorValue *clear_color);206207void radv_decompress_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,208const VkImageSubresourceRange *subresourceRange,209struct radv_sample_locations_state *sample_locs);210void radv_resummarize_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,211const VkImageSubresourceRange *subresourceRange,212struct radv_sample_locations_state *sample_locs);213void radv_fast_clear_flush_image_inplace(struct radv_cmd_buffer *cmd_buffer,214struct radv_image *image,215const VkImageSubresourceRange *subresourceRange);216void radv_decompress_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,217const VkImageSubresourceRange *subresourceRange);218void radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image);219void radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,220const VkImageSubresourceRange *subresourceRange);221void radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_image,222VkExtent2D *extent, struct radv_image *dst_image);223224void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,225struct radv_image *src_image, VkFormat src_format,226VkImageLayout src_image_layout, struct radv_image *dest_image,227VkFormat dest_format, VkImageLayout dest_image_layout,228const VkImageResolve2KHR *region);229230void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,231struct radv_image *src_image, VkImageLayout src_image_layout,232struct radv_image *dest_image,233VkImageLayout dest_image_layout,234const VkImageResolve2KHR *region);235236void radv_decompress_resolve_subpass_src(struct radv_cmd_buffer *cmd_buffer);237238void radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,239VkImageLayout src_image_layout, const VkImageResolve2KHR *region);240241uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,242const VkImageSubresourceRange *range, uint32_t value);243uint32_t radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,244const VkImageSubresourceRange *range, uint32_t value);245uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,246const VkImageSubresourceRange *range, uint32_t value);247uint32_t radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image,248const VkImageSubresourceRange *range, uint32_t value);249250/**251* Return whether the bound pipeline is the FMASK decompress pass.252*/253static inline bool254radv_is_fmask_decompress_pipeline(struct radv_cmd_buffer *cmd_buffer)255{256struct radv_meta_state *meta_state = &cmd_buffer->device->meta_state;257struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;258259return radv_pipeline_to_handle(pipeline) ==260meta_state->fast_clear_flush.fmask_decompress_pipeline;261}262263/**264* Return whether the bound pipeline is the DCC decompress pass.265*/266static inline bool267radv_is_dcc_decompress_pipeline(struct radv_cmd_buffer *cmd_buffer)268{269struct radv_meta_state *meta_state = &cmd_buffer->device->meta_state;270struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;271272return radv_pipeline_to_handle(pipeline) == meta_state->fast_clear_flush.dcc_decompress_pipeline;273}274275/* common nir builder helpers */276#include "nir/nir_builder.h"277278nir_ssa_def *radv_meta_gen_rect_vertices(nir_builder *vs_b);279nir_ssa_def *radv_meta_gen_rect_vertices_comp2(nir_builder *vs_b, nir_ssa_def *comp2);280nir_shader *radv_meta_build_nir_vs_generate_vertices(void);281nir_shader *radv_meta_build_nir_fs_noop(void);282283void radv_meta_build_resolve_shader_core(nir_builder *b, bool is_integer, int samples,284nir_variable *input_img, nir_variable *color,285nir_ssa_def *img_coord);286287nir_ssa_def *radv_meta_load_descriptor(nir_builder *b, unsigned desc_set, unsigned binding);288289#ifdef __cplusplus290}291#endif292293#endif /* RADV_META_H */294295296