Path: blob/21.2-virgl/src/amd/vulkan/radv_query.c
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/*1* Copyrigh 2016 Red Hat Inc.2* Based on anv:3* Copyright © 2015 Intel Corporation4*5* Permission is hereby granted, free of charge, to any person obtaining a6* copy of this software and associated documentation files (the "Software"),7* to deal in the Software without restriction, including without limitation8* the rights to use, copy, modify, merge, publish, distribute, sublicense,9* and/or sell copies of the Software, and to permit persons to whom the10* Software is furnished to do so, subject to the following conditions:11*12* The above copyright notice and this permission notice (including the next13* paragraph) shall be included in all copies or substantial portions of the14* Software.15*16* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER20* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING21* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS22* IN THE SOFTWARE.23*/2425#include <assert.h>26#include <fcntl.h>27#include <stdbool.h>28#include <string.h>2930#include "nir/nir_builder.h"31#include "util/u_atomic.h"32#include "radv_cs.h"33#include "radv_meta.h"34#include "radv_private.h"35#include "sid.h"3637#define TIMESTAMP_NOT_READY UINT64_MAX3839static const int pipelinestat_block_size = 11 * 8;40static const unsigned pipeline_statistics_indices[] = {7, 6, 3, 4, 5, 2, 1, 0, 8, 9, 10};4142static unsigned43radv_get_pipeline_statistics_index(const VkQueryPipelineStatisticFlagBits flag)44{45int offset = ffs(flag) - 1;46assert(offset < ARRAY_SIZE(pipeline_statistics_indices));47return pipeline_statistics_indices[offset];48}4950static nir_ssa_def *51nir_test_flag(nir_builder *b, nir_ssa_def *flags, uint32_t flag)52{53return nir_i2b(b, nir_iand(b, flags, nir_imm_int(b, flag)));54}5556static void57radv_break_on_count(nir_builder *b, nir_variable *var, nir_ssa_def *count)58{59nir_ssa_def *counter = nir_load_var(b, var);6061nir_push_if(b, nir_uge(b, counter, count));62nir_jump(b, nir_jump_break);63nir_pop_if(b, NULL);6465counter = nir_iadd(b, counter, nir_imm_int(b, 1));66nir_store_var(b, var, counter, 0x1);67}6869static void70radv_store_availability(nir_builder *b, nir_ssa_def *flags, nir_ssa_def *dst_buf,71nir_ssa_def *offset, nir_ssa_def *value32)72{73nir_push_if(b, nir_test_flag(b, flags, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT));7475nir_push_if(b, nir_test_flag(b, flags, VK_QUERY_RESULT_64_BIT));7677nir_store_ssbo(b, nir_vec2(b, value32, nir_imm_int(b, 0)), dst_buf, offset, .write_mask = 0x3,78.align_mul = 8);7980nir_push_else(b, NULL);8182nir_store_ssbo(b, value32, dst_buf, offset, .write_mask = 0x1, .align_mul = 4);8384nir_pop_if(b, NULL);8586nir_pop_if(b, NULL);87}8889static nir_shader *90build_occlusion_query_shader(struct radv_device *device)91{92/* the shader this builds is roughly93*94* push constants {95* uint32_t flags;96* uint32_t dst_stride;97* };98*99* uint32_t src_stride = 16 * db_count;100*101* location(binding = 0) buffer dst_buf;102* location(binding = 1) buffer src_buf;103*104* void main() {105* uint64_t result = 0;106* uint64_t src_offset = src_stride * global_id.x;107* uint64_t dst_offset = dst_stride * global_id.x;108* bool available = true;109* for (int i = 0; i < db_count; ++i) {110* if (enabled_rb_mask & (1 << i)) {111* uint64_t start = src_buf[src_offset + 16 * i];112* uint64_t end = src_buf[src_offset + 16 * i + 8];113* if ((start & (1ull << 63)) && (end & (1ull << 63)))114* result += end - start;115* else116* available = false;117* }118* }119* uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;120* if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {121* if (flags & VK_QUERY_RESULT_64_BIT)122* dst_buf[dst_offset] = result;123* else124* dst_buf[dst_offset] = (uint32_t)result.125* }126* if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {127* dst_buf[dst_offset + elem_size] = available;128* }129* }130*/131nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "occlusion_query");132b.shader->info.workgroup_size[0] = 64;133b.shader->info.workgroup_size[1] = 1;134b.shader->info.workgroup_size[2] = 1;135136nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result");137nir_variable *outer_counter =138nir_local_variable_create(b.impl, glsl_int_type(), "outer_counter");139nir_variable *start = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "start");140nir_variable *end = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "end");141nir_variable *available = nir_local_variable_create(b.impl, glsl_bool_type(), "available");142unsigned enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;143unsigned db_count = device->physical_device->rad_info.max_render_backends;144145nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range = 16);146147nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0);148nir_ssa_def *src_buf = radv_meta_load_descriptor(&b, 0, 1);149150nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);151nir_ssa_def *wg_id = nir_load_workgroup_id(&b, 32);152nir_ssa_def *block_size =153nir_imm_ivec4(&b, b.shader->info.workgroup_size[0], b.shader->info.workgroup_size[1],154b.shader->info.workgroup_size[2], 0);155nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);156global_id = nir_channel(&b, global_id, 0); // We only care about x here.157158nir_ssa_def *input_stride = nir_imm_int(&b, db_count * 16);159nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);160nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range = 16);161nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);162163nir_store_var(&b, result, nir_imm_int64(&b, 0), 0x1);164nir_store_var(&b, outer_counter, nir_imm_int(&b, 0), 0x1);165nir_store_var(&b, available, nir_imm_true(&b), 0x1);166167nir_push_loop(&b);168169nir_ssa_def *current_outer_count = nir_load_var(&b, outer_counter);170radv_break_on_count(&b, outer_counter, nir_imm_int(&b, db_count));171172nir_ssa_def *enabled_cond = nir_iand(&b, nir_imm_int(&b, enabled_rb_mask),173nir_ishl(&b, nir_imm_int(&b, 1), current_outer_count));174175nir_push_if(&b, nir_i2b(&b, enabled_cond));176177nir_ssa_def *load_offset = nir_imul(&b, current_outer_count, nir_imm_int(&b, 16));178load_offset = nir_iadd(&b, input_base, load_offset);179180nir_ssa_def *load = nir_load_ssbo(&b, 2, 64, src_buf, load_offset, .align_mul = 16);181182nir_store_var(&b, start, nir_channel(&b, load, 0), 0x1);183nir_store_var(&b, end, nir_channel(&b, load, 1), 0x1);184185nir_ssa_def *start_done = nir_ilt(&b, nir_load_var(&b, start), nir_imm_int64(&b, 0));186nir_ssa_def *end_done = nir_ilt(&b, nir_load_var(&b, end), nir_imm_int64(&b, 0));187188nir_push_if(&b, nir_iand(&b, start_done, end_done));189190nir_store_var(&b, result,191nir_iadd(&b, nir_load_var(&b, result),192nir_isub(&b, nir_load_var(&b, end), nir_load_var(&b, start))),1930x1);194195nir_push_else(&b, NULL);196197nir_store_var(&b, available, nir_imm_false(&b), 0x1);198199nir_pop_if(&b, NULL);200nir_pop_if(&b, NULL);201nir_pop_loop(&b, NULL);202203/* Store the result if complete or if partial results have been requested. */204205nir_ssa_def *result_is_64bit = nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT);206nir_ssa_def *result_size =207nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));208nir_push_if(&b, nir_ior(&b, nir_test_flag(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT),209nir_load_var(&b, available)));210211nir_push_if(&b, result_is_64bit);212213nir_store_ssbo(&b, nir_load_var(&b, result), dst_buf, output_base, .write_mask = 0x1,214.align_mul = 8);215216nir_push_else(&b, NULL);217218nir_store_ssbo(&b, nir_u2u32(&b, nir_load_var(&b, result)), dst_buf, output_base,219.write_mask = 0x1, .align_mul = 8);220221nir_pop_if(&b, NULL);222nir_pop_if(&b, NULL);223224radv_store_availability(&b, flags, dst_buf, nir_iadd(&b, result_size, output_base),225nir_b2i32(&b, nir_load_var(&b, available)));226227return b.shader;228}229230static nir_shader *231build_pipeline_statistics_query_shader(struct radv_device *device)232{233/* the shader this builds is roughly234*235* push constants {236* uint32_t flags;237* uint32_t dst_stride;238* uint32_t stats_mask;239* uint32_t avail_offset;240* };241*242* uint32_t src_stride = pipelinestat_block_size * 2;243*244* location(binding = 0) buffer dst_buf;245* location(binding = 1) buffer src_buf;246*247* void main() {248* uint64_t src_offset = src_stride * global_id.x;249* uint64_t dst_base = dst_stride * global_id.x;250* uint64_t dst_offset = dst_base;251* uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;252* uint32_t elem_count = stats_mask >> 16;253* uint32_t available32 = src_buf[avail_offset + 4 * global_id.x];254* if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {255* dst_buf[dst_offset + elem_count * elem_size] = available32;256* }257* if ((bool)available32) {258* // repeat 11 times:259* if (stats_mask & (1 << 0)) {260* uint64_t start = src_buf[src_offset + 8 * indices[0]];261* uint64_t end = src_buf[src_offset + 8 * indices[0] +262* pipelinestat_block_size]; uint64_t result = end - start; if (flags & VK_QUERY_RESULT_64_BIT)263* dst_buf[dst_offset] = result;264* else265* dst_buf[dst_offset] = (uint32_t)result.266* dst_offset += elem_size;267* }268* } else if (flags & VK_QUERY_RESULT_PARTIAL_BIT) {269* // Set everything to 0 as we don't know what is valid.270* for (int i = 0; i < elem_count; ++i)271* dst_buf[dst_base + elem_size * i] = 0;272* }273* }274*/275nir_builder b =276nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "pipeline_statistics_query");277b.shader->info.workgroup_size[0] = 64;278b.shader->info.workgroup_size[1] = 1;279b.shader->info.workgroup_size[2] = 1;280281nir_variable *output_offset =282nir_local_variable_create(b.impl, glsl_int_type(), "output_offset");283284nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range = 16);285nir_ssa_def *stats_mask = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 8), .range = 16);286nir_ssa_def *avail_offset = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 12), .range = 16);287288nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0);289nir_ssa_def *src_buf = radv_meta_load_descriptor(&b, 0, 1);290291nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);292nir_ssa_def *wg_id = nir_load_workgroup_id(&b, 32);293nir_ssa_def *block_size =294nir_imm_ivec4(&b, b.shader->info.workgroup_size[0], b.shader->info.workgroup_size[1],295b.shader->info.workgroup_size[2], 0);296nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);297global_id = nir_channel(&b, global_id, 0); // We only care about x here.298299nir_ssa_def *input_stride = nir_imm_int(&b, pipelinestat_block_size * 2);300nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);301nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range = 16);302nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);303304avail_offset = nir_iadd(&b, avail_offset, nir_imul(&b, global_id, nir_imm_int(&b, 4)));305306nir_ssa_def *available32 = nir_load_ssbo(&b, 1, 32, src_buf, avail_offset, .align_mul = 4);307308nir_ssa_def *result_is_64bit = nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT);309nir_ssa_def *elem_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));310nir_ssa_def *elem_count = nir_ushr(&b, stats_mask, nir_imm_int(&b, 16));311312radv_store_availability(&b, flags, dst_buf,313nir_iadd(&b, output_base, nir_imul(&b, elem_count, elem_size)),314available32);315316nir_push_if(&b, nir_i2b(&b, available32));317318nir_store_var(&b, output_offset, output_base, 0x1);319for (int i = 0; i < ARRAY_SIZE(pipeline_statistics_indices); ++i) {320nir_push_if(&b, nir_test_flag(&b, stats_mask, 1u << i));321322nir_ssa_def *start_offset =323nir_iadd(&b, input_base, nir_imm_int(&b, pipeline_statistics_indices[i] * 8));324nir_ssa_def *start = nir_load_ssbo(&b, 1, 64, src_buf, start_offset, .align_mul = 8);325326nir_ssa_def *end_offset =327nir_iadd(&b, input_base,328nir_imm_int(&b, pipeline_statistics_indices[i] * 8 + pipelinestat_block_size));329nir_ssa_def *end = nir_load_ssbo(&b, 1, 64, src_buf, end_offset, .align_mul = 8);330331nir_ssa_def *result = nir_isub(&b, end, start);332333/* Store result */334nir_push_if(&b, result_is_64bit);335336nir_store_ssbo(&b, result, dst_buf, nir_load_var(&b, output_offset), .write_mask = 0x1,337.align_mul = 8);338339nir_push_else(&b, NULL);340341nir_store_ssbo(&b, nir_u2u32(&b, result), dst_buf, nir_load_var(&b, output_offset),342.write_mask = 0x1, .align_mul = 4);343344nir_pop_if(&b, NULL);345346nir_store_var(&b, output_offset, nir_iadd(&b, nir_load_var(&b, output_offset), elem_size),3470x1);348349nir_pop_if(&b, NULL);350}351352nir_push_else(&b, NULL); /* nir_i2b(&b, available32) */353354nir_push_if(&b, nir_test_flag(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT));355356/* Stores zeros in all outputs. */357358nir_variable *counter = nir_local_variable_create(b.impl, glsl_int_type(), "counter");359nir_store_var(&b, counter, nir_imm_int(&b, 0), 0x1);360361nir_loop *loop = nir_push_loop(&b);362363nir_ssa_def *current_counter = nir_load_var(&b, counter);364radv_break_on_count(&b, counter, elem_count);365366nir_ssa_def *output_elem = nir_iadd(&b, output_base, nir_imul(&b, elem_size, current_counter));367nir_push_if(&b, result_is_64bit);368369nir_store_ssbo(&b, nir_imm_int64(&b, 0), dst_buf, output_elem, .write_mask = 0x1,370.align_mul = 8);371372nir_push_else(&b, NULL);373374nir_store_ssbo(&b, nir_imm_int(&b, 0), dst_buf, output_elem, .write_mask = 0x1, .align_mul = 4);375376nir_pop_if(&b, NULL);377378nir_pop_loop(&b, loop);379nir_pop_if(&b, NULL); /* VK_QUERY_RESULT_PARTIAL_BIT */380nir_pop_if(&b, NULL); /* nir_i2b(&b, available32) */381return b.shader;382}383384static nir_shader *385build_tfb_query_shader(struct radv_device *device)386{387/* the shader this builds is roughly388*389* uint32_t src_stride = 32;390*391* location(binding = 0) buffer dst_buf;392* location(binding = 1) buffer src_buf;393*394* void main() {395* uint64_t result[2] = {};396* bool available = false;397* uint64_t src_offset = src_stride * global_id.x;398* uint64_t dst_offset = dst_stride * global_id.x;399* uint64_t *src_data = src_buf[src_offset];400* uint32_t avail = (src_data[0] >> 32) &401* (src_data[1] >> 32) &402* (src_data[2] >> 32) &403* (src_data[3] >> 32);404* if (avail & 0x80000000) {405* result[0] = src_data[3] - src_data[1];406* result[1] = src_data[2] - src_data[0];407* available = true;408* }409* uint32_t result_size = flags & VK_QUERY_RESULT_64_BIT ? 16 : 8;410* if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {411* if (flags & VK_QUERY_RESULT_64_BIT) {412* dst_buf[dst_offset] = result;413* } else {414* dst_buf[dst_offset] = (uint32_t)result;415* }416* }417* if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {418* dst_buf[dst_offset + result_size] = available;419* }420* }421*/422nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "tfb_query");423b.shader->info.workgroup_size[0] = 64;424b.shader->info.workgroup_size[1] = 1;425b.shader->info.workgroup_size[2] = 1;426427/* Create and initialize local variables. */428nir_variable *result =429nir_local_variable_create(b.impl, glsl_vector_type(GLSL_TYPE_UINT64, 2), "result");430nir_variable *available = nir_local_variable_create(b.impl, glsl_bool_type(), "available");431432nir_store_var(&b, result, nir_vec2(&b, nir_imm_int64(&b, 0), nir_imm_int64(&b, 0)), 0x3);433nir_store_var(&b, available, nir_imm_false(&b), 0x1);434435nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range = 16);436437/* Load resources. */438nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0);439nir_ssa_def *src_buf = radv_meta_load_descriptor(&b, 0, 1);440441/* Compute global ID. */442nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);443nir_ssa_def *wg_id = nir_load_workgroup_id(&b, 32);444nir_ssa_def *block_size =445nir_imm_ivec4(&b, b.shader->info.workgroup_size[0], b.shader->info.workgroup_size[1],446b.shader->info.workgroup_size[2], 0);447nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);448global_id = nir_channel(&b, global_id, 0); // We only care about x here.449450/* Compute src/dst strides. */451nir_ssa_def *input_stride = nir_imm_int(&b, 32);452nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);453nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range = 16);454nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);455456/* Load data from the query pool. */457nir_ssa_def *load1 = nir_load_ssbo(&b, 4, 32, src_buf, input_base, .align_mul = 32);458nir_ssa_def *load2 = nir_load_ssbo(459&b, 4, 32, src_buf, nir_iadd(&b, input_base, nir_imm_int(&b, 16)), .align_mul = 16);460461/* Check if result is available. */462nir_ssa_def *avails[2];463avails[0] = nir_iand(&b, nir_channel(&b, load1, 1), nir_channel(&b, load1, 3));464avails[1] = nir_iand(&b, nir_channel(&b, load2, 1), nir_channel(&b, load2, 3));465nir_ssa_def *result_is_available =466nir_i2b(&b, nir_iand(&b, nir_iand(&b, avails[0], avails[1]), nir_imm_int(&b, 0x80000000)));467468/* Only compute result if available. */469nir_push_if(&b, result_is_available);470471/* Pack values. */472nir_ssa_def *packed64[4];473packed64[0] =474nir_pack_64_2x32(&b, nir_vec2(&b, nir_channel(&b, load1, 0), nir_channel(&b, load1, 1)));475packed64[1] =476nir_pack_64_2x32(&b, nir_vec2(&b, nir_channel(&b, load1, 2), nir_channel(&b, load1, 3)));477packed64[2] =478nir_pack_64_2x32(&b, nir_vec2(&b, nir_channel(&b, load2, 0), nir_channel(&b, load2, 1)));479packed64[3] =480nir_pack_64_2x32(&b, nir_vec2(&b, nir_channel(&b, load2, 2), nir_channel(&b, load2, 3)));481482/* Compute result. */483nir_ssa_def *num_primitive_written = nir_isub(&b, packed64[3], packed64[1]);484nir_ssa_def *primitive_storage_needed = nir_isub(&b, packed64[2], packed64[0]);485486nir_store_var(&b, result, nir_vec2(&b, num_primitive_written, primitive_storage_needed), 0x3);487nir_store_var(&b, available, nir_imm_true(&b), 0x1);488489nir_pop_if(&b, NULL);490491/* Determine if result is 64 or 32 bit. */492nir_ssa_def *result_is_64bit = nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT);493nir_ssa_def *result_size =494nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 16), nir_imm_int(&b, 8));495496/* Store the result if complete or partial results have been requested. */497nir_push_if(&b, nir_ior(&b, nir_test_flag(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT),498nir_load_var(&b, available)));499500/* Store result. */501nir_push_if(&b, result_is_64bit);502503nir_store_ssbo(&b, nir_load_var(&b, result), dst_buf, output_base, .write_mask = 0x3,504.align_mul = 8);505506nir_push_else(&b, NULL);507508nir_store_ssbo(&b, nir_u2u32(&b, nir_load_var(&b, result)), dst_buf, output_base,509.write_mask = 0x3, .align_mul = 4);510511nir_pop_if(&b, NULL);512nir_pop_if(&b, NULL);513514radv_store_availability(&b, flags, dst_buf, nir_iadd(&b, result_size, output_base),515nir_b2i32(&b, nir_load_var(&b, available)));516517return b.shader;518}519520static nir_shader *521build_timestamp_query_shader(struct radv_device *device)522{523/* the shader this builds is roughly524*525* uint32_t src_stride = 8;526*527* location(binding = 0) buffer dst_buf;528* location(binding = 1) buffer src_buf;529*530* void main() {531* uint64_t result = 0;532* bool available = false;533* uint64_t src_offset = src_stride * global_id.x;534* uint64_t dst_offset = dst_stride * global_id.x;535* uint64_t timestamp = src_buf[src_offset];536* if (timestamp != TIMESTAMP_NOT_READY) {537* result = timestamp;538* available = true;539* }540* uint32_t result_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;541* if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {542* if (flags & VK_QUERY_RESULT_64_BIT) {543* dst_buf[dst_offset] = result;544* } else {545* dst_buf[dst_offset] = (uint32_t)result;546* }547* }548* if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {549* dst_buf[dst_offset + result_size] = available;550* }551* }552*/553nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "timestamp_query");554b.shader->info.workgroup_size[0] = 64;555b.shader->info.workgroup_size[1] = 1;556b.shader->info.workgroup_size[2] = 1;557558/* Create and initialize local variables. */559nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result");560nir_variable *available = nir_local_variable_create(b.impl, glsl_bool_type(), "available");561562nir_store_var(&b, result, nir_imm_int64(&b, 0), 0x1);563nir_store_var(&b, available, nir_imm_false(&b), 0x1);564565nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range = 16);566567/* Load resources. */568nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0);569nir_ssa_def *src_buf = radv_meta_load_descriptor(&b, 0, 1);570571/* Compute global ID. */572nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);573nir_ssa_def *wg_id = nir_load_workgroup_id(&b, 32);574nir_ssa_def *block_size =575nir_imm_ivec4(&b, b.shader->info.workgroup_size[0], b.shader->info.workgroup_size[1],576b.shader->info.workgroup_size[2], 0);577nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);578global_id = nir_channel(&b, global_id, 0); // We only care about x here.579580/* Compute src/dst strides. */581nir_ssa_def *input_stride = nir_imm_int(&b, 8);582nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);583nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range = 16);584nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);585586/* Load data from the query pool. */587nir_ssa_def *load = nir_load_ssbo(&b, 2, 32, src_buf, input_base, .align_mul = 8);588589/* Pack the timestamp. */590nir_ssa_def *timestamp;591timestamp =592nir_pack_64_2x32(&b, nir_vec2(&b, nir_channel(&b, load, 0), nir_channel(&b, load, 1)));593594/* Check if result is available. */595nir_ssa_def *result_is_available =596nir_i2b(&b, nir_ine(&b, timestamp, nir_imm_int64(&b, TIMESTAMP_NOT_READY)));597598/* Only store result if available. */599nir_push_if(&b, result_is_available);600601nir_store_var(&b, result, timestamp, 0x1);602nir_store_var(&b, available, nir_imm_true(&b), 0x1);603604nir_pop_if(&b, NULL);605606/* Determine if result is 64 or 32 bit. */607nir_ssa_def *result_is_64bit = nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT);608nir_ssa_def *result_size =609nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));610611/* Store the result if complete or partial results have been requested. */612nir_push_if(&b, nir_ior(&b, nir_test_flag(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT),613nir_load_var(&b, available)));614615/* Store result. */616nir_push_if(&b, result_is_64bit);617618nir_store_ssbo(&b, nir_load_var(&b, result), dst_buf, output_base, .write_mask = 0x1,619.align_mul = 8);620621nir_push_else(&b, NULL);622623nir_store_ssbo(&b, nir_u2u32(&b, nir_load_var(&b, result)), dst_buf, output_base,624.write_mask = 0x1, .align_mul = 4);625626nir_pop_if(&b, NULL);627628nir_pop_if(&b, NULL);629630radv_store_availability(&b, flags, dst_buf, nir_iadd(&b, result_size, output_base),631nir_b2i32(&b, nir_load_var(&b, available)));632633return b.shader;634}635636static VkResult637radv_device_init_meta_query_state_internal(struct radv_device *device)638{639VkResult result;640nir_shader *occlusion_cs = NULL;641nir_shader *pipeline_statistics_cs = NULL;642nir_shader *tfb_cs = NULL;643nir_shader *timestamp_cs = NULL;644645mtx_lock(&device->meta_state.mtx);646if (device->meta_state.query.pipeline_statistics_query_pipeline) {647mtx_unlock(&device->meta_state.mtx);648return VK_SUCCESS;649}650occlusion_cs = build_occlusion_query_shader(device);651pipeline_statistics_cs = build_pipeline_statistics_query_shader(device);652tfb_cs = build_tfb_query_shader(device);653timestamp_cs = build_timestamp_query_shader(device);654655VkDescriptorSetLayoutCreateInfo occlusion_ds_create_info = {656.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,657.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,658.bindingCount = 2,659.pBindings = (VkDescriptorSetLayoutBinding[]){660{.binding = 0,661.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,662.descriptorCount = 1,663.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,664.pImmutableSamplers = NULL},665{.binding = 1,666.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,667.descriptorCount = 1,668.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,669.pImmutableSamplers = NULL},670}};671672result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &occlusion_ds_create_info,673&device->meta_state.alloc,674&device->meta_state.query.ds_layout);675if (result != VK_SUCCESS)676goto fail;677678VkPipelineLayoutCreateInfo occlusion_pl_create_info = {679.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,680.setLayoutCount = 1,681.pSetLayouts = &device->meta_state.query.ds_layout,682.pushConstantRangeCount = 1,683.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},684};685686result =687radv_CreatePipelineLayout(radv_device_to_handle(device), &occlusion_pl_create_info,688&device->meta_state.alloc, &device->meta_state.query.p_layout);689if (result != VK_SUCCESS)690goto fail;691692VkPipelineShaderStageCreateInfo occlusion_pipeline_shader_stage = {693.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,694.stage = VK_SHADER_STAGE_COMPUTE_BIT,695.module = vk_shader_module_handle_from_nir(occlusion_cs),696.pName = "main",697.pSpecializationInfo = NULL,698};699700VkComputePipelineCreateInfo occlusion_vk_pipeline_info = {701.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,702.stage = occlusion_pipeline_shader_stage,703.flags = 0,704.layout = device->meta_state.query.p_layout,705};706707result = radv_CreateComputePipelines(708radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,709&occlusion_vk_pipeline_info, NULL, &device->meta_state.query.occlusion_query_pipeline);710if (result != VK_SUCCESS)711goto fail;712713VkPipelineShaderStageCreateInfo pipeline_statistics_pipeline_shader_stage = {714.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,715.stage = VK_SHADER_STAGE_COMPUTE_BIT,716.module = vk_shader_module_handle_from_nir(pipeline_statistics_cs),717.pName = "main",718.pSpecializationInfo = NULL,719};720721VkComputePipelineCreateInfo pipeline_statistics_vk_pipeline_info = {722.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,723.stage = pipeline_statistics_pipeline_shader_stage,724.flags = 0,725.layout = device->meta_state.query.p_layout,726};727728result = radv_CreateComputePipelines(729radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,730&pipeline_statistics_vk_pipeline_info, NULL,731&device->meta_state.query.pipeline_statistics_query_pipeline);732if (result != VK_SUCCESS)733goto fail;734735VkPipelineShaderStageCreateInfo tfb_pipeline_shader_stage = {736.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,737.stage = VK_SHADER_STAGE_COMPUTE_BIT,738.module = vk_shader_module_handle_from_nir(tfb_cs),739.pName = "main",740.pSpecializationInfo = NULL,741};742743VkComputePipelineCreateInfo tfb_pipeline_info = {744.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,745.stage = tfb_pipeline_shader_stage,746.flags = 0,747.layout = device->meta_state.query.p_layout,748};749750result = radv_CreateComputePipelines(751radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,752&tfb_pipeline_info, NULL, &device->meta_state.query.tfb_query_pipeline);753if (result != VK_SUCCESS)754goto fail;755756VkPipelineShaderStageCreateInfo timestamp_pipeline_shader_stage = {757.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,758.stage = VK_SHADER_STAGE_COMPUTE_BIT,759.module = vk_shader_module_handle_from_nir(timestamp_cs),760.pName = "main",761.pSpecializationInfo = NULL,762};763764VkComputePipelineCreateInfo timestamp_pipeline_info = {765.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,766.stage = timestamp_pipeline_shader_stage,767.flags = 0,768.layout = device->meta_state.query.p_layout,769};770771result = radv_CreateComputePipelines(772radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,773×tamp_pipeline_info, NULL, &device->meta_state.query.timestamp_query_pipeline);774775fail:776if (result != VK_SUCCESS)777radv_device_finish_meta_query_state(device);778ralloc_free(occlusion_cs);779ralloc_free(pipeline_statistics_cs);780ralloc_free(tfb_cs);781ralloc_free(timestamp_cs);782mtx_unlock(&device->meta_state.mtx);783return result;784}785786VkResult787radv_device_init_meta_query_state(struct radv_device *device, bool on_demand)788{789if (on_demand)790return VK_SUCCESS;791792return radv_device_init_meta_query_state_internal(device);793}794795void796radv_device_finish_meta_query_state(struct radv_device *device)797{798if (device->meta_state.query.tfb_query_pipeline)799radv_DestroyPipeline(radv_device_to_handle(device),800device->meta_state.query.tfb_query_pipeline, &device->meta_state.alloc);801802if (device->meta_state.query.pipeline_statistics_query_pipeline)803radv_DestroyPipeline(radv_device_to_handle(device),804device->meta_state.query.pipeline_statistics_query_pipeline,805&device->meta_state.alloc);806807if (device->meta_state.query.occlusion_query_pipeline)808radv_DestroyPipeline(radv_device_to_handle(device),809device->meta_state.query.occlusion_query_pipeline,810&device->meta_state.alloc);811812if (device->meta_state.query.timestamp_query_pipeline)813radv_DestroyPipeline(radv_device_to_handle(device),814device->meta_state.query.timestamp_query_pipeline,815&device->meta_state.alloc);816817if (device->meta_state.query.p_layout)818radv_DestroyPipelineLayout(radv_device_to_handle(device), device->meta_state.query.p_layout,819&device->meta_state.alloc);820821if (device->meta_state.query.ds_layout)822radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),823device->meta_state.query.ds_layout,824&device->meta_state.alloc);825}826827static void828radv_query_shader(struct radv_cmd_buffer *cmd_buffer, VkPipeline *pipeline,829struct radeon_winsys_bo *src_bo, struct radeon_winsys_bo *dst_bo,830uint64_t src_offset, uint64_t dst_offset, uint32_t src_stride,831uint32_t dst_stride, uint32_t count, uint32_t flags, uint32_t pipeline_stats_mask,832uint32_t avail_offset)833{834struct radv_device *device = cmd_buffer->device;835struct radv_meta_saved_state saved_state;836bool old_predicating;837838if (!*pipeline) {839VkResult ret = radv_device_init_meta_query_state_internal(device);840if (ret != VK_SUCCESS) {841cmd_buffer->record_result = ret;842return;843}844}845846radv_meta_save(847&saved_state, cmd_buffer,848RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);849850/* VK_EXT_conditional_rendering says that copy commands should not be851* affected by conditional rendering.852*/853old_predicating = cmd_buffer->state.predicating;854cmd_buffer->state.predicating = false;855856struct radv_buffer dst_buffer = {.bo = dst_bo, .offset = dst_offset, .size = dst_stride * count};857858struct radv_buffer src_buffer = {859.bo = src_bo,860.offset = src_offset,861.size = MAX2(src_stride * count, avail_offset + 4 * count - src_offset)};862863radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,864*pipeline);865866radv_meta_push_descriptor_set(867cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, device->meta_state.query.p_layout, 0, /* set */8682, /* descriptorWriteCount */869(VkWriteDescriptorSet[]){870{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,871.dstBinding = 0,872.dstArrayElement = 0,873.descriptorCount = 1,874.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,875.pBufferInfo = &(VkDescriptorBufferInfo){.buffer = radv_buffer_to_handle(&dst_buffer),876.offset = 0,877.range = VK_WHOLE_SIZE}},878{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,879.dstBinding = 1,880.dstArrayElement = 0,881.descriptorCount = 1,882.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,883.pBufferInfo = &(VkDescriptorBufferInfo){.buffer = radv_buffer_to_handle(&src_buffer),884.offset = 0,885.range = VK_WHOLE_SIZE}}});886887/* Encode the number of elements for easy access by the shader. */888pipeline_stats_mask &= 0x7ff;889pipeline_stats_mask |= util_bitcount(pipeline_stats_mask) << 16;890891avail_offset -= src_offset;892893struct {894uint32_t flags;895uint32_t dst_stride;896uint32_t pipeline_stats_mask;897uint32_t avail_offset;898} push_constants = {flags, dst_stride, pipeline_stats_mask, avail_offset};899900radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.query.p_layout,901VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants), &push_constants);902903cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_INV_VCACHE;904905if (flags & VK_QUERY_RESULT_WAIT_BIT)906cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER;907908radv_unaligned_dispatch(cmd_buffer, count, 1, 1);909910/* Restore conditional rendering. */911cmd_buffer->state.predicating = old_predicating;912913radv_meta_restore(&saved_state, cmd_buffer);914}915916static bool917radv_query_pool_needs_gds(struct radv_device *device, struct radv_query_pool *pool)918{919/* The number of primitives generated by geometry shader invocations is920* only counted by the hardware if GS uses the legacy path. When NGG GS921* is used, the hardware can't know the number of generated primitives922* and we have to it manually inside the shader. To achieve that, the923* driver does a plain GDS atomic to accumulate that value.924* TODO: fix use of NGG GS and non-NGG GS inside the same begin/end925* query.926*/927return device->physical_device->use_ngg &&928(pool->pipeline_stats_mask & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT);929}930931static void932radv_destroy_query_pool(struct radv_device *device, const VkAllocationCallbacks *pAllocator,933struct radv_query_pool *pool)934{935if (pool->bo)936device->ws->buffer_destroy(device->ws, pool->bo);937vk_object_base_finish(&pool->base);938vk_free2(&device->vk.alloc, pAllocator, pool);939}940941VkResult942radv_CreateQueryPool(VkDevice _device, const VkQueryPoolCreateInfo *pCreateInfo,943const VkAllocationCallbacks *pAllocator, VkQueryPool *pQueryPool)944{945RADV_FROM_HANDLE(radv_device, device, _device);946struct radv_query_pool *pool =947vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);948949if (!pool)950return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);951952vk_object_base_init(&device->vk, &pool->base, VK_OBJECT_TYPE_QUERY_POOL);953954switch (pCreateInfo->queryType) {955case VK_QUERY_TYPE_OCCLUSION:956pool->stride = 16 * device->physical_device->rad_info.max_render_backends;957break;958case VK_QUERY_TYPE_PIPELINE_STATISTICS:959pool->stride = pipelinestat_block_size * 2;960break;961case VK_QUERY_TYPE_TIMESTAMP:962pool->stride = 8;963break;964case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:965pool->stride = 32;966break;967default:968unreachable("creating unhandled query type");969}970971pool->type = pCreateInfo->queryType;972pool->pipeline_stats_mask = pCreateInfo->pipelineStatistics;973pool->availability_offset = pool->stride * pCreateInfo->queryCount;974pool->size = pool->availability_offset;975if (pCreateInfo->queryType == VK_QUERY_TYPE_PIPELINE_STATISTICS)976pool->size += 4 * pCreateInfo->queryCount;977978VkResult result = device->ws->buffer_create(device->ws, pool->size, 64, RADEON_DOMAIN_GTT,979RADEON_FLAG_NO_INTERPROCESS_SHARING,980RADV_BO_PRIORITY_QUERY_POOL, 0, &pool->bo);981if (result != VK_SUCCESS) {982radv_destroy_query_pool(device, pAllocator, pool);983return vk_error(device->instance, result);984}985986pool->ptr = device->ws->buffer_map(pool->bo);987if (!pool->ptr) {988radv_destroy_query_pool(device, pAllocator, pool);989return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);990}991992*pQueryPool = radv_query_pool_to_handle(pool);993return VK_SUCCESS;994}995996void997radv_DestroyQueryPool(VkDevice _device, VkQueryPool _pool, const VkAllocationCallbacks *pAllocator)998{999RADV_FROM_HANDLE(radv_device, device, _device);1000RADV_FROM_HANDLE(radv_query_pool, pool, _pool);10011002if (!pool)1003return;10041005radv_destroy_query_pool(device, pAllocator, pool);1006}10071008VkResult1009radv_GetQueryPoolResults(VkDevice _device, VkQueryPool queryPool, uint32_t firstQuery,1010uint32_t queryCount, size_t dataSize, void *pData, VkDeviceSize stride,1011VkQueryResultFlags flags)1012{1013RADV_FROM_HANDLE(radv_device, device, _device);1014RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);1015char *data = pData;1016VkResult result = VK_SUCCESS;10171018if (radv_device_is_lost(device))1019return VK_ERROR_DEVICE_LOST;10201021for (unsigned query_idx = 0; query_idx < queryCount; ++query_idx, data += stride) {1022char *dest = data;1023unsigned query = firstQuery + query_idx;1024char *src = pool->ptr + query * pool->stride;1025uint32_t available;10261027switch (pool->type) {1028case VK_QUERY_TYPE_TIMESTAMP: {1029uint64_t const *src64 = (uint64_t const *)src;1030uint64_t value;10311032do {1033value = p_atomic_read(src64);1034} while (value == TIMESTAMP_NOT_READY && (flags & VK_QUERY_RESULT_WAIT_BIT));10351036available = value != TIMESTAMP_NOT_READY;10371038if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT))1039result = VK_NOT_READY;10401041if (flags & VK_QUERY_RESULT_64_BIT) {1042if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))1043*(uint64_t *)dest = value;1044dest += 8;1045} else {1046if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))1047*(uint32_t *)dest = (uint32_t)value;1048dest += 4;1049}1050break;1051}1052case VK_QUERY_TYPE_OCCLUSION: {1053uint64_t const *src64 = (uint64_t const *)src;1054uint32_t db_count = device->physical_device->rad_info.max_render_backends;1055uint32_t enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;1056uint64_t sample_count = 0;1057available = 1;10581059for (int i = 0; i < db_count; ++i) {1060uint64_t start, end;10611062if (!(enabled_rb_mask & (1 << i)))1063continue;10641065do {1066start = p_atomic_read(src64 + 2 * i);1067end = p_atomic_read(src64 + 2 * i + 1);1068} while ((!(start & (1ull << 63)) || !(end & (1ull << 63))) &&1069(flags & VK_QUERY_RESULT_WAIT_BIT));10701071if (!(start & (1ull << 63)) || !(end & (1ull << 63)))1072available = 0;1073else {1074sample_count += end - start;1075}1076}10771078if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT))1079result = VK_NOT_READY;10801081if (flags & VK_QUERY_RESULT_64_BIT) {1082if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))1083*(uint64_t *)dest = sample_count;1084dest += 8;1085} else {1086if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))1087*(uint32_t *)dest = sample_count;1088dest += 4;1089}1090break;1091}1092case VK_QUERY_TYPE_PIPELINE_STATISTICS: {1093const uint32_t *avail_ptr =1094(const uint32_t *)(pool->ptr + pool->availability_offset + 4 * query);10951096do {1097available = p_atomic_read(avail_ptr);1098} while (!available && (flags & VK_QUERY_RESULT_WAIT_BIT));10991100if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT))1101result = VK_NOT_READY;11021103const uint64_t *start = (uint64_t *)src;1104const uint64_t *stop = (uint64_t *)(src + pipelinestat_block_size);1105if (flags & VK_QUERY_RESULT_64_BIT) {1106uint64_t *dst = (uint64_t *)dest;1107dest += util_bitcount(pool->pipeline_stats_mask) * 8;1108for (int i = 0; i < ARRAY_SIZE(pipeline_statistics_indices); ++i) {1109if (pool->pipeline_stats_mask & (1u << i)) {1110if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))1111*dst = stop[pipeline_statistics_indices[i]] -1112start[pipeline_statistics_indices[i]];1113dst++;1114}1115}11161117} else {1118uint32_t *dst = (uint32_t *)dest;1119dest += util_bitcount(pool->pipeline_stats_mask) * 4;1120for (int i = 0; i < ARRAY_SIZE(pipeline_statistics_indices); ++i) {1121if (pool->pipeline_stats_mask & (1u << i)) {1122if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))1123*dst = stop[pipeline_statistics_indices[i]] -1124start[pipeline_statistics_indices[i]];1125dst++;1126}1127}1128}1129break;1130}1131case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT: {1132uint64_t const *src64 = (uint64_t const *)src;1133uint64_t num_primitives_written;1134uint64_t primitive_storage_needed;11351136/* SAMPLE_STREAMOUTSTATS stores this structure:1137* {1138* u64 NumPrimitivesWritten;1139* u64 PrimitiveStorageNeeded;1140* }1141*/1142available = 1;1143for (int j = 0; j < 4; j++) {1144if (!(p_atomic_read(src64 + j) & 0x8000000000000000UL))1145available = 0;1146}11471148if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT))1149result = VK_NOT_READY;11501151num_primitives_written = src64[3] - src64[1];1152primitive_storage_needed = src64[2] - src64[0];11531154if (flags & VK_QUERY_RESULT_64_BIT) {1155if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))1156*(uint64_t *)dest = num_primitives_written;1157dest += 8;1158if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))1159*(uint64_t *)dest = primitive_storage_needed;1160dest += 8;1161} else {1162if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))1163*(uint32_t *)dest = num_primitives_written;1164dest += 4;1165if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))1166*(uint32_t *)dest = primitive_storage_needed;1167dest += 4;1168}1169break;1170}1171default:1172unreachable("trying to get results of unhandled query type");1173}11741175if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {1176if (flags & VK_QUERY_RESULT_64_BIT) {1177*(uint64_t *)dest = available;1178} else {1179*(uint32_t *)dest = available;1180}1181}1182}11831184return result;1185}11861187static void1188emit_query_flush(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool)1189{1190if (cmd_buffer->pending_reset_query) {1191if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) {1192/* Only need to flush caches if the query pool size is1193* large enough to be resetted using the compute shader1194* path. Small pools don't need any cache flushes1195* because we use a CP dma clear.1196*/1197si_emit_cache_flush(cmd_buffer);1198}1199}1200}12011202void1203radv_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool,1204uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer,1205VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags)1206{1207RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);1208RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);1209RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer);1210struct radeon_cmdbuf *cs = cmd_buffer->cs;1211uint64_t va = radv_buffer_get_va(pool->bo);1212uint64_t dest_va = radv_buffer_get_va(dst_buffer->bo);1213dest_va += dst_buffer->offset + dstOffset;12141215radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pool->bo);1216radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo);12171218/* From the Vulkan spec 1.1.108:1219*1220* "vkCmdCopyQueryPoolResults is guaranteed to see the effect of1221* previous uses of vkCmdResetQueryPool in the same queue, without any1222* additional synchronization."1223*1224* So, we have to flush the caches if the compute shader path was used.1225*/1226emit_query_flush(cmd_buffer, pool);12271228switch (pool->type) {1229case VK_QUERY_TYPE_OCCLUSION:1230if (flags & VK_QUERY_RESULT_WAIT_BIT) {1231unsigned enabled_rb_mask = cmd_buffer->device->physical_device->rad_info.enabled_rb_mask;1232uint32_t rb_avail_offset = 16 * util_last_bit(enabled_rb_mask) - 4;1233for (unsigned i = 0; i < queryCount; ++i, dest_va += stride) {1234unsigned query = firstQuery + i;1235uint64_t src_va = va + query * pool->stride + rb_avail_offset;12361237radeon_check_space(cmd_buffer->device->ws, cs, 7);12381239/* Waits on the upper word of the last DB entry */1240radv_cp_wait_mem(cs, WAIT_REG_MEM_GREATER_OR_EQUAL, src_va, 0x80000000, 0xffffffff);1241}1242}1243radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.occlusion_query_pipeline,1244pool->bo, dst_buffer->bo, firstQuery * pool->stride,1245dst_buffer->offset + dstOffset, pool->stride, stride, queryCount, flags, 0,12460);1247break;1248case VK_QUERY_TYPE_PIPELINE_STATISTICS:1249if (flags & VK_QUERY_RESULT_WAIT_BIT) {1250for (unsigned i = 0; i < queryCount; ++i, dest_va += stride) {1251unsigned query = firstQuery + i;12521253radeon_check_space(cmd_buffer->device->ws, cs, 7);12541255uint64_t avail_va = va + pool->availability_offset + 4 * query;12561257/* This waits on the ME. All copies below are done on the ME */1258radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, avail_va, 1, 0xffffffff);1259}1260}1261radv_query_shader(cmd_buffer,1262&cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,1263pool->bo, dst_buffer->bo, firstQuery * pool->stride,1264dst_buffer->offset + dstOffset, pool->stride, stride, queryCount, flags,1265pool->pipeline_stats_mask, pool->availability_offset + 4 * firstQuery);1266break;1267case VK_QUERY_TYPE_TIMESTAMP:1268if (flags & VK_QUERY_RESULT_WAIT_BIT) {1269for (unsigned i = 0; i < queryCount; ++i, dest_va += stride) {1270unsigned query = firstQuery + i;1271uint64_t local_src_va = va + query * pool->stride;12721273radeon_check_space(cmd_buffer->device->ws, cs, 7);12741275/* Wait on the high 32 bits of the timestamp in1276* case the low part is 0xffffffff.1277*/1278radv_cp_wait_mem(cs, WAIT_REG_MEM_NOT_EQUAL, local_src_va + 4,1279TIMESTAMP_NOT_READY >> 32, 0xffffffff);1280}1281}12821283radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.timestamp_query_pipeline,1284pool->bo, dst_buffer->bo, firstQuery * pool->stride,1285dst_buffer->offset + dstOffset, pool->stride, stride, queryCount, flags, 0,12860);1287break;1288case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:1289if (flags & VK_QUERY_RESULT_WAIT_BIT) {1290for (unsigned i = 0; i < queryCount; i++) {1291unsigned query = firstQuery + i;1292uint64_t src_va = va + query * pool->stride;12931294radeon_check_space(cmd_buffer->device->ws, cs, 7 * 4);12951296/* Wait on the upper word of all results. */1297for (unsigned j = 0; j < 4; j++, src_va += 8) {1298radv_cp_wait_mem(cs, WAIT_REG_MEM_GREATER_OR_EQUAL, src_va + 4, 0x80000000,12990xffffffff);1300}1301}1302}13031304radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.tfb_query_pipeline,1305pool->bo, dst_buffer->bo, firstQuery * pool->stride,1306dst_buffer->offset + dstOffset, pool->stride, stride, queryCount, flags, 0,13070);1308break;1309default:1310unreachable("trying to get results of unhandled query type");1311}1312}13131314void1315radv_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery,1316uint32_t queryCount)1317{1318RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);1319RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);1320uint32_t value = pool->type == VK_QUERY_TYPE_TIMESTAMP ? (uint32_t)TIMESTAMP_NOT_READY : 0;1321uint32_t flush_bits = 0;13221323/* Make sure to sync all previous work if the given command buffer has1324* pending active queries. Otherwise the GPU might write queries data1325* after the reset operation.1326*/1327cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;13281329flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo, firstQuery * pool->stride,1330queryCount * pool->stride, value);13311332if (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) {1333flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo,1334pool->availability_offset + firstQuery * 4, queryCount * 4, 0);1335}13361337if (flush_bits) {1338/* Only need to flush caches for the compute shader path. */1339cmd_buffer->pending_reset_query = true;1340cmd_buffer->state.flush_bits |= flush_bits;1341}1342}13431344void1345radv_ResetQueryPool(VkDevice _device, VkQueryPool queryPool, uint32_t firstQuery,1346uint32_t queryCount)1347{1348RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);13491350uint32_t value = pool->type == VK_QUERY_TYPE_TIMESTAMP ? (uint32_t)TIMESTAMP_NOT_READY : 0;1351uint32_t *data = (uint32_t *)(pool->ptr + firstQuery * pool->stride);1352uint32_t *data_end = (uint32_t *)(pool->ptr + (firstQuery + queryCount) * pool->stride);13531354for (uint32_t *p = data; p != data_end; ++p)1355*p = value;13561357if (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) {1358memset(pool->ptr + pool->availability_offset + firstQuery * 4, 0, queryCount * 4);1359}1360}13611362static unsigned1363event_type_for_stream(unsigned stream)1364{1365switch (stream) {1366default:1367case 0:1368return V_028A90_SAMPLE_STREAMOUTSTATS;1369case 1:1370return V_028A90_SAMPLE_STREAMOUTSTATS1;1371case 2:1372return V_028A90_SAMPLE_STREAMOUTSTATS2;1373case 3:1374return V_028A90_SAMPLE_STREAMOUTSTATS3;1375}1376}13771378static void1379emit_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool, uint64_t va,1380VkQueryType query_type, VkQueryControlFlags flags, uint32_t index)1381{1382struct radeon_cmdbuf *cs = cmd_buffer->cs;1383switch (query_type) {1384case VK_QUERY_TYPE_OCCLUSION:1385radeon_check_space(cmd_buffer->device->ws, cs, 7);13861387++cmd_buffer->state.active_occlusion_queries;1388if (cmd_buffer->state.active_occlusion_queries == 1) {1389if (flags & VK_QUERY_CONTROL_PRECISE_BIT) {1390/* This is the first occlusion query, enable1391* the hint if the precision bit is set.1392*/1393cmd_buffer->state.perfect_occlusion_queries_enabled = true;1394}13951396radv_set_db_count_control(cmd_buffer);1397} else {1398if ((flags & VK_QUERY_CONTROL_PRECISE_BIT) &&1399!cmd_buffer->state.perfect_occlusion_queries_enabled) {1400/* This is not the first query, but this one1401* needs to enable precision, DB_COUNT_CONTROL1402* has to be updated accordingly.1403*/1404cmd_buffer->state.perfect_occlusion_queries_enabled = true;14051406radv_set_db_count_control(cmd_buffer);1407}1408}14091410radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));1411radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));1412radeon_emit(cs, va);1413radeon_emit(cs, va >> 32);1414break;1415case VK_QUERY_TYPE_PIPELINE_STATISTICS:1416radeon_check_space(cmd_buffer->device->ws, cs, 4);14171418++cmd_buffer->state.active_pipeline_queries;1419if (cmd_buffer->state.active_pipeline_queries == 1) {1420cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_STOP_PIPELINE_STATS;1421cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_START_PIPELINE_STATS;1422}14231424radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));1425radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));1426radeon_emit(cs, va);1427radeon_emit(cs, va >> 32);14281429if (radv_query_pool_needs_gds(cmd_buffer->device, pool)) {1430int idx = radv_get_pipeline_statistics_index(1431VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT);14321433/* Make sure GDS is idle before copying the value. */1434cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_L2;1435si_emit_cache_flush(cmd_buffer);14361437va += 8 * idx;14381439radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));1440radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_GDS) | COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |1441COPY_DATA_WR_CONFIRM);1442radeon_emit(cs, 0);1443radeon_emit(cs, 0);1444radeon_emit(cs, va);1445radeon_emit(cs, va >> 32);14461447/* Record that the command buffer needs GDS. */1448cmd_buffer->gds_needed = true;14491450cmd_buffer->state.active_pipeline_gds_queries++;1451}1452break;1453case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:1454radeon_check_space(cmd_buffer->device->ws, cs, 4);14551456assert(index < MAX_SO_STREAMS);14571458radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));1459radeon_emit(cs, EVENT_TYPE(event_type_for_stream(index)) | EVENT_INDEX(3));1460radeon_emit(cs, va);1461radeon_emit(cs, va >> 32);1462break;1463default:1464unreachable("beginning unhandled query type");1465}1466}14671468static void1469emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool, uint64_t va,1470uint64_t avail_va, VkQueryType query_type, uint32_t index)1471{1472struct radeon_cmdbuf *cs = cmd_buffer->cs;1473switch (query_type) {1474case VK_QUERY_TYPE_OCCLUSION:1475radeon_check_space(cmd_buffer->device->ws, cs, 14);14761477cmd_buffer->state.active_occlusion_queries--;1478if (cmd_buffer->state.active_occlusion_queries == 0) {1479radv_set_db_count_control(cmd_buffer);14801481/* Reset the perfect occlusion queries hint now that no1482* queries are active.1483*/1484cmd_buffer->state.perfect_occlusion_queries_enabled = false;1485}14861487radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));1488radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));1489radeon_emit(cs, va + 8);1490radeon_emit(cs, (va + 8) >> 32);14911492break;1493case VK_QUERY_TYPE_PIPELINE_STATISTICS:1494radeon_check_space(cmd_buffer->device->ws, cs, 16);14951496cmd_buffer->state.active_pipeline_queries--;1497if (cmd_buffer->state.active_pipeline_queries == 0) {1498cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_START_PIPELINE_STATS;1499cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_STOP_PIPELINE_STATS;1500}1501va += pipelinestat_block_size;15021503radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));1504radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));1505radeon_emit(cs, va);1506radeon_emit(cs, va >> 32);15071508si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.chip_class,1509radv_cmd_buffer_uses_mec(cmd_buffer), V_028A90_BOTTOM_OF_PIPE_TS,15100, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, avail_va, 1,1511cmd_buffer->gfx9_eop_bug_va);15121513if (radv_query_pool_needs_gds(cmd_buffer->device, pool)) {1514int idx = radv_get_pipeline_statistics_index(1515VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT);15161517/* Make sure GDS is idle before copying the value. */1518cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_L2;1519si_emit_cache_flush(cmd_buffer);15201521va += 8 * idx;15221523radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));1524radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_GDS) | COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |1525COPY_DATA_WR_CONFIRM);1526radeon_emit(cs, 0);1527radeon_emit(cs, 0);1528radeon_emit(cs, va);1529radeon_emit(cs, va >> 32);15301531cmd_buffer->state.active_pipeline_gds_queries--;1532}1533break;1534case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:1535radeon_check_space(cmd_buffer->device->ws, cs, 4);15361537assert(index < MAX_SO_STREAMS);15381539radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));1540radeon_emit(cs, EVENT_TYPE(event_type_for_stream(index)) | EVENT_INDEX(3));1541radeon_emit(cs, (va + 16));1542radeon_emit(cs, (va + 16) >> 32);1543break;1544default:1545unreachable("ending unhandled query type");1546}15471548cmd_buffer->active_query_flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |1549RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_L2 |1550RADV_CMD_FLAG_INV_VCACHE;1551if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {1552cmd_buffer->active_query_flush_bits |=1553RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB;1554}1555}15561557void1558radv_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query,1559VkQueryControlFlags flags, uint32_t index)1560{1561RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);1562RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);1563struct radeon_cmdbuf *cs = cmd_buffer->cs;1564uint64_t va = radv_buffer_get_va(pool->bo);15651566radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);15671568emit_query_flush(cmd_buffer, pool);15691570va += pool->stride * query;15711572emit_begin_query(cmd_buffer, pool, va, pool->type, flags, index);1573}15741575void1576radv_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query,1577VkQueryControlFlags flags)1578{1579radv_CmdBeginQueryIndexedEXT(commandBuffer, queryPool, query, flags, 0);1580}15811582void1583radv_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query,1584uint32_t index)1585{1586RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);1587RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);1588uint64_t va = radv_buffer_get_va(pool->bo);1589uint64_t avail_va = va + pool->availability_offset + 4 * query;1590va += pool->stride * query;15911592/* Do not need to add the pool BO to the list because the query must1593* currently be active, which means the BO is already in the list.1594*/1595emit_end_query(cmd_buffer, pool, va, avail_va, pool->type, index);15961597/*1598* For multiview we have to emit a query for each bit in the mask,1599* however the first query we emit will get the totals for all the1600* operations, so we don't want to get a real value in the other1601* queries. This emits a fake begin/end sequence so the waiting1602* code gets a completed query value and doesn't hang, but the1603* query returns 0.1604*/1605if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {1606for (unsigned i = 1; i < util_bitcount(cmd_buffer->state.subpass->view_mask); i++) {1607va += pool->stride;1608avail_va += 4;1609emit_begin_query(cmd_buffer, pool, va, pool->type, 0, 0);1610emit_end_query(cmd_buffer, pool, va, avail_va, pool->type, 0);1611}1612}1613}16141615void1616radv_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query)1617{1618radv_CmdEndQueryIndexedEXT(commandBuffer, queryPool, query, 0);1619}16201621void1622radv_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage,1623VkQueryPool queryPool, uint32_t query)1624{1625RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);1626RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);1627bool mec = radv_cmd_buffer_uses_mec(cmd_buffer);1628struct radeon_cmdbuf *cs = cmd_buffer->cs;1629uint64_t va = radv_buffer_get_va(pool->bo);1630uint64_t query_va = va + pool->stride * query;16311632radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);16331634emit_query_flush(cmd_buffer, pool);16351636int num_queries = 1;1637if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask)1638num_queries = util_bitcount(cmd_buffer->state.subpass->view_mask);16391640ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28 * num_queries);16411642for (unsigned i = 0; i < num_queries; i++) {1643switch (pipelineStage) {1644case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:1645radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));1646radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM |1647COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) | COPY_DATA_DST_SEL(V_370_MEM));1648radeon_emit(cs, 0);1649radeon_emit(cs, 0);1650radeon_emit(cs, query_va);1651radeon_emit(cs, query_va >> 32);1652break;1653default:1654si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.chip_class,1655mec, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM,1656EOP_DATA_SEL_TIMESTAMP, query_va, 0,1657cmd_buffer->gfx9_eop_bug_va);1658break;1659}1660query_va += pool->stride;1661}16621663cmd_buffer->active_query_flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |1664RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_L2 |1665RADV_CMD_FLAG_INV_VCACHE;1666if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {1667cmd_buffer->active_query_flush_bits |=1668RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB;1669}16701671assert(cmd_buffer->cs->cdw <= cdw_max);1672}167316741675