CoCalc -- radv_shader

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/amd/vulkan/radv_shader_args.c
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/*
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 * Copyright © 2019 Valve Corporation.
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 * Copyright © 2016 Red Hat.
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 * Copyright © 2016 Bas Nieuwenhuizen
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 *
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 * based in part on anv driver which is:
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 * Copyright © 2015 Intel Corporation
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the next
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 * paragraph) shall be included in all copies or substantial portions of the
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 * Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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 * IN THE SOFTWARE.
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 */
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#include "radv_shader_args.h"
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#include "radv_private.h"
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#include "radv_shader.h"
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static void
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set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
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{
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   ud_info->sgpr_idx = *sgpr_idx;
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   ud_info->num_sgprs = num_sgprs;
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   *sgpr_idx += num_sgprs;
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}
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static void
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set_loc_shader(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
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{
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   struct radv_userdata_info *ud_info = &args->shader_info->user_sgprs_locs.shader_data[idx];
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   assert(ud_info);
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   set_loc(ud_info, sgpr_idx, num_sgprs);
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}
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static void
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set_loc_shader_ptr(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx)
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{
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   bool use_32bit_pointers = idx != AC_UD_SCRATCH_RING_OFFSETS;
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   set_loc_shader(args, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
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}
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static void
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set_loc_desc(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx)
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{
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   struct radv_userdata_locations *locs = &args->shader_info->user_sgprs_locs;
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   struct radv_userdata_info *ud_info = &locs->descriptor_sets[idx];
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   assert(ud_info);
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   set_loc(ud_info, sgpr_idx, 1);
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   locs->descriptor_sets_enabled |= 1u << idx;
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}
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struct user_sgpr_info {
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   bool indirect_all_descriptor_sets;
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   uint8_t remaining_sgprs;
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};
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static bool
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needs_view_index_sgpr(struct radv_shader_args *args, gl_shader_stage stage)
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{
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   switch (stage) {
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   case MESA_SHADER_VERTEX:
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      if (args->shader_info->needs_multiview_view_index ||
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          (!args->options->key.vs_common_out.as_es && !args->options->key.vs_common_out.as_ls &&
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           args->options->key.has_multiview_view_index))
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         return true;
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      break;
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   case MESA_SHADER_TESS_EVAL:
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      if (args->shader_info->needs_multiview_view_index ||
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          (!args->options->key.vs_common_out.as_es && args->options->key.has_multiview_view_index))
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         return true;
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      break;
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   case MESA_SHADER_TESS_CTRL:
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      if (args->shader_info->needs_multiview_view_index)
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         return true;
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      break;
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   case MESA_SHADER_GEOMETRY:
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      if (args->shader_info->needs_multiview_view_index ||
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          (args->options->key.vs_common_out.as_ngg && args->options->key.has_multiview_view_index))
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         return true;
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      break;
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   default:
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      break;
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   }
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   return false;
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}
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static uint8_t
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count_vs_user_sgprs(struct radv_shader_args *args)
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{
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   uint8_t count = 1; /* vertex offset */
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   if (args->shader_info->vs.vb_desc_usage_mask)
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      count++;
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   if (args->shader_info->vs.needs_draw_id)
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      count++;
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   if (args->shader_info->vs.needs_base_instance)
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      count++;
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   return count;
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}
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static unsigned
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count_ngg_sgprs(struct radv_shader_args *args, gl_shader_stage stage)
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{
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   unsigned count = 0;
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   if (stage == MESA_SHADER_GEOMETRY)
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      count += 1; /* ngg_gs_state */
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   if (args->shader_info->has_ngg_culling)
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      count += 5; /* ngg_culling_settings + 4x ngg_viewport_* */
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   return count;
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}
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static void
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allocate_inline_push_consts(struct radv_shader_args *args, struct user_sgpr_info *user_sgpr_info)
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{
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   uint8_t remaining_sgprs = user_sgpr_info->remaining_sgprs;
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   /* Only supported if shaders use push constants. */
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   if (args->shader_info->min_push_constant_used == UINT8_MAX)
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      return;
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   /* Only supported if shaders don't have indirect push constants. */
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   if (args->shader_info->has_indirect_push_constants)
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      return;
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   /* Only supported for 32-bit push constants. */
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   if (!args->shader_info->has_only_32bit_push_constants)
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      return;
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   uint8_t num_push_consts =
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      (args->shader_info->max_push_constant_used - args->shader_info->min_push_constant_used) / 4;
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   /* Check if the number of user SGPRs is large enough. */
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   if (num_push_consts < remaining_sgprs) {
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      args->shader_info->num_inline_push_consts = num_push_consts;
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   } else {
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      args->shader_info->num_inline_push_consts = remaining_sgprs;
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   }
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   /* Clamp to the maximum number of allowed inlined push constants. */
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   if (args->shader_info->num_inline_push_consts > AC_MAX_INLINE_PUSH_CONSTS)
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      args->shader_info->num_inline_push_consts = AC_MAX_INLINE_PUSH_CONSTS;
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   if (args->shader_info->num_inline_push_consts == num_push_consts &&
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       !args->shader_info->loads_dynamic_offsets) {
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      /* Disable the default push constants path if all constants are
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       * inlined and if shaders don't use dynamic descriptors.
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       */
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      args->shader_info->loads_push_constants = false;
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   }
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   args->shader_info->base_inline_push_consts = args->shader_info->min_push_constant_used / 4;
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}
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static void
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allocate_user_sgprs(struct radv_shader_args *args, gl_shader_stage stage, bool has_previous_stage,
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                    gl_shader_stage previous_stage, bool needs_view_index,
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                    struct user_sgpr_info *user_sgpr_info)
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{
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   uint8_t user_sgpr_count = 0;
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   memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
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   /* 2 user sgprs will always be allocated for scratch/rings */
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   user_sgpr_count += 2;
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   switch (stage) {
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   case MESA_SHADER_COMPUTE:
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      if (args->shader_info->cs.uses_sbt)
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         user_sgpr_count += 1;
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      if (args->shader_info->cs.uses_grid_size)
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         user_sgpr_count += 3;
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      break;
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   case MESA_SHADER_FRAGMENT:
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      user_sgpr_count += args->shader_info->ps.needs_sample_positions;
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      break;
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   case MESA_SHADER_VERTEX:
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      if (!args->is_gs_copy_shader)
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         user_sgpr_count += count_vs_user_sgprs(args);
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      if (args->options->key.vs_common_out.as_ngg)
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         user_sgpr_count += count_ngg_sgprs(args, stage);
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      break;
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   case MESA_SHADER_TESS_CTRL:
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      if (has_previous_stage) {
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         if (previous_stage == MESA_SHADER_VERTEX)
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            user_sgpr_count += count_vs_user_sgprs(args);
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      }
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      break;
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   case MESA_SHADER_TESS_EVAL:
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      if (args->options->key.vs_common_out.as_ngg)
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         user_sgpr_count += count_ngg_sgprs(args, stage);
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      break;
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   case MESA_SHADER_GEOMETRY:
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      if (has_previous_stage) {
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         if (args->options->key.vs_common_out.as_ngg)
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            user_sgpr_count += count_ngg_sgprs(args, stage);
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         if (previous_stage == MESA_SHADER_VERTEX) {
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            user_sgpr_count += count_vs_user_sgprs(args);
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         }
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      }
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      break;
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   default:
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      break;
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   }
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   if (needs_view_index)
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      user_sgpr_count++;
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   if (args->shader_info->loads_push_constants)
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      user_sgpr_count++;
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   if (args->shader_info->so.num_outputs)
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      user_sgpr_count++;
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   uint32_t available_sgprs =
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      args->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
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   uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
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   uint32_t num_desc_set = util_bitcount(args->shader_info->desc_set_used_mask);
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   if (remaining_sgprs < num_desc_set) {
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      user_sgpr_info->indirect_all_descriptor_sets = true;
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      user_sgpr_info->remaining_sgprs = remaining_sgprs - 1;
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   } else {
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      user_sgpr_info->remaining_sgprs = remaining_sgprs - num_desc_set;
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   }
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   allocate_inline_push_consts(args, user_sgpr_info);
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}
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static void
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declare_global_input_sgprs(struct radv_shader_args *args,
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                           const struct user_sgpr_info *user_sgpr_info)
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{
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   /* 1 for each descriptor set */
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   if (!user_sgpr_info->indirect_all_descriptor_sets) {
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      uint32_t mask = args->shader_info->desc_set_used_mask;
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      while (mask) {
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         int i = u_bit_scan(&mask);
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         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_PTR, &args->descriptor_sets[i]);
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      }
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   } else {
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      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_PTR_PTR, &args->descriptor_sets[0]);
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   }
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   if (args->shader_info->loads_push_constants) {
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      /* 1 for push constants and dynamic descriptors */
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      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_PTR, &args->ac.push_constants);
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   }
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   for (unsigned i = 0; i < args->shader_info->num_inline_push_consts; i++) {
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      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.inline_push_consts[i]);
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   }
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   args->ac.num_inline_push_consts = args->shader_info->num_inline_push_consts;
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   args->ac.base_inline_push_consts = args->shader_info->base_inline_push_consts;
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   if (args->shader_info->so.num_outputs) {
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      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR, &args->streamout_buffers);
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   }
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}
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static void
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declare_vs_specific_input_sgprs(struct radv_shader_args *args, gl_shader_stage stage,
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                                bool has_previous_stage, gl_shader_stage previous_stage)
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{
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   if (!args->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX ||
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                                    (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
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      if (args->shader_info->vs.vb_desc_usage_mask) {
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         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR, &args->ac.vertex_buffers);
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      }
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      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.base_vertex);
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      if (args->shader_info->vs.needs_draw_id) {
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         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.draw_id);
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      }
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      if (args->shader_info->vs.needs_base_instance) {
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         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.start_instance);
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      }
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   }
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}
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static void
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declare_vs_input_vgprs(struct radv_shader_args *args)
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{
306
   ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.vertex_id);
307
   if (!args->is_gs_copy_shader) {
308
      if (args->options->key.vs_common_out.as_ls) {
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         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.vs_rel_patch_id);
310
         if (args->options->chip_class >= GFX10) {
311
            ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user vgpr */
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            ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.instance_id);
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         } else {
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            ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.instance_id);
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            ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* unused */
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         }
317
      } else {
318
         if (args->options->chip_class >= GFX10) {
319
            if (args->options->key.vs_common_out.as_ngg) {
320
               ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user vgpr */
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               ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user vgpr */
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               ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.instance_id);
323
            } else {
324
               ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* unused */
325
               ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.vs_prim_id);
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               ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.instance_id);
327
            }
328
         } else {
329
            ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.instance_id);
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            ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.vs_prim_id);
331
            ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* unused */
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         }
333
      }
334
   }
335
}
336

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static void
338
declare_streamout_sgprs(struct radv_shader_args *args, gl_shader_stage stage)
339
{
340
   int i;
341

342
   if (args->options->use_ngg_streamout) {
343
      if (stage == MESA_SHADER_TESS_EVAL)
344
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
345
      return;
346
   }
347

348
   /* Streamout SGPRs. */
349
   if (args->shader_info->so.num_outputs) {
350
      assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL);
351

352
      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.streamout_config);
353
      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.streamout_write_index);
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   } else if (stage == MESA_SHADER_TESS_EVAL) {
355
      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
356
   }
357

358
   /* A streamout buffer offset is loaded if the stride is non-zero. */
359
   for (i = 0; i < 4; i++) {
360
      if (!args->shader_info->so.strides[i])
361
         continue;
362

363
      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.streamout_offset[i]);
364
   }
365
}
366

367
static void
368
declare_tes_input_vgprs(struct radv_shader_args *args)
369
{
370
   ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &args->ac.tes_u);
371
   ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &args->ac.tes_v);
372
   ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tes_rel_patch_id);
373
   ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tes_patch_id);
374
}
375

376
static void
377
declare_ngg_sgprs(struct radv_shader_args *args, gl_shader_stage stage)
378
{
379
   if (stage == MESA_SHADER_GEOMETRY) {
380
      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ngg_gs_state);
381
   }
382

383
   if (args->shader_info->has_ngg_culling) {
384
      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ngg_culling_settings);
385
      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ngg_viewport_scale[0]);
386
      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ngg_viewport_scale[1]);
387
      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ngg_viewport_translate[0]);
388
      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ngg_viewport_translate[1]);
389
   }
390
}
391

392
static void
393
set_global_input_locs(struct radv_shader_args *args, const struct user_sgpr_info *user_sgpr_info,
394
                      uint8_t *user_sgpr_idx)
395
{
396
   uint32_t mask = args->shader_info->desc_set_used_mask;
397

398
   if (!user_sgpr_info->indirect_all_descriptor_sets) {
399
      while (mask) {
400
         int i = u_bit_scan(&mask);
401

402
         set_loc_desc(args, i, user_sgpr_idx);
403
      }
404
   } else {
405
      set_loc_shader_ptr(args, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx);
406

407
      args->shader_info->need_indirect_descriptor_sets = true;
408
   }
409

410
   if (args->shader_info->loads_push_constants) {
411
      set_loc_shader_ptr(args, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
412
   }
413

414
   if (args->shader_info->num_inline_push_consts) {
415
      set_loc_shader(args, AC_UD_INLINE_PUSH_CONSTANTS, user_sgpr_idx,
416
                     args->shader_info->num_inline_push_consts);
417
   }
418

419
   if (args->streamout_buffers.used) {
420
      set_loc_shader_ptr(args, AC_UD_STREAMOUT_BUFFERS, user_sgpr_idx);
421
   }
422
}
423

424
static void
425
set_vs_specific_input_locs(struct radv_shader_args *args, gl_shader_stage stage,
426
                           bool has_previous_stage, gl_shader_stage previous_stage,
427
                           uint8_t *user_sgpr_idx)
428
{
429
   if (!args->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX ||
430
                                    (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
431
      if (args->shader_info->vs.vb_desc_usage_mask) {
432
         set_loc_shader_ptr(args, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx);
433
      }
434

435
      unsigned vs_num =
436
         count_vs_user_sgprs(args) - (args->shader_info->vs.vb_desc_usage_mask ? 1 : 0);
437
      set_loc_shader(args, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
438
   }
439
}
440

441
static void
442
set_ngg_sgprs_locs(struct radv_shader_args *args, gl_shader_stage stage, uint8_t *user_sgpr_idx)
443
{
444
   if (stage == MESA_SHADER_GEOMETRY) {
445
      assert(args->ngg_gs_state.used);
446
      set_loc_shader(args, AC_UD_NGG_GS_STATE, user_sgpr_idx, 1);
447
   }
448

449
   if (args->shader_info->has_ngg_culling) {
450
      assert(args->ngg_culling_settings.used &&
451
             args->ngg_viewport_scale[0].used && args->ngg_viewport_scale[1].used &&
452
             args->ngg_viewport_translate[0].used && args->ngg_viewport_translate[1].used);
453

454
      set_loc_shader(args, AC_UD_NGG_CULLING_SETTINGS, user_sgpr_idx, 1);
455
      set_loc_shader(args, AC_UD_NGG_VIEWPORT, user_sgpr_idx, 4);
456
   }
457
}
458

459
/* Returns whether the stage is a stage that can be directly before the GS */
460
static bool
461
is_pre_gs_stage(gl_shader_stage stage)
462
{
463
   return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
464
}
465

466
void
467
radv_declare_shader_args(struct radv_shader_args *args, gl_shader_stage stage,
468
                         bool has_previous_stage, gl_shader_stage previous_stage)
469
{
470
   struct user_sgpr_info user_sgpr_info;
471
   bool needs_view_index = needs_view_index_sgpr(args, stage);
472

473
   if (args->options->chip_class >= GFX10) {
474
      if (is_pre_gs_stage(stage) && args->options->key.vs_common_out.as_ngg) {
475
         /* On GFX10, VS is merged into GS for NGG. */
476
         previous_stage = stage;
477
         stage = MESA_SHADER_GEOMETRY;
478
         has_previous_stage = true;
479
      }
480
   }
481

482
   for (int i = 0; i < MAX_SETS; i++)
483
      args->shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
484
   for (int i = 0; i < AC_UD_MAX_UD; i++)
485
      args->shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
486

487
   allocate_user_sgprs(args, stage, has_previous_stage, previous_stage, needs_view_index,
488
                       &user_sgpr_info);
489

490
   if (args->options->explicit_scratch_args) {
491
      ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_DESC_PTR, &args->ring_offsets);
492
   }
493

494
   switch (stage) {
495
   case MESA_SHADER_COMPUTE:
496
      declare_global_input_sgprs(args, &user_sgpr_info);
497

498
      if (args->shader_info->cs.uses_sbt) {
499
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR, &args->ac.sbt_descriptors);
500
      }
501

502
      if (args->shader_info->cs.uses_grid_size) {
503
         ac_add_arg(&args->ac, AC_ARG_SGPR, 3, AC_ARG_INT, &args->ac.num_work_groups);
504
      }
505

506
      for (int i = 0; i < 3; i++) {
507
         if (args->shader_info->cs.uses_block_id[i]) {
508
            ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.workgroup_ids[i]);
509
         }
510
      }
511

512
      if (args->shader_info->cs.uses_local_invocation_idx) {
513
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tg_size);
514
      }
515

516
      if (args->options->explicit_scratch_args) {
517
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset);
518
      }
519

520
      ac_add_arg(&args->ac, AC_ARG_VGPR, 3, AC_ARG_INT, &args->ac.local_invocation_ids);
521
      break;
522
   case MESA_SHADER_VERTEX:
523
      declare_global_input_sgprs(args, &user_sgpr_info);
524

525
      declare_vs_specific_input_sgprs(args, stage, has_previous_stage, previous_stage);
526

527
      if (needs_view_index) {
528
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.view_index);
529
      }
530

531
      if (args->options->key.vs_common_out.as_es) {
532
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.es2gs_offset);
533
      } else if (args->options->key.vs_common_out.as_ls) {
534
         /* no extra parameters */
535
      } else {
536
         declare_streamout_sgprs(args, stage);
537
      }
538

539
      if (args->options->explicit_scratch_args) {
540
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset);
541
      }
542
      if (args->options->key.vs_common_out.as_ngg) {
543
         declare_ngg_sgprs(args, stage);
544
      }
545

546
      declare_vs_input_vgprs(args);
547
      break;
548
   case MESA_SHADER_TESS_CTRL:
549
      if (has_previous_stage) {
550
         // First 6 system regs
551
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset);
552
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.merged_wave_info);
553
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tcs_factor_offset);
554

555
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset);
556
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); // unknown
557
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); // unknown
558

559
         declare_global_input_sgprs(args, &user_sgpr_info);
560

561
         declare_vs_specific_input_sgprs(args, stage, has_previous_stage, previous_stage);
562

563
         if (needs_view_index) {
564
            ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.view_index);
565
         }
566

567
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tcs_patch_id);
568
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tcs_rel_ids);
569

570
         declare_vs_input_vgprs(args);
571
      } else {
572
         declare_global_input_sgprs(args, &user_sgpr_info);
573

574
         if (needs_view_index) {
575
            ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.view_index);
576
         }
577

578
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset);
579
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tcs_factor_offset);
580
         if (args->options->explicit_scratch_args) {
581
            ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset);
582
         }
583
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tcs_patch_id);
584
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tcs_rel_ids);
585
      }
586
      break;
587
   case MESA_SHADER_TESS_EVAL:
588
      declare_global_input_sgprs(args, &user_sgpr_info);
589

590
      if (needs_view_index)
591
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.view_index);
592

593
      if (args->options->key.vs_common_out.as_es) {
594
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset);
595
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
596
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.es2gs_offset);
597
      } else {
598
         declare_streamout_sgprs(args, stage);
599
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset);
600
      }
601
      if (args->options->explicit_scratch_args) {
602
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset);
603
      }
604
      if (args->options->key.vs_common_out.as_ngg) {
605
         declare_ngg_sgprs(args, stage);
606
      }
607
      declare_tes_input_vgprs(args);
608
      break;
609
   case MESA_SHADER_GEOMETRY:
610
      if (has_previous_stage) {
611
         // First 6 system regs
612
         if (args->options->key.vs_common_out.as_ngg) {
613
            ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.gs_tg_info);
614
         } else {
615
            ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.gs2vs_offset);
616
         }
617

618
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.merged_wave_info);
619
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset);
620

621
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset);
622
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); // unknown
623
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); // unknown
624

625
         declare_global_input_sgprs(args, &user_sgpr_info);
626

627
         if (previous_stage != MESA_SHADER_TESS_EVAL) {
628
            declare_vs_specific_input_sgprs(args, stage, has_previous_stage, previous_stage);
629
         }
630

631
         if (needs_view_index) {
632
            ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.view_index);
633
         }
634

635
         if (args->options->key.vs_common_out.as_ngg) {
636
            declare_ngg_sgprs(args, stage);
637
         }
638

639
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[0]);
640
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[2]);
641
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_prim_id);
642
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_invocation_id);
643
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[4]);
644

645
         if (previous_stage == MESA_SHADER_VERTEX) {
646
            declare_vs_input_vgprs(args);
647
         } else {
648
            declare_tes_input_vgprs(args);
649
         }
650
      } else {
651
         declare_global_input_sgprs(args, &user_sgpr_info);
652

653
         if (needs_view_index) {
654
            ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.view_index);
655
         }
656

657
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.gs2vs_offset);
658
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.gs_wave_id);
659
         if (args->options->explicit_scratch_args) {
660
            ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset);
661
         }
662
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[0]);
663
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[1]);
664
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_prim_id);
665
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[2]);
666
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[3]);
667
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[4]);
668
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[5]);
669
         ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_invocation_id);
670
      }
671
      break;
672
   case MESA_SHADER_FRAGMENT:
673
      declare_global_input_sgprs(args, &user_sgpr_info);
674

675
      ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.prim_mask);
676
      if (args->options->explicit_scratch_args) {
677
         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset);
678
      }
679
      ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_INT, &args->ac.persp_sample);
680
      ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_INT, &args->ac.persp_center);
681
      ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_INT, &args->ac.persp_centroid);
682
      ac_add_arg(&args->ac, AC_ARG_VGPR, 3, AC_ARG_INT, &args->ac.pull_model);
683
      ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_INT, &args->ac.linear_sample);
684
      ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_INT, &args->ac.linear_center);
685
      ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_INT, &args->ac.linear_centroid);
686
      ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, NULL); /* line stipple tex */
687
      ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &args->ac.frag_pos[0]);
688
      ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &args->ac.frag_pos[1]);
689
      ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &args->ac.frag_pos[2]);
690
      ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &args->ac.frag_pos[3]);
691
      ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.front_face);
692
      ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.ancillary);
693
      ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.sample_coverage);
694
      ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* fixed pt */
695
      break;
696
   default:
697
      unreachable("Shader stage not implemented");
698
   }
699

700
   args->shader_info->num_input_vgprs = 0;
701
   args->shader_info->num_input_sgprs = 2;
702
   args->shader_info->num_input_sgprs += args->ac.num_sgprs_used;
703
   args->shader_info->num_input_vgprs = args->ac.num_vgprs_used;
704

705
   uint8_t user_sgpr_idx = 0;
706

707
   set_loc_shader_ptr(args, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx);
708

709
   /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
710
    * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
711
   if (has_previous_stage)
712
      user_sgpr_idx = 0;
713

714
   set_global_input_locs(args, &user_sgpr_info, &user_sgpr_idx);
715

716
   switch (stage) {
717
   case MESA_SHADER_COMPUTE:
718
      if (args->shader_info->cs.uses_sbt) {
719
         set_loc_shader_ptr(args, AC_UD_CS_SBT_DESCRIPTORS, &user_sgpr_idx);
720
      }
721
      if (args->shader_info->cs.uses_grid_size) {
722
         set_loc_shader(args, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, 3);
723
      }
724
      break;
725
   case MESA_SHADER_VERTEX:
726
      set_vs_specific_input_locs(args, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
727
      if (args->ac.view_index.used)
728
         set_loc_shader(args, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
729
      if (args->options->key.vs_common_out.as_ngg)
730
         set_ngg_sgprs_locs(args, stage, &user_sgpr_idx);
731
      break;
732
   case MESA_SHADER_TESS_CTRL:
733
      set_vs_specific_input_locs(args, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
734
      if (args->ac.view_index.used)
735
         set_loc_shader(args, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
736
      break;
737
   case MESA_SHADER_TESS_EVAL:
738
      if (args->ac.view_index.used)
739
         set_loc_shader(args, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
740
      if (args->options->key.vs_common_out.as_ngg)
741
         set_ngg_sgprs_locs(args, stage, &user_sgpr_idx);
742
      break;
743
   case MESA_SHADER_GEOMETRY:
744
      if (has_previous_stage) {
745
         if (previous_stage == MESA_SHADER_VERTEX)
746
            set_vs_specific_input_locs(args, stage, has_previous_stage, previous_stage,
747
                                       &user_sgpr_idx);
748
      }
749
      if (args->ac.view_index.used)
750
         set_loc_shader(args, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
751

752
      if (args->options->key.vs_common_out.as_ngg)
753
         set_ngg_sgprs_locs(args, stage, &user_sgpr_idx);
754
      break;
755
   case MESA_SHADER_FRAGMENT:
756
      break;
757
   default:
758
      unreachable("Shader stage not implemented");
759
   }
760

761
   args->shader_info->num_user_sgprs = user_sgpr_idx;
762
}
763

764
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