Path: blob/21.2-virgl/src/compiler/nir/nir_format_convert.h
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/*1* Copyright © 2017 Intel Corporation2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING19* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS20* IN THE SOFTWARE.21*/2223#include "nir_builder.h"2425#include "util/format_rgb9e5.h"2627static inline nir_ssa_def *28nir_shift_imm(nir_builder *b, nir_ssa_def *value, int left_shift)29{30if (left_shift > 0)31return nir_ishl(b, value, nir_imm_int(b, left_shift));32else if (left_shift < 0)33return nir_ushr(b, value, nir_imm_int(b, -left_shift));34else35return value;36}3738static inline nir_ssa_def *39nir_shift(nir_builder *b, nir_ssa_def *value, nir_ssa_def *left_shift)40{41return nir_bcsel(b,42nir_ige(b, left_shift, nir_imm_int(b, 0)),43nir_ishl(b, value, left_shift),44nir_ushr(b, value, nir_ineg(b, left_shift)));45}4647static inline nir_ssa_def *48nir_mask_shift(struct nir_builder *b, nir_ssa_def *src,49uint32_t mask, int left_shift)50{51return nir_shift_imm(b, nir_iand(b, src, nir_imm_int(b, mask)), left_shift);52}5354static inline nir_ssa_def *55nir_mask_shift_or(struct nir_builder *b, nir_ssa_def *dst, nir_ssa_def *src,56uint32_t src_mask, int src_left_shift)57{58return nir_ior(b, nir_mask_shift(b, src, src_mask, src_left_shift), dst);59}6061static inline nir_ssa_def *62nir_format_mask_uvec(nir_builder *b, nir_ssa_def *src, const unsigned *bits)63{64nir_const_value mask[NIR_MAX_VEC_COMPONENTS];65memset(mask, 0, sizeof(mask));66for (unsigned i = 0; i < src->num_components; i++) {67assert(bits[i] < 32);68mask[i].u32 = (1u << bits[i]) - 1;69}70return nir_iand(b, src, nir_build_imm(b, src->num_components, 32, mask));71}7273static inline nir_ssa_def *74nir_format_sign_extend_ivec(nir_builder *b, nir_ssa_def *src,75const unsigned *bits)76{77assert(src->num_components <= 4);78nir_ssa_def *comps[4];79for (unsigned i = 0; i < src->num_components; i++) {80nir_ssa_def *shift = nir_imm_int(b, src->bit_size - bits[i]);81comps[i] = nir_ishr(b, nir_ishl(b, nir_channel(b, src, i), shift), shift);82}83return nir_vec(b, comps, src->num_components);84}858687static inline nir_ssa_def *88nir_format_unpack_int(nir_builder *b, nir_ssa_def *packed,89const unsigned *bits, unsigned num_components,90bool sign_extend)91{92assert(num_components >= 1 && num_components <= 4);93const unsigned bit_size = packed->bit_size;94nir_ssa_def *comps[4];9596if (bits[0] >= bit_size) {97assert(bits[0] == bit_size);98assert(num_components == 1);99return packed;100}101102unsigned next_chan = 0;103unsigned offset = 0;104for (unsigned i = 0; i < num_components; i++) {105assert(bits[i] < bit_size);106assert(offset + bits[i] <= bit_size);107nir_ssa_def *chan = nir_channel(b, packed, next_chan);108nir_ssa_def *lshift = nir_imm_int(b, bit_size - (offset + bits[i]));109nir_ssa_def *rshift = nir_imm_int(b, bit_size - bits[i]);110if (sign_extend)111comps[i] = nir_ishr(b, nir_ishl(b, chan, lshift), rshift);112else113comps[i] = nir_ushr(b, nir_ishl(b, chan, lshift), rshift);114offset += bits[i];115if (offset >= bit_size) {116next_chan++;117offset -= bit_size;118}119}120121return nir_vec(b, comps, num_components);122}123124static inline nir_ssa_def *125nir_format_unpack_uint(nir_builder *b, nir_ssa_def *packed,126const unsigned *bits, unsigned num_components)127{128return nir_format_unpack_int(b, packed, bits, num_components, false);129}130131static inline nir_ssa_def *132nir_format_unpack_sint(nir_builder *b, nir_ssa_def *packed,133const unsigned *bits, unsigned num_components)134{135return nir_format_unpack_int(b, packed, bits, num_components, true);136}137138static inline nir_ssa_def *139nir_format_pack_uint_unmasked(nir_builder *b, nir_ssa_def *color,140const unsigned *bits, unsigned num_components)141{142assert(num_components >= 1 && num_components <= 4);143nir_ssa_def *packed = nir_imm_int(b, 0);144unsigned offset = 0;145for (unsigned i = 0; i < num_components; i++) {146packed = nir_ior(b, packed, nir_shift_imm(b, nir_channel(b, color, i),147offset));148offset += bits[i];149}150assert(offset <= packed->bit_size);151152return packed;153}154155static inline nir_ssa_def *156nir_format_pack_uint_unmasked_ssa(nir_builder *b, nir_ssa_def *color,157nir_ssa_def *bits)158{159nir_ssa_def *packed = nir_imm_int(b, 0);160nir_ssa_def *offset = nir_imm_int(b, 0);161for (unsigned i = 0; i < bits->num_components; i++) {162packed = nir_ior(b, packed, nir_ishl(b, nir_channel(b, color, i), offset));163offset = nir_iadd(b, offset, nir_channel(b, bits, i));164}165return packed;166}167168static inline nir_ssa_def *169nir_format_pack_uint(nir_builder *b, nir_ssa_def *color,170const unsigned *bits, unsigned num_components)171{172return nir_format_pack_uint_unmasked(b, nir_format_mask_uvec(b, color, bits),173bits, num_components);174}175176static inline nir_ssa_def *177nir_format_bitcast_uvec_unmasked(nir_builder *b, nir_ssa_def *src,178unsigned src_bits, unsigned dst_bits)179{180assert(src->bit_size >= src_bits && src->bit_size >= dst_bits);181assert(src_bits == 8 || src_bits == 16 || src_bits == 32);182assert(dst_bits == 8 || dst_bits == 16 || dst_bits == 32);183184if (src_bits == dst_bits)185return src;186187const unsigned dst_components =188DIV_ROUND_UP(src->num_components * src_bits, dst_bits);189assert(dst_components <= 4);190191nir_ssa_def *dst_chan[4] = {0};192if (dst_bits > src_bits) {193unsigned shift = 0;194unsigned dst_idx = 0;195for (unsigned i = 0; i < src->num_components; i++) {196nir_ssa_def *shifted = nir_ishl(b, nir_channel(b, src, i),197nir_imm_int(b, shift));198if (shift == 0) {199dst_chan[dst_idx] = shifted;200} else {201dst_chan[dst_idx] = nir_ior(b, dst_chan[dst_idx], shifted);202}203204shift += src_bits;205if (shift >= dst_bits) {206dst_idx++;207shift = 0;208}209}210} else {211nir_ssa_def *mask = nir_imm_int(b, ~0u >> (32 - dst_bits));212213unsigned src_idx = 0;214unsigned shift = 0;215for (unsigned i = 0; i < dst_components; i++) {216dst_chan[i] = nir_iand(b, nir_ushr_imm(b, nir_channel(b, src, src_idx),217shift),218mask);219shift += dst_bits;220if (shift >= src_bits) {221src_idx++;222shift = 0;223}224}225}226227return nir_vec(b, dst_chan, dst_components);228}229230static inline nir_ssa_def *231_nir_format_norm_factor(nir_builder *b, const unsigned *bits,232unsigned num_components,233bool is_signed)234{235nir_const_value factor[NIR_MAX_VEC_COMPONENTS];236memset(factor, 0, sizeof(factor));237for (unsigned i = 0; i < num_components; i++) {238assert(bits[i] <= 32);239factor[i].f32 = (1ull << (bits[i] - is_signed)) - 1;240}241return nir_build_imm(b, num_components, 32, factor);242}243244static inline nir_ssa_def *245nir_format_unorm_to_float(nir_builder *b, nir_ssa_def *u, const unsigned *bits)246{247nir_ssa_def *factor =248_nir_format_norm_factor(b, bits, u->num_components, false);249250return nir_fdiv(b, nir_u2f32(b, u), factor);251}252253static inline nir_ssa_def *254nir_format_snorm_to_float(nir_builder *b, nir_ssa_def *s, const unsigned *bits)255{256nir_ssa_def *factor =257_nir_format_norm_factor(b, bits, s->num_components, true);258259return nir_fmax(b, nir_fdiv(b, nir_i2f32(b, s), factor),260nir_imm_float(b, -1.0f));261}262263static inline nir_ssa_def *264nir_format_float_to_unorm(nir_builder *b, nir_ssa_def *f, const unsigned *bits)265{266nir_ssa_def *factor =267_nir_format_norm_factor(b, bits, f->num_components, false);268269/* Clamp to the range [0, 1] */270f = nir_fsat(b, f);271272return nir_f2u32(b, nir_fround_even(b, nir_fmul(b, f, factor)));273}274275static inline nir_ssa_def *276nir_format_float_to_snorm(nir_builder *b, nir_ssa_def *f, const unsigned *bits)277{278nir_ssa_def *factor =279_nir_format_norm_factor(b, bits, f->num_components, true);280281/* Clamp to the range [-1, 1] */282f = nir_fmin(b, nir_fmax(b, f, nir_imm_float(b, -1)), nir_imm_float(b, 1));283284return nir_f2i32(b, nir_fround_even(b, nir_fmul(b, f, factor)));285}286287/* Converts a vector of floats to a vector of half-floats packed in the low 16288* bits.289*/290static inline nir_ssa_def *291nir_format_float_to_half(nir_builder *b, nir_ssa_def *f)292{293nir_ssa_def *zero = nir_imm_float(b, 0);294nir_ssa_def *f16comps[4];295for (unsigned i = 0; i < f->num_components; i++)296f16comps[i] = nir_pack_half_2x16_split(b, nir_channel(b, f, i), zero);297return nir_vec(b, f16comps, f->num_components);298}299300static inline nir_ssa_def *301nir_format_linear_to_srgb(nir_builder *b, nir_ssa_def *c)302{303nir_ssa_def *linear = nir_fmul(b, c, nir_imm_float(b, 12.92f));304nir_ssa_def *curved =305nir_fsub(b, nir_fmul(b, nir_imm_float(b, 1.055f),306nir_fpow(b, c, nir_imm_float(b, 1.0 / 2.4))),307nir_imm_float(b, 0.055f));308309return nir_fsat(b, nir_bcsel(b, nir_flt(b, c, nir_imm_float(b, 0.0031308f)),310linear, curved));311}312313static inline nir_ssa_def *314nir_format_srgb_to_linear(nir_builder *b, nir_ssa_def *c)315{316nir_ssa_def *linear = nir_fdiv(b, c, nir_imm_float(b, 12.92f));317nir_ssa_def *curved =318nir_fpow(b, nir_fdiv(b, nir_fadd(b, c, nir_imm_float(b, 0.055f)),319nir_imm_float(b, 1.055f)),320nir_imm_float(b, 2.4f));321322return nir_fsat(b, nir_bcsel(b, nir_fge(b, nir_imm_float(b, 0.04045f), c),323linear, curved));324}325326/* Clamps a vector of uints so they don't extend beyond the given number of327* bits per channel.328*/329static inline nir_ssa_def *330nir_format_clamp_uint(nir_builder *b, nir_ssa_def *f, const unsigned *bits)331{332if (bits[0] == 32)333return f;334335nir_const_value max[NIR_MAX_VEC_COMPONENTS];336memset(max, 0, sizeof(max));337for (unsigned i = 0; i < f->num_components; i++) {338assert(bits[i] < 32);339max[i].u32 = (1 << bits[i]) - 1;340}341return nir_umin(b, f, nir_build_imm(b, f->num_components, 32, max));342}343344/* Clamps a vector of sints so they don't extend beyond the given number of345* bits per channel.346*/347static inline nir_ssa_def *348nir_format_clamp_sint(nir_builder *b, nir_ssa_def *f, const unsigned *bits)349{350if (bits[0] == 32)351return f;352353nir_const_value min[NIR_MAX_VEC_COMPONENTS], max[NIR_MAX_VEC_COMPONENTS];354memset(min, 0, sizeof(min));355memset(max, 0, sizeof(max));356for (unsigned i = 0; i < f->num_components; i++) {357assert(bits[i] < 32);358max[i].i32 = (1 << (bits[i] - 1)) - 1;359min[i].i32 = -(1 << (bits[i] - 1));360}361f = nir_imin(b, f, nir_build_imm(b, f->num_components, 32, max));362f = nir_imax(b, f, nir_build_imm(b, f->num_components, 32, min));363364return f;365}366367static inline nir_ssa_def *368nir_format_unpack_11f11f10f(nir_builder *b, nir_ssa_def *packed)369{370nir_ssa_def *chans[3];371chans[0] = nir_mask_shift(b, packed, 0x000007ff, 4);372chans[1] = nir_mask_shift(b, packed, 0x003ff800, -7);373chans[2] = nir_mask_shift(b, packed, 0xffc00000, -17);374375for (unsigned i = 0; i < 3; i++)376chans[i] = nir_unpack_half_2x16_split_x(b, chans[i]);377378return nir_vec(b, chans, 3);379}380381static inline nir_ssa_def *382nir_format_pack_11f11f10f(nir_builder *b, nir_ssa_def *color)383{384/* 10 and 11-bit floats are unsigned. Clamp to non-negative */385nir_ssa_def *clamped = nir_fmax(b, color, nir_imm_float(b, 0));386387nir_ssa_def *undef = nir_ssa_undef(b, 1, color->bit_size);388nir_ssa_def *p1 = nir_pack_half_2x16_split(b, nir_channel(b, clamped, 0),389nir_channel(b, clamped, 1));390nir_ssa_def *p2 = nir_pack_half_2x16_split(b, nir_channel(b, clamped, 2),391undef);392393/* A 10 or 11-bit float has the same exponent as a 16-bit float but with394* fewer mantissa bits and no sign bit. All we have to do is throw away395* the sign bit and the bottom mantissa bits and shift it into place.396*/397nir_ssa_def *packed = nir_imm_int(b, 0);398packed = nir_mask_shift_or(b, packed, p1, 0x00007ff0, -4);399packed = nir_mask_shift_or(b, packed, p1, 0x7ff00000, -9);400packed = nir_mask_shift_or(b, packed, p2, 0x00007fe0, 17);401402return packed;403}404405static inline nir_ssa_def *406nir_format_pack_r9g9b9e5(nir_builder *b, nir_ssa_def *color)407{408/* See also float3_to_rgb9e5 */409410/* First, we need to clamp it to range. */411nir_ssa_def *clamped = nir_fmin(b, color, nir_imm_float(b, MAX_RGB9E5));412413/* Get rid of negatives and NaN */414clamped = nir_bcsel(b, nir_ult(b, nir_imm_int(b, 0x7f800000), color),415nir_imm_float(b, 0), clamped);416417/* maxrgb.u = MAX3(rc.u, gc.u, bc.u); */418nir_ssa_def *maxu = nir_umax(b, nir_channel(b, clamped, 0),419nir_umax(b, nir_channel(b, clamped, 1),420nir_channel(b, clamped, 2)));421422/* maxrgb.u += maxrgb.u & (1 << (23-9)); */423maxu = nir_iadd(b, maxu, nir_iand(b, maxu, nir_imm_int(b, 1 << 14)));424425/* exp_shared = MAX2((maxrgb.u >> 23), -RGB9E5_EXP_BIAS - 1 + 127) +426* 1 + RGB9E5_EXP_BIAS - 127;427*/428nir_ssa_def *exp_shared =429nir_iadd(b, nir_umax(b, nir_ushr_imm(b, maxu, 23),430nir_imm_int(b, -RGB9E5_EXP_BIAS - 1 + 127)),431nir_imm_int(b, 1 + RGB9E5_EXP_BIAS - 127));432433/* revdenom_biasedexp = 127 - (exp_shared - RGB9E5_EXP_BIAS -434* RGB9E5_MANTISSA_BITS) + 1;435*/436nir_ssa_def *revdenom_biasedexp =437nir_isub(b, nir_imm_int(b, 127 + RGB9E5_EXP_BIAS +438RGB9E5_MANTISSA_BITS + 1),439exp_shared);440441/* revdenom.u = revdenom_biasedexp << 23; */442nir_ssa_def *revdenom =443nir_ishl(b, revdenom_biasedexp, nir_imm_int(b, 23));444445/* rm = (int) (rc.f * revdenom.f);446* gm = (int) (gc.f * revdenom.f);447* bm = (int) (bc.f * revdenom.f);448*/449nir_ssa_def *mantissa =450nir_f2i32(b, nir_fmul(b, clamped, revdenom));451452/* rm = (rm & 1) + (rm >> 1);453* gm = (gm & 1) + (gm >> 1);454* bm = (bm & 1) + (bm >> 1);455*/456mantissa = nir_iadd(b, nir_iand_imm(b, mantissa, 1),457nir_ushr_imm(b, mantissa, 1));458459nir_ssa_def *packed = nir_channel(b, mantissa, 0);460packed = nir_mask_shift_or(b, packed, nir_channel(b, mantissa, 1), ~0, 9);461packed = nir_mask_shift_or(b, packed, nir_channel(b, mantissa, 2), ~0, 18);462packed = nir_mask_shift_or(b, packed, exp_shared, ~0, 27);463464return packed;465}466467468