Path: blob/21.2-virgl/src/compiler/nir/nir_inline_helpers.h
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/* _nir_foreach_dest() needs to be ALWAYS_INLINE so that it can inline the1* callback if it was declared with ALWAYS_INLINE.2*/3static ALWAYS_INLINE bool4_nir_foreach_dest(nir_instr *instr, nir_foreach_dest_cb cb, void *state)5{6switch (instr->type) {7case nir_instr_type_alu:8return cb(&nir_instr_as_alu(instr)->dest.dest, state);9case nir_instr_type_deref:10return cb(&nir_instr_as_deref(instr)->dest, state);11case nir_instr_type_intrinsic: {12nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);13if (nir_intrinsic_infos[intrin->intrinsic].has_dest)14return cb(&intrin->dest, state);15return true;16}17case nir_instr_type_tex:18return cb(&nir_instr_as_tex(instr)->dest, state);19case nir_instr_type_phi:20return cb(&nir_instr_as_phi(instr)->dest, state);21case nir_instr_type_parallel_copy: {22nir_foreach_parallel_copy_entry(entry, nir_instr_as_parallel_copy(instr)) {23if (!cb(&entry->dest, state))24return false;25}26return true;27}2829case nir_instr_type_load_const:30case nir_instr_type_ssa_undef:31case nir_instr_type_call:32case nir_instr_type_jump:33break;3435default:36unreachable("Invalid instruction type");37break;38}3940return true;41}4243static ALWAYS_INLINE bool44_nir_visit_src(nir_src *src, nir_foreach_src_cb cb, void *state)45{46if (!cb(src, state))47return false;48if (!src->is_ssa && src->reg.indirect)49return cb(src->reg.indirect, state);50return true;51}5253typedef struct {54void *state;55nir_foreach_src_cb cb;56} _nir_visit_dest_indirect_state;5758static ALWAYS_INLINE bool59_nir_visit_dest_indirect(nir_dest *dest, void *_state)60{61_nir_visit_dest_indirect_state *state = (_nir_visit_dest_indirect_state *) _state;6263if (!dest->is_ssa && dest->reg.indirect)64return state->cb(dest->reg.indirect, state->state);6566return true;67}6869static inline bool70nir_foreach_dest(nir_instr *instr, nir_foreach_dest_cb cb, void *state)71{72return _nir_foreach_dest(instr, cb, state);73}7475static inline bool76nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state)77{78switch (instr->type) {79case nir_instr_type_alu: {80nir_alu_instr *alu = nir_instr_as_alu(instr);81for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++)82if (!_nir_visit_src(&alu->src[i].src, cb, state))83return false;84break;85}86case nir_instr_type_deref: {87nir_deref_instr *deref = nir_instr_as_deref(instr);8889if (deref->deref_type != nir_deref_type_var) {90if (!_nir_visit_src(&deref->parent, cb, state))91return false;92}9394if (deref->deref_type == nir_deref_type_array ||95deref->deref_type == nir_deref_type_ptr_as_array) {96if (!_nir_visit_src(&deref->arr.index, cb, state))97return false;98}99break;100}101case nir_instr_type_intrinsic: {102nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);103unsigned num_srcs = nir_intrinsic_infos[intrin->intrinsic].num_srcs;104for (unsigned i = 0; i < num_srcs; i++) {105if (!_nir_visit_src(&intrin->src[i], cb, state))106return false;107}108break;109}110case nir_instr_type_tex: {111nir_tex_instr *tex = nir_instr_as_tex(instr);112for (unsigned i = 0; i < tex->num_srcs; i++) {113if (!_nir_visit_src(&tex->src[i].src, cb, state))114return false;115}116break;117}118case nir_instr_type_call: {119nir_call_instr *call = nir_instr_as_call(instr);120for (unsigned i = 0; i < call->num_params; i++) {121if (!_nir_visit_src(&call->params[i], cb, state))122return false;123}124break;125}126case nir_instr_type_phi: {127nir_phi_instr *phi = nir_instr_as_phi(instr);128nir_foreach_phi_src(src, phi) {129if (!_nir_visit_src(&src->src, cb, state))130return false;131}132break;133}134case nir_instr_type_parallel_copy: {135nir_parallel_copy_instr *pc = nir_instr_as_parallel_copy(instr);136nir_foreach_parallel_copy_entry(entry, pc) {137if (!_nir_visit_src(&entry->src, cb, state))138return false;139}140break;141}142case nir_instr_type_jump: {143nir_jump_instr *jump = nir_instr_as_jump(instr);144145if (jump->type == nir_jump_goto_if && !_nir_visit_src(&jump->condition, cb, state))146return false;147return true;148}149150case nir_instr_type_load_const:151case nir_instr_type_ssa_undef:152return true;153154default:155unreachable("Invalid instruction type");156break;157}158159_nir_visit_dest_indirect_state dest_state;160dest_state.state = state;161dest_state.cb = cb;162return _nir_foreach_dest(instr, _nir_visit_dest_indirect, &dest_state);163}164165166