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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/compiler/nir/nir_lower_alu.c
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/*
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* Copyright © 2010 Intel Corporation
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* Copyright © 2018 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "nir.h"
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#include "nir_builder.h"
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/** nir_lower_alu.c
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*
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* NIR's home for miscellaneous ALU operation lowering implementations.
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*
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* Most NIR ALU lowering occurs in nir_opt_algebraic.py, since it's generally
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* easy to write them there. However, if terms appear multiple times in the
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* lowered code, it can get very verbose and cause a lot of work for CSE, so
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* it may end up being easier to write out in C code.
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*
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* The shader must be in SSA for this pass.
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*/
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#define LOWER_MUL_HIGH (1 << 0)
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static bool
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lower_alu_instr(nir_alu_instr *instr, nir_builder *b)
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{
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nir_ssa_def *lowered = NULL;
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assert(instr->dest.dest.is_ssa);
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b->cursor = nir_before_instr(&instr->instr);
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b->exact = instr->exact;
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switch (instr->op) {
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case nir_op_bitfield_reverse:
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if (b->shader->options->lower_bitfield_reverse) {
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/* For more details, see:
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*
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* http://graphics.stanford.edu/~seander/bithacks.html#ReverseParallel
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*/
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nir_ssa_def *c1 = nir_imm_int(b, 1);
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nir_ssa_def *c2 = nir_imm_int(b, 2);
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nir_ssa_def *c4 = nir_imm_int(b, 4);
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nir_ssa_def *c8 = nir_imm_int(b, 8);
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nir_ssa_def *c16 = nir_imm_int(b, 16);
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nir_ssa_def *c33333333 = nir_imm_int(b, 0x33333333);
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nir_ssa_def *c55555555 = nir_imm_int(b, 0x55555555);
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nir_ssa_def *c0f0f0f0f = nir_imm_int(b, 0x0f0f0f0f);
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nir_ssa_def *c00ff00ff = nir_imm_int(b, 0x00ff00ff);
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lowered = nir_ssa_for_alu_src(b, instr, 0);
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/* Swap odd and even bits. */
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lowered = nir_ior(b,
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nir_iand(b, nir_ushr(b, lowered, c1), c55555555),
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nir_ishl(b, nir_iand(b, lowered, c55555555), c1));
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/* Swap consecutive pairs. */
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lowered = nir_ior(b,
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nir_iand(b, nir_ushr(b, lowered, c2), c33333333),
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nir_ishl(b, nir_iand(b, lowered, c33333333), c2));
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/* Swap nibbles. */
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lowered = nir_ior(b,
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nir_iand(b, nir_ushr(b, lowered, c4), c0f0f0f0f),
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nir_ishl(b, nir_iand(b, lowered, c0f0f0f0f), c4));
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/* Swap bytes. */
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lowered = nir_ior(b,
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nir_iand(b, nir_ushr(b, lowered, c8), c00ff00ff),
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nir_ishl(b, nir_iand(b, lowered, c00ff00ff), c8));
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lowered = nir_ior(b,
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nir_ushr(b, lowered, c16),
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nir_ishl(b, lowered, c16));
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}
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break;
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case nir_op_bit_count:
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if (b->shader->options->lower_bit_count) {
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/* For more details, see:
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*
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* http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
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*/
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nir_ssa_def *c1 = nir_imm_int(b, 1);
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nir_ssa_def *c2 = nir_imm_int(b, 2);
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nir_ssa_def *c4 = nir_imm_int(b, 4);
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nir_ssa_def *c24 = nir_imm_int(b, 24);
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nir_ssa_def *c33333333 = nir_imm_int(b, 0x33333333);
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nir_ssa_def *c55555555 = nir_imm_int(b, 0x55555555);
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nir_ssa_def *c0f0f0f0f = nir_imm_int(b, 0x0f0f0f0f);
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nir_ssa_def *c01010101 = nir_imm_int(b, 0x01010101);
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lowered = nir_ssa_for_alu_src(b, instr, 0);
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lowered = nir_isub(b, lowered,
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nir_iand(b, nir_ushr(b, lowered, c1), c55555555));
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lowered = nir_iadd(b,
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nir_iand(b, lowered, c33333333),
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nir_iand(b, nir_ushr(b, lowered, c2), c33333333));
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lowered = nir_ushr(b,
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nir_imul(b,
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nir_iand(b,
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nir_iadd(b,
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lowered,
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nir_ushr(b, lowered, c4)),
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c0f0f0f0f),
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c01010101),
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c24);
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}
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break;
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case nir_op_imul_high:
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case nir_op_umul_high:
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if (b->shader->options->lower_mul_high) {
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nir_ssa_def *src0 = nir_ssa_for_alu_src(b, instr, 0);
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nir_ssa_def *src1 = nir_ssa_for_alu_src(b, instr, 1);
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if (src0->bit_size < 32) {
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/* Just do the math in 32-bit space and shift the result */
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nir_alu_type base_type = nir_op_infos[instr->op].output_type;
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nir_op upcast_op = nir_type_conversion_op(base_type | src0->bit_size, base_type | 32, nir_rounding_mode_undef);
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nir_op downscast_op = nir_type_conversion_op(base_type | 32, base_type | src0->bit_size, nir_rounding_mode_undef);
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nir_ssa_def *src0_32 = nir_build_alu(b, upcast_op, src0, NULL, NULL, NULL);
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nir_ssa_def *src1_32 = nir_build_alu(b, upcast_op, src1, NULL, NULL, NULL);
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nir_ssa_def *dest_32 = nir_imul(b, src0_32, src1_32);
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nir_ssa_def *dest_shifted = nir_ishr(b, dest_32, nir_imm_int(b, src0->bit_size));
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lowered = nir_build_alu(b, downscast_op, dest_shifted, NULL, NULL, NULL);
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} else {
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nir_ssa_def *c1 = nir_imm_intN_t(b, 1, src0->bit_size);
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nir_ssa_def *cshift = nir_imm_int(b, src0->bit_size / 2);
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nir_ssa_def *cmask = nir_imm_intN_t(b, (1ull << (src0->bit_size / 2)) - 1, src0->bit_size);
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nir_ssa_def *different_signs = NULL;
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if (instr->op == nir_op_imul_high) {
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nir_ssa_def *c0 = nir_imm_intN_t(b, 0, src0->bit_size);
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different_signs = nir_ixor(b,
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nir_ilt(b, src0, c0),
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nir_ilt(b, src1, c0));
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src0 = nir_iabs(b, src0);
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src1 = nir_iabs(b, src1);
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}
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/* ABCD
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* * EFGH
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* ======
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* (GH * CD) + (GH * AB) << 16 + (EF * CD) << 16 + (EF * AB) << 32
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*
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* Start by splitting into the 4 multiplies.
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*/
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nir_ssa_def *src0l = nir_iand(b, src0, cmask);
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nir_ssa_def *src1l = nir_iand(b, src1, cmask);
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nir_ssa_def *src0h = nir_ushr(b, src0, cshift);
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nir_ssa_def *src1h = nir_ushr(b, src1, cshift);
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nir_ssa_def *lo = nir_imul(b, src0l, src1l);
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nir_ssa_def *m1 = nir_imul(b, src0l, src1h);
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nir_ssa_def *m2 = nir_imul(b, src0h, src1l);
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nir_ssa_def *hi = nir_imul(b, src0h, src1h);
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nir_ssa_def *tmp;
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tmp = nir_ishl(b, m1, cshift);
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hi = nir_iadd(b, hi, nir_iand(b, nir_uadd_carry(b, lo, tmp), c1));
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lo = nir_iadd(b, lo, tmp);
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hi = nir_iadd(b, hi, nir_ushr(b, m1, cshift));
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tmp = nir_ishl(b, m2, cshift);
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hi = nir_iadd(b, hi, nir_iand(b, nir_uadd_carry(b, lo, tmp), c1));
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lo = nir_iadd(b, lo, tmp);
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hi = nir_iadd(b, hi, nir_ushr(b, m2, cshift));
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if (instr->op == nir_op_imul_high) {
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/* For channels where different_signs is set we have to perform a
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* 64-bit negation. This is *not* the same as just negating the
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* high 32-bits. Consider -3 * 2. The high 32-bits is 0, but the
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* desired result is -1, not -0! Recall -x == ~x + 1.
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*/
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hi = nir_bcsel(b, different_signs,
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nir_iadd(b,
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nir_inot(b, hi),
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nir_iand(b,
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nir_uadd_carry(b,
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nir_inot(b, lo),
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c1),
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nir_imm_intN_t(b, 1, src0->bit_size))),
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hi);
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}
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lowered = hi;
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}
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}
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break;
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default:
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break;
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}
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if (lowered) {
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nir_ssa_def_rewrite_uses(&instr->dest.dest.ssa, lowered);
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nir_instr_remove(&instr->instr);
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return true;
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} else {
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return false;
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}
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}
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bool
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nir_lower_alu(nir_shader *shader)
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{
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bool progress = false;
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if (!shader->options->lower_bitfield_reverse &&
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!shader->options->lower_mul_high)
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return false;
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nir_foreach_function(function, shader) {
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if (function->impl) {
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nir_builder builder;
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nir_builder_init(&builder, function->impl);
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nir_foreach_block(block, function->impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type == nir_instr_type_alu) {
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progress = lower_alu_instr(nir_instr_as_alu(instr),
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&builder) || progress;
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}
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}
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}
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if (progress) {
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nir_metadata_preserve(function->impl,
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nir_metadata_block_index |
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nir_metadata_dominance);
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}
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}
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}
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return progress;
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}
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