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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/freedreno/ir3/disasm-a3xx.c
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/*
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* Copyright (c) 2013 Rob Clark <[email protected]>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <util/log.h>
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#include <util/u_debug.h>
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#include "isa/isa.h"
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#include "disasm.h"
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#include "instr-a3xx.h"
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static enum debug_t debug;
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static const char *levels[] = {
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"",
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"\t",
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"\t\t",
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"\t\t\t",
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"\t\t\t\t",
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"\t\t\t\t\t",
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"\t\t\t\t\t\t",
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"\t\t\t\t\t\t\t",
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"\t\t\t\t\t\t\t\t",
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"\t\t\t\t\t\t\t\t\t",
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"x",
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"x",
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"x",
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"x",
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"x",
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"x",
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};
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struct disasm_ctx {
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FILE *out;
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struct isa_decode_options *options;
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unsigned level;
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unsigned extra_cycles;
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/**
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* nop_count/has_end used to detect the real end of shader. Since
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* in some cases there can be a epilogue following an `end` we look
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* for a sequence of `nop`s following the `end`
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*/
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int nop_count; /* number of nop's since non-nop instruction: */
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bool has_end; /* have we seen end instruction */
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int cur_n; /* current instr # */
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int cur_opc_cat; /* current opc_cat */
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int sfu_delay;
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/**
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* State accumulated decoding fields of the current instruction,
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* handled after decoding is complete (ie. at start of next instr)
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*/
83
struct {
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bool ss;
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uint8_t nop;
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uint8_t repeat;
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} last;
88
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/**
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* State accumulated decoding fields of src or dst register
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*/
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struct {
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bool half;
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bool r;
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enum {
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FILE_GPR = 1,
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FILE_CONST = 2,
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} file;
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unsigned num;
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} reg;
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struct shader_stats *stats;
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};
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static void
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print_stats(struct disasm_ctx *ctx)
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{
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if (ctx->options->gpu_id >= 600) {
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/* handle MERGEREGS case.. this isn't *entirely* accurate, as
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* you can have shader stages not using merged register file,
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* but it is good enough for a guestimate:
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*/
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unsigned n = (ctx->stats->halfreg + 1) / 2;
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ctx->stats->halfreg = 0;
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ctx->stats->fullreg = MAX2(ctx->stats->fullreg, n);
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}
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unsigned instructions = ctx->cur_n + ctx->extra_cycles + 1;
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fprintf(ctx->out, "%sStats:\n", levels[ctx->level]);
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fprintf(ctx->out,
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"%s- shaderdb: %u instr, %u nops, %u non-nops, %u mov, %u cov\n",
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levels[ctx->level], instructions, ctx->stats->nops,
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instructions - ctx->stats->nops, ctx->stats->mov_count,
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ctx->stats->cov_count);
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fprintf(ctx->out,
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"%s- shaderdb: %u last-baryf, %d half, %d full, %u constlen\n",
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levels[ctx->level], ctx->stats->last_baryf,
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DIV_ROUND_UP(ctx->stats->halfreg, 4),
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DIV_ROUND_UP(ctx->stats->fullreg, 4),
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DIV_ROUND_UP(ctx->stats->constlen, 4));
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fprintf(
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ctx->out,
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"%s- shaderdb: %u cat0, %u cat1, %u cat2, %u cat3, %u cat4, %u cat5, %u cat6, %u cat7\n",
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levels[ctx->level], ctx->stats->instrs_per_cat[0],
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ctx->stats->instrs_per_cat[1], ctx->stats->instrs_per_cat[2],
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ctx->stats->instrs_per_cat[3], ctx->stats->instrs_per_cat[4],
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ctx->stats->instrs_per_cat[5], ctx->stats->instrs_per_cat[6],
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ctx->stats->instrs_per_cat[7]);
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fprintf(ctx->out, "%s- shaderdb: %u sstall, %u (ss), %u (sy)\n",
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levels[ctx->level], ctx->stats->sstall, ctx->stats->ss,
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ctx->stats->sy);
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}
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/* size of largest OPC field of all the instruction categories: */
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#define NOPC_BITS 6
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static const struct opc_info {
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const char *name;
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} opcs[1 << (3 + NOPC_BITS)] = {
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#define OPC(cat, opc, name) [(opc)] = {#name}
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/* clang-format off */
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/* category 0: */
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OPC(0, OPC_NOP, nop),
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OPC(0, OPC_B, b),
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OPC(0, OPC_JUMP, jump),
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OPC(0, OPC_CALL, call),
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OPC(0, OPC_RET, ret),
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OPC(0, OPC_KILL, kill),
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OPC(0, OPC_DEMOTE, demote),
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OPC(0, OPC_END, end),
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OPC(0, OPC_EMIT, emit),
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OPC(0, OPC_CUT, cut),
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OPC(0, OPC_CHMASK, chmask),
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OPC(0, OPC_CHSH, chsh),
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OPC(0, OPC_FLOW_REV, flow_rev),
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OPC(0, OPC_PREDT, predt),
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OPC(0, OPC_PREDF, predf),
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OPC(0, OPC_PREDE, prede),
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OPC(0, OPC_BKT, bkt),
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OPC(0, OPC_STKS, stks),
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OPC(0, OPC_STKR, stkr),
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OPC(0, OPC_XSET, xset),
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OPC(0, OPC_XCLR, xclr),
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OPC(0, OPC_GETONE, getone),
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OPC(0, OPC_DBG, dbg),
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OPC(0, OPC_SHPS, shps),
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OPC(0, OPC_SHPE, shpe),
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/* category 1: */
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OPC(1, OPC_MOV, ),
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OPC(1, OPC_MOVMSK, movmsk),
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OPC(1, OPC_SWZ, swz),
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OPC(1, OPC_SCT, sct),
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OPC(1, OPC_GAT, gat),
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OPC(1, OPC_BALLOT_MACRO, ballot.macro),
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OPC(1, OPC_ANY_MACRO, any.macro),
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OPC(1, OPC_ALL_MACRO, all.macro),
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OPC(1, OPC_ELECT_MACRO, elect.macro),
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OPC(1, OPC_READ_COND_MACRO, read_cond.macro),
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OPC(1, OPC_READ_FIRST_MACRO, read_first.macro),
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OPC(1, OPC_SWZ_SHARED_MACRO, swz_shared.macro),
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/* category 2: */
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OPC(2, OPC_ADD_F, add.f),
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OPC(2, OPC_MIN_F, min.f),
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OPC(2, OPC_MAX_F, max.f),
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OPC(2, OPC_MUL_F, mul.f),
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OPC(2, OPC_SIGN_F, sign.f),
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OPC(2, OPC_CMPS_F, cmps.f),
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OPC(2, OPC_ABSNEG_F, absneg.f),
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OPC(2, OPC_CMPV_F, cmpv.f),
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OPC(2, OPC_FLOOR_F, floor.f),
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OPC(2, OPC_CEIL_F, ceil.f),
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OPC(2, OPC_RNDNE_F, rndne.f),
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OPC(2, OPC_RNDAZ_F, rndaz.f),
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OPC(2, OPC_TRUNC_F, trunc.f),
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OPC(2, OPC_ADD_U, add.u),
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OPC(2, OPC_ADD_S, add.s),
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OPC(2, OPC_SUB_U, sub.u),
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OPC(2, OPC_SUB_S, sub.s),
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OPC(2, OPC_CMPS_U, cmps.u),
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OPC(2, OPC_CMPS_S, cmps.s),
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OPC(2, OPC_MIN_U, min.u),
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OPC(2, OPC_MIN_S, min.s),
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OPC(2, OPC_MAX_U, max.u),
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OPC(2, OPC_MAX_S, max.s),
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OPC(2, OPC_ABSNEG_S, absneg.s),
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OPC(2, OPC_AND_B, and.b),
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OPC(2, OPC_OR_B, or.b),
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OPC(2, OPC_NOT_B, not.b),
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OPC(2, OPC_XOR_B, xor.b),
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OPC(2, OPC_CMPV_U, cmpv.u),
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OPC(2, OPC_CMPV_S, cmpv.s),
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OPC(2, OPC_MUL_U24, mul.u24),
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OPC(2, OPC_MUL_S24, mul.s24),
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OPC(2, OPC_MULL_U, mull.u),
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OPC(2, OPC_BFREV_B, bfrev.b),
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OPC(2, OPC_CLZ_S, clz.s),
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OPC(2, OPC_CLZ_B, clz.b),
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OPC(2, OPC_SHL_B, shl.b),
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OPC(2, OPC_SHR_B, shr.b),
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OPC(2, OPC_ASHR_B, ashr.b),
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OPC(2, OPC_BARY_F, bary.f),
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OPC(2, OPC_MGEN_B, mgen.b),
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OPC(2, OPC_GETBIT_B, getbit.b),
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OPC(2, OPC_SETRM, setrm),
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OPC(2, OPC_CBITS_B, cbits.b),
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OPC(2, OPC_SHB, shb),
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OPC(2, OPC_MSAD, msad),
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/* category 3: */
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OPC(3, OPC_MAD_U16, mad.u16),
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OPC(3, OPC_MADSH_U16, madsh.u16),
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OPC(3, OPC_MAD_S16, mad.s16),
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OPC(3, OPC_MADSH_M16, madsh.m16),
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OPC(3, OPC_MAD_U24, mad.u24),
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OPC(3, OPC_MAD_S24, mad.s24),
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OPC(3, OPC_MAD_F16, mad.f16),
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OPC(3, OPC_MAD_F32, mad.f32),
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OPC(3, OPC_SEL_B16, sel.b16),
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OPC(3, OPC_SEL_B32, sel.b32),
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OPC(3, OPC_SEL_S16, sel.s16),
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OPC(3, OPC_SEL_S32, sel.s32),
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OPC(3, OPC_SEL_F16, sel.f16),
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OPC(3, OPC_SEL_F32, sel.f32),
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OPC(3, OPC_SAD_S16, sad.s16),
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OPC(3, OPC_SAD_S32, sad.s32),
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OPC(3, OPC_SHLG_B16, shlg.b16),
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/* category 4: */
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OPC(4, OPC_RCP, rcp),
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OPC(4, OPC_RSQ, rsq),
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OPC(4, OPC_LOG2, log2),
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OPC(4, OPC_EXP2, exp2),
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OPC(4, OPC_SIN, sin),
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OPC(4, OPC_COS, cos),
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OPC(4, OPC_SQRT, sqrt),
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OPC(4, OPC_HRSQ, hrsq),
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OPC(4, OPC_HLOG2, hlog2),
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OPC(4, OPC_HEXP2, hexp2),
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/* category 5: */
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OPC(5, OPC_ISAM, isam),
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OPC(5, OPC_ISAML, isaml),
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OPC(5, OPC_ISAMM, isamm),
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OPC(5, OPC_SAM, sam),
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OPC(5, OPC_SAMB, samb),
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OPC(5, OPC_SAML, saml),
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OPC(5, OPC_SAMGQ, samgq),
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OPC(5, OPC_GETLOD, getlod),
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OPC(5, OPC_CONV, conv),
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OPC(5, OPC_CONVM, convm),
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OPC(5, OPC_GETSIZE, getsize),
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OPC(5, OPC_GETBUF, getbuf),
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OPC(5, OPC_GETPOS, getpos),
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OPC(5, OPC_GETINFO, getinfo),
292
OPC(5, OPC_DSX, dsx),
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OPC(5, OPC_DSY, dsy),
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OPC(5, OPC_GATHER4R, gather4r),
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OPC(5, OPC_GATHER4G, gather4g),
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OPC(5, OPC_GATHER4B, gather4b),
297
OPC(5, OPC_GATHER4A, gather4a),
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OPC(5, OPC_SAMGP0, samgp0),
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OPC(5, OPC_SAMGP1, samgp1),
300
OPC(5, OPC_SAMGP2, samgp2),
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OPC(5, OPC_SAMGP3, samgp3),
302
OPC(5, OPC_DSXPP_1, dsxpp.1),
303
OPC(5, OPC_DSYPP_1, dsypp.1),
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OPC(5, OPC_RGETPOS, rgetpos),
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OPC(5, OPC_RGETINFO, rgetinfo),
306
/* macros are needed here for ir3_print */
307
OPC(5, OPC_DSXPP_MACRO, dsxpp.macro),
308
OPC(5, OPC_DSYPP_MACRO, dsypp.macro),
309
310
311
/* category 6: */
312
OPC(6, OPC_LDG, ldg),
313
OPC(6, OPC_LDG_A, ldg.a),
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OPC(6, OPC_LDL, ldl),
315
OPC(6, OPC_LDP, ldp),
316
OPC(6, OPC_STG, stg),
317
OPC(6, OPC_STG_A, stg.a),
318
OPC(6, OPC_STL, stl),
319
OPC(6, OPC_STP, stp),
320
OPC(6, OPC_LDIB, ldib),
321
OPC(6, OPC_G2L, g2l),
322
OPC(6, OPC_L2G, l2g),
323
OPC(6, OPC_PREFETCH, prefetch),
324
OPC(6, OPC_LDLW, ldlw),
325
OPC(6, OPC_STLW, stlw),
326
OPC(6, OPC_RESFMT, resfmt),
327
OPC(6, OPC_RESINFO, resinfo),
328
OPC(6, OPC_ATOMIC_ADD, atomic.add),
329
OPC(6, OPC_ATOMIC_SUB, atomic.sub),
330
OPC(6, OPC_ATOMIC_XCHG, atomic.xchg),
331
OPC(6, OPC_ATOMIC_INC, atomic.inc),
332
OPC(6, OPC_ATOMIC_DEC, atomic.dec),
333
OPC(6, OPC_ATOMIC_CMPXCHG, atomic.cmpxchg),
334
OPC(6, OPC_ATOMIC_MIN, atomic.min),
335
OPC(6, OPC_ATOMIC_MAX, atomic.max),
336
OPC(6, OPC_ATOMIC_AND, atomic.and),
337
OPC(6, OPC_ATOMIC_OR, atomic.or),
338
OPC(6, OPC_ATOMIC_XOR, atomic.xor),
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OPC(6, OPC_LDGB, ldgb),
340
OPC(6, OPC_STGB, stgb),
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OPC(6, OPC_STIB, stib),
342
OPC(6, OPC_LDC, ldc),
343
OPC(6, OPC_LDLV, ldlv),
344
OPC(6, OPC_PIPR, pipr),
345
OPC(6, OPC_PIPC, pipc),
346
OPC(6, OPC_EMIT2, emit),
347
OPC(6, OPC_ENDLS, endls),
348
OPC(6, OPC_GETSPID, getspid),
349
OPC(6, OPC_GETWID, getwid),
350
351
OPC(7, OPC_BAR, bar),
352
OPC(7, OPC_FENCE, fence),
353
/* clang-format on */
354
#undef OPC
355
};
356
357
#define GETINFO(instr) \
358
(&(opcs[((instr)->opc_cat << NOPC_BITS) | instr_opc(instr, ctx->gpu_id)]))
359
360
const char *
361
disasm_a3xx_instr_name(opc_t opc)
362
{
363
if (opc_cat(opc) == -1)
364
return "??meta??";
365
return opcs[opc].name;
366
}
367
368
static void
369
disasm_field_cb(void *d, const char *field_name, struct isa_decode_value *val)
370
{
371
struct disasm_ctx *ctx = d;
372
373
if (!strcmp(field_name, "NAME")) {
374
if (!strcmp("nop", val->str)) {
375
if (ctx->has_end) {
376
ctx->nop_count++;
377
if (ctx->nop_count > 3) {
378
ctx->options->stop = true;
379
}
380
}
381
ctx->stats->nops += 1 + ctx->last.repeat;
382
} else {
383
ctx->nop_count = 0;
384
}
385
386
if (!strcmp("end", val->str)) {
387
ctx->has_end = true;
388
ctx->nop_count = 0;
389
} else if (!strcmp("chsh", val->str)) {
390
ctx->options->stop = true;
391
} else if (!strcmp("bary.f", val->str)) {
392
ctx->stats->last_baryf = ctx->cur_n;
393
}
394
} else if (!strcmp(field_name, "REPEAT")) {
395
ctx->extra_cycles += val->num;
396
ctx->stats->instrs_per_cat[ctx->cur_opc_cat] += val->num;
397
ctx->last.repeat = val->num;
398
} else if (!strcmp(field_name, "NOP")) {
399
ctx->extra_cycles += val->num;
400
ctx->stats->instrs_per_cat[0] += val->num;
401
ctx->stats->nops += val->num;
402
ctx->last.nop = val->num;
403
} else if (!strcmp(field_name, "SY")) {
404
ctx->stats->sy += val->num;
405
} else if (!strcmp(field_name, "SS")) {
406
ctx->stats->ss += val->num;
407
ctx->last.ss = !!val->num;
408
} else if (!strcmp(field_name, "CONST")) {
409
ctx->reg.num = val->num;
410
ctx->reg.file = FILE_CONST;
411
} else if (!strcmp(field_name, "GPR")) {
412
/* don't count GPR regs r48.x (shared) or higher: */
413
if (val->num < 48) {
414
ctx->reg.num = val->num;
415
ctx->reg.file = FILE_GPR;
416
}
417
} else if (!strcmp(field_name, "SRC_R") || !strcmp(field_name, "SRC1_R") ||
418
!strcmp(field_name, "SRC2_R") || !strcmp(field_name, "SRC3_R")) {
419
ctx->reg.r = val->num;
420
} else if (!strcmp(field_name, "DST")) {
421
/* Dest register is always repeated
422
*
423
* Note that this doesn't really properly handle instructions
424
* that write multiple components.. the old disasm didn't handle
425
* that case either.
426
*/
427
ctx->reg.r = true;
428
} else if (strstr(field_name, "HALF")) {
429
ctx->reg.half = val->num;
430
} else if (!strcmp(field_name, "SWIZ")) {
431
unsigned num = (ctx->reg.num << 2) | val->num;
432
if (ctx->reg.r)
433
num += ctx->last.repeat;
434
435
if (ctx->reg.file == FILE_CONST) {
436
ctx->stats->constlen = MAX2(ctx->stats->constlen, num);
437
} else if (ctx->reg.file == FILE_GPR) {
438
if (ctx->reg.half) {
439
ctx->stats->halfreg = MAX2(ctx->stats->halfreg, num);
440
} else {
441
ctx->stats->fullreg = MAX2(ctx->stats->fullreg, num);
442
}
443
}
444
445
memset(&ctx->reg, 0, sizeof(ctx->reg));
446
}
447
}
448
449
/**
450
* Handle stat updates dealt with at the end of instruction decoding,
451
* ie. before beginning of next instruction
452
*/
453
static void
454
disasm_handle_last(struct disasm_ctx *ctx)
455
{
456
if (ctx->last.ss) {
457
ctx->stats->sstall += ctx->sfu_delay;
458
ctx->sfu_delay = 0;
459
}
460
461
if (ctx->cur_opc_cat == 4) {
462
ctx->sfu_delay = 10;
463
} else {
464
int n = MIN2(ctx->sfu_delay, 1 + ctx->last.repeat + ctx->last.nop);
465
ctx->sfu_delay -= n;
466
}
467
468
memset(&ctx->last, 0, sizeof(ctx->last));
469
}
470
471
static void
472
disasm_instr_cb(void *d, unsigned n, uint64_t instr)
473
{
474
struct disasm_ctx *ctx = d;
475
uint32_t *dwords = (uint32_t *)&instr;
476
unsigned opc_cat = instr >> 61;
477
478
/* There are some cases where we can get instr_cb called multiple
479
* times per instruction (like when we need an extra line for branch
480
* target labels), don't update stats in these cases:
481
*/
482
if (n != ctx->cur_n) {
483
if (n > 0) {
484
disasm_handle_last(ctx);
485
}
486
ctx->stats->instrs_per_cat[opc_cat]++;
487
ctx->cur_n = n;
488
489
/* mov vs cov stats are a bit harder to fish out of the field
490
* names, because current ir3-cat1.xml doesn't use {NAME} for
491
* this distinction. So for now just handle this case with
492
* some hand-coded parsing:
493
*/
494
if (opc_cat == 1) {
495
unsigned opc = (instr >> 57) & 0x3;
496
unsigned src_type = (instr >> 50) & 0x7;
497
unsigned dst_type = (instr >> 46) & 0x7;
498
499
if (opc == 0) {
500
if (src_type == dst_type) {
501
ctx->stats->mov_count++;
502
} else {
503
ctx->stats->cov_count++;
504
}
505
}
506
}
507
}
508
509
ctx->cur_opc_cat = opc_cat;
510
511
if (debug & PRINT_RAW) {
512
fprintf(ctx->out, "%s:%d:%04d:%04d[%08xx_%08xx] ", levels[ctx->level],
513
opc_cat, n, ctx->extra_cycles + n, dwords[1], dwords[0]);
514
}
515
}
516
517
int
518
disasm_a3xx_stat(uint32_t *dwords, int sizedwords, int level, FILE *out,
519
unsigned gpu_id, struct shader_stats *stats)
520
{
521
struct isa_decode_options decode_options = {
522
.gpu_id = gpu_id,
523
.show_errors = true,
524
.max_errors = 5,
525
.branch_labels = true,
526
.field_cb = disasm_field_cb,
527
.instr_cb = disasm_instr_cb,
528
};
529
struct disasm_ctx ctx = {
530
.out = out,
531
.level = level,
532
.options = &decode_options,
533
.stats = stats,
534
.cur_n = -1,
535
};
536
537
memset(stats, 0, sizeof(*stats));
538
539
decode_options.cbdata = &ctx;
540
541
isa_decode(dwords, sizedwords * 4, out, &decode_options);
542
543
disasm_handle_last(&ctx);
544
545
if (debug & PRINT_STATS)
546
print_stats(&ctx);
547
548
return 0;
549
}
550
551
void
552
disasm_a3xx_set_debug(enum debug_t d)
553
{
554
debug = d;
555
}
556
557
#include <setjmp.h>
558
559
static bool jmp_env_valid;
560
static jmp_buf jmp_env;
561
562
void
563
ir3_assert_handler(const char *expr, const char *file, int line,
564
const char *func)
565
{
566
mesa_loge("%s:%u: %s: Assertion `%s' failed.", file, line, func, expr);
567
if (jmp_env_valid)
568
longjmp(jmp_env, 1);
569
abort();
570
}
571
572
#define TRY(x) \
573
do { \
574
assert(!jmp_env_valid); \
575
if (setjmp(jmp_env) == 0) { \
576
jmp_env_valid = true; \
577
x; \
578
} \
579
jmp_env_valid = false; \
580
} while (0)
581
582
int
583
disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out,
584
unsigned gpu_id)
585
{
586
struct shader_stats stats;
587
return disasm_a3xx_stat(dwords, sizedwords, level, out, gpu_id, &stats);
588
}
589
590
int
591
try_disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out,
592
unsigned gpu_id)
593
{
594
struct shader_stats stats;
595
int ret = -1;
596
TRY(ret = disasm_a3xx_stat(dwords, sizedwords, level, out, gpu_id, &stats));
597
return ret;
598
}
599
600