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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/freedreno/ir3/ir3_cse.c
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/*
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* Copyright (C) 2014 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "ir3.h"
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#define XXH_INLINE_ALL
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#include "xxhash.h"
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/* This pass handles CSE'ing repeated expressions created in the process of
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* translating from NIR. Currently this is just collect's. Also, currently
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* this is intra-block only, to make it work over multiple block we'd need to
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* bring forward dominance calculation.
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*/
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#define HASH(hash, data) XXH32(&(data), sizeof(data), hash)
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static uint32_t
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hash_instr(const void *data)
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{
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const struct ir3_instruction *instr = data;
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uint32_t hash = 0;
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hash = HASH(hash, instr->opc);
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hash = HASH(hash, instr->dsts[0]->flags);
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foreach_src (src, (struct ir3_instruction *)instr) {
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if (src->flags & IR3_REG_CONST)
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hash = HASH(hash, src->num);
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else if (src->flags & IR3_REG_IMMED)
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hash = HASH(hash, src->uim_val);
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else
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hash = HASH(hash, src->def);
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}
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return hash;
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}
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static bool
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instrs_equal(const struct ir3_instruction *i1, const struct ir3_instruction *i2)
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{
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if (i1->opc != i2->opc)
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return false;
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if (i1->dsts_count != i2->dsts_count)
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return false;
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if (i1->srcs_count != i2->srcs_count)
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return false;
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if (i1->dsts[0]->flags != i2->dsts[0]->flags)
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return false;
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for (unsigned i = 0; i < i1->srcs_count; i++) {
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const struct ir3_register *i1_reg = i1->srcs[i], *i2_reg = i2->srcs[i];
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if (i1_reg->flags != i2_reg->flags)
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return false;
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if (i1_reg->flags & IR3_REG_CONST) {
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if (i1_reg->num != i2_reg->num)
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return false;
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} else if (i1_reg->flags & IR3_REG_IMMED) {
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if (i1_reg->uim_val != i2_reg->uim_val)
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return false;
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} else {
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if (i1_reg->def != i2_reg->def)
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return false;
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}
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}
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return true;
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}
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static bool
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instr_can_cse(const struct ir3_instruction *instr)
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{
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if (instr->opc != OPC_META_COLLECT)
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return false;
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return true;
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}
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static bool
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cmp_func(const void *data1, const void *data2)
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{
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return instrs_equal(data1, data2);
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}
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bool
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ir3_cse(struct ir3 *ir)
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{
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struct set *instr_set = _mesa_set_create(NULL, hash_instr, cmp_func);
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foreach_block (block, &ir->block_list) {
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_mesa_set_clear(instr_set, NULL);
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foreach_instr (instr, &block->instr_list) {
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instr->data = NULL;
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if (!instr_can_cse(instr))
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continue;
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bool found;
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struct set_entry *entry =
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_mesa_set_search_or_add(instr_set, instr, &found);
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if (found)
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instr->data = (void *)entry->key;
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}
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}
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bool progress = false;
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foreach_block (block, &ir->block_list) {
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foreach_instr (instr, &block->instr_list) {
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foreach_src (src, instr) {
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if ((src->flags & IR3_REG_SSA) && src->def &&
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src->def->instr->data) {
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progress = true;
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struct ir3_instruction *instr = src->def->instr->data;
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src->def = instr->dsts[0];
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}
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}
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}
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}
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_mesa_set_destroy(instr_set, NULL);
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return progress;
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}
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