CoCalc -- a2xx.xml

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/freedreno/registers/adreno/a2xx.xml
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<?xml version="1.0" encoding="UTF-8"?>
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<database xmlns="http://nouveau.freedesktop.org/"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
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<import file="freedreno_copyright.xml"/>
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<import file="adreno/adreno_common.xml"/>
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<import file="adreno/adreno_pm4.xml"/>
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<enum name="a2xx_rb_dither_type">
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	<value name="DITHER_PIXEL" value="0"/>
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	<value name="DITHER_SUBPIXEL" value="1"/>
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</enum>
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<enum name="a2xx_colorformatx">
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	<value name="COLORX_4_4_4_4" value="0"/>
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	<value name="COLORX_1_5_5_5" value="1"/>
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	<value name="COLORX_5_6_5" value="2"/>
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	<value name="COLORX_8" value="3"/>
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	<value name="COLORX_8_8" value="4"/>
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	<value name="COLORX_8_8_8_8" value="5"/>
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	<value name="COLORX_S8_8_8_8" value="6"/>
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	<value name="COLORX_16_FLOAT" value="7"/>
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	<value name="COLORX_16_16_FLOAT" value="8"/>
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	<value name="COLORX_16_16_16_16_FLOAT" value="9"/>
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	<value name="COLORX_32_FLOAT" value="10"/>
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	<value name="COLORX_32_32_FLOAT" value="11"/>
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	<value name="COLORX_32_32_32_32_FLOAT" value="12"/>
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	<value name="COLORX_2_3_3" value="13"/>
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	<value name="COLORX_8_8_8" value="14"/>
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</enum>
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<enum name="a2xx_sq_surfaceformat">
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	<value name="FMT_1_REVERSE" value="0"/>
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	<value name="FMT_1" value="1"/>
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	<value name="FMT_8" value="2"/>
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	<value name="FMT_1_5_5_5" value="3"/>
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	<value name="FMT_5_6_5" value="4"/>
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	<value name="FMT_6_5_5" value="5"/>
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	<value name="FMT_8_8_8_8" value="6"/>
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	<value name="FMT_2_10_10_10" value="7"/>
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	<value name="FMT_8_A" value="8"/>
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	<value name="FMT_8_B" value="9"/>
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	<value name="FMT_8_8" value="10"/>
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	<value name="FMT_Cr_Y1_Cb_Y0" value="11"/>
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	<value name="FMT_Y1_Cr_Y0_Cb" value="12"/>
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	<value name="FMT_5_5_5_1" value="13"/>
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	<value name="FMT_8_8_8_8_A" value="14"/>
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	<value name="FMT_4_4_4_4" value="15"/>
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	<value name="FMT_8_8_8" value="16"/>
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	<value name="FMT_DXT1" value="18"/>
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	<value name="FMT_DXT2_3" value="19"/>
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	<value name="FMT_DXT4_5" value="20"/>
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	<value name="FMT_10_10_10_2" value="21"/>
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	<value name="FMT_24_8" value="22"/>
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	<value name="FMT_16" value="24"/>
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	<value name="FMT_16_16" value="25"/>
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	<value name="FMT_16_16_16_16" value="26"/>
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	<value name="FMT_16_EXPAND" value="27"/>
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	<value name="FMT_16_16_EXPAND" value="28"/>
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	<value name="FMT_16_16_16_16_EXPAND" value="29"/>
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	<value name="FMT_16_FLOAT" value="30"/>
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	<value name="FMT_16_16_FLOAT" value="31"/>
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	<value name="FMT_16_16_16_16_FLOAT" value="32"/>
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	<value name="FMT_32" value="33"/>
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	<value name="FMT_32_32" value="34"/>
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	<value name="FMT_32_32_32_32" value="35"/>
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	<value name="FMT_32_FLOAT" value="36"/>
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	<value name="FMT_32_32_FLOAT" value="37"/>
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	<value name="FMT_32_32_32_32_FLOAT" value="38"/>
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	<value name="FMT_ATI_TC_RGB" value="39"/>
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	<value name="FMT_ATI_TC_RGBA" value="40"/>
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	<value name="FMT_ATI_TC_555_565_RGB" value="41"/>
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	<value name="FMT_ATI_TC_555_565_RGBA" value="42"/>
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	<value name="FMT_ATI_TC_RGBA_INTERP" value="43"/>
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	<value name="FMT_ATI_TC_555_565_RGBA_INTERP" value="44"/>
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	<value name="FMT_ETC1_RGBA_INTERP" value="46"/>
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	<value name="FMT_ETC1_RGB" value="47"/>
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	<value name="FMT_ETC1_RGBA" value="48"/>
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	<value name="FMT_DXN" value="49"/>
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	<value name="FMT_2_3_3" value="51"/>
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	<value name="FMT_2_10_10_10_AS_16_16_16_16" value="54"/>
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	<value name="FMT_10_10_10_2_AS_16_16_16_16" value="55"/>
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	<value name="FMT_32_32_32_FLOAT" value="57"/>
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	<value name="FMT_DXT3A" value="58"/>
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	<value name="FMT_DXT5A" value="59"/>
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	<value name="FMT_CTX1" value="60"/>
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</enum>
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<enum name="a2xx_sq_ps_vtx_mode">
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	<value name="POSITION_1_VECTOR" value="0"/>
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	<value name="POSITION_2_VECTORS_UNUSED" value="1"/>
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	<value name="POSITION_2_VECTORS_SPRITE" value="2"/>
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	<value name="POSITION_2_VECTORS_EDGE" value="3"/>
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	<value name="POSITION_2_VECTORS_KILL" value="4"/>
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	<value name="POSITION_2_VECTORS_SPRITE_KILL" value="5"/>
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	<value name="POSITION_2_VECTORS_EDGE_KILL" value="6"/>
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	<value name="MULTIPASS" value="7"/>
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</enum>
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<enum name="a2xx_sq_sample_cntl">
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	<value name="CENTROIDS_ONLY" value="0"/>
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	<value name="CENTERS_ONLY" value="1"/>
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	<value name="CENTROIDS_AND_CENTERS" value="2"/>
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</enum>
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<enum name="a2xx_dx_clip_space">
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	<value name="DXCLIP_OPENGL" value="0"/>
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	<value name="DXCLIP_DIRECTX" value="1"/>
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</enum>
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<enum name="a2xx_pa_su_sc_polymode">
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	<value name="POLY_DISABLED" value="0"/>
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	<value name="POLY_DUALMODE" value="1"/>
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</enum>
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<enum name="a2xx_rb_edram_mode">
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	<value name="EDRAM_NOP" value="0"/>
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	<value name="COLOR_DEPTH" value="4"/>
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	<value name="DEPTH_ONLY" value="5"/>
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	<value name="EDRAM_COPY" value="6"/>
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</enum>
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<enum name="a2xx_pa_sc_pattern_bit_order">
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	<value name="LITTLE" value="0"/>
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	<value name="BIG" value="1"/>
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</enum>
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<enum name="a2xx_pa_sc_auto_reset_cntl">
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	<value name="NEVER" value="0"/>
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	<value name="EACH_PRIMITIVE" value="1"/>
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	<value name="EACH_PACKET" value="2"/>
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</enum>
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<enum name="a2xx_pa_pixcenter">
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	<value name="PIXCENTER_D3D" value="0"/>
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	<value name="PIXCENTER_OGL" value="1"/>
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</enum>
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<enum name="a2xx_pa_roundmode">
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	<value name="TRUNCATE" value="0"/>
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	<value name="ROUND" value="1"/>
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	<value name="ROUNDTOEVEN" value="2"/>
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	<value name="ROUNDTOODD" value="3"/>
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</enum>
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<enum name="a2xx_pa_quantmode">
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	<value name="ONE_SIXTEENTH" value="0"/>
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	<value name="ONE_EIGTH" value="1"/>
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	<value name="ONE_QUARTER" value="2"/>
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	<value name="ONE_HALF" value="3"/>
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	<value name="ONE" value="4"/>
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</enum>
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<enum name="a2xx_rb_copy_sample_select">
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	<value name="SAMPLE_0" value="0"/>
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	<value name="SAMPLE_1" value="1"/>
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	<value name="SAMPLE_2" value="2"/>
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	<value name="SAMPLE_3" value="3"/>
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	<value name="SAMPLE_01" value="4"/>
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	<value name="SAMPLE_23" value="5"/>
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	<value name="SAMPLE_0123" value="6"/>
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</enum>
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<enum name="a2xx_rb_blend_opcode">
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	<value name="BLEND2_DST_PLUS_SRC" value="0"/>
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	<value name="BLEND2_SRC_MINUS_DST" value="1"/>
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	<value name="BLEND2_MIN_DST_SRC" value="2"/>
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	<value name="BLEND2_MAX_DST_SRC" value="3"/>
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	<value name="BLEND2_DST_MINUS_SRC" value="4"/>
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	<value name="BLEND2_DST_PLUS_SRC_BIAS" value="5"/>
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</enum>
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<enum name="a2xx_su_perfcnt_select">
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	<value value="0" name="PERF_PAPC_PASX_REQ"/>
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	<value value="2" name="PERF_PAPC_PASX_FIRST_VECTOR"/>
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	<value value="3" name="PERF_PAPC_PASX_SECOND_VECTOR"/>
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	<value value="4" name="PERF_PAPC_PASX_FIRST_DEAD"/>
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	<value value="5" name="PERF_PAPC_PASX_SECOND_DEAD"/>
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	<value value="6" name="PERF_PAPC_PASX_VTX_KILL_DISCARD"/>
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	<value value="7" name="PERF_PAPC_PASX_VTX_NAN_DISCARD"/>
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	<value value="8" name="PERF_PAPC_PA_INPUT_PRIM"/>
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	<value value="9" name="PERF_PAPC_PA_INPUT_NULL_PRIM"/>
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	<value value="10" name="PERF_PAPC_PA_INPUT_EVENT_FLAG"/>
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	<value value="11" name="PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT"/>
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	<value value="12" name="PERF_PAPC_PA_INPUT_END_OF_PACKET"/>
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	<value value="13" name="PERF_PAPC_CLPR_CULL_PRIM"/>
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	<value value="15" name="PERF_PAPC_CLPR_VV_CULL_PRIM"/>
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	<value value="17" name="PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM"/>
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	<value value="18" name="PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM"/>
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	<value value="19" name="PERF_PAPC_CLPR_CULL_TO_NULL_PRIM"/>
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	<value value="21" name="PERF_PAPC_CLPR_VV_CLIP_PRIM"/>
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	<value value="23" name="PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE"/>
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	<value value="24" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_1"/>
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	<value value="25" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_2"/>
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	<value value="26" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_3"/>
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	<value value="27" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_4"/>
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	<value value="28" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_5"/>
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	<value value="29" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_6"/>
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	<value value="30" name="PERF_PAPC_CLPR_CLIP_PLANE_NEAR"/>
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	<value value="31" name="PERF_PAPC_CLPR_CLIP_PLANE_FAR"/>
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	<value value="32" name="PERF_PAPC_CLPR_CLIP_PLANE_LEFT"/>
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	<value value="33" name="PERF_PAPC_CLPR_CLIP_PLANE_RIGHT"/>
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	<value value="34" name="PERF_PAPC_CLPR_CLIP_PLANE_TOP"/>
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	<value value="35" name="PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM"/>
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	<value value="36" name="PERF_PAPC_CLSM_NULL_PRIM"/>
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	<value value="37" name="PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM"/>
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	<value value="38" name="PERF_PAPC_CLSM_CLIP_PRIM"/>
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	<value value="39" name="PERF_PAPC_CLSM_CULL_TO_NULL_PRIM"/>
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	<value value="40" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_1"/>
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	<value value="41" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_2"/>
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	<value value="42" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_3"/>
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	<value value="43" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_4"/>
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	<value value="44" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_5"/>
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	<value value="45" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7"/>
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	<value value="46" name="PERF_PAPC_CLSM_NON_TRIVIAL_CULL"/>
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	<value value="47" name="PERF_PAPC_SU_INPUT_PRIM"/>
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	<value value="48" name="PERF_PAPC_SU_INPUT_CLIP_PRIM"/>
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	<value value="49" name="PERF_PAPC_SU_INPUT_NULL_PRIM"/>
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	<value value="50" name="PERF_PAPC_SU_ZERO_AREA_CULL_PRIM"/>
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	<value value="51" name="PERF_PAPC_SU_BACK_FACE_CULL_PRIM"/>
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	<value value="52" name="PERF_PAPC_SU_FRONT_FACE_CULL_PRIM"/>
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	<value value="53" name="PERF_PAPC_SU_POLYMODE_FACE_CULL"/>
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	<value value="54" name="PERF_PAPC_SU_POLYMODE_BACK_CULL"/>
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	<value value="55" name="PERF_PAPC_SU_POLYMODE_FRONT_CULL"/>
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	<value value="56" name="PERF_PAPC_SU_POLYMODE_INVALID_FILL"/>
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	<value value="57" name="PERF_PAPC_SU_OUTPUT_PRIM"/>
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	<value value="58" name="PERF_PAPC_SU_OUTPUT_CLIP_PRIM"/>
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	<value value="59" name="PERF_PAPC_SU_OUTPUT_NULL_PRIM"/>
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	<value value="60" name="PERF_PAPC_SU_OUTPUT_EVENT_FLAG"/>
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	<value value="61" name="PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT"/>
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	<value value="62" name="PERF_PAPC_SU_OUTPUT_END_OF_PACKET"/>
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	<value value="63" name="PERF_PAPC_SU_OUTPUT_POLYMODE_FACE"/>
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	<value value="64" name="PERF_PAPC_SU_OUTPUT_POLYMODE_BACK"/>
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	<value value="65" name="PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT"/>
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	<value value="66" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE"/>
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	<value value="67" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK"/>
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	<value value="68" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT"/>
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	<value value="69" name="PERF_PAPC_PASX_REQ_IDLE"/>
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	<value value="70" name="PERF_PAPC_PASX_REQ_BUSY"/>
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	<value value="71" name="PERF_PAPC_PASX_REQ_STALLED"/>
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	<value value="72" name="PERF_PAPC_PASX_REC_IDLE"/>
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	<value value="73" name="PERF_PAPC_PASX_REC_BUSY"/>
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	<value value="74" name="PERF_PAPC_PASX_REC_STARVED_SX"/>
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	<value value="75" name="PERF_PAPC_PASX_REC_STALLED"/>
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	<value value="76" name="PERF_PAPC_PASX_REC_STALLED_POS_MEM"/>
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	<value value="77" name="PERF_PAPC_PASX_REC_STALLED_CCGSM_IN"/>
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	<value value="78" name="PERF_PAPC_CCGSM_IDLE"/>
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	<value value="79" name="PERF_PAPC_CCGSM_BUSY"/>
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	<value value="80" name="PERF_PAPC_CCGSM_STALLED"/>
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	<value value="81" name="PERF_PAPC_CLPRIM_IDLE"/>
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	<value value="82" name="PERF_PAPC_CLPRIM_BUSY"/>
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	<value value="83" name="PERF_PAPC_CLPRIM_STALLED"/>
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	<value value="84" name="PERF_PAPC_CLPRIM_STARVED_CCGSM"/>
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	<value value="85" name="PERF_PAPC_CLIPSM_IDLE"/>
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	<value value="86" name="PERF_PAPC_CLIPSM_BUSY"/>
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	<value value="87" name="PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH"/>
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	<value value="88" name="PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ"/>
259
	<value value="89" name="PERF_PAPC_CLIPSM_WAIT_CLIPGA"/>
260
	<value value="90" name="PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP"/>
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	<value value="91" name="PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM"/>
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	<value value="92" name="PERF_PAPC_CLIPGA_IDLE"/>
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	<value value="93" name="PERF_PAPC_CLIPGA_BUSY"/>
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	<value value="94" name="PERF_PAPC_CLIPGA_STARVED_VTE_CLIP"/>
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	<value value="95" name="PERF_PAPC_CLIPGA_STALLED"/>
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	<value value="96" name="PERF_PAPC_CLIP_IDLE"/>
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	<value value="97" name="PERF_PAPC_CLIP_BUSY"/>
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	<value value="98" name="PERF_PAPC_SU_IDLE"/>
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	<value value="99" name="PERF_PAPC_SU_BUSY"/>
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	<value value="100" name="PERF_PAPC_SU_STARVED_CLIP"/>
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	<value value="101" name="PERF_PAPC_SU_STALLED_SC"/>
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	<value value="102" name="PERF_PAPC_SU_FACENESS_CULL"/>
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</enum>
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<enum name="a2xx_sc_perfcnt_select">
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	<value value="0" name="SC_SR_WINDOW_VALID"/>
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	<value value="1" name="SC_CW_WINDOW_VALID"/>
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	<value value="2" name="SC_QM_WINDOW_VALID"/>
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	<value value="3" name="SC_FW_WINDOW_VALID"/>
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	<value value="4" name="SC_EZ_WINDOW_VALID"/>
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	<value value="5" name="SC_IT_WINDOW_VALID"/>
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	<value value="6" name="SC_STARVED_BY_PA"/>
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	<value value="7" name="SC_STALLED_BY_RB_TILE"/>
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	<value value="8" name="SC_STALLED_BY_RB_SAMP"/>
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	<value value="9" name="SC_STARVED_BY_RB_EZ"/>
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	<value value="10" name="SC_STALLED_BY_SAMPLE_FF"/>
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	<value value="11" name="SC_STALLED_BY_SQ"/>
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	<value value="12" name="SC_STALLED_BY_SP"/>
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	<value value="13" name="SC_TOTAL_NO_PRIMS"/>
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	<value value="14" name="SC_NON_EMPTY_PRIMS"/>
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	<value value="15" name="SC_NO_TILES_PASSING_QM"/>
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	<value value="16" name="SC_NO_PIXELS_PRE_EZ"/>
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	<value value="17" name="SC_NO_PIXELS_POST_EZ"/>
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</enum>
295

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<enum name="a2xx_vgt_perfcount_select">
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	<value value="0" name="VGT_SQ_EVENT_WINDOW_ACTIVE"/>
298
	<value value="1" name="VGT_SQ_SEND"/>
299
	<value value="2" name="VGT_SQ_STALLED"/>
300
	<value value="3" name="VGT_SQ_STARVED_BUSY"/>
301
	<value value="4" name="VGT_SQ_STARVED_IDLE"/>
302
	<value value="5" name="VGT_SQ_STATIC"/>
303
	<value value="6" name="VGT_PA_EVENT_WINDOW_ACTIVE"/>
304
	<value value="7" name="VGT_PA_CLIP_V_SEND"/>
305
	<value value="8" name="VGT_PA_CLIP_V_STALLED"/>
306
	<value value="9" name="VGT_PA_CLIP_V_STARVED_BUSY"/>
307
	<value value="10" name="VGT_PA_CLIP_V_STARVED_IDLE"/>
308
	<value value="11" name="VGT_PA_CLIP_V_STATIC"/>
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	<value value="12" name="VGT_PA_CLIP_P_SEND"/>
310
	<value value="13" name="VGT_PA_CLIP_P_STALLED"/>
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	<value value="14" name="VGT_PA_CLIP_P_STARVED_BUSY"/>
312
	<value value="15" name="VGT_PA_CLIP_P_STARVED_IDLE"/>
313
	<value value="16" name="VGT_PA_CLIP_P_STATIC"/>
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	<value value="17" name="VGT_PA_CLIP_S_SEND"/>
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	<value value="18" name="VGT_PA_CLIP_S_STALLED"/>
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	<value value="19" name="VGT_PA_CLIP_S_STARVED_BUSY"/>
317
	<value value="20" name="VGT_PA_CLIP_S_STARVED_IDLE"/>
318
	<value value="21" name="VGT_PA_CLIP_S_STATIC"/>
319
	<value value="22" name="RBIU_FIFOS_EVENT_WINDOW_ACTIVE"/>
320
	<value value="23" name="RBIU_IMMED_DATA_FIFO_STARVED"/>
321
	<value value="24" name="RBIU_IMMED_DATA_FIFO_STALLED"/>
322
	<value value="25" name="RBIU_DMA_REQUEST_FIFO_STARVED"/>
323
	<value value="26" name="RBIU_DMA_REQUEST_FIFO_STALLED"/>
324
	<value value="27" name="RBIU_DRAW_INITIATOR_FIFO_STARVED"/>
325
	<value value="28" name="RBIU_DRAW_INITIATOR_FIFO_STALLED"/>
326
	<value value="29" name="BIN_PRIM_NEAR_CULL"/>
327
	<value value="30" name="BIN_PRIM_ZERO_CULL"/>
328
	<value value="31" name="BIN_PRIM_FAR_CULL"/>
329
	<value value="32" name="BIN_PRIM_BIN_CULL"/>
330
	<value value="33" name="BIN_PRIM_FACE_CULL"/>
331
	<value value="34" name="SPARE34"/>
332
	<value value="35" name="SPARE35"/>
333
	<value value="36" name="SPARE36"/>
334
	<value value="37" name="SPARE37"/>
335
	<value value="38" name="SPARE38"/>
336
	<value value="39" name="SPARE39"/>
337
	<value value="40" name="TE_SU_IN_VALID"/>
338
	<value value="41" name="TE_SU_IN_READ"/>
339
	<value value="42" name="TE_SU_IN_PRIM"/>
340
	<value value="43" name="TE_SU_IN_EOP"/>
341
	<value value="44" name="TE_SU_IN_NULL_PRIM"/>
342
	<value value="45" name="TE_WK_IN_VALID"/>
343
	<value value="46" name="TE_WK_IN_READ"/>
344
	<value value="47" name="TE_OUT_PRIM_VALID"/>
345
	<value value="48" name="TE_OUT_PRIM_READ"/>
346
</enum>
347

348
<enum name="a2xx_tcr_perfcount_select">
349
	<value value="0" name="DGMMPD_IPMUX0_STALL"/>
350
	<value value="4" name="DGMMPD_IPMUX_ALL_STALL"/>
351
	<value value="5" name="OPMUX0_L2_WRITES"/>
352
</enum>
353

354
<enum name="a2xx_tp_perfcount_select">
355
	<value value="0" name="POINT_QUADS"/>
356
	<value value="1" name="BILIN_QUADS"/>
357
	<value value="2" name="ANISO_QUADS"/>
358
	<value value="3" name="MIP_QUADS"/>
359
	<value value="4" name="VOL_QUADS"/>
360
	<value value="5" name="MIP_VOL_QUADS"/>
361
	<value value="6" name="MIP_ANISO_QUADS"/>
362
	<value value="7" name="VOL_ANISO_QUADS"/>
363
	<value value="8" name="ANISO_2_1_QUADS"/>
364
	<value value="9" name="ANISO_4_1_QUADS"/>
365
	<value value="10" name="ANISO_6_1_QUADS"/>
366
	<value value="11" name="ANISO_8_1_QUADS"/>
367
	<value value="12" name="ANISO_10_1_QUADS"/>
368
	<value value="13" name="ANISO_12_1_QUADS"/>
369
	<value value="14" name="ANISO_14_1_QUADS"/>
370
	<value value="15" name="ANISO_16_1_QUADS"/>
371
	<value value="16" name="MIP_VOL_ANISO_QUADS"/>
372
	<value value="17" name="ALIGN_2_QUADS"/>
373
	<value value="18" name="ALIGN_4_QUADS"/>
374
	<value value="19" name="PIX_0_QUAD"/>
375
	<value value="20" name="PIX_1_QUAD"/>
376
	<value value="21" name="PIX_2_QUAD"/>
377
	<value value="22" name="PIX_3_QUAD"/>
378
	<value value="23" name="PIX_4_QUAD"/>
379
	<value value="24" name="TP_MIPMAP_LOD0"/>
380
	<value value="25" name="TP_MIPMAP_LOD1"/>
381
	<value value="26" name="TP_MIPMAP_LOD2"/>
382
	<value value="27" name="TP_MIPMAP_LOD3"/>
383
	<value value="28" name="TP_MIPMAP_LOD4"/>
384
	<value value="29" name="TP_MIPMAP_LOD5"/>
385
	<value value="30" name="TP_MIPMAP_LOD6"/>
386
	<value value="31" name="TP_MIPMAP_LOD7"/>
387
	<value value="32" name="TP_MIPMAP_LOD8"/>
388
	<value value="33" name="TP_MIPMAP_LOD9"/>
389
	<value value="34" name="TP_MIPMAP_LOD10"/>
390
	<value value="35" name="TP_MIPMAP_LOD11"/>
391
	<value value="36" name="TP_MIPMAP_LOD12"/>
392
	<value value="37" name="TP_MIPMAP_LOD13"/>
393
	<value value="38" name="TP_MIPMAP_LOD14"/>
394
</enum>
395

396
<enum name="a2xx_tcm_perfcount_select">
397
	<value value="0" name="QUAD0_RD_LAT_FIFO_EMPTY"/>
398
	<value value="3" name="QUAD0_RD_LAT_FIFO_4TH_FULL"/>
399
	<value value="4" name="QUAD0_RD_LAT_FIFO_HALF_FULL"/>
400
	<value value="5" name="QUAD0_RD_LAT_FIFO_FULL"/>
401
	<value value="6" name="QUAD0_RD_LAT_FIFO_LT_4TH_FULL"/>
402
	<value value="28" name="READ_STARVED_QUAD0"/>
403
	<value value="32" name="READ_STARVED"/>
404
	<value value="33" name="READ_STALLED_QUAD0"/>
405
	<value value="37" name="READ_STALLED"/>
406
	<value value="38" name="VALID_READ_QUAD0"/>
407
	<value value="42" name="TC_TP_STARVED_QUAD0"/>
408
	<value value="46" name="TC_TP_STARVED"/>
409
</enum>
410

411
<enum name="a2xx_tcf_perfcount_select">
412
	<value value="0" name="VALID_CYCLES"/>
413
	<value value="1" name="SINGLE_PHASES"/>
414
	<value value="2" name="ANISO_PHASES"/>
415
	<value value="3" name="MIP_PHASES"/>
416
	<value value="4" name="VOL_PHASES"/>
417
	<value value="5" name="MIP_VOL_PHASES"/>
418
	<value value="6" name="MIP_ANISO_PHASES"/>
419
	<value value="7" name="VOL_ANISO_PHASES"/>
420
	<value value="8" name="ANISO_2_1_PHASES"/>
421
	<value value="9" name="ANISO_4_1_PHASES"/>
422
	<value value="10" name="ANISO_6_1_PHASES"/>
423
	<value value="11" name="ANISO_8_1_PHASES"/>
424
	<value value="12" name="ANISO_10_1_PHASES"/>
425
	<value value="13" name="ANISO_12_1_PHASES"/>
426
	<value value="14" name="ANISO_14_1_PHASES"/>
427
	<value value="15" name="ANISO_16_1_PHASES"/>
428
	<value value="16" name="MIP_VOL_ANISO_PHASES"/>
429
	<value value="17" name="ALIGN_2_PHASES"/>
430
	<value value="18" name="ALIGN_4_PHASES"/>
431
	<value value="19" name="TPC_BUSY"/>
432
	<value value="20" name="TPC_STALLED"/>
433
	<value value="21" name="TPC_STARVED"/>
434
	<value value="22" name="TPC_WORKING"/>
435
	<value value="23" name="TPC_WALKER_BUSY"/>
436
	<value value="24" name="TPC_WALKER_STALLED"/>
437
	<value value="25" name="TPC_WALKER_WORKING"/>
438
	<value value="26" name="TPC_ALIGNER_BUSY"/>
439
	<value value="27" name="TPC_ALIGNER_STALLED"/>
440
	<value value="28" name="TPC_ALIGNER_STALLED_BY_BLEND"/>
441
	<value value="29" name="TPC_ALIGNER_STALLED_BY_CACHE"/>
442
	<value value="30" name="TPC_ALIGNER_WORKING"/>
443
	<value value="31" name="TPC_BLEND_BUSY"/>
444
	<value value="32" name="TPC_BLEND_SYNC"/>
445
	<value value="33" name="TPC_BLEND_STARVED"/>
446
	<value value="34" name="TPC_BLEND_WORKING"/>
447
	<value value="35" name="OPCODE_0x00"/>
448
	<value value="36" name="OPCODE_0x01"/>
449
	<value value="37" name="OPCODE_0x04"/>
450
	<value value="38" name="OPCODE_0x10"/>
451
	<value value="39" name="OPCODE_0x11"/>
452
	<value value="40" name="OPCODE_0x12"/>
453
	<value value="41" name="OPCODE_0x13"/>
454
	<value value="42" name="OPCODE_0x18"/>
455
	<value value="43" name="OPCODE_0x19"/>
456
	<value value="44" name="OPCODE_0x1A"/>
457
	<value value="45" name="OPCODE_OTHER"/>
458
	<value value="56" name="IN_FIFO_0_EMPTY"/>
459
	<value value="57" name="IN_FIFO_0_LT_HALF_FULL"/>
460
	<value value="58" name="IN_FIFO_0_HALF_FULL"/>
461
	<value value="59" name="IN_FIFO_0_FULL"/>
462
	<value value="72" name="IN_FIFO_TPC_EMPTY"/>
463
	<value value="73" name="IN_FIFO_TPC_LT_HALF_FULL"/>
464
	<value value="74" name="IN_FIFO_TPC_HALF_FULL"/>
465
	<value value="75" name="IN_FIFO_TPC_FULL"/>
466
	<value value="76" name="TPC_TC_XFC"/>
467
	<value value="77" name="TPC_TC_STATE"/>
468
	<value value="78" name="TC_STALL"/>
469
	<value value="79" name="QUAD0_TAPS"/>
470
	<value value="83" name="QUADS"/>
471
	<value value="84" name="TCA_SYNC_STALL"/>
472
	<value value="85" name="TAG_STALL"/>
473
	<value value="88" name="TCB_SYNC_STALL"/>
474
	<value value="89" name="TCA_VALID"/>
475
	<value value="90" name="PROBES_VALID"/>
476
	<value value="91" name="MISS_STALL"/>
477
	<value value="92" name="FETCH_FIFO_STALL"/>
478
	<value value="93" name="TCO_STALL"/>
479
	<value value="94" name="ANY_STALL"/>
480
	<value value="95" name="TAG_MISSES"/>
481
	<value value="96" name="TAG_HITS"/>
482
	<value value="97" name="SUB_TAG_MISSES"/>
483
	<value value="98" name="SET0_INVALIDATES"/>
484
	<value value="99" name="SET1_INVALIDATES"/>
485
	<value value="100" name="SET2_INVALIDATES"/>
486
	<value value="101" name="SET3_INVALIDATES"/>
487
	<value value="102" name="SET0_TAG_MISSES"/>
488
	<value value="103" name="SET1_TAG_MISSES"/>
489
	<value value="104" name="SET2_TAG_MISSES"/>
490
	<value value="105" name="SET3_TAG_MISSES"/>
491
	<value value="106" name="SET0_TAG_HITS"/>
492
	<value value="107" name="SET1_TAG_HITS"/>
493
	<value value="108" name="SET2_TAG_HITS"/>
494
	<value value="109" name="SET3_TAG_HITS"/>
495
	<value value="110" name="SET0_SUB_TAG_MISSES"/>
496
	<value value="111" name="SET1_SUB_TAG_MISSES"/>
497
	<value value="112" name="SET2_SUB_TAG_MISSES"/>
498
	<value value="113" name="SET3_SUB_TAG_MISSES"/>
499
	<value value="114" name="SET0_EVICT1"/>
500
	<value value="115" name="SET0_EVICT2"/>
501
	<value value="116" name="SET0_EVICT3"/>
502
	<value value="117" name="SET0_EVICT4"/>
503
	<value value="118" name="SET0_EVICT5"/>
504
	<value value="119" name="SET0_EVICT6"/>
505
	<value value="120" name="SET0_EVICT7"/>
506
	<value value="121" name="SET0_EVICT8"/>
507
	<value value="130" name="SET1_EVICT1"/>
508
	<value value="131" name="SET1_EVICT2"/>
509
	<value value="132" name="SET1_EVICT3"/>
510
	<value value="133" name="SET1_EVICT4"/>
511
	<value value="134" name="SET1_EVICT5"/>
512
	<value value="135" name="SET1_EVICT6"/>
513
	<value value="136" name="SET1_EVICT7"/>
514
	<value value="137" name="SET1_EVICT8"/>
515
	<value value="146" name="SET2_EVICT1"/>
516
	<value value="147" name="SET2_EVICT2"/>
517
	<value value="148" name="SET2_EVICT3"/>
518
	<value value="149" name="SET2_EVICT4"/>
519
	<value value="150" name="SET2_EVICT5"/>
520
	<value value="151" name="SET2_EVICT6"/>
521
	<value value="152" name="SET2_EVICT7"/>
522
	<value value="153" name="SET2_EVICT8"/>
523
	<value value="162" name="SET3_EVICT1"/>
524
	<value value="163" name="SET3_EVICT2"/>
525
	<value value="164" name="SET3_EVICT3"/>
526
	<value value="165" name="SET3_EVICT4"/>
527
	<value value="166" name="SET3_EVICT5"/>
528
	<value value="167" name="SET3_EVICT6"/>
529
	<value value="168" name="SET3_EVICT7"/>
530
	<value value="169" name="SET3_EVICT8"/>
531
	<value value="178" name="FF_EMPTY"/>
532
	<value value="179" name="FF_LT_HALF_FULL"/>
533
	<value value="180" name="FF_HALF_FULL"/>
534
	<value value="181" name="FF_FULL"/>
535
	<value value="182" name="FF_XFC"/>
536
	<value value="183" name="FF_STALLED"/>
537
	<value value="184" name="FG_MASKS"/>
538
	<value value="185" name="FG_LEFT_MASKS"/>
539
	<value value="186" name="FG_LEFT_MASK_STALLED"/>
540
	<value value="187" name="FG_LEFT_NOT_DONE_STALL"/>
541
	<value value="188" name="FG_LEFT_FG_STALL"/>
542
	<value value="189" name="FG_LEFT_SECTORS"/>
543
	<value value="195" name="FG0_REQUESTS"/>
544
	<value value="196" name="FG0_STALLED"/>
545
	<value value="199" name="MEM_REQ512"/>
546
	<value value="200" name="MEM_REQ_SENT"/>
547
	<value value="202" name="MEM_LOCAL_READ_REQ"/>
548
	<value value="203" name="TC0_MH_STALLED"/>
549
</enum>
550

551
<enum name="a2xx_sq_perfcnt_select">
552
	<value value="0" name="SQ_PIXEL_VECTORS_SUB"/>
553
	<value value="1" name="SQ_VERTEX_VECTORS_SUB"/>
554
	<value value="2" name="SQ_ALU0_ACTIVE_VTX_SIMD0"/>
555
	<value value="3" name="SQ_ALU1_ACTIVE_VTX_SIMD0"/>
556
	<value value="4" name="SQ_ALU0_ACTIVE_PIX_SIMD0"/>
557
	<value value="5" name="SQ_ALU1_ACTIVE_PIX_SIMD0"/>
558
	<value value="6" name="SQ_ALU0_ACTIVE_VTX_SIMD1"/>
559
	<value value="7" name="SQ_ALU1_ACTIVE_VTX_SIMD1"/>
560
	<value value="8" name="SQ_ALU0_ACTIVE_PIX_SIMD1"/>
561
	<value value="9" name="SQ_ALU1_ACTIVE_PIX_SIMD1"/>
562
	<value value="10" name="SQ_EXPORT_CYCLES"/>
563
	<value value="11" name="SQ_ALU_CST_WRITTEN"/>
564
	<value value="12" name="SQ_TEX_CST_WRITTEN"/>
565
	<value value="13" name="SQ_ALU_CST_STALL"/>
566
	<value value="14" name="SQ_ALU_TEX_STALL"/>
567
	<value value="15" name="SQ_INST_WRITTEN"/>
568
	<value value="16" name="SQ_BOOLEAN_WRITTEN"/>
569
	<value value="17" name="SQ_LOOPS_WRITTEN"/>
570
	<value value="18" name="SQ_PIXEL_SWAP_IN"/>
571
	<value value="19" name="SQ_PIXEL_SWAP_OUT"/>
572
	<value value="20" name="SQ_VERTEX_SWAP_IN"/>
573
	<value value="21" name="SQ_VERTEX_SWAP_OUT"/>
574
	<value value="22" name="SQ_ALU_VTX_INST_ISSUED"/>
575
	<value value="23" name="SQ_TEX_VTX_INST_ISSUED"/>
576
	<value value="24" name="SQ_VC_VTX_INST_ISSUED"/>
577
	<value value="25" name="SQ_CF_VTX_INST_ISSUED"/>
578
	<value value="26" name="SQ_ALU_PIX_INST_ISSUED"/>
579
	<value value="27" name="SQ_TEX_PIX_INST_ISSUED"/>
580
	<value value="28" name="SQ_VC_PIX_INST_ISSUED"/>
581
	<value value="29" name="SQ_CF_PIX_INST_ISSUED"/>
582
	<value value="30" name="SQ_ALU0_FIFO_EMPTY_SIMD0"/>
583
	<value value="31" name="SQ_ALU1_FIFO_EMPTY_SIMD0"/>
584
	<value value="32" name="SQ_ALU0_FIFO_EMPTY_SIMD1"/>
585
	<value value="33" name="SQ_ALU1_FIFO_EMPTY_SIMD1"/>
586
	<value value="34" name="SQ_ALU_NOPS"/>
587
	<value value="35" name="SQ_PRED_SKIP"/>
588
	<value value="36" name="SQ_SYNC_ALU_STALL_SIMD0_VTX"/>
589
	<value value="37" name="SQ_SYNC_ALU_STALL_SIMD1_VTX"/>
590
	<value value="38" name="SQ_SYNC_TEX_STALL_VTX"/>
591
	<value value="39" name="SQ_SYNC_VC_STALL_VTX"/>
592
	<value value="40" name="SQ_CONSTANTS_USED_SIMD0"/>
593
	<value value="41" name="SQ_CONSTANTS_SENT_SP_SIMD0"/>
594
	<value value="42" name="SQ_GPR_STALL_VTX"/>
595
	<value value="43" name="SQ_GPR_STALL_PIX"/>
596
	<value value="44" name="SQ_VTX_RS_STALL"/>
597
	<value value="45" name="SQ_PIX_RS_STALL"/>
598
	<value value="46" name="SQ_SX_PC_FULL"/>
599
	<value value="47" name="SQ_SX_EXP_BUFF_FULL"/>
600
	<value value="48" name="SQ_SX_POS_BUFF_FULL"/>
601
	<value value="49" name="SQ_INTERP_QUADS"/>
602
	<value value="50" name="SQ_INTERP_ACTIVE"/>
603
	<value value="51" name="SQ_IN_PIXEL_STALL"/>
604
	<value value="52" name="SQ_IN_VTX_STALL"/>
605
	<value value="53" name="SQ_VTX_CNT"/>
606
	<value value="54" name="SQ_VTX_VECTOR2"/>
607
	<value value="55" name="SQ_VTX_VECTOR3"/>
608
	<value value="56" name="SQ_VTX_VECTOR4"/>
609
	<value value="57" name="SQ_PIXEL_VECTOR1"/>
610
	<value value="58" name="SQ_PIXEL_VECTOR23"/>
611
	<value value="59" name="SQ_PIXEL_VECTOR4"/>
612
	<value value="60" name="SQ_CONSTANTS_USED_SIMD1"/>
613
	<value value="61" name="SQ_CONSTANTS_SENT_SP_SIMD1"/>
614
	<value value="62" name="SQ_SX_MEM_EXP_FULL"/>
615
	<value value="63" name="SQ_ALU0_ACTIVE_VTX_SIMD2"/>
616
	<value value="64" name="SQ_ALU1_ACTIVE_VTX_SIMD2"/>
617
	<value value="65" name="SQ_ALU0_ACTIVE_PIX_SIMD2"/>
618
	<value value="66" name="SQ_ALU1_ACTIVE_PIX_SIMD2"/>
619
	<value value="67" name="SQ_ALU0_ACTIVE_VTX_SIMD3"/>
620
	<value value="68" name="SQ_PERFCOUNT_VTX_QUAL_TP_DONE"/>
621
	<value value="69" name="SQ_ALU0_ACTIVE_PIX_SIMD3"/>
622
	<value value="70" name="SQ_PERFCOUNT_PIX_QUAL_TP_DONE"/>
623
	<value value="71" name="SQ_ALU0_FIFO_EMPTY_SIMD2"/>
624
	<value value="72" name="SQ_ALU1_FIFO_EMPTY_SIMD2"/>
625
	<value value="73" name="SQ_ALU0_FIFO_EMPTY_SIMD3"/>
626
	<value value="74" name="SQ_ALU1_FIFO_EMPTY_SIMD3"/>
627
	<value value="75" name="SQ_SYNC_ALU_STALL_SIMD2_VTX"/>
628
	<value value="76" name="SQ_PERFCOUNT_VTX_POP_THREAD"/>
629
	<value value="77" name="SQ_SYNC_ALU_STALL_SIMD0_PIX"/>
630
	<value value="78" name="SQ_SYNC_ALU_STALL_SIMD1_PIX"/>
631
	<value value="79" name="SQ_SYNC_ALU_STALL_SIMD2_PIX"/>
632
	<value value="80" name="SQ_PERFCOUNT_PIX_POP_THREAD"/>
633
	<value value="81" name="SQ_SYNC_TEX_STALL_PIX"/>
634
	<value value="82" name="SQ_SYNC_VC_STALL_PIX"/>
635
	<value value="83" name="SQ_CONSTANTS_USED_SIMD2"/>
636
	<value value="84" name="SQ_CONSTANTS_SENT_SP_SIMD2"/>
637
	<value value="85" name="SQ_PERFCOUNT_VTX_DEALLOC_ACK"/>
638
	<value value="86" name="SQ_PERFCOUNT_PIX_DEALLOC_ACK"/>
639
	<value value="87" name="SQ_ALU0_FIFO_FULL_SIMD0"/>
640
	<value value="88" name="SQ_ALU1_FIFO_FULL_SIMD0"/>
641
	<value value="89" name="SQ_ALU0_FIFO_FULL_SIMD1"/>
642
	<value value="90" name="SQ_ALU1_FIFO_FULL_SIMD1"/>
643
	<value value="91" name="SQ_ALU0_FIFO_FULL_SIMD2"/>
644
	<value value="92" name="SQ_ALU1_FIFO_FULL_SIMD2"/>
645
	<value value="93" name="SQ_ALU0_FIFO_FULL_SIMD3"/>
646
	<value value="94" name="SQ_ALU1_FIFO_FULL_SIMD3"/>
647
	<value value="95" name="VC_PERF_STATIC"/>
648
	<value value="96" name="VC_PERF_STALLED"/>
649
	<value value="97" name="VC_PERF_STARVED"/>
650
	<value value="98" name="VC_PERF_SEND"/>
651
	<value value="99" name="VC_PERF_ACTUAL_STARVED"/>
652
	<value value="100" name="PIXEL_THREAD_0_ACTIVE"/>
653
	<value value="101" name="VERTEX_THREAD_0_ACTIVE"/>
654
	<value value="102" name="PIXEL_THREAD_0_NUMBER"/>
655
	<value value="103" name="VERTEX_THREAD_0_NUMBER"/>
656
	<value value="104" name="VERTEX_EVENT_NUMBER"/>
657
	<value value="105" name="PIXEL_EVENT_NUMBER"/>
658
	<value value="106" name="PTRBUFF_EF_PUSH"/>
659
	<value value="107" name="PTRBUFF_EF_POP_EVENT"/>
660
	<value value="108" name="PTRBUFF_EF_POP_NEW_VTX"/>
661
	<value value="109" name="PTRBUFF_EF_POP_DEALLOC"/>
662
	<value value="110" name="PTRBUFF_EF_POP_PVECTOR"/>
663
	<value value="111" name="PTRBUFF_EF_POP_PVECTOR_X"/>
664
	<value value="112" name="PTRBUFF_EF_POP_PVECTOR_VNZ"/>
665
	<value value="113" name="PTRBUFF_PB_DEALLOC"/>
666
	<value value="114" name="PTRBUFF_PI_STATE_PPB_POP"/>
667
	<value value="115" name="PTRBUFF_PI_RTR"/>
668
	<value value="116" name="PTRBUFF_PI_READ_EN"/>
669
	<value value="117" name="PTRBUFF_PI_BUFF_SWAP"/>
670
	<value value="118" name="PTRBUFF_SQ_FREE_BUFF"/>
671
	<value value="119" name="PTRBUFF_SQ_DEC"/>
672
	<value value="120" name="PTRBUFF_SC_VALID_CNTL_EVENT"/>
673
	<value value="121" name="PTRBUFF_SC_VALID_IJ_XFER"/>
674
	<value value="122" name="PTRBUFF_SC_NEW_VECTOR_1_Q"/>
675
	<value value="123" name="PTRBUFF_QUAL_NEW_VECTOR"/>
676
	<value value="124" name="PTRBUFF_QUAL_EVENT"/>
677
	<value value="125" name="PTRBUFF_END_BUFFER"/>
678
	<value value="126" name="PTRBUFF_FILL_QUAD"/>
679
	<value value="127" name="VERTS_WRITTEN_SPI"/>
680
	<value value="128" name="TP_FETCH_INSTR_EXEC"/>
681
	<value value="129" name="TP_FETCH_INSTR_REQ"/>
682
	<value value="130" name="TP_DATA_RETURN"/>
683
	<value value="131" name="SPI_WRITE_CYCLES_SP"/>
684
	<value value="132" name="SPI_WRITES_SP"/>
685
	<value value="133" name="SP_ALU_INSTR_EXEC"/>
686
	<value value="134" name="SP_CONST_ADDR_TO_SQ"/>
687
	<value value="135" name="SP_PRED_KILLS_TO_SQ"/>
688
	<value value="136" name="SP_EXPORT_CYCLES_TO_SX"/>
689
	<value value="137" name="SP_EXPORTS_TO_SX"/>
690
	<value value="138" name="SQ_CYCLES_ELAPSED"/>
691
	<value value="139" name="SQ_TCFS_OPT_ALLOC_EXEC"/>
692
	<value value="140" name="SQ_TCFS_NO_OPT_ALLOC"/>
693
	<value value="141" name="SQ_ALU0_NO_OPT_ALLOC"/>
694
	<value value="142" name="SQ_ALU1_NO_OPT_ALLOC"/>
695
	<value value="143" name="SQ_TCFS_ARB_XFC_CNT"/>
696
	<value value="144" name="SQ_ALU0_ARB_XFC_CNT"/>
697
	<value value="145" name="SQ_ALU1_ARB_XFC_CNT"/>
698
	<value value="146" name="SQ_TCFS_CFS_UPDATE_CNT"/>
699
	<value value="147" name="SQ_ALU0_CFS_UPDATE_CNT"/>
700
	<value value="148" name="SQ_ALU1_CFS_UPDATE_CNT"/>
701
	<value value="149" name="SQ_VTX_PUSH_THREAD_CNT"/>
702
	<value value="150" name="SQ_VTX_POP_THREAD_CNT"/>
703
	<value value="151" name="SQ_PIX_PUSH_THREAD_CNT"/>
704
	<value value="152" name="SQ_PIX_POP_THREAD_CNT"/>
705
	<value value="153" name="SQ_PIX_TOTAL"/>
706
	<value value="154" name="SQ_PIX_KILLED"/>
707
</enum>
708

709
<enum name="a2xx_sx_perfcnt_select">
710
	<value value="0" name="SX_EXPORT_VECTORS"/>
711
	<value value="1" name="SX_DUMMY_QUADS"/>
712
	<value value="2" name="SX_ALPHA_FAIL"/>
713
	<value value="3" name="SX_RB_QUAD_BUSY"/>
714
	<value value="4" name="SX_RB_COLOR_BUSY"/>
715
	<value value="5" name="SX_RB_QUAD_STALL"/>
716
	<value value="6" name="SX_RB_COLOR_STALL"/>
717
</enum>
718

719
<enum name="a2xx_rbbm_perfcount1_sel">
720
	<value value="0" name="RBBM1_COUNT"/>
721
	<value value="1" name="RBBM1_NRT_BUSY"/>
722
	<value value="2" name="RBBM1_RB_BUSY"/>
723
	<value value="3" name="RBBM1_SQ_CNTX0_BUSY"/>
724
	<value value="4" name="RBBM1_SQ_CNTX17_BUSY"/>
725
	<value value="5" name="RBBM1_VGT_BUSY"/>
726
	<value value="6" name="RBBM1_VGT_NODMA_BUSY"/>
727
	<value value="7" name="RBBM1_PA_BUSY"/>
728
	<value value="8" name="RBBM1_SC_CNTX_BUSY"/>
729
	<value value="9" name="RBBM1_TPC_BUSY"/>
730
	<value value="10" name="RBBM1_TC_BUSY"/>
731
	<value value="11" name="RBBM1_SX_BUSY"/>
732
	<value value="12" name="RBBM1_CP_COHER_BUSY"/>
733
	<value value="13" name="RBBM1_CP_NRT_BUSY"/>
734
	<value value="14" name="RBBM1_GFX_IDLE_STALL"/>
735
	<value value="15" name="RBBM1_INTERRUPT"/>
736
</enum>
737

738
<enum name="a2xx_cp_perfcount_sel">
739
	<value value="0" name="ALWAYS_COUNT"/>
740
	<value value="1" name="TRANS_FIFO_FULL"/>
741
	<value value="2" name="TRANS_FIFO_AF"/>
742
	<value value="3" name="RCIU_PFPTRANS_WAIT"/>
743
	<value value="6" name="RCIU_NRTTRANS_WAIT"/>
744
	<value value="8" name="CSF_NRT_READ_WAIT"/>
745
	<value value="9" name="CSF_I1_FIFO_FULL"/>
746
	<value value="10" name="CSF_I2_FIFO_FULL"/>
747
	<value value="11" name="CSF_ST_FIFO_FULL"/>
748
	<value value="13" name="CSF_RING_ROQ_FULL"/>
749
	<value value="14" name="CSF_I1_ROQ_FULL"/>
750
	<value value="15" name="CSF_I2_ROQ_FULL"/>
751
	<value value="16" name="CSF_ST_ROQ_FULL"/>
752
	<value value="18" name="MIU_TAG_MEM_FULL"/>
753
	<value value="19" name="MIU_WRITECLEAN"/>
754
	<value value="22" name="MIU_NRT_WRITE_STALLED"/>
755
	<value value="23" name="MIU_NRT_READ_STALLED"/>
756
	<value value="24" name="ME_WRITE_CONFIRM_FIFO_FULL"/>
757
	<value value="25" name="ME_VS_DEALLOC_FIFO_FULL"/>
758
	<value value="26" name="ME_PS_DEALLOC_FIFO_FULL"/>
759
	<value value="27" name="ME_REGS_VS_EVENT_FIFO_FULL"/>
760
	<value value="28" name="ME_REGS_PS_EVENT_FIFO_FULL"/>
761
	<value value="29" name="ME_REGS_CF_EVENT_FIFO_FULL"/>
762
	<value value="30" name="ME_MICRO_RB_STARVED"/>
763
	<value value="31" name="ME_MICRO_I1_STARVED"/>
764
	<value value="32" name="ME_MICRO_I2_STARVED"/>
765
	<value value="33" name="ME_MICRO_ST_STARVED"/>
766
	<value value="40" name="RCIU_RBBM_DWORD_SENT"/>
767
	<value value="41" name="ME_BUSY_CLOCKS"/>
768
	<value value="42" name="ME_WAIT_CONTEXT_AVAIL"/>
769
	<value value="43" name="PFP_TYPE0_PACKET"/>
770
	<value value="44" name="PFP_TYPE3_PACKET"/>
771
	<value value="45" name="CSF_RB_WPTR_NEQ_RPTR"/>
772
	<value value="46" name="CSF_I1_SIZE_NEQ_ZERO"/>
773
	<value value="47" name="CSF_I2_SIZE_NEQ_ZERO"/>
774
	<value value="48" name="CSF_RBI1I2_FETCHING"/>
775
</enum>
776

777
<enum name="a2xx_rb_perfcnt_select">
778
	<value value="0" name="RBPERF_CNTX_BUSY"/>
779
	<value value="1" name="RBPERF_CNTX_BUSY_MAX"/>
780
	<value value="2" name="RBPERF_SX_QUAD_STARVED"/>
781
	<value value="3" name="RBPERF_SX_QUAD_STARVED_MAX"/>
782
	<value value="4" name="RBPERF_GA_GC_CH0_SYS_REQ"/>
783
	<value value="5" name="RBPERF_GA_GC_CH0_SYS_REQ_MAX"/>
784
	<value value="6" name="RBPERF_GA_GC_CH1_SYS_REQ"/>
785
	<value value="7" name="RBPERF_GA_GC_CH1_SYS_REQ_MAX"/>
786
	<value value="8" name="RBPERF_MH_STARVED"/>
787
	<value value="9" name="RBPERF_MH_STARVED_MAX"/>
788
	<value value="10" name="RBPERF_AZ_BC_COLOR_BUSY"/>
789
	<value value="11" name="RBPERF_AZ_BC_COLOR_BUSY_MAX"/>
790
	<value value="12" name="RBPERF_AZ_BC_Z_BUSY"/>
791
	<value value="13" name="RBPERF_AZ_BC_Z_BUSY_MAX"/>
792
	<value value="14" name="RBPERF_RB_SC_TILE_RTR_N"/>
793
	<value value="15" name="RBPERF_RB_SC_TILE_RTR_N_MAX"/>
794
	<value value="16" name="RBPERF_RB_SC_SAMP_RTR_N"/>
795
	<value value="17" name="RBPERF_RB_SC_SAMP_RTR_N_MAX"/>
796
	<value value="18" name="RBPERF_RB_SX_QUAD_RTR_N"/>
797
	<value value="19" name="RBPERF_RB_SX_QUAD_RTR_N_MAX"/>
798
	<value value="20" name="RBPERF_RB_SX_COLOR_RTR_N"/>
799
	<value value="21" name="RBPERF_RB_SX_COLOR_RTR_N_MAX"/>
800
	<value value="22" name="RBPERF_RB_SC_SAMP_LZ_BUSY"/>
801
	<value value="23" name="RBPERF_RB_SC_SAMP_LZ_BUSY_MAX"/>
802
	<value value="24" name="RBPERF_ZXP_STALL"/>
803
	<value value="25" name="RBPERF_ZXP_STALL_MAX"/>
804
	<value value="26" name="RBPERF_EVENT_PENDING"/>
805
	<value value="27" name="RBPERF_EVENT_PENDING_MAX"/>
806
	<value value="28" name="RBPERF_RB_MH_VALID"/>
807
	<value value="29" name="RBPERF_RB_MH_VALID_MAX"/>
808
	<value value="30" name="RBPERF_SX_RB_QUAD_SEND"/>
809
	<value value="31" name="RBPERF_SX_RB_COLOR_SEND"/>
810
	<value value="32" name="RBPERF_SC_RB_TILE_SEND"/>
811
	<value value="33" name="RBPERF_SC_RB_SAMPLE_SEND"/>
812
	<value value="34" name="RBPERF_SX_RB_MEM_EXPORT"/>
813
	<value value="35" name="RBPERF_SX_RB_QUAD_EVENT"/>
814
	<value value="36" name="RBPERF_SC_RB_TILE_EVENT_FILTERED"/>
815
	<value value="37" name="RBPERF_SC_RB_TILE_EVENT_ALL"/>
816
	<value value="38" name="RBPERF_RB_SC_EZ_SEND"/>
817
	<value value="39" name="RBPERF_RB_SX_INDEX_SEND"/>
818
	<value value="40" name="RBPERF_GMEM_INTFO_RD"/>
819
	<value value="41" name="RBPERF_GMEM_INTF1_RD"/>
820
	<value value="42" name="RBPERF_GMEM_INTFO_WR"/>
821
	<value value="43" name="RBPERF_GMEM_INTF1_WR"/>
822
	<value value="44" name="RBPERF_RB_CP_CONTEXT_DONE"/>
823
	<value value="45" name="RBPERF_RB_CP_CACHE_FLUSH"/>
824
	<value value="46" name="RBPERF_ZPASS_DONE"/>
825
	<value value="47" name="RBPERF_ZCMD_VALID"/>
826
	<value value="48" name="RBPERF_CCMD_VALID"/>
827
	<value value="49" name="RBPERF_ACCUM_GRANT"/>
828
	<value value="50" name="RBPERF_ACCUM_C0_GRANT"/>
829
	<value value="51" name="RBPERF_ACCUM_C1_GRANT"/>
830
	<value value="52" name="RBPERF_ACCUM_FULL_BE_WR"/>
831
	<value value="53" name="RBPERF_ACCUM_REQUEST_NO_GRANT"/>
832
	<value value="54" name="RBPERF_ACCUM_TIMEOUT_PULSE"/>
833
	<value value="55" name="RBPERF_ACCUM_LIN_TIMEOUT_PULSE"/>
834
	<value value="56" name="RBPERF_ACCUM_CAM_HIT_FLUSHING"/>
835
</enum>
836

837
<enum name="a2xx_mh_perfcnt_select">
838
	<value value="0" name="CP_R0_REQUESTS"/>
839
	<value value="1" name="CP_R1_REQUESTS"/>
840
	<value value="2" name="CP_R2_REQUESTS"/>
841
	<value value="3" name="CP_R3_REQUESTS"/>
842
	<value value="4" name="CP_R4_REQUESTS"/>
843
	<value value="5" name="CP_TOTAL_READ_REQUESTS"/>
844
	<value value="6" name="CP_TOTAL_WRITE_REQUESTS"/>
845
	<value value="7" name="CP_TOTAL_REQUESTS"/>
846
	<value value="8" name="CP_DATA_BYTES_WRITTEN"/>
847
	<value value="9" name="CP_WRITE_CLEAN_RESPONSES"/>
848
	<value value="10" name="CP_R0_READ_BURSTS_RECEIVED"/>
849
	<value value="11" name="CP_R1_READ_BURSTS_RECEIVED"/>
850
	<value value="12" name="CP_R2_READ_BURSTS_RECEIVED"/>
851
	<value value="13" name="CP_R3_READ_BURSTS_RECEIVED"/>
852
	<value value="14" name="CP_R4_READ_BURSTS_RECEIVED"/>
853
	<value value="15" name="CP_TOTAL_READ_BURSTS_RECEIVED"/>
854
	<value value="16" name="CP_R0_DATA_BEATS_READ"/>
855
	<value value="17" name="CP_R1_DATA_BEATS_READ"/>
856
	<value value="18" name="CP_R2_DATA_BEATS_READ"/>
857
	<value value="19" name="CP_R3_DATA_BEATS_READ"/>
858
	<value value="20" name="CP_R4_DATA_BEATS_READ"/>
859
	<value value="21" name="CP_TOTAL_DATA_BEATS_READ"/>
860
	<value value="22" name="VGT_R0_REQUESTS"/>
861
	<value value="23" name="VGT_R1_REQUESTS"/>
862
	<value value="24" name="VGT_TOTAL_REQUESTS"/>
863
	<value value="25" name="VGT_R0_READ_BURSTS_RECEIVED"/>
864
	<value value="26" name="VGT_R1_READ_BURSTS_RECEIVED"/>
865
	<value value="27" name="VGT_TOTAL_READ_BURSTS_RECEIVED"/>
866
	<value value="28" name="VGT_R0_DATA_BEATS_READ"/>
867
	<value value="29" name="VGT_R1_DATA_BEATS_READ"/>
868
	<value value="30" name="VGT_TOTAL_DATA_BEATS_READ"/>
869
	<value value="31" name="TC_TOTAL_REQUESTS"/>
870
	<value value="32" name="TC_ROQ_REQUESTS"/>
871
	<value value="33" name="TC_INFO_SENT"/>
872
	<value value="34" name="TC_READ_BURSTS_RECEIVED"/>
873
	<value value="35" name="TC_DATA_BEATS_READ"/>
874
	<value value="36" name="TCD_BURSTS_READ"/>
875
	<value value="37" name="RB_REQUESTS"/>
876
	<value value="38" name="RB_DATA_BYTES_WRITTEN"/>
877
	<value value="39" name="RB_WRITE_CLEAN_RESPONSES"/>
878
	<value value="40" name="AXI_READ_REQUESTS_ID_0"/>
879
	<value value="41" name="AXI_READ_REQUESTS_ID_1"/>
880
	<value value="42" name="AXI_READ_REQUESTS_ID_2"/>
881
	<value value="43" name="AXI_READ_REQUESTS_ID_3"/>
882
	<value value="44" name="AXI_READ_REQUESTS_ID_4"/>
883
	<value value="45" name="AXI_READ_REQUESTS_ID_5"/>
884
	<value value="46" name="AXI_READ_REQUESTS_ID_6"/>
885
	<value value="47" name="AXI_READ_REQUESTS_ID_7"/>
886
	<value value="48" name="AXI_TOTAL_READ_REQUESTS"/>
887
	<value value="49" name="AXI_WRITE_REQUESTS_ID_0"/>
888
	<value value="50" name="AXI_WRITE_REQUESTS_ID_1"/>
889
	<value value="51" name="AXI_WRITE_REQUESTS_ID_2"/>
890
	<value value="52" name="AXI_WRITE_REQUESTS_ID_3"/>
891
	<value value="53" name="AXI_WRITE_REQUESTS_ID_4"/>
892
	<value value="54" name="AXI_WRITE_REQUESTS_ID_5"/>
893
	<value value="55" name="AXI_WRITE_REQUESTS_ID_6"/>
894
	<value value="56" name="AXI_WRITE_REQUESTS_ID_7"/>
895
	<value value="57" name="AXI_TOTAL_WRITE_REQUESTS"/>
896
	<value value="58" name="AXI_TOTAL_REQUESTS_ID_0"/>
897
	<value value="59" name="AXI_TOTAL_REQUESTS_ID_1"/>
898
	<value value="60" name="AXI_TOTAL_REQUESTS_ID_2"/>
899
	<value value="61" name="AXI_TOTAL_REQUESTS_ID_3"/>
900
	<value value="62" name="AXI_TOTAL_REQUESTS_ID_4"/>
901
	<value value="63" name="AXI_TOTAL_REQUESTS_ID_5"/>
902
	<value value="64" name="AXI_TOTAL_REQUESTS_ID_6"/>
903
	<value value="65" name="AXI_TOTAL_REQUESTS_ID_7"/>
904
	<value value="66" name="AXI_TOTAL_REQUESTS"/>
905
	<value value="67" name="AXI_READ_CHANNEL_BURSTS_ID_0"/>
906
	<value value="68" name="AXI_READ_CHANNEL_BURSTS_ID_1"/>
907
	<value value="69" name="AXI_READ_CHANNEL_BURSTS_ID_2"/>
908
	<value value="70" name="AXI_READ_CHANNEL_BURSTS_ID_3"/>
909
	<value value="71" name="AXI_READ_CHANNEL_BURSTS_ID_4"/>
910
	<value value="72" name="AXI_READ_CHANNEL_BURSTS_ID_5"/>
911
	<value value="73" name="AXI_READ_CHANNEL_BURSTS_ID_6"/>
912
	<value value="74" name="AXI_READ_CHANNEL_BURSTS_ID_7"/>
913
	<value value="75" name="AXI_READ_CHANNEL_TOTAL_BURSTS"/>
914
	<value value="76" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0"/>
915
	<value value="77" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1"/>
916
	<value value="78" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2"/>
917
	<value value="79" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3"/>
918
	<value value="80" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4"/>
919
	<value value="81" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5"/>
920
	<value value="82" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6"/>
921
	<value value="83" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7"/>
922
	<value value="84" name="AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ"/>
923
	<value value="85" name="AXI_WRITE_CHANNEL_BURSTS_ID_0"/>
924
	<value value="86" name="AXI_WRITE_CHANNEL_BURSTS_ID_1"/>
925
	<value value="87" name="AXI_WRITE_CHANNEL_BURSTS_ID_2"/>
926
	<value value="88" name="AXI_WRITE_CHANNEL_BURSTS_ID_3"/>
927
	<value value="89" name="AXI_WRITE_CHANNEL_BURSTS_ID_4"/>
928
	<value value="90" name="AXI_WRITE_CHANNEL_BURSTS_ID_5"/>
929
	<value value="91" name="AXI_WRITE_CHANNEL_BURSTS_ID_6"/>
930
	<value value="92" name="AXI_WRITE_CHANNEL_BURSTS_ID_7"/>
931
	<value value="93" name="AXI_WRITE_CHANNEL_TOTAL_BURSTS"/>
932
	<value value="94" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0"/>
933
	<value value="95" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1"/>
934
	<value value="96" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2"/>
935
	<value value="97" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3"/>
936
	<value value="98" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4"/>
937
	<value value="99" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5"/>
938
	<value value="100" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6"/>
939
	<value value="101" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7"/>
940
	<value value="102" name="AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN"/>
941
	<value value="103" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0"/>
942
	<value value="104" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1"/>
943
	<value value="105" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2"/>
944
	<value value="106" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3"/>
945
	<value value="107" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4"/>
946
	<value value="108" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5"/>
947
	<value value="109" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6"/>
948
	<value value="110" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7"/>
949
	<value value="111" name="AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES"/>
950
	<value value="112" name="TOTAL_MMU_MISSES"/>
951
	<value value="113" name="MMU_READ_MISSES"/>
952
	<value value="114" name="MMU_WRITE_MISSES"/>
953
	<value value="115" name="TOTAL_MMU_HITS"/>
954
	<value value="116" name="MMU_READ_HITS"/>
955
	<value value="117" name="MMU_WRITE_HITS"/>
956
	<value value="118" name="SPLIT_MODE_TC_HITS"/>
957
	<value value="119" name="SPLIT_MODE_TC_MISSES"/>
958
	<value value="120" name="SPLIT_MODE_NON_TC_HITS"/>
959
	<value value="121" name="SPLIT_MODE_NON_TC_MISSES"/>
960
	<value value="122" name="STALL_AWAITING_TLB_MISS_FETCH"/>
961
	<value value="123" name="MMU_TLB_MISS_READ_BURSTS_RECEIVED"/>
962
	<value value="124" name="MMU_TLB_MISS_DATA_BEATS_READ"/>
963
	<value value="125" name="CP_CYCLES_HELD_OFF"/>
964
	<value value="126" name="VGT_CYCLES_HELD_OFF"/>
965
	<value value="127" name="TC_CYCLES_HELD_OFF"/>
966
	<value value="128" name="TC_ROQ_CYCLES_HELD_OFF"/>
967
	<value value="129" name="TC_CYCLES_HELD_OFF_TCD_FULL"/>
968
	<value value="130" name="RB_CYCLES_HELD_OFF"/>
969
	<value value="131" name="TOTAL_CYCLES_ANY_CLNT_HELD_OFF"/>
970
	<value value="132" name="TLB_MISS_CYCLES_HELD_OFF"/>
971
	<value value="133" name="AXI_READ_REQUEST_HELD_OFF"/>
972
	<value value="134" name="AXI_WRITE_REQUEST_HELD_OFF"/>
973
	<value value="135" name="AXI_REQUEST_HELD_OFF"/>
974
	<value value="136" name="AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT"/>
975
	<value value="137" name="AXI_WRITE_DATA_HELD_OFF"/>
976
	<value value="138" name="CP_SAME_PAGE_BANK_REQUESTS"/>
977
	<value value="139" name="VGT_SAME_PAGE_BANK_REQUESTS"/>
978
	<value value="140" name="TC_SAME_PAGE_BANK_REQUESTS"/>
979
	<value value="141" name="TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS"/>
980
	<value value="142" name="RB_SAME_PAGE_BANK_REQUESTS"/>
981
	<value value="143" name="TOTAL_SAME_PAGE_BANK_REQUESTS"/>
982
	<value value="144" name="CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
983
	<value value="145" name="VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
984
	<value value="146" name="TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
985
	<value value="147" name="RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
986
	<value value="148" name="TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT"/>
987
	<value value="149" name="TOTAL_MH_READ_REQUESTS"/>
988
	<value value="150" name="TOTAL_MH_WRITE_REQUESTS"/>
989
	<value value="151" name="TOTAL_MH_REQUESTS"/>
990
	<value value="152" name="MH_BUSY"/>
991
	<value value="153" name="CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
992
	<value value="154" name="VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
993
	<value value="155" name="TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
994
	<value value="156" name="RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
995
	<value value="157" name="TC_ROQ_N_VALID_ENTRIES"/>
996
	<value value="158" name="ARQ_N_ENTRIES"/>
997
	<value value="159" name="WDB_N_ENTRIES"/>
998
	<value value="160" name="MH_READ_LATENCY_OUTST_REQ_SUM"/>
999
	<value value="161" name="MC_READ_LATENCY_OUTST_REQ_SUM"/>
1000
	<value value="162" name="MC_TOTAL_READ_REQUESTS"/>
1001
	<value value="163" name="ELAPSED_CYCLES_MH_GATED_CLK"/>
1002
	<value value="164" name="ELAPSED_CLK_CYCLES"/>
1003
	<value value="165" name="CP_W_16B_REQUESTS"/>
1004
	<value value="166" name="CP_W_32B_REQUESTS"/>
1005
	<value value="167" name="TC_16B_REQUESTS"/>
1006
	<value value="168" name="TC_32B_REQUESTS"/>
1007
	<value value="169" name="PA_REQUESTS"/>
1008
	<value value="170" name="PA_DATA_BYTES_WRITTEN"/>
1009
	<value value="171" name="PA_WRITE_CLEAN_RESPONSES"/>
1010
	<value value="172" name="PA_CYCLES_HELD_OFF"/>
1011
	<value value="173" name="AXI_READ_REQUEST_DATA_BEATS_ID_0"/>
1012
	<value value="174" name="AXI_READ_REQUEST_DATA_BEATS_ID_1"/>
1013
	<value value="175" name="AXI_READ_REQUEST_DATA_BEATS_ID_2"/>
1014
	<value value="176" name="AXI_READ_REQUEST_DATA_BEATS_ID_3"/>
1015
	<value value="177" name="AXI_READ_REQUEST_DATA_BEATS_ID_4"/>
1016
	<value value="178" name="AXI_READ_REQUEST_DATA_BEATS_ID_5"/>
1017
	<value value="179" name="AXI_READ_REQUEST_DATA_BEATS_ID_6"/>
1018
	<value value="180" name="AXI_READ_REQUEST_DATA_BEATS_ID_7"/>
1019
	<value value="181" name="AXI_TOTAL_READ_REQUEST_DATA_BEATS"/>
1020
</enum>
1021

1022
<domain name="A2XX" width="32">
1023

1024
	<bitset name="a2xx_vgt_current_bin_id_min_max" inline="yes">
1025
		<bitfield name="COLUMN" low="0" high="2" type="uint"/>
1026
		<bitfield name="ROW" low="3" high="5" type="uint"/>
1027
		<bitfield name="GUARD_BAND_MASK" low="6" high="8" type="uint"/>
1028
	</bitset>
1029

1030
	<reg32 offset="0x0001" name="RBBM_PATCH_RELEASE"/>
1031
	<reg32 offset="0x003b" name="RBBM_CNTL"/>
1032
	<reg32 offset="0x003c" name="RBBM_SOFT_RESET"/>
1033
	<reg32 offset="0x00c0" name="CP_PFP_UCODE_ADDR"/>
1034
	<reg32 offset="0x00c1" name="CP_PFP_UCODE_DATA"/>
1035

1036
	<enum name="adreno_mmu_clnt_beh">
1037
		<value name="BEH_NEVR" value="0"/>
1038
		<value name="BEH_TRAN_RNG" value="1"/>
1039
		<value name="BEH_TRAN_FLT" value="2"/>
1040
	</enum>
1041

1042
	<!--
1043
		Note: these seem applicable only for a2xx devices with gpummu?  At
1044
		any rate, MH_MMU_CONFIG shows up in places in a3xx firmware where
1045
		it doesn't make sense, so I think offset 0x40 must be a different
1046
		register on a3xx.. so moving this back into A2XX domain:
1047
	 -->
1048
	<reg32 offset="0x0040" name="MH_MMU_CONFIG">
1049
		<bitfield name="MMU_ENABLE" pos="0" type="boolean"/>
1050
		<bitfield name="SPLIT_MODE_ENABLE" pos="1" type="boolean"/>
1051
		<bitfield name="RB_W_CLNT_BEHAVIOR" low="4" high="5" type="adreno_mmu_clnt_beh"/>
1052
		<bitfield name="CP_W_CLNT_BEHAVIOR" low="6" high="7" type="adreno_mmu_clnt_beh"/>
1053
		<bitfield name="CP_R0_CLNT_BEHAVIOR" low="8" high="9" type="adreno_mmu_clnt_beh"/>
1054
		<bitfield name="CP_R1_CLNT_BEHAVIOR" low="10" high="11" type="adreno_mmu_clnt_beh"/>
1055
		<bitfield name="CP_R2_CLNT_BEHAVIOR" low="12" high="13" type="adreno_mmu_clnt_beh"/>
1056
		<bitfield name="CP_R3_CLNT_BEHAVIOR" low="14" high="15" type="adreno_mmu_clnt_beh"/>
1057
		<bitfield name="CP_R4_CLNT_BEHAVIOR" low="16" high="17" type="adreno_mmu_clnt_beh"/>
1058
		<bitfield name="VGT_R0_CLNT_BEHAVIOR" low="18" high="19" type="adreno_mmu_clnt_beh"/>
1059
		<bitfield name="VGT_R1_CLNT_BEHAVIOR" low="20" high="21" type="adreno_mmu_clnt_beh"/>
1060
		<bitfield name="TC_R_CLNT_BEHAVIOR" low="22" high="23" type="adreno_mmu_clnt_beh"/>
1061
		<bitfield name="PA_W_CLNT_BEHAVIOR" low="24" high="25" type="adreno_mmu_clnt_beh"/>
1062
	</reg32>
1063
	<reg32 offset="0x0041" name="MH_MMU_VA_RANGE">
1064
		<bitfield name="NUM_64KB_REGIONS" low="0" high="11" type="uint"/>
1065
		<bitfield name="VA_BASE" low="12" high="31" type="uint"/>
1066
	</reg32>
1067
	<reg32 offset="0x0042" name="MH_MMU_PT_BASE"/>
1068
	<reg32 offset="0x0043" name="MH_MMU_PAGE_FAULT"/>
1069
	<reg32 offset="0x0044" name="MH_MMU_TRAN_ERROR"/>
1070
	<reg32 offset="0x0045" name="MH_MMU_INVALIDATE">
1071
		<bitfield name="INVALIDATE_ALL" pos="0" type="boolean"/>
1072
		<bitfield name="INVALIDATE_TC" pos="1" type="boolean"/>
1073
	</reg32>
1074
	<reg32 offset="0x0046" name="MH_MMU_MPU_BASE"/>
1075
	<reg32 offset="0x0047" name="MH_MMU_MPU_END"/>
1076

1077
	<reg32 offset="0x0394" name="NQWAIT_UNTIL"/>
1078
	<reg32 offset="0x0395" name="RBBM_PERFCOUNTER0_SELECT"/>
1079
	<reg32 offset="0x0396" name="RBBM_PERFCOUNTER1_SELECT"/>
1080
	<reg32 offset="0x0397" name="RBBM_PERFCOUNTER0_LO"/>
1081
	<reg32 offset="0x0398" name="RBBM_PERFCOUNTER0_HI"/>
1082
	<reg32 offset="0x0399" name="RBBM_PERFCOUNTER1_LO"/>
1083
	<reg32 offset="0x039a" name="RBBM_PERFCOUNTER1_HI"/>
1084
	<reg32 offset="0x039b" name="RBBM_DEBUG"/>
1085
	<reg32 offset="0x039c" name="RBBM_PM_OVERRIDE1">
1086
		<bitfield name="RBBM_AHBCLK_PM_OVERRIDE" pos="0" type="boolean"/>
1087
		<bitfield name="SC_REG_SCLK_PM_OVERRIDE" pos="1" type="boolean"/>
1088
		<bitfield name="SC_SCLK_PM_OVERRIDE" pos="2" type="boolean"/>
1089
		<bitfield name="SP_TOP_SCLK_PM_OVERRIDE" pos="3" type="boolean"/>
1090
		<bitfield name="SP_V0_SCLK_PM_OVERRIDE" pos="4" type="boolean"/>
1091
		<bitfield name="SQ_REG_SCLK_PM_OVERRIDE" pos="5" type="boolean"/>
1092
		<bitfield name="SQ_REG_FIFOS_SCLK_PM_OVERRIDE" pos="6" type="boolean"/>
1093
		<bitfield name="SQ_CONST_MEM_SCLK_PM_OVERRIDE" pos="7" type="boolean"/>
1094
		<bitfield name="SQ_SQ_SCLK_PM_OVERRIDE" pos="8" type="boolean"/>
1095
		<bitfield name="SX_SCLK_PM_OVERRIDE" pos="9" type="boolean"/>
1096
		<bitfield name="SX_REG_SCLK_PM_OVERRIDE" pos="10" type="boolean"/>
1097
		<bitfield name="TCM_TCO_SCLK_PM_OVERRIDE" pos="11" type="boolean"/>
1098
		<bitfield name="TCM_TCM_SCLK_PM_OVERRIDE" pos="12" type="boolean"/>
1099
		<bitfield name="TCM_TCD_SCLK_PM_OVERRIDE" pos="13" type="boolean"/>
1100
		<bitfield name="TCM_REG_SCLK_PM_OVERRIDE" pos="14" type="boolean"/>
1101
		<bitfield name="TPC_TPC_SCLK_PM_OVERRIDE" pos="15" type="boolean"/>
1102
		<bitfield name="TPC_REG_SCLK_PM_OVERRIDE" pos="16" type="boolean"/>
1103
		<bitfield name="TCF_TCA_SCLK_PM_OVERRIDE" pos="17" type="boolean"/>
1104
		<bitfield name="TCF_TCB_SCLK_PM_OVERRIDE" pos="18" type="boolean"/>
1105
		<bitfield name="TCF_TCB_READ_SCLK_PM_OVERRIDE" pos="19" type="boolean"/>
1106
		<bitfield name="TP_TP_SCLK_PM_OVERRIDE" pos="20" type="boolean"/>
1107
		<bitfield name="TP_REG_SCLK_PM_OVERRIDE" pos="21" type="boolean"/>
1108
		<bitfield name="CP_G_SCLK_PM_OVERRIDE" pos="22" type="boolean"/>
1109
		<bitfield name="CP_REG_SCLK_PM_OVERRIDE" pos="23" type="boolean"/>
1110
		<bitfield name="CP_G_REG_SCLK_PM_OVERRIDE" pos="24" type="boolean"/>
1111
		<bitfield name="SPI_SCLK_PM_OVERRIDE" pos="25" type="boolean"/>
1112
		<bitfield name="RB_REG_SCLK_PM_OVERRIDE" pos="26" type="boolean"/>
1113
		<bitfield name="RB_SCLK_PM_OVERRIDE" pos="27" type="boolean"/>
1114
		<bitfield name="MH_MH_SCLK_PM_OVERRIDE" pos="28" type="boolean"/>
1115
		<bitfield name="MH_REG_SCLK_PM_OVERRIDE" pos="29" type="boolean"/>
1116
		<bitfield name="MH_MMU_SCLK_PM_OVERRIDE" pos="30" type="boolean"/>
1117
		<bitfield name="MH_TCROQ_SCLK_PM_OVERRIDE" pos="31" type="boolean"/>
1118
	</reg32>
1119
	<reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2"/>
1120
	<reg32 offset="0x03a0" name="RBBM_DEBUG_OUT"/>
1121
	<reg32 offset="0x03a1" name="RBBM_DEBUG_CNTL"/>
1122
	<reg32 offset="0x03b3" name="RBBM_READ_ERROR"/>
1123
	<reg32 offset="0x03b4" name="RBBM_INT_CNTL">
1124
		<bitfield name="RDERR_INT_MASK" pos="0" type="boolean"/>
1125
		<bitfield name="DISPLAY_UPDATE_INT_MASK" pos="1" type="boolean"/>
1126
		<bitfield name="GUI_IDLE_INT_MASK" pos="19" type="boolean"/>
1127
	</reg32>
1128
	<reg32 offset="0x03b5" name="RBBM_INT_STATUS"/>
1129
	<reg32 offset="0x03b6" name="RBBM_INT_ACK"/>
1130
	<reg32 offset="0x03b7" name="MASTER_INT_SIGNAL">
1131
		<bitfield name="MH_INT_STAT" pos="5" type="boolean"/>
1132
		<bitfield name="SQ_INT_STAT" pos="26" type="boolean"/>
1133
		<bitfield name="CP_INT_STAT" pos="30" type="boolean"/>
1134
		<bitfield name="RBBM_INT_STAT" pos="31" type="boolean"/>
1135
	</reg32>
1136
	<reg32 offset="0x03f9" name="RBBM_PERIPHID1"/>
1137
	<reg32 offset="0x03fa" name="RBBM_PERIPHID2"/>
1138
	<reg32 offset="0x0444" name="CP_PERFMON_CNTL"/>
1139
	<reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT"/>
1140
	<reg32 offset="0x0446" name="CP_PERFCOUNTER_LO"/>
1141
	<reg32 offset="0x0447" name="CP_PERFCOUNTER_HI"/>
1142
	<reg32 offset="0x05d0" name="RBBM_STATUS">
1143
		<bitfield name="CMDFIFO_AVAIL" low="0" high="4" type="uint"/>
1144
		<bitfield name="TC_BUSY" pos="5" type="boolean"/>
1145
		<bitfield name="HIRQ_PENDING" pos="8" type="boolean"/>
1146
		<bitfield name="CPRQ_PENDING" pos="9" type="boolean"/>
1147
		<bitfield name="CFRQ_PENDING" pos="10" type="boolean"/>
1148
		<bitfield name="PFRQ_PENDING" pos="11" type="boolean"/>
1149
		<bitfield name="VGT_BUSY_NO_DMA" pos="12" type="boolean"/>
1150
		<bitfield name="RBBM_WU_BUSY" pos="14" type="boolean"/>
1151
		<bitfield name="CP_NRT_BUSY" pos="16" type="boolean"/>
1152
		<bitfield name="MH_BUSY" pos="18" type="boolean"/>
1153
		<bitfield name="MH_COHERENCY_BUSY" pos="19" type="boolean"/>
1154
		<bitfield name="SX_BUSY" pos="21" type="boolean"/>
1155
		<bitfield name="TPC_BUSY" pos="22" type="boolean"/>
1156
		<bitfield name="SC_CNTX_BUSY" pos="24" type="boolean"/>
1157
		<bitfield name="PA_BUSY" pos="25" type="boolean"/>
1158
		<bitfield name="VGT_BUSY" pos="26" type="boolean"/>
1159
		<bitfield name="SQ_CNTX17_BUSY" pos="27" type="boolean"/>
1160
		<bitfield name="SQ_CNTX0_BUSY" pos="28" type="boolean"/>
1161
		<bitfield name="RB_CNTX_BUSY" pos="30" type="boolean"/>
1162
		<bitfield name="GUI_ACTIVE" pos="31" type="boolean"/>
1163
	</reg32>
1164
	<reg32 offset="0x0a40" name="MH_ARBITER_CONFIG">
1165
		<bitfield name="SAME_PAGE_LIMIT" low="0" high="5" type="uint"/>
1166
		<bitfield name="SAME_PAGE_GRANULARITY" pos="6" type="boolean"/>
1167
		<bitfield name="L1_ARB_ENABLE" pos="7" type="boolean"/>
1168
		<bitfield name="L1_ARB_HOLD_ENABLE" pos="8" type="boolean"/>
1169
		<bitfield name="L2_ARB_CONTROL" pos="9" type="boolean"/>
1170
		<bitfield name="PAGE_SIZE" low="10" high="12" type="uint"/>
1171
		<bitfield name="TC_REORDER_ENABLE" pos="13" type="boolean"/>
1172
		<bitfield name="TC_ARB_HOLD_ENABLE" pos="14" type="boolean"/>
1173
		<bitfield name="IN_FLIGHT_LIMIT_ENABLE" pos="15" type="boolean"/>
1174
		<bitfield name="IN_FLIGHT_LIMIT" low="16" high="21" type="uint"/>
1175
		<bitfield name="CP_CLNT_ENABLE" pos="22" type="boolean"/>
1176
		<bitfield name="VGT_CLNT_ENABLE" pos="23" type="boolean"/>
1177
		<bitfield name="TC_CLNT_ENABLE" pos="24" type="boolean"/>
1178
		<bitfield name="RB_CLNT_ENABLE" pos="25" type="boolean"/>
1179
		<bitfield name="PA_CLNT_ENABLE" pos="26" type="boolean"/>
1180
	</reg32>
1181
	<reg32 offset="0x0a42" name="MH_INTERRUPT_MASK">
1182
		<bitfield name="AXI_READ_ERROR" pos="0" type="boolean"/>
1183
		<bitfield name="AXI_WRITE_ERROR" pos="1" type="boolean"/>
1184
		<bitfield name="MMU_PAGE_FAULT" pos="2" type="boolean"/>
1185
	</reg32>
1186
	<reg32 offset="0x0a43" name="MH_INTERRUPT_STATUS"/>
1187
	<reg32 offset="0x0a44" name="MH_INTERRUPT_CLEAR"/>
1188
	<reg32 offset="0x0a54" name="MH_CLNT_INTF_CTRL_CONFIG1"/>
1189
	<reg32 offset="0x0a55" name="MH_CLNT_INTF_CTRL_CONFIG2"/>
1190
	<reg32 offset="0x0c01" name="A220_VSC_BIN_SIZE">
1191
		<bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
1192
		<bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
1193
	</reg32>
1194
	<array offset="0x0c06" name="VSC_PIPE" stride="3" length="8">
1195
		<reg32 offset="0x0" name="CONFIG"/>
1196
		<reg32 offset="0x1" name="DATA_ADDRESS"/>
1197
		<reg32 offset="0x2" name="DATA_LENGTH"/>
1198
	</array>
1199
	<reg32 offset="0x0c38" name="PC_DEBUG_CNTL"/>
1200
	<reg32 offset="0x0c39" name="PC_DEBUG_DATA"/>
1201
	<reg32 offset="0x0c44" name="PA_SC_VIZ_QUERY_STATUS"/>
1202
	<reg32 offset="0x0c80" name="GRAS_DEBUG_CNTL"/>
1203
	<reg32 offset="0x0c80" name="PA_SU_DEBUG_CNTL"/>
1204
	<reg32 offset="0x0c81" name="GRAS_DEBUG_DATA"/>
1205
	<reg32 offset="0x0c81" name="PA_SU_DEBUG_DATA"/>
1206
	<reg32 offset="0x0c86" name="PA_SU_FACE_DATA">
1207
		<bitfield name="BASE_ADDR" low="5" high="31" type="uint"/>
1208
	</reg32>
1209
	<reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT">
1210
		<bitfield name="REG_DYNAMIC" pos="0" type="boolean"/>
1211
		<bitfield name="REG_SIZE_PIX" low="4" high="11" type="uint"/>
1212
		<bitfield name="REG_SIZE_VTX" low="12" high="19" type="uint"/>
1213
	</reg32>
1214
	<reg32 offset="0x0d01" name="SQ_FLOW_CONTROL"/>
1215
	<reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT">
1216
		<bitfield name="INST_BASE_PIX" low="0" high="11" type="uint"/>
1217
		<bitfield name="INST_BASE_VTX" low="16" high="27" type="uint"/>
1218
	</reg32>
1219
	<reg32 offset="0x0d05" name="SQ_DEBUG_MISC"/>
1220
	<reg32 offset="0x0d34" name="SQ_INT_CNTL"/>
1221
	<reg32 offset="0x0d35" name="SQ_INT_STATUS"/>
1222
	<reg32 offset="0x0d36" name="SQ_INT_ACK"/>
1223
	<reg32 offset="0x0dae" name="SQ_DEBUG_INPUT_FSM"/>
1224
	<reg32 offset="0x0daf" name="SQ_DEBUG_CONST_MGR_FSM"/>
1225
	<reg32 offset="0x0db0" name="SQ_DEBUG_TP_FSM"/>
1226
	<reg32 offset="0x0db1" name="SQ_DEBUG_FSM_ALU_0"/>
1227
	<reg32 offset="0x0db2" name="SQ_DEBUG_FSM_ALU_1"/>
1228
	<reg32 offset="0x0db3" name="SQ_DEBUG_EXP_ALLOC"/>
1229
	<reg32 offset="0x0db4" name="SQ_DEBUG_PTR_BUFF"/>
1230
	<reg32 offset="0x0db5" name="SQ_DEBUG_GPR_VTX"/>
1231
	<reg32 offset="0x0db6" name="SQ_DEBUG_GPR_PIX"/>
1232
	<reg32 offset="0x0db7" name="SQ_DEBUG_TB_STATUS_SEL"/>
1233
	<reg32 offset="0x0db8" name="SQ_DEBUG_VTX_TB_0"/>
1234
	<reg32 offset="0x0db9" name="SQ_DEBUG_VTX_TB_1"/>
1235
	<reg32 offset="0x0dba" name="SQ_DEBUG_VTX_TB_STATUS_REG"/>
1236
	<reg32 offset="0x0dbb" name="SQ_DEBUG_VTX_TB_STATE_MEM"/>
1237
	<reg32 offset="0x0dbc" name="SQ_DEBUG_PIX_TB_0"/>
1238
	<reg32 offset="0x0dbd" name="SQ_DEBUG_PIX_TB_STATUS_REG_0"/>
1239
	<reg32 offset="0x0dbe" name="SQ_DEBUG_PIX_TB_STATUS_REG_1"/>
1240
	<reg32 offset="0x0dbf" name="SQ_DEBUG_PIX_TB_STATUS_REG_2"/>
1241
	<reg32 offset="0x0dc0" name="SQ_DEBUG_PIX_TB_STATUS_REG_3"/>
1242
	<reg32 offset="0x0dc1" name="SQ_DEBUG_PIX_TB_STATE_MEM"/>
1243
	<reg32 offset="0x0e00" name="TC_CNTL_STATUS">
1244
		<bitfield name="L2_INVALIDATE" pos="0" type="boolean"/>
1245
	</reg32>
1246
	<reg32 offset="0x0e1e" name="TP0_CHICKEN"/>
1247
	<reg32 offset="0x0f01" name="RB_BC_CONTROL">
1248
		<bitfield name="ACCUM_LINEAR_MODE_ENABLE" pos="0" type="boolean"/>
1249
		<bitfield name="ACCUM_TIMEOUT_SELECT" low="1" high="2" type="uint"/>
1250
		<bitfield name="DISABLE_EDRAM_CAM" pos="3" type="boolean"/>
1251
		<bitfield name="DISABLE_EZ_FAST_CONTEXT_SWITCH" pos="4" type="boolean"/>
1252
		<bitfield name="DISABLE_EZ_NULL_ZCMD_DROP" pos="5" type="boolean"/>
1253
		<bitfield name="DISABLE_LZ_NULL_ZCMD_DROP" pos="6" type="boolean"/>
1254
		<bitfield name="ENABLE_AZ_THROTTLE" pos="7" type="boolean"/>
1255
		<bitfield name="AZ_THROTTLE_COUNT" low="8" high="12" type="uint"/>
1256
		<bitfield name="ENABLE_CRC_UPDATE" pos="14" type="boolean"/>
1257
		<bitfield name="CRC_MODE" pos="15" type="boolean"/>
1258
		<bitfield name="DISABLE_SAMPLE_COUNTERS" pos="16" type="boolean"/>
1259
		<bitfield name="DISABLE_ACCUM" pos="17" type="boolean"/>
1260
		<bitfield name="ACCUM_ALLOC_MASK" low="18" high="21" type="uint"/>
1261
		<bitfield name="LINEAR_PERFORMANCE_ENABLE" pos="22" type="boolean"/>
1262
		<bitfield name="ACCUM_DATA_FIFO_LIMIT" low="23" high="26" type="uint"/>
1263
		<bitfield name="MEM_EXPORT_TIMEOUT_SELECT" low="27" high="28" type="uint"/>
1264
		<bitfield name="MEM_EXPORT_LINEAR_MODE_ENABLE" pos="29" type="boolean"/>
1265
		<bitfield name="CRC_SYSTEM" pos="30" type="boolean"/>
1266
		<bitfield name="RESERVED6" pos="31" type="boolean"/>
1267
	</reg32>
1268
	<reg32 offset="0x0f02" name="RB_EDRAM_INFO"/>
1269
	<reg32 offset="0x0f26" name="RB_DEBUG_CNTL"/>
1270
	<reg32 offset="0x0f27" name="RB_DEBUG_DATA"/>
1271
	<reg32 offset="0x2000" name="RB_SURFACE_INFO">
1272
		<bitfield name="SURFACE_PITCH" low="0" high="13" type="uint"/>
1273
		<bitfield name="MSAA_SAMPLES" low="14" high="15" type="uint"/>
1274
	</reg32>
1275
	<reg32 offset="0x2001" name="RB_COLOR_INFO">
1276
		<bitfield name="FORMAT" low="0" high="3" type="a2xx_colorformatx"/>
1277
		<bitfield name="ROUND_MODE" low="4" high="5" type="uint"/>
1278
		<bitfield name="LINEAR" pos="6" type="boolean"/>
1279
		<bitfield name="ENDIAN" low="7" high="8" type="uint"/>
1280
		<bitfield name="SWAP" low="9" high="10" type="uint"/>
1281
		<bitfield name="BASE" low="12" high="31" shr="12"/>
1282
	</reg32>
1283
	<reg32 offset="0x2002" name="RB_DEPTH_INFO">
1284
		<bitfield name="DEPTH_FORMAT" pos="0" type="adreno_rb_depth_format"/>
1285
		<bitfield name="DEPTH_BASE" low="12" high="31" type="uint" shr="12"/>
1286
	</reg32>
1287
	<reg32 offset="0x2005" name="A225_RB_COLOR_INFO3"/>
1288
	<reg32 offset="0x2006" name="COHER_DEST_BASE_0"/>
1289
	<reg32 offset="0x200e" name="PA_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
1290
	<reg32 offset="0x200f" name="PA_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
1291
	<reg32 offset="0x2080" name="PA_SC_WINDOW_OFFSET">
1292
		<bitfield name="X" low="0" high="14" type="int"/>
1293
		<bitfield name="Y" low="16" high="30" type="int"/>
1294
		<bitfield name="DISABLE" pos="31" type="boolean"/>
1295
	</reg32>
1296
	<reg32 offset="0x2081" name="PA_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1297
	<reg32 offset="0x2082" name="PA_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1298
	<reg32 offset="0x2010" name="UNKNOWN_2010"/>
1299
	<reg32 offset="0x2100" name="VGT_MAX_VTX_INDX"/>
1300
	<reg32 offset="0x2101" name="VGT_MIN_VTX_INDX"/>
1301
	<reg32 offset="0x2102" name="VGT_INDX_OFFSET"/>
1302
	<reg32 offset="0x2103" name="A225_PC_MULTI_PRIM_IB_RESET_INDX"/>
1303
	<reg32 offset="0x2104" name="RB_COLOR_MASK">
1304
		<bitfield name="WRITE_RED" pos="0" type="boolean"/>
1305
		<bitfield name="WRITE_GREEN" pos="1" type="boolean"/>
1306
		<bitfield name="WRITE_BLUE" pos="2" type="boolean"/>
1307
		<bitfield name="WRITE_ALPHA" pos="3" type="boolean"/>
1308
	</reg32>
1309
	<reg32 offset="0x2105" name="RB_BLEND_RED"/>
1310
	<reg32 offset="0x2106" name="RB_BLEND_GREEN"/>
1311
	<reg32 offset="0x2107" name="RB_BLEND_BLUE"/>
1312
	<reg32 offset="0x2108" name="RB_BLEND_ALPHA"/>
1313
	<reg32 offset="0x2109" name="RB_FOG_COLOR">
1314
		<bitfield name="FOG_RED" low="0" high="7" type="uint"/>
1315
		<bitfield name="FOG_GREEN" low="8" high="15" type="uint"/>
1316
		<bitfield name="FOG_BLUE" low="16" high="23" type="uint"/>
1317
	</reg32>
1318
	<reg32 offset="0x210c" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
1319
	<reg32 offset="0x210d" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
1320
	<reg32 offset="0x210e" name="RB_ALPHA_REF"/>
1321
	<reg32 offset="0x210f" name="PA_CL_VPORT_XSCALE" type="float"/>
1322
	<reg32 offset="0x2110" name="PA_CL_VPORT_XOFFSET" type="float"/>
1323
	<reg32 offset="0x2111" name="PA_CL_VPORT_YSCALE" type="float"/>
1324
	<reg32 offset="0x2112" name="PA_CL_VPORT_YOFFSET" type="float"/>
1325
	<reg32 offset="0x2113" name="PA_CL_VPORT_ZSCALE" type="float"/>
1326
	<reg32 offset="0x2114" name="PA_CL_VPORT_ZOFFSET" type="float"/>
1327
	<reg32 offset="0x2180" name="SQ_PROGRAM_CNTL">
1328
		<doc>
1329
			note: only 0x3f worth of valid register values for VS_REGS and
1330
			PS_REGS, but high bit is set to indicate '0 registers used':
1331
		</doc>
1332
		<bitfield name="VS_REGS" low="0" high="7" type="uint"/>
1333
		<bitfield name="PS_REGS" low="8" high="15" type="uint"/>
1334
		<bitfield name="VS_RESOURCE" pos="16" type="boolean"/>
1335
		<bitfield name="PS_RESOURCE" pos="17" type="boolean"/>
1336
		<bitfield name="PARAM_GEN" pos="18" type="boolean"/>
1337
		<bitfield name="GEN_INDEX_PIX" pos="19" type="boolean"/>
1338
		<bitfield name="VS_EXPORT_COUNT" low="20" high="23" type="uint"/>
1339
		<bitfield name="VS_EXPORT_MODE" low="24" high="26" type="a2xx_sq_ps_vtx_mode"/>
1340
		<bitfield name="PS_EXPORT_MODE" low="27" high="30" type="uint"/>
1341
		<bitfield name="GEN_INDEX_VTX" pos="31" type="boolean"/>
1342
	</reg32>
1343
	<reg32 offset="0x2181" name="SQ_CONTEXT_MISC">
1344
		<bitfield name="INST_PRED_OPTIMIZE" pos="0" type="boolean"/>
1345
		<bitfield name="SC_OUTPUT_SCREEN_XY" pos="1" type="boolean"/>
1346
		<bitfield name="SC_SAMPLE_CNTL" low="2" high="3" type="a2xx_sq_sample_cntl"/>
1347
		<bitfield name="PARAM_GEN_POS" low="8" high="15" type="uint"/>
1348
		<bitfield name="PERFCOUNTER_REF" pos="16" type="boolean"/>
1349
		<bitfield name="YEILD_OPTIMIZE" pos="17" type="boolean"/>
1350
		<bitfield name="TX_CACHE_SEL" pos="18" type="boolean"/>
1351
	</reg32>
1352
	<reg32 offset="0x2182" name="SQ_INTERPOLATOR_CNTL">
1353
		<bitfield name="PARAM_SHADE" low="0" high="15" type="uint"/>
1354
		<bitfield name="SAMPLING_PATTERN" low="16" high="31" type="uint"/>
1355
	</reg32>
1356
	<reg32 offset="0x2183" name="SQ_WRAPPING_0">
1357
		<bitfield name="PARAM_WRAP_0" low="0" high="3" type="uint"/>
1358
		<bitfield name="PARAM_WRAP_1" low="4" high="7" type="uint"/>
1359
		<bitfield name="PARAM_WRAP_2" low="8" high="11" type="uint"/>
1360
		<bitfield name="PARAM_WRAP_3" low="12" high="15" type="uint"/>
1361
		<bitfield name="PARAM_WRAP_4" low="16" high="19" type="uint"/>
1362
		<bitfield name="PARAM_WRAP_5" low="20" high="23" type="uint"/>
1363
		<bitfield name="PARAM_WRAP_6" low="24" high="27" type="uint"/>
1364
		<bitfield name="PARAM_WRAP_7" low="28" high="31" type="uint"/>
1365
	</reg32>
1366
	<reg32 offset="0x2184" name="SQ_WRAPPING_1">
1367
		<bitfield name="PARAM_WRAP_8" low="0" high="3" type="uint"/>
1368
		<bitfield name="PARAM_WRAP_9" low="4" high="7" type="uint"/>
1369
		<bitfield name="PARAM_WRAP_10" low="8" high="11" type="uint"/>
1370
		<bitfield name="PARAM_WRAP_11" low="12" high="15" type="uint"/>
1371
		<bitfield name="PARAM_WRAP_12" low="16" high="19" type="uint"/>
1372
		<bitfield name="PARAM_WRAP_13" low="20" high="23" type="uint"/>
1373
		<bitfield name="PARAM_WRAP_14" low="24" high="27" type="uint"/>
1374
		<bitfield name="PARAM_WRAP_15" low="28" high="31" type="uint"/>
1375
	</reg32>
1376
	<reg32 offset="0x21f6" name="SQ_PS_PROGRAM">
1377
		<bitfield name="BASE" low="0" high="11" type="uint"/>
1378
		<bitfield name="SIZE" low="12" high="23" type="uint"/>
1379
	</reg32>
1380
	<reg32 offset="0x21f7" name="SQ_VS_PROGRAM">
1381
		<bitfield name="BASE" low="0" high="11" type="uint"/>
1382
		<bitfield name="SIZE" low="12" high="23" type="uint"/>
1383
	</reg32>
1384
	<reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/>
1385
	<reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/>
1386
	<reg32 offset="0x21fd" name="VGT_IMMED_DATA"/>
1387
	<reg32 offset="0x2200" name="RB_DEPTHCONTROL">
1388
		<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
1389
		<bitfield name="Z_ENABLE" pos="1" type="boolean"/>
1390
		<bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
1391
		<bitfield name="EARLY_Z_ENABLE" pos="3" type="boolean"/>
1392
		<bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
1393
		<bitfield name="BACKFACE_ENABLE" pos="7" type="boolean"/>
1394
		<bitfield name="STENCILFUNC" low="8" high="10" type="adreno_compare_func"/>
1395
		<bitfield name="STENCILFAIL" low="11" high="13" type="adreno_stencil_op"/>
1396
		<bitfield name="STENCILZPASS" low="14" high="16" type="adreno_stencil_op"/>
1397
		<bitfield name="STENCILZFAIL" low="17" high="19" type="adreno_stencil_op"/>
1398
		<bitfield name="STENCILFUNC_BF" low="20" high="22" type="adreno_compare_func"/>
1399
		<bitfield name="STENCILFAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
1400
		<bitfield name="STENCILZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
1401
		<bitfield name="STENCILZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
1402
	</reg32>
1403
	<reg32 offset="0x2201" name="RB_BLEND_CONTROL">
1404
		<bitfield name="COLOR_SRCBLEND" low="0" high="4" type="adreno_rb_blend_factor"/>
1405
		<bitfield name="COLOR_COMB_FCN" low="5" high="7" type="a2xx_rb_blend_opcode"/>
1406
		<bitfield name="COLOR_DESTBLEND" low="8" high="12" type="adreno_rb_blend_factor"/>
1407
		<bitfield name="ALPHA_SRCBLEND" low="16" high="20" type="adreno_rb_blend_factor"/>
1408
		<bitfield name="ALPHA_COMB_FCN" low="21" high="23" type="a2xx_rb_blend_opcode"/>
1409
		<bitfield name="ALPHA_DESTBLEND" low="24" high="28" type="adreno_rb_blend_factor"/>
1410
		<bitfield name="BLEND_FORCE_ENABLE" pos="29" type="boolean"/>
1411
		<bitfield name="BLEND_FORCE" pos="30" type="boolean"/>
1412
	</reg32>
1413
	<reg32 offset="0x2202" name="RB_COLORCONTROL">
1414
		<bitfield name="ALPHA_FUNC" low="0" high="2" type="adreno_compare_func"/>
1415
		<bitfield name="ALPHA_TEST_ENABLE" pos="3" type="boolean"/>
1416
		<bitfield name="ALPHA_TO_MASK_ENABLE" pos="4" type="boolean"/>
1417
		<bitfield name="BLEND_DISABLE" pos="5" type="boolean"/>
1418
		<bitfield name="VOB_ENABLE" pos="6" type="boolean"/>
1419
		<bitfield name="VS_EXPORTS_FOG" pos="7" type="boolean"/>
1420
		<bitfield name="ROP_CODE" low="8" high="11" type="uint"/>
1421
		<bitfield name="DITHER_MODE" low="12" high="13" type="adreno_rb_dither_mode"/>
1422
		<bitfield name="DITHER_TYPE" low="14" high="15" type="a2xx_rb_dither_type"/>
1423
		<bitfield name="PIXEL_FOG" pos="16" type="boolean"/>
1424
		<bitfield name="ALPHA_TO_MASK_OFFSET0" low="24" high="25" type="uint"/>
1425
		<bitfield name="ALPHA_TO_MASK_OFFSET1" low="26" high="27" type="uint"/>
1426
		<bitfield name="ALPHA_TO_MASK_OFFSET2" low="28" high="29" type="uint"/>
1427
		<bitfield name="ALPHA_TO_MASK_OFFSET3" low="30" high="31" type="uint"/>
1428
	</reg32>
1429
	<reg32 offset="0x2203" name="VGT_CURRENT_BIN_ID_MAX" type="a2xx_vgt_current_bin_id_min_max"/>
1430
	<reg32 offset="0x2204" name="PA_CL_CLIP_CNTL">
1431
		<bitfield name="CLIP_DISABLE" pos="16" type="boolean"/>
1432
		<bitfield name="BOUNDARY_EDGE_FLAG_ENA" pos="18" type="boolean"/>
1433
		<bitfield name="DX_CLIP_SPACE_DEF" pos="19" type="a2xx_dx_clip_space"/>
1434
		<bitfield name="DIS_CLIP_ERR_DETECT" pos="20" type="boolean"/>
1435
		<bitfield name="VTX_KILL_OR" pos="21" type="boolean"/>
1436
		<bitfield name="XY_NAN_RETAIN" pos="22" type="boolean"/>
1437
		<bitfield name="Z_NAN_RETAIN" pos="23" type="boolean"/>
1438
		<bitfield name="W_NAN_RETAIN" pos="24" type="boolean"/>
1439
	</reg32>
1440
	<reg32 offset="0x2205" name="PA_SU_SC_MODE_CNTL">
1441
		<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1442
		<bitfield name="CULL_BACK" pos="1" type="boolean"/>
1443
		<bitfield name="FACE" pos="2" type="boolean"/>
1444
		<bitfield name="POLYMODE" low="3" high="4" type="a2xx_pa_su_sc_polymode"/>
1445
		<bitfield name="FRONT_PTYPE" low="5" high="7" type="adreno_pa_su_sc_draw"/>
1446
		<bitfield name="BACK_PTYPE" low="8" high="10" type="adreno_pa_su_sc_draw"/>
1447
		<bitfield name="POLY_OFFSET_FRONT_ENABLE" pos="11" type="boolean"/>
1448
		<bitfield name="POLY_OFFSET_BACK_ENABLE" pos="12" type="boolean"/>
1449
		<bitfield name="POLY_OFFSET_PARA_ENABLE" pos="13" type="boolean"/>
1450
		<bitfield name="MSAA_ENABLE" pos="15" type="boolean"/>
1451
		<bitfield name="VTX_WINDOW_OFFSET_ENABLE" pos="16" type="boolean"/>
1452
		<bitfield name="LINE_STIPPLE_ENABLE" pos="18" type="boolean"/>
1453
		<bitfield name="PROVOKING_VTX_LAST" pos="19" type="boolean"/>
1454
		<bitfield name="PERSP_CORR_DIS" pos="20" type="boolean"/>
1455
		<bitfield name="MULTI_PRIM_IB_ENA" pos="21" type="boolean"/>
1456
		<bitfield name="QUAD_ORDER_ENABLE" pos="23" type="boolean"/>
1457
		<bitfield name="WAIT_RB_IDLE_ALL_TRI" pos="25" type="boolean"/>
1458
		<bitfield name="WAIT_RB_IDLE_FIRST_TRI_NEW_STATE" pos="26" type="boolean"/>
1459
		<bitfield name="CLAMPED_FACENESS" pos="28" type="boolean"/>
1460
		<bitfield name="ZERO_AREA_FACENESS" pos="29" type="boolean"/>
1461
		<bitfield name="FACE_KILL_ENABLE" pos="30" type="boolean"/>
1462
		<bitfield name="FACE_WRITE_ENABLE" pos="31" type="boolean"/>
1463
	</reg32>
1464
	<reg32 offset="0x2206" name="PA_CL_VTE_CNTL">
1465
		<bitfield name="VPORT_X_SCALE_ENA" pos="0" type="boolean"/>
1466
		<bitfield name="VPORT_X_OFFSET_ENA" pos="1" type="boolean"/>
1467
		<bitfield name="VPORT_Y_SCALE_ENA" pos="2" type="boolean"/>
1468
		<bitfield name="VPORT_Y_OFFSET_ENA" pos="3" type="boolean"/>
1469
		<bitfield name="VPORT_Z_SCALE_ENA" pos="4" type="boolean"/>
1470
		<bitfield name="VPORT_Z_OFFSET_ENA" pos="5" type="boolean"/>
1471
		<bitfield name="VTX_XY_FMT" pos="8" type="boolean"/>
1472
		<bitfield name="VTX_Z_FMT" pos="9" type="boolean"/>
1473
		<bitfield name="VTX_W0_FMT" pos="10" type="boolean"/>
1474
		<bitfield name="PERFCOUNTER_REF" pos="11" type="boolean"/>
1475
	</reg32>
1476
	<reg32 offset="0x2207" name="VGT_CURRENT_BIN_ID_MIN" type="a2xx_vgt_current_bin_id_min_max"/>
1477
	<reg32 offset="0x2208" name="RB_MODECONTROL">
1478
		<bitfield name="EDRAM_MODE" low="0" high="2" type="a2xx_rb_edram_mode"/>
1479
	</reg32>
1480
	<reg32 offset="0x2209" name="A220_RB_LRZ_VSC_CONTROL"/>
1481
	<reg32 offset="0x220a" name="RB_SAMPLE_POS"/>
1482
	<reg32 offset="0x220b" name="CLEAR_COLOR">
1483
		<bitfield name="RED" low="0" high="7"/>
1484
		<bitfield name="GREEN" low="8" high="15"/>
1485
		<bitfield name="BLUE" low="16" high="23"/>
1486
		<bitfield name="ALPHA" low="24" high="31"/>
1487
	</reg32>
1488
	<reg32 offset="0x2210" name="A220_GRAS_CONTROL"/>
1489
	<reg32 offset="0x2280" name="PA_SU_POINT_SIZE">
1490
		<bitfield name="HEIGHT" low="0" high="15" type="ufixed" radix="4"/>
1491
		<bitfield name="WIDTH" low="16" high="31" type="ufixed" radix="4"/>
1492
	</reg32>
1493
	<reg32 offset="0x2281" name="PA_SU_POINT_MINMAX">
1494
		<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1495
		<bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1496
	</reg32>
1497
	<reg32 offset="0x2282" name="PA_SU_LINE_CNTL">
1498
		<bitfield name="WIDTH" low="0" high="15" type="ufixed" radix="4"/>
1499
	</reg32>
1500
	<reg32 offset="0x2283" name="PA_SC_LINE_STIPPLE">
1501
		<bitfield name="LINE_PATTERN" low="0" high="15" type="hex"/>
1502
		<bitfield name="REPEAT_COUNT" low="16" high="23" type="uint"/>
1503
		<bitfield name="PATTERN_BIT_ORDER" pos="28" type="a2xx_pa_sc_pattern_bit_order"/>
1504
		<bitfield name="AUTO_RESET_CNTL" low="29" high="30" type="a2xx_pa_sc_auto_reset_cntl"/>
1505
	</reg32>
1506
	<reg32 offset="0x2293" name="PA_SC_VIZ_QUERY">
1507
		<bitfield name="VIZ_QUERY_ENA" pos="0" type="boolean"/>
1508
		<bitfield name="VIZ_QUERY_ID" low="1" high="6" type="uint"/>
1509
		<bitfield name="KILL_PIX_POST_EARLY_Z" pos="8" type="boolean"/>
1510
	</reg32>
1511
	<reg32 offset="0x2294" name="VGT_ENHANCE"/>
1512
	<reg32 offset="0x2300" name="PA_SC_LINE_CNTL">
1513
		<bitfield name="BRES_CNTL" low="0" high="15" type="uint"/>
1514
		<bitfield name="USE_BRES_CNTL" pos="8" type="boolean"/>
1515
		<bitfield name="EXPAND_LINE_WIDTH" pos="9" type="boolean"/>
1516
		<bitfield name="LAST_PIXEL" pos="10" type="boolean"/>
1517
	</reg32>
1518
	<reg32 offset="0x2301" name="PA_SC_AA_CONFIG">
1519
		<bitfield name="MSAA_NUM_SAMPLES" low="0" high="2" type="uint"/>
1520
		<bitfield name="MAX_SAMPLE_DIST" low="13" high="16" type="uint"/>
1521
	</reg32>
1522
	<reg32 offset="0x2302" name="PA_SU_VTX_CNTL">
1523
		<bitfield name="PIX_CENTER" pos="0" type="a2xx_pa_pixcenter"/>
1524
		<bitfield name="ROUND_MODE" low="1" high="2" type="a2xx_pa_roundmode"/>
1525
		<bitfield name="QUANT_MODE" low="7" high="9" type="a2xx_pa_quantmode"/>
1526
	</reg32>
1527
	<reg32 offset="0x2303" name="PA_CL_GB_VERT_CLIP_ADJ" type="float"/>
1528
	<reg32 offset="0x2304" name="PA_CL_GB_VERT_DISC_ADJ" type="float"/>
1529
	<reg32 offset="0x2305" name="PA_CL_GB_HORZ_CLIP_ADJ" type="float"/>
1530
	<reg32 offset="0x2306" name="PA_CL_GB_HORZ_DISC_ADJ" type="float"/>
1531
	<reg32 offset="0x2307" name="SQ_VS_CONST">
1532
		<bitfield name="BASE" low="0" high="8" type="uint"/>
1533
		<bitfield name="SIZE" low="12" high="20" type="uint"/>
1534
	</reg32>
1535
	<reg32 offset="0x2308" name="SQ_PS_CONST">
1536
		<bitfield name="BASE" low="0" high="8" type="uint"/>
1537
		<bitfield name="SIZE" low="12" high="20" type="uint"/>
1538
	</reg32>
1539
	<reg32 offset="0x2309" name="SQ_DEBUG_MISC_0"/>
1540
	<reg32 offset="0x230a" name="SQ_DEBUG_MISC_1"/>
1541
	<reg32 offset="0x2312" name="PA_SC_AA_MASK"/>
1542
	<reg32 offset="0x2316" name="VGT_VERTEX_REUSE_BLOCK_CNTL">
1543
		<bitfield name="VTX_REUSE_DEPTH" low="0" high="2" type="uint"/>
1544
	</reg32>
1545
	<reg32 offset="0x2317" name="VGT_OUT_DEALLOC_CNTL">
1546
		<bitfield name="DEALLOC_DIST" low="0" high="1" type="uint"/>
1547
	</reg32>
1548
	<reg32 offset="0x2318" name="RB_COPY_CONTROL">
1549
		<bitfield name="COPY_SAMPLE_SELECT" low="0" high="2" type="a2xx_rb_copy_sample_select"/>
1550
		<bitfield name="DEPTH_CLEAR_ENABLE" pos="3" type="boolean"/>
1551
		<bitfield name="CLEAR_MASK" low="4" high="7" type="hex"/>
1552
	</reg32>
1553
	<reg32 offset="0x2319" name="RB_COPY_DEST_BASE"/>
1554
	<reg32 offset="0x231a" name="RB_COPY_DEST_PITCH" shr="5" type="uint"/>
1555
	<reg32 offset="0x231b" name="RB_COPY_DEST_INFO">
1556
		<bitfield name="DEST_ENDIAN" low="0" high="2" type="adreno_rb_surface_endian"/>
1557
		<bitfield name="LINEAR" pos="3" type="boolean"/>
1558
		<bitfield name="FORMAT" low="4" high="7" type="a2xx_colorformatx"/>
1559
		<bitfield name="SWAP" low="8" high="9" type="uint"/>
1560
		<bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
1561
		<bitfield name="DITHER_TYPE" low="12" high="13" type="a2xx_rb_dither_type"/>
1562
		<bitfield name="WRITE_RED" pos="14" type="boolean"/>
1563
		<bitfield name="WRITE_GREEN" pos="15" type="boolean"/>
1564
		<bitfield name="WRITE_BLUE" pos="16" type="boolean"/>
1565
		<bitfield name="WRITE_ALPHA" pos="17" type="boolean"/>
1566
	</reg32>
1567
	<reg32 offset="0x231c" name="RB_COPY_DEST_OFFSET">
1568
		<bitfield name="X" low="0" high="12" type="uint"/>
1569
		<bitfield name="Y" low="13" high="25" type="uint"/>
1570
	</reg32>
1571
	<reg32 offset="0x231d" name="RB_DEPTH_CLEAR"/>
1572
	<reg32 offset="0x2324" name="RB_SAMPLE_COUNT_CTL"/>
1573
	<reg32 offset="0x2326" name="RB_COLOR_DEST_MASK"/>
1574
	<reg32 offset="0x2340" name="A225_GRAS_UCP0X"/>
1575
	<reg32 offset="0x2357" name="A225_GRAS_UCP5W"/>
1576
	<reg32 offset="0x2360" name="A225_GRAS_UCP_ENABLED"/>
1577
	<reg32 offset="0x2380" name="PA_SU_POLY_OFFSET_FRONT_SCALE"/>
1578
	<reg32 offset="0x2381" name="PA_SU_POLY_OFFSET_FRONT_OFFSET"/>
1579
	<reg32 offset="0x2382" name="PA_SU_POLY_OFFSET_BACK_SCALE"/>
1580
	<reg32 offset="0x2383" name="PA_SU_POLY_OFFSET_BACK_OFFSET"/>
1581
	<reg32 offset="0x4000" name="SQ_CONSTANT_0"/>
1582
	<reg32 offset="0x4800" name="SQ_FETCH_0"/>
1583
	<reg32 offset="0x4900" name="SQ_CF_BOOLEANS"/>
1584
	<reg32 offset="0x4908" name="SQ_CF_LOOP"/>
1585
	<reg32 offset="0xa29" name="COHER_SIZE_PM4"/>
1586
	<reg32 offset="0xa2a" name="COHER_BASE_PM4"/>
1587
	<reg32 offset="0xa2b" name="COHER_STATUS_PM4"/>
1588

1589
	<reg32 offset="0x0c88" name="PA_SU_PERFCOUNTER0_SELECT"/>
1590
	<reg32 offset="0x0c89" name="PA_SU_PERFCOUNTER1_SELECT"/>
1591
	<reg32 offset="0x0c8a" name="PA_SU_PERFCOUNTER2_SELECT"/>
1592
	<reg32 offset="0x0c8b" name="PA_SU_PERFCOUNTER3_SELECT"/>
1593
	<reg32 offset="0x0c8c" name="PA_SU_PERFCOUNTER0_LOW"/>
1594
	<reg32 offset="0x0c8d" name="PA_SU_PERFCOUNTER0_HI"/>
1595
	<reg32 offset="0x0c8e" name="PA_SU_PERFCOUNTER1_LOW"/>
1596
	<reg32 offset="0x0c8f" name="PA_SU_PERFCOUNTER1_HI"/>
1597
	<reg32 offset="0x0c90" name="PA_SU_PERFCOUNTER2_LOW"/>
1598
	<reg32 offset="0x0c91" name="PA_SU_PERFCOUNTER2_HI"/>
1599
	<reg32 offset="0x0c92" name="PA_SU_PERFCOUNTER3_LOW"/>
1600
	<reg32 offset="0x0c93" name="PA_SU_PERFCOUNTER3_HI"/>
1601
	<reg32 offset="0x0c98" name="PA_SC_PERFCOUNTER0_SELECT"/>
1602
	<reg32 offset="0x0c99" name="PA_SC_PERFCOUNTER0_LOW"/>
1603
	<reg32 offset="0x0c9a" name="PA_SC_PERFCOUNTER0_HI"/>
1604
	<reg32 offset="0x0c48" name="VGT_PERFCOUNTER0_SELECT"/>
1605
	<reg32 offset="0x0c49" name="VGT_PERFCOUNTER1_SELECT"/>
1606
	<reg32 offset="0x0c4a" name="VGT_PERFCOUNTER2_SELECT"/>
1607
	<reg32 offset="0x0c4b" name="VGT_PERFCOUNTER3_SELECT"/>
1608
	<reg32 offset="0x0c4c" name="VGT_PERFCOUNTER0_LOW"/>
1609
	<reg32 offset="0x0c4e" name="VGT_PERFCOUNTER1_LOW"/>
1610
	<reg32 offset="0x0c50" name="VGT_PERFCOUNTER2_LOW"/>
1611
	<reg32 offset="0x0c52" name="VGT_PERFCOUNTER3_LOW"/>
1612
	<reg32 offset="0x0c4d" name="VGT_PERFCOUNTER0_HI"/>
1613
	<reg32 offset="0x0c4f" name="VGT_PERFCOUNTER1_HI"/>
1614
	<reg32 offset="0x0c51" name="VGT_PERFCOUNTER2_HI"/>
1615
	<reg32 offset="0x0c53" name="VGT_PERFCOUNTER3_HI"/>
1616
	<reg32 offset="0x0e05" name="TCR_PERFCOUNTER0_SELECT"/>
1617
	<reg32 offset="0x0e08" name="TCR_PERFCOUNTER1_SELECT"/>
1618
	<reg32 offset="0x0e06" name="TCR_PERFCOUNTER0_HI"/>
1619
	<reg32 offset="0x0e09" name="TCR_PERFCOUNTER1_HI"/>
1620
	<reg32 offset="0x0e07" name="TCR_PERFCOUNTER0_LOW"/>
1621
	<reg32 offset="0x0e0a" name="TCR_PERFCOUNTER1_LOW"/>
1622
	<reg32 offset="0x0e1f" name="TP0_PERFCOUNTER0_SELECT"/>
1623
	<reg32 offset="0x0e20" name="TP0_PERFCOUNTER0_HI"/>
1624
	<reg32 offset="0x0e21" name="TP0_PERFCOUNTER0_LOW"/>
1625
	<reg32 offset="0x0e22" name="TP0_PERFCOUNTER1_SELECT"/>
1626
	<reg32 offset="0x0e23" name="TP0_PERFCOUNTER1_HI"/>
1627
	<reg32 offset="0x0e24" name="TP0_PERFCOUNTER1_LOW"/>
1628
	<reg32 offset="0x0e54" name="TCM_PERFCOUNTER0_SELECT"/>
1629
	<reg32 offset="0x0e57" name="TCM_PERFCOUNTER1_SELECT"/>
1630
	<reg32 offset="0x0e55" name="TCM_PERFCOUNTER0_HI"/>
1631
	<reg32 offset="0x0e58" name="TCM_PERFCOUNTER1_HI"/>
1632
	<reg32 offset="0x0e56" name="TCM_PERFCOUNTER0_LOW"/>
1633
	<reg32 offset="0x0e59" name="TCM_PERFCOUNTER1_LOW"/>
1634
	<reg32 offset="0x0e5a" name="TCF_PERFCOUNTER0_SELECT"/>
1635
	<reg32 offset="0x0e5d" name="TCF_PERFCOUNTER1_SELECT"/>
1636
	<reg32 offset="0x0e60" name="TCF_PERFCOUNTER2_SELECT"/>
1637
	<reg32 offset="0x0e63" name="TCF_PERFCOUNTER3_SELECT"/>
1638
	<reg32 offset="0x0e66" name="TCF_PERFCOUNTER4_SELECT"/>
1639
	<reg32 offset="0x0e69" name="TCF_PERFCOUNTER5_SELECT"/>
1640
	<reg32 offset="0x0e6c" name="TCF_PERFCOUNTER6_SELECT"/>
1641
	<reg32 offset="0x0e6f" name="TCF_PERFCOUNTER7_SELECT"/>
1642
	<reg32 offset="0x0e72" name="TCF_PERFCOUNTER8_SELECT"/>
1643
	<reg32 offset="0x0e75" name="TCF_PERFCOUNTER9_SELECT"/>
1644
	<reg32 offset="0x0e78" name="TCF_PERFCOUNTER10_SELECT"/>
1645
	<reg32 offset="0x0e7b" name="TCF_PERFCOUNTER11_SELECT"/>
1646
	<reg32 offset="0x0e5b" name="TCF_PERFCOUNTER0_HI"/>
1647
	<reg32 offset="0x0e5e" name="TCF_PERFCOUNTER1_HI"/>
1648
	<reg32 offset="0x0e61" name="TCF_PERFCOUNTER2_HI"/>
1649
	<reg32 offset="0x0e64" name="TCF_PERFCOUNTER3_HI"/>
1650
	<reg32 offset="0x0e67" name="TCF_PERFCOUNTER4_HI"/>
1651
	<reg32 offset="0x0e6a" name="TCF_PERFCOUNTER5_HI"/>
1652
	<reg32 offset="0x0e6d" name="TCF_PERFCOUNTER6_HI"/>
1653
	<reg32 offset="0x0e70" name="TCF_PERFCOUNTER7_HI"/>
1654
	<reg32 offset="0x0e73" name="TCF_PERFCOUNTER8_HI"/>
1655
	<reg32 offset="0x0e76" name="TCF_PERFCOUNTER9_HI"/>
1656
	<reg32 offset="0x0e79" name="TCF_PERFCOUNTER10_HI"/>
1657
	<reg32 offset="0x0e7c" name="TCF_PERFCOUNTER11_HI"/>
1658
	<reg32 offset="0x0e5c" name="TCF_PERFCOUNTER0_LOW"/>
1659
	<reg32 offset="0x0e5f" name="TCF_PERFCOUNTER1_LOW"/>
1660
	<reg32 offset="0x0e62" name="TCF_PERFCOUNTER2_LOW"/>
1661
	<reg32 offset="0x0e65" name="TCF_PERFCOUNTER3_LOW"/>
1662
	<reg32 offset="0x0e68" name="TCF_PERFCOUNTER4_LOW"/>
1663
	<reg32 offset="0x0e6b" name="TCF_PERFCOUNTER5_LOW"/>
1664
	<reg32 offset="0x0e6e" name="TCF_PERFCOUNTER6_LOW"/>
1665
	<reg32 offset="0x0e71" name="TCF_PERFCOUNTER7_LOW"/>
1666
	<reg32 offset="0x0e74" name="TCF_PERFCOUNTER8_LOW"/>
1667
	<reg32 offset="0x0e77" name="TCF_PERFCOUNTER9_LOW"/>
1668
	<reg32 offset="0x0e7a" name="TCF_PERFCOUNTER10_LOW"/>
1669
	<reg32 offset="0x0e7d" name="TCF_PERFCOUNTER11_LOW"/>
1670
	<reg32 offset="0x0dc8" name="SQ_PERFCOUNTER0_SELECT"/>
1671
	<reg32 offset="0x0dc9" name="SQ_PERFCOUNTER1_SELECT"/>
1672
	<reg32 offset="0x0dca" name="SQ_PERFCOUNTER2_SELECT"/>
1673
	<reg32 offset="0x0dcb" name="SQ_PERFCOUNTER3_SELECT"/>
1674
	<reg32 offset="0x0dcc" name="SQ_PERFCOUNTER0_LOW"/>
1675
	<reg32 offset="0x0dcd" name="SQ_PERFCOUNTER0_HI"/>
1676
	<reg32 offset="0x0dce" name="SQ_PERFCOUNTER1_LOW"/>
1677
	<reg32 offset="0x0dcf" name="SQ_PERFCOUNTER1_HI"/>
1678
	<reg32 offset="0x0dd0" name="SQ_PERFCOUNTER2_LOW"/>
1679
	<reg32 offset="0x0dd1" name="SQ_PERFCOUNTER2_HI"/>
1680
	<reg32 offset="0x0dd2" name="SQ_PERFCOUNTER3_LOW"/>
1681
	<reg32 offset="0x0dd3" name="SQ_PERFCOUNTER3_HI"/>
1682
	<reg32 offset="0x0dd4" name="SX_PERFCOUNTER0_SELECT"/>
1683
	<reg32 offset="0x0dd8" name="SX_PERFCOUNTER0_LOW"/>
1684
	<reg32 offset="0x0dd9" name="SX_PERFCOUNTER0_HI"/>
1685
	<reg32 offset="0x0a46" name="MH_PERFCOUNTER0_SELECT"/>
1686
	<reg32 offset="0x0a4a" name="MH_PERFCOUNTER1_SELECT"/>
1687
	<reg32 offset="0x0a47" name="MH_PERFCOUNTER0_CONFIG"/>
1688
	<reg32 offset="0x0a4b" name="MH_PERFCOUNTER1_CONFIG"/>
1689
	<reg32 offset="0x0a48" name="MH_PERFCOUNTER0_LOW"/>
1690
	<reg32 offset="0x0a4c" name="MH_PERFCOUNTER1_LOW"/>
1691
	<reg32 offset="0x0a49" name="MH_PERFCOUNTER0_HI"/>
1692
	<reg32 offset="0x0a4d" name="MH_PERFCOUNTER1_HI"/>
1693
	<reg32 offset="0x0f04" name="RB_PERFCOUNTER0_SELECT"/>
1694
	<reg32 offset="0x0f05" name="RB_PERFCOUNTER1_SELECT"/>
1695
	<reg32 offset="0x0f06" name="RB_PERFCOUNTER2_SELECT"/>
1696
	<reg32 offset="0x0f07" name="RB_PERFCOUNTER3_SELECT"/>
1697
	<reg32 offset="0x0f08" name="RB_PERFCOUNTER0_LOW"/>
1698
	<reg32 offset="0x0f09" name="RB_PERFCOUNTER0_HI"/>
1699
	<reg32 offset="0x0f0a" name="RB_PERFCOUNTER1_LOW"/>
1700
	<reg32 offset="0x0f0b" name="RB_PERFCOUNTER1_HI"/>
1701
	<reg32 offset="0x0f0c" name="RB_PERFCOUNTER2_LOW"/>
1702
	<reg32 offset="0x0f0d" name="RB_PERFCOUNTER2_HI"/>
1703
	<reg32 offset="0x0f0e" name="RB_PERFCOUNTER3_LOW"/>
1704
	<reg32 offset="0x0f0f" name="RB_PERFCOUNTER3_HI"/>
1705
</domain>
1706

1707
<domain name="A2XX_SQ_TEX" width="32">
1708
	<doc>Texture state dwords</doc>
1709
	<enum name="sq_tex_clamp">
1710
		<value name="SQ_TEX_WRAP" value="0"/>
1711
		<value name="SQ_TEX_MIRROR" value="1"/>
1712
		<value name="SQ_TEX_CLAMP_LAST_TEXEL" value="2"/>
1713
		<value name="SQ_TEX_MIRROR_ONCE_LAST_TEXEL" value="3"/>
1714
		<value name="SQ_TEX_CLAMP_HALF_BORDER" value="4"/>
1715
		<value name="SQ_TEX_MIRROR_ONCE_HALF_BORDER" value="5"/>
1716
		<value name="SQ_TEX_CLAMP_BORDER" value="6"/>
1717
		<value name="SQ_TEX_MIRROR_ONCE_BORDER" value="7"/>
1718
	</enum>
1719
	<enum name="sq_tex_swiz">
1720
		<value name="SQ_TEX_X" value="0"/>
1721
		<value name="SQ_TEX_Y" value="1"/>
1722
		<value name="SQ_TEX_Z" value="2"/>
1723
		<value name="SQ_TEX_W" value="3"/>
1724
		<value name="SQ_TEX_ZERO" value="4"/>
1725
		<value name="SQ_TEX_ONE" value="5"/>
1726
	</enum>
1727
	<enum name="sq_tex_filter">
1728
		<value name="SQ_TEX_FILTER_POINT" value="0"/>
1729
		<value name="SQ_TEX_FILTER_BILINEAR" value="1"/>
1730
		<value name="SQ_TEX_FILTER_BASEMAP" value="2"/>
1731
		<value name="SQ_TEX_FILTER_USE_FETCH_CONST" value="3"/>
1732
	</enum>
1733
	<enum name="sq_tex_aniso_filter">
1734
		<value name="SQ_TEX_ANISO_FILTER_DISABLED" value="0"/>
1735
		<value name="SQ_TEX_ANISO_FILTER_MAX_1_1" value="1"/>
1736
		<value name="SQ_TEX_ANISO_FILTER_MAX_2_1" value="2"/>
1737
		<value name="SQ_TEX_ANISO_FILTER_MAX_4_1" value="3"/>
1738
		<value name="SQ_TEX_ANISO_FILTER_MAX_8_1" value="4"/>
1739
		<value name="SQ_TEX_ANISO_FILTER_MAX_16_1" value="5"/>
1740
		<value name="SQ_TEX_ANISO_FILTER_USE_FETCH_CONST" value="7"/>
1741
	</enum>
1742
	<enum name="sq_tex_dimension">
1743
		<value name="SQ_TEX_DIMENSION_1D" value="0"/>
1744
		<value name="SQ_TEX_DIMENSION_2D" value="1"/>
1745
		<value name="SQ_TEX_DIMENSION_3D" value="2"/>
1746
		<value name="SQ_TEX_DIMENSION_CUBE" value="3"/>
1747
	</enum>
1748
	<enum name="sq_tex_border_color">
1749
		<value name="SQ_TEX_BORDER_COLOR_BLACK" value="0"/>
1750
		<value name="SQ_TEX_BORDER_COLOR_WHITE" value="1"/>
1751
		<value name="SQ_TEX_BORDER_COLOR_ACBYCR_BLACK" value="2"/>
1752
		<value name="SQ_TEX_BORDER_COLOR_ACBCRY_BLACK" value="3"/>
1753
	</enum>
1754
	<enum name="sq_tex_sign">
1755
		<value name="SQ_TEX_SIGN_UNSIGNED" value="0"/>
1756
		<value name="SQ_TEX_SIGN_SIGNED" value="1"/>
1757
		<!-- biased: 2*color-1 (range -1,1 when sampling) -->
1758
		<value name="SQ_TEX_SIGN_UNSIGNED_BIASED" value="2"/>
1759
		<!-- gamma: sRGB to linear - doesn't seem to work on adreno? -->
1760
		<value name="SQ_TEX_SIGN_GAMMA" value="3"/>
1761
	</enum>
1762
	<enum name="sq_tex_endian">
1763
		<value name="SQ_TEX_ENDIAN_NONE" value="0"/>
1764
		<value name="SQ_TEX_ENDIAN_8IN16" value="1"/>
1765
		<value name="SQ_TEX_ENDIAN_8IN32" value="2"/>
1766
		<value name="SQ_TEX_ENDIAN_16IN32" value="3"/>
1767
	</enum>
1768
	<enum name="sq_tex_clamp_policy">
1769
		<value name="SQ_TEX_CLAMP_POLICY_D3D" value="0"/>
1770
		<value name="SQ_TEX_CLAMP_POLICY_OGL" value="1"/>
1771
	</enum>
1772
	<enum name="sq_tex_num_format">
1773
		<value name="SQ_TEX_NUM_FORMAT_FRAC" value="0"/>
1774
		<value name="SQ_TEX_NUM_FORMAT_INT" value="1"/>
1775
	</enum>
1776
	<enum name="sq_tex_type">
1777
		<value name="SQ_TEX_TYPE_0" value="0"/>
1778
		<value name="SQ_TEX_TYPE_1" value="1"/>
1779
		<value name="SQ_TEX_TYPE_2" value="2"/>
1780
		<value name="SQ_TEX_TYPE_3" value="3"/>
1781
	</enum>
1782
	<reg32 offset="0" name="0">
1783
		<bitfield name="TYPE" low="0" high="1" type="sq_tex_type"/>
1784
		<bitfield name="SIGN_X" low="2" high="3" type="sq_tex_sign"/>
1785
		<bitfield name="SIGN_Y" low="4" high="5" type="sq_tex_sign"/>
1786
		<bitfield name="SIGN_Z" low="6" high="7" type="sq_tex_sign"/>
1787
		<bitfield name="SIGN_W" low="8" high="9" type="sq_tex_sign"/>
1788
		<bitfield name="CLAMP_X" low="10" high="12" type="sq_tex_clamp"/>
1789
		<bitfield name="CLAMP_Y" low="13" high="15" type="sq_tex_clamp"/>
1790
		<bitfield name="CLAMP_Z" low="16" high="18" type="sq_tex_clamp"/>
1791
		<bitfield name="PITCH" low="22" high="30" shr="5" type="uint"/>
1792
		<bitfield name="TILED" pos="31" type="boolean"/>
1793
	</reg32>
1794
	<reg32 offset="1" name="1">
1795
		<bitfield name="FORMAT" low="0" high="5" type="a2xx_sq_surfaceformat"/>
1796
		<bitfield name="ENDIANNESS" low="6" high="7" type="sq_tex_endian"/>
1797
		<bitfield name="REQUEST_SIZE" low="8" high="9" type="uint"/>
1798
		<bitfield name="STACKED" pos="10" type="boolean"/>
1799
		<bitfield name="CLAMP_POLICY" pos="11" type="sq_tex_clamp_policy"/>
1800
		<bitfield name="BASE_ADDRESS" low="12" high="31" type="uint" shr="12"/>
1801
	</reg32>
1802
	<reg32 offset="2" name="2">
1803
		<bitfield name="WIDTH" low="0" high="12" type="uint"/>
1804
		<bitfield name="HEIGHT" low="13" high="25" type="uint"/>
1805
		<bitfield name="DEPTH" low="26" high="31" type="uint"/>
1806
		<!-- 1d/3d have different bit configurations -->
1807
	</reg32>
1808
	<reg32 offset="3" name="3">
1809
		<bitfield name="NUM_FORMAT" pos="0" type="sq_tex_num_format"/>
1810
		<bitfield name="SWIZ_X" low="1" high="3" type="sq_tex_swiz"/>
1811
		<bitfield name="SWIZ_Y" low="4" high="6" type="sq_tex_swiz"/>
1812
		<bitfield name="SWIZ_Z" low="7" high="9" type="sq_tex_swiz"/>
1813
		<bitfield name="SWIZ_W" low="10" high="12" type="sq_tex_swiz"/>
1814
		<bitfield name="EXP_ADJUST" low="13" high="18" type="int"/>
1815
		<bitfield name="XY_MAG_FILTER" low="19" high="20" type="sq_tex_filter"/>
1816
		<bitfield name="XY_MIN_FILTER" low="21" high="22" type="sq_tex_filter"/>
1817
		<bitfield name="MIP_FILTER" low="23" high="24" type="sq_tex_filter"/>
1818
		<bitfield name="ANISO_FILTER" low="25" high="27" type="sq_tex_aniso_filter"/>
1819
		<bitfield name="BORDER_SIZE" pos="31" type="uint"/>
1820
	</reg32>
1821
	<reg32 offset="4" name="4">
1822
		<bitfield name="VOL_MAG_FILTER" pos="0" type="sq_tex_filter"/>
1823
		<bitfield name="VOL_MIN_FILTER" pos="1" type="sq_tex_filter"/>
1824
		<bitfield name="MIP_MIN_LEVEL" low="2" high="5" type="uint"/>
1825
		<bitfield name="MIP_MAX_LEVEL" low="6" high="9" type="uint"/>
1826
		<bitfield name="MAX_ANISO_WALK" pos="10" type="boolean"/>
1827
		<bitfield name="MIN_ANISO_WALK" pos="11" type="boolean"/>
1828
		<bitfield name="LOD_BIAS" low="12" high="21" type="fixed" radix="5"/>
1829
		<bitfield name="GRAD_EXP_ADJUST_H" low="22" high="26" type="uint"/>
1830
		<bitfield name="GRAD_EXP_ADJUST_V" low="27" high="31" type="uint"/>
1831
	</reg32>
1832
	<reg32 offset="5" name="5">
1833
		<bitfield name="BORDER_COLOR" low="0" high="1" type="sq_tex_border_color"/>
1834
		<bitfield name="FORCE_BCW_MAX" pos="2" type="boolean"/>
1835
		<bitfield name="TRI_CLAMP" low="3" high="4" type="uint"/>
1836
		<bitfield name="ANISO_BIAS" low="5" high="8" type="fixed" radix="0"/> <!-- radix unknown -->
1837
		<bitfield name="DIMENSION" low="9" high="10" type="sq_tex_dimension"/>
1838
		<bitfield name="PACKED_MIPS" pos="11" type="boolean"/>
1839
		<bitfield name="MIP_ADDRESS" low="12" high="31" type="uint" shr="12"/>
1840
	</reg32>
1841
</domain>
1842

1843
</database>
1844

1845
Product

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