CoCalc -- a6xx.xml

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/freedreno/registers/adreno/a6xx.xml
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<?xml version="1.0" encoding="UTF-8"?>
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<database xmlns="http://nouveau.freedesktop.org/"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
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<import file="freedreno_copyright.xml"/>
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<import file="adreno/adreno_common.xml"/>
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<import file="adreno/adreno_pm4.xml"/>
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<!-- these might be same as a5xx -->
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<enum name="a6xx_tile_mode">
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	<value name="TILE6_LINEAR" value="0"/>
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	<value name="TILE6_2" value="2"/>
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	<value name="TILE6_3" value="3"/>
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</enum>
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<enum name="a6xx_format">
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	<value value="0x02" name="FMT6_A8_UNORM"/>
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	<value value="0x03" name="FMT6_8_UNORM"/>
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	<value value="0x04" name="FMT6_8_SNORM"/>
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	<value value="0x05" name="FMT6_8_UINT"/>
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	<value value="0x06" name="FMT6_8_SINT"/>
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	<value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
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	<value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
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	<value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
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	<value value="0x0e" name="FMT6_5_6_5_UNORM"/>
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	<value value="0x0f" name="FMT6_8_8_UNORM"/>
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	<value value="0x10" name="FMT6_8_8_SNORM"/>
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	<value value="0x11" name="FMT6_8_8_UINT"/>
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	<value value="0x12" name="FMT6_8_8_SINT"/>
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	<value value="0x13" name="FMT6_L8_A8_UNORM"/>
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	<value value="0x15" name="FMT6_16_UNORM"/>
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	<value value="0x16" name="FMT6_16_SNORM"/>
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	<value value="0x17" name="FMT6_16_FLOAT"/>
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	<value value="0x18" name="FMT6_16_UINT"/>
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	<value value="0x19" name="FMT6_16_SINT"/>
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	<value value="0x21" name="FMT6_8_8_8_UNORM"/>
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	<value value="0x22" name="FMT6_8_8_8_SNORM"/>
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	<value value="0x23" name="FMT6_8_8_8_UINT"/>
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	<value value="0x24" name="FMT6_8_8_8_SINT"/>
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	<value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
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	<value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
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	<value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
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	<value value="0x33" name="FMT6_8_8_8_8_UINT"/>
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	<value value="0x34" name="FMT6_8_8_8_8_SINT"/>
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	<value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
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	<value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
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	<value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
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	<value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
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	<value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
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	<value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
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	<value value="0x42" name="FMT6_11_11_10_FLOAT"/>
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	<value value="0x43" name="FMT6_16_16_UNORM"/>
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	<value value="0x44" name="FMT6_16_16_SNORM"/>
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	<value value="0x45" name="FMT6_16_16_FLOAT"/>
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	<value value="0x46" name="FMT6_16_16_UINT"/>
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	<value value="0x47" name="FMT6_16_16_SINT"/>
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	<value value="0x48" name="FMT6_32_UNORM"/>
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	<value value="0x49" name="FMT6_32_SNORM"/>
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	<value value="0x4a" name="FMT6_32_FLOAT"/>
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	<value value="0x4b" name="FMT6_32_UINT"/>
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	<value value="0x4c" name="FMT6_32_SINT"/>
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	<value value="0x4d" name="FMT6_32_FIXED"/>
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	<value value="0x58" name="FMT6_16_16_16_UNORM"/>
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	<value value="0x59" name="FMT6_16_16_16_SNORM"/>
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	<value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
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	<value value="0x5b" name="FMT6_16_16_16_UINT"/>
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	<value value="0x5c" name="FMT6_16_16_16_SINT"/>
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	<value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
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	<value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
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	<value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
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	<value value="0x63" name="FMT6_16_16_16_16_UINT"/>
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	<value value="0x64" name="FMT6_16_16_16_16_SINT"/>
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	<value value="0x65" name="FMT6_32_32_UNORM"/>
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	<value value="0x66" name="FMT6_32_32_SNORM"/>
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	<value value="0x67" name="FMT6_32_32_FLOAT"/>
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	<value value="0x68" name="FMT6_32_32_UINT"/>
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	<value value="0x69" name="FMT6_32_32_SINT"/>
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	<value value="0x6a" name="FMT6_32_32_FIXED"/>
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	<value value="0x70" name="FMT6_32_32_32_UNORM"/>
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	<value value="0x71" name="FMT6_32_32_32_SNORM"/>
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	<value value="0x72" name="FMT6_32_32_32_UINT"/>
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	<value value="0x73" name="FMT6_32_32_32_SINT"/>
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	<value value="0x74" name="FMT6_32_32_32_FLOAT"/>
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	<value value="0x75" name="FMT6_32_32_32_FIXED"/>
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	<value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
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	<value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
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	<value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
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	<value value="0x83" name="FMT6_32_32_32_32_UINT"/>
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	<value value="0x84" name="FMT6_32_32_32_32_SINT"/>
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	<value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
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	<value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/>
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	<value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/>
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	<value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/>
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	<value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/>
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	<value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
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	<!-- used with the Y plane of FMT6_R8_G8B8_2PLANE_420_UNORM
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	     which has different UBWC compression from regular 8_UNORM format -->
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	<value value="0x94" name="FMT6_8_PLANE_UNORM"/>
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	<value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
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	<value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
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	<value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
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	<value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
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	<value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
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	<value value="0xaf" name="FMT6_ETC1"/>
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	<value value="0xb0" name="FMT6_ETC2_RGB8"/>
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	<value value="0xb1" name="FMT6_ETC2_RGBA8"/>
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	<value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
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	<value value="0xb3" name="FMT6_DXT1"/>
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	<value value="0xb4" name="FMT6_DXT3"/>
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	<value value="0xb5" name="FMT6_DXT5"/>
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	<value value="0xb7" name="FMT6_RGTC1_UNORM"/>
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	<value value="0xb8" name="FMT6_RGTC1_SNORM"/>
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	<value value="0xbb" name="FMT6_RGTC2_UNORM"/>
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	<value value="0xbc" name="FMT6_RGTC2_SNORM"/>
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	<value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
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	<value value="0xbf" name="FMT6_BPTC_FLOAT"/>
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	<value value="0xc0" name="FMT6_BPTC"/>
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	<value value="0xc1" name="FMT6_ASTC_4x4"/>
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	<value value="0xc2" name="FMT6_ASTC_5x4"/>
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	<value value="0xc3" name="FMT6_ASTC_5x5"/>
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	<value value="0xc4" name="FMT6_ASTC_6x5"/>
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	<value value="0xc5" name="FMT6_ASTC_6x6"/>
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	<value value="0xc6" name="FMT6_ASTC_8x5"/>
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	<value value="0xc7" name="FMT6_ASTC_8x6"/>
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	<value value="0xc8" name="FMT6_ASTC_8x8"/>
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	<value value="0xc9" name="FMT6_ASTC_10x5"/>
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	<value value="0xca" name="FMT6_ASTC_10x6"/>
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	<value value="0xcb" name="FMT6_ASTC_10x8"/>
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	<value value="0xcc" name="FMT6_ASTC_10x10"/>
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	<value value="0xcd" name="FMT6_ASTC_12x10"/>
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	<value value="0xce" name="FMT6_ASTC_12x12"/>
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	<!-- for sampling stencil (integer, 2nd channel), not available on a630 -->
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	<value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/>
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	<!-- Not a hw enum, used internally in driver -->
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	<value value="0xff" name="FMT6_NONE"/>
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</enum>
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<!-- probably same as a5xx -->
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<enum name="a6xx_polygon_mode">
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	<value name="POLYMODE6_POINTS" value="1"/>
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	<value name="POLYMODE6_LINES" value="2"/>
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	<value name="POLYMODE6_TRIANGLES" value="3"/>
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</enum>
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<enum name="a6xx_depth_format">
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	<value name="DEPTH6_NONE" value="0"/>
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	<value name="DEPTH6_16" value="1"/>
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	<value name="DEPTH6_24_8" value="2"/>
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	<value name="DEPTH6_32" value="4"/>
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</enum>
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<bitset name="a6x_cp_protect" inline="yes">
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	<bitfield name="BASE_ADDR" low="0" high="17"/>
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	<bitfield name="MASK_LEN" low="18" high="30"/>
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	<bitfield name="READ" pos="31" type="boolean"/>
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</bitset>
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<enum name="a6xx_shader_id">
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	<value value="0x9" name="A6XX_TP0_TMO_DATA"/>
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	<value value="0xa" name="A6XX_TP0_SMO_DATA"/>
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	<value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
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	<value value="0x19" name="A6XX_TP1_TMO_DATA"/>
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	<value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
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	<value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
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	<value value="0x29" name="A6XX_SP_INST_DATA"/>
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	<value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
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	<value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
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	<value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
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	<value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
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	<value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
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	<value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
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	<value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
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	<value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
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	<value value="0x32" name="A6XX_SP_UAV_DATA"/>
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	<value value="0x33" name="A6XX_SP_INST_TAG"/>
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	<value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
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	<value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
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	<value value="0x36" name="A6XX_SP_SMO_TAG"/>
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	<value value="0x37" name="A6XX_SP_STATE_DATA"/>
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	<value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
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	<value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
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	<value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
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	<value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
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	<value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
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	<value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
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	<value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
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	<value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
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	<value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
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	<value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
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	<value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
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	<value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
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	<value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
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	<value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
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	<value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
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	<value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
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	<value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
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	<value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
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	<value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
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	<value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
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	<value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
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	<value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
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</enum>
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<enum name="a6xx_debugbus_id">
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	<value value="0x1" name="A6XX_DBGBUS_CP"/>
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	<value value="0x2" name="A6XX_DBGBUS_RBBM"/>
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	<value value="0x3" name="A6XX_DBGBUS_VBIF"/>
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	<value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
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	<value value="0x5" name="A6XX_DBGBUS_UCHE"/>
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	<value value="0x6" name="A6XX_DBGBUS_DPM"/>
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	<value value="0x7" name="A6XX_DBGBUS_TESS"/>
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	<value value="0x8" name="A6XX_DBGBUS_PC"/>
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	<value value="0x9" name="A6XX_DBGBUS_VFDP"/>
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	<value value="0xa" name="A6XX_DBGBUS_VPC"/>
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	<value value="0xb" name="A6XX_DBGBUS_TSE"/>
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	<value value="0xc" name="A6XX_DBGBUS_RAS"/>
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	<value value="0xd" name="A6XX_DBGBUS_VSC"/>
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	<value value="0xe" name="A6XX_DBGBUS_COM"/>
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	<value value="0x10" name="A6XX_DBGBUS_LRZ"/>
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	<value value="0x11" name="A6XX_DBGBUS_A2D"/>
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	<value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
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	<value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
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	<value value="0x14" name="A6XX_DBGBUS_RBP"/>
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	<value value="0x15" name="A6XX_DBGBUS_DCS"/>
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	<value value="0x16" name="A6XX_DBGBUS_DBGC"/>
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	<value value="0x17" name="A6XX_DBGBUS_CX"/>
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	<value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
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	<value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
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	<value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
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	<value value="0x1d" name="A6XX_DBGBUS_GPC"/>
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	<value value="0x1e" name="A6XX_DBGBUS_LARC"/>
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	<value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
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	<value value="0x20" name="A6XX_DBGBUS_RB_0"/>
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	<value value="0x21" name="A6XX_DBGBUS_RB_1"/>
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	<value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
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	<value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
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	<value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
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	<value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
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	<value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
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	<value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
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	<value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
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	<value value="0x40" name="A6XX_DBGBUS_SP_0"/>
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	<value value="0x41" name="A6XX_DBGBUS_SP_1"/>
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	<value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
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	<value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
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	<value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
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	<value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
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</enum>
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<enum name="a6xx_cp_perfcounter_select">
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	<value value="0" name="PERF_CP_ALWAYS_COUNT"/>
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	<value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
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	<value value="2" name="PERF_CP_BUSY_CYCLES"/>
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	<value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
278
	<value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
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	<value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
280
	<value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
281
	<value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
282
	<value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
283
	<value value="9" name="PERF_CP_MODE_SWITCH"/>
284
	<value value="10" name="PERF_CP_ZPASS_DONE"/>
285
	<value value="11" name="PERF_CP_CONTEXT_DONE"/>
286
	<value value="12" name="PERF_CP_CACHE_FLUSH"/>
287
	<value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
288
	<value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
289
	<value value="15" name="PERF_CP_SQE_IDLE"/>
290
	<value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
291
	<value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
292
	<value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
293
	<value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
294
	<value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
295
	<value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
296
	<value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
297
	<value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
298
	<value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
299
	<value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
300
	<value value="26" name="PERF_CP_SQE_T4_EXEC"/>
301
	<value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
302
	<value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
303
	<value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
304
	<value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
305
	<value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
306
	<value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
307
	<value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
308
	<value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
309
	<value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
310
	<value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
311
	<value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
312
	<value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
313
	<value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
314
	<value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
315
	<value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
316
	<value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
317
	<value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
318
	<value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
319
	<value value="45" name="PERF_CP_PM4_DATA"/>
320
	<value value="46" name="PERF_CP_PM4_HEADERS"/>
321
	<value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
322
	<value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
323
	<value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
324
</enum>
325

326
<enum name="a6xx_rbbm_perfcounter_select">
327
	<value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
328
	<value value="1" name="PERF_RBBM_ALWAYS_ON"/>
329
	<value value="2" name="PERF_RBBM_TSE_BUSY"/>
330
	<value value="3" name="PERF_RBBM_RAS_BUSY"/>
331
	<value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
332
	<value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
333
	<value value="6" name="PERF_RBBM_STATUS_MASKED"/>
334
	<value value="7" name="PERF_RBBM_COM_BUSY"/>
335
	<value value="8" name="PERF_RBBM_DCOM_BUSY"/>
336
	<value value="9" name="PERF_RBBM_VBIF_BUSY"/>
337
	<value value="10" name="PERF_RBBM_VSC_BUSY"/>
338
	<value value="11" name="PERF_RBBM_TESS_BUSY"/>
339
	<value value="12" name="PERF_RBBM_UCHE_BUSY"/>
340
	<value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
341
</enum>
342

343
<enum name="a6xx_pc_perfcounter_select">
344
	<value value="0" name="PERF_PC_BUSY_CYCLES"/>
345
	<value value="1" name="PERF_PC_WORKING_CYCLES"/>
346
	<value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
347
	<value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
348
	<value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
349
	<value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
350
	<value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
351
	<value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
352
	<value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
353
	<value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
354
	<value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
355
	<value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
356
	<value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
357
	<value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
358
	<value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
359
	<value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
360
	<value value="16" name="PERF_PC_INSTANCES"/>
361
	<value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
362
	<value value="18" name="PERF_PC_DEAD_PRIM"/>
363
	<value value="19" name="PERF_PC_LIVE_PRIM"/>
364
	<value value="20" name="PERF_PC_VERTEX_HITS"/>
365
	<value value="21" name="PERF_PC_IA_VERTICES"/>
366
	<value value="22" name="PERF_PC_IA_PRIMITIVES"/>
367
	<value value="23" name="PERF_PC_GS_PRIMITIVES"/>
368
	<value value="24" name="PERF_PC_HS_INVOCATIONS"/>
369
	<value value="25" name="PERF_PC_DS_INVOCATIONS"/>
370
	<value value="26" name="PERF_PC_VS_INVOCATIONS"/>
371
	<value value="27" name="PERF_PC_GS_INVOCATIONS"/>
372
	<value value="28" name="PERF_PC_DS_PRIMITIVES"/>
373
	<value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
374
	<value value="30" name="PERF_PC_3D_DRAWCALLS"/>
375
	<value value="31" name="PERF_PC_2D_DRAWCALLS"/>
376
	<value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
377
	<value value="33" name="PERF_TESS_BUSY_CYCLES"/>
378
	<value value="34" name="PERF_TESS_WORKING_CYCLES"/>
379
	<value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
380
	<value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
381
	<value value="37" name="PERF_PC_TSE_TRANSACTION"/>
382
	<value value="38" name="PERF_PC_TSE_VERTEX"/>
383
	<value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
384
	<value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
385
	<value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
386
</enum>
387

388
<enum name="a6xx_vfd_perfcounter_select">
389
	<value value="0" name="PERF_VFD_BUSY_CYCLES"/>
390
	<value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
391
	<value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
392
	<value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
393
	<value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
394
	<value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
395
	<value value="6" name="PERF_VFD_RBUFFER_FULL"/>
396
	<value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
397
	<value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
398
	<value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
399
	<value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
400
	<value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
401
	<value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
402
	<value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
403
	<value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
404
	<value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
405
	<value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
406
	<value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
407
	<value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
408
	<value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
409
	<value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
410
	<value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
411
	<value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
412
</enum>
413

414
<enum name="a6xx_hlsq_perfcounter_select">
415
	<value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
416
	<value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
417
	<value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
418
	<value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
419
	<value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
420
	<value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
421
	<value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
422
	<value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
423
	<value value="8" name="PERF_HLSQ_QUADS"/>
424
	<value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
425
	<value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
426
	<value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
427
	<value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
428
	<value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
429
	<value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
430
	<value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
431
	<value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
432
	<value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
433
	<value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
434
	<value value="19" name="PERF_HLSQ_PIXELS"/>
435
	<value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
436
</enum>
437

438
<enum name="a6xx_vpc_perfcounter_select">
439
	<value value="0" name="PERF_VPC_BUSY_CYCLES"/>
440
	<value value="1" name="PERF_VPC_WORKING_CYCLES"/>
441
	<value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
442
	<value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
443
	<value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
444
	<value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
445
	<value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
446
	<value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
447
	<value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
448
	<value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
449
	<value value="10" name="PERF_VPC_SP_COMPONENTS"/>
450
	<value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
451
	<value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
452
	<value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
453
	<value value="14" name="PERF_VPC_LM_TRANSACTION"/>
454
	<value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
455
	<value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
456
	<value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
457
	<value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
458
	<value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
459
	<value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
460
	<value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
461
	<value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
462
	<value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
463
	<value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
464
	<value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
465
	<value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
466
	<value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
467
</enum>
468

469
<enum name="a6xx_tse_perfcounter_select">
470
	<value value="0" name="PERF_TSE_BUSY_CYCLES"/>
471
	<value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
472
	<value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
473
	<value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
474
	<value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
475
	<value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
476
	<value value="6" name="PERF_TSE_INPUT_PRIM"/>
477
	<value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
478
	<value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
479
	<value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
480
	<value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
481
	<value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
482
	<value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
483
	<value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
484
	<value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
485
	<value value="15" name="PERF_TSE_CINVOCATION"/>
486
	<value value="16" name="PERF_TSE_CPRIMITIVES"/>
487
	<value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
488
	<value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
489
	<value value="19" name="PERF_TSE_CLIP_PLANES"/>
490
</enum>
491

492
<enum name="a6xx_ras_perfcounter_select">
493
	<value value="0" name="PERF_RAS_BUSY_CYCLES"/>
494
	<value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
495
	<value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
496
	<value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
497
	<value value="4" name="PERF_RAS_SUPER_TILES"/>
498
	<value value="5" name="PERF_RAS_8X4_TILES"/>
499
	<value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
500
	<value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
501
	<value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
502
	<value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
503
	<value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
504
	<value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
505
	<value value="12" name="PERF_RAS_BLOCKS"/>
506
</enum>
507

508
<enum name="a6xx_uche_perfcounter_select">
509
	<value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
510
	<value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
511
	<value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
512
	<value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
513
	<value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
514
	<value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
515
	<value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
516
	<value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
517
	<value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
518
	<value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
519
	<value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
520
	<value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
521
	<value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
522
	<value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
523
	<value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
524
	<value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
525
	<value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
526
	<value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
527
	<value value="18" name="PERF_UCHE_EVICTS"/>
528
	<value value="19" name="PERF_UCHE_BANK_REQ0"/>
529
	<value value="20" name="PERF_UCHE_BANK_REQ1"/>
530
	<value value="21" name="PERF_UCHE_BANK_REQ2"/>
531
	<value value="22" name="PERF_UCHE_BANK_REQ3"/>
532
	<value value="23" name="PERF_UCHE_BANK_REQ4"/>
533
	<value value="24" name="PERF_UCHE_BANK_REQ5"/>
534
	<value value="25" name="PERF_UCHE_BANK_REQ6"/>
535
	<value value="26" name="PERF_UCHE_BANK_REQ7"/>
536
	<value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
537
	<value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
538
	<value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
539
	<value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
540
	<value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
541
	<value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
542
	<value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
543
	<value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
544
	<value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
545
	<value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
546
	<value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
547
	<value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
548
	<value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
549
</enum>
550

551
<enum name="a6xx_tp_perfcounter_select">
552
	<value value="0" name="PERF_TP_BUSY_CYCLES"/>
553
	<value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
554
	<value value="2" name="PERF_TP_LATENCY_CYCLES"/>
555
	<value value="3" name="PERF_TP_LATENCY_TRANS"/>
556
	<value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
557
	<value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
558
	<value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
559
	<value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
560
	<value value="8" name="PERF_TP_SP_TP_TRANS"/>
561
	<value value="9" name="PERF_TP_TP_SP_TRANS"/>
562
	<value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
563
	<value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
564
	<value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
565
	<value value="13" name="PERF_TP_QUADS_RECEIVED"/>
566
	<value value="14" name="PERF_TP_QUADS_OFFSET"/>
567
	<value value="15" name="PERF_TP_QUADS_SHADOW"/>
568
	<value value="16" name="PERF_TP_QUADS_ARRAY"/>
569
	<value value="17" name="PERF_TP_QUADS_GRADIENT"/>
570
	<value value="18" name="PERF_TP_QUADS_1D"/>
571
	<value value="19" name="PERF_TP_QUADS_2D"/>
572
	<value value="20" name="PERF_TP_QUADS_BUFFER"/>
573
	<value value="21" name="PERF_TP_QUADS_3D"/>
574
	<value value="22" name="PERF_TP_QUADS_CUBE"/>
575
	<value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
576
	<value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
577
	<value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
578
	<value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
579
	<value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
580
	<value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
581
	<value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
582
	<value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
583
	<value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
584
	<value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
585
	<value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
586
	<value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
587
	<value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
588
	<value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
589
	<value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
590
	<value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
591
	<value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
592
	<value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
593
	<value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
594
	<value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
595
	<value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
596
	<value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
597
	<value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
598
	<value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
599
	<value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
600
	<value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
601
	<value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
602
	<value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
603
	<value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
604
	<value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
605
	<value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
606
	<value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
607
	<value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
608
	<value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
609
</enum>
610

611
<enum name="a6xx_sp_perfcounter_select">
612
	<value value="0" name="PERF_SP_BUSY_CYCLES"/>
613
	<value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
614
	<value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
615
	<value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
616
	<value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
617
	<value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
618
	<value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
619
	<value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
620
	<value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
621
	<value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
622
	<value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
623
	<value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
624
	<value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
625
	<value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
626
	<value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
627
	<value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
628
	<value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
629
	<value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
630
	<value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
631
	<value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
632
	<value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
633
	<value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
634
	<value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
635
	<value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
636
	<value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
637
	<value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
638
	<value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
639
	<value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
640
	<value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
641
	<value value="29" name="PERF_SP_LM_ATOMICS"/>
642
	<value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
643
	<value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
644
	<value value="32" name="PERF_SP_GM_ATOMICS"/>
645
	<value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
646
	<value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
647
	<value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
648
	<value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
649
	<value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
650
	<value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
651
	<value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
652
	<value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
653
	<value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
654
	<value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
655
	<value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
656
	<value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
657
	<value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
658
	<value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
659
	<value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
660
	<value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
661
	<value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
662
	<value value="50" name="PERF_SP_PIXELS_KILLED"/>
663
	<value value="51" name="PERF_SP_ICL1_REQUESTS"/>
664
	<value value="52" name="PERF_SP_ICL1_MISSES"/>
665
	<value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
666
	<value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
667
	<value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
668
	<value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
669
	<value value="57" name="PERF_SP_GPR_READ"/>
670
	<value value="58" name="PERF_SP_GPR_WRITE"/>
671
	<value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
672
	<value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
673
	<value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
674
	<value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
675
	<value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
676
	<value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
677
	<value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
678
	<value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
679
	<value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
680
	<value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
681
	<value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
682
	<value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
683
	<value value="71" name="PERF_SP_WORKING_EU"/>
684
	<value value="72" name="PERF_SP_ANY_EU_WORKING"/>
685
	<value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
686
	<value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
687
	<value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
688
	<value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
689
	<value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
690
	<value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
691
	<value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
692
	<value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
693
	<value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
694
	<value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
695
	<value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
696
	<value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
697
</enum>
698

699
<enum name="a6xx_rb_perfcounter_select">
700
	<value value="0" name="PERF_RB_BUSY_CYCLES"/>
701
	<value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
702
	<value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
703
	<value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
704
	<value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
705
	<value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
706
	<value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
707
	<value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
708
	<value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
709
	<value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
710
	<value value="10" name="PERF_RB_Z_WORKLOAD"/>
711
	<value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
712
	<value value="12" name="PERF_RB_Z_READ"/>
713
	<value value="13" name="PERF_RB_Z_WRITE"/>
714
	<value value="14" name="PERF_RB_C_READ"/>
715
	<value value="15" name="PERF_RB_C_WRITE"/>
716
	<value value="16" name="PERF_RB_TOTAL_PASS"/>
717
	<value value="17" name="PERF_RB_Z_PASS"/>
718
	<value value="18" name="PERF_RB_Z_FAIL"/>
719
	<value value="19" name="PERF_RB_S_FAIL"/>
720
	<value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
721
	<value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
722
	<value value="22" name="PERF_RB_PS_INVOCATIONS"/>
723
	<value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
724
	<value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
725
	<value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
726
	<value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
727
	<value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
728
	<value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
729
	<value value="29" name="PERF_RB_3D_PIXELS"/>
730
	<value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
731
	<value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
732
	<value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
733
	<value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
734
	<value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
735
	<value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
736
	<value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
737
	<value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
738
	<value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
739
	<value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
740
	<value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
741
	<value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
742
	<value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
743
	<value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
744
	<value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
745
	<value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
746
	<value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
747
	<value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
748
</enum>
749

750
<enum name="a6xx_vsc_perfcounter_select">
751
	<value value="0" name="PERF_VSC_BUSY_CYCLES"/>
752
	<value value="1" name="PERF_VSC_WORKING_CYCLES"/>
753
	<value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
754
	<value value="3" name="PERF_VSC_EOT_NUM"/>
755
	<value value="4" name="PERF_VSC_INPUT_TILES"/>
756
</enum>
757

758
<enum name="a6xx_ccu_perfcounter_select">
759
	<value value="0" name="PERF_CCU_BUSY_CYCLES"/>
760
	<value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
761
	<value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
762
	<value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
763
	<value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
764
	<value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
765
	<value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
766
	<value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
767
	<value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
768
	<value value="9" name="PERF_CCU_GMEM_READ"/>
769
	<value value="10" name="PERF_CCU_GMEM_WRITE"/>
770
	<value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
771
	<value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
772
	<value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
773
	<value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
774
	<value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
775
	<value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
776
	<value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
777
	<value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
778
	<value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
779
	<value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
780
	<value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
781
	<value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
782
	<value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
783
	<value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
784
	<value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
785
	<value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
786
	<value value="27" name="PERF_CCU_2D_RD_REQ"/>
787
	<value value="28" name="PERF_CCU_2D_WR_REQ"/>
788
</enum>
789

790
<enum name="a6xx_lrz_perfcounter_select">
791
	<value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
792
	<value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
793
	<value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
794
	<value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
795
	<value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
796
	<value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
797
	<value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
798
	<value value="7" name="PERF_LRZ_LRZ_READ"/>
799
	<value value="8" name="PERF_LRZ_LRZ_WRITE"/>
800
	<value value="9" name="PERF_LRZ_READ_LATENCY"/>
801
	<value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
802
	<value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
803
	<value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
804
	<value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
805
	<value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
806
	<value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
807
	<value value="16" name="PERF_LRZ_TILE_KILLED"/>
808
	<value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
809
	<value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
810
	<value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
811
	<value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
812
	<value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
813
	<value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
814
	<value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
815
	<value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
816
	<value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
817
	<value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
818
	<value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
819
</enum>
820

821
<enum name="a6xx_cmp_perfcounter_select">
822
	<value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
823
	<value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
824
	<value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
825
	<value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
826
	<value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
827
	<value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
828
	<value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
829
	<value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
830
	<value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
831
	<value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
832
	<value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
833
	<value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
834
	<value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
835
	<value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
836
	<value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
837
	<value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
838
	<value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
839
	<value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
840
	<value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
841
	<value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
842
	<value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
843
	<value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
844
	<value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
845
	<value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
846
	<value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
847
	<value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
848
	<value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
849
	<value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
850
	<value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
851
	<value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
852
	<value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
853
	<value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
854
	<value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
855
	<value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
856
	<value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
857
	<value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
858
	<value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
859
	<value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
860
	<value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
861
	<value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
862
</enum>
863

864
<!--
865
Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
866
component type/size, so I think it relates to internal format used for
867
blending?  The one exception is that 16b unorm and 32b float use the
868
same value... maybe 16b unorm is uncommon enough that it was just easier
869
to upconvert to 32b float internally?
870

871
 8b unorm:  10 (sometimes 0, is the high bit part of something else?)
872
16b unorm:   4
873

874
32b int:     7
875
16b int:     6
876
 8b int:     5
877

878
32b float:   4
879
16b float:   3
880
 -->
881
<enum name="a6xx_2d_ifmt">
882
	<value value="0x10" name="R2D_UNORM8"/>
883
	<value value="0x7"  name="R2D_INT32"/>
884
	<value value="0x6"  name="R2D_INT16"/>
885
	<value value="0x5"  name="R2D_INT8"/>
886
	<value value="0x4"  name="R2D_FLOAT32"/>
887
	<value value="0x3"  name="R2D_FLOAT16"/>
888
	<value value="0x1"  name="R2D_UNORM8_SRGB"/>
889
	<value value="0x0"  name="R2D_RAW"/>
890
</enum>
891

892
<enum name="a6xx_ztest_mode">
893
	<doc>Allow early z-test and early-lrz (if applicable)</doc>
894
	<value value="0x0" name="A6XX_EARLY_Z"/>
895
	<doc>Disable early z-test and early-lrz test (if applicable)</doc>
896
	<value value="0x1" name="A6XX_LATE_Z"/>
897
	<doc>
898
		A special mode that allows early-lrz test but disables
899
		early-z test.  Which might sound a bit funny, since
900
		lrz-test happens before z-test.  But as long as a couple
901
		conditions are maintained this allows using lrz-test in
902
		cases where fragment shader has kill/discard:
903

904
		1) Disable lrz-write in cases where it is uncertain during
905
		   binning pass that a fragment will pass.  Ie.  if frag
906
		   shader has-kill, writes-z, or alpha/stencil test is
907
		   enabled.  (For correctness, lrz-write must be disabled
908
		   when blend is enabled.)  This is analogous to how a
909
		   z-prepass works.
910

911
		2) Disable lrz-write and test if a depth-test direction
912
		   reversal is detected.  Due to condition (1), the contents
913
		   of the lrz buffer are a conservative estimation of the
914
		   depth buffer during the draw pass.  Meaning that geometry
915
		   that we know for certain will not be visible will not pass
916
		   lrz-test.  But geometry which may be (or contributes to
917
		   blend) will pass the lrz-test.
918

919
		This allows us to keep early-lrz-test in cases where the frag
920
		shader does not write-z (ie. we know the z-value before FS)
921
		and does not have side-effects (image/ssbo writes, etc), but
922
		does have kill/discard.  Which turns out to be a common
923
		enough case that it is useful to keep early-lrz test against
924
		the conservative lrz buffer to discard fragments that we
925
		know will definitely not be visible.
926
	</doc>
927
	<value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/>
928
</enum>
929

930
<domain name="A6XX" width="32">
931
	<bitset name="A6XX_RBBM_INT_0_MASK" inline="no">
932
		<bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
933
		<bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/>
934
		<bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/>
935
		<bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
936
		<bitfield name="CP_SW" pos="8" type="boolean"/>
937
		<bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
938
		<bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
939
		<bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
940
		<bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
941
		<bitfield name="CP_IB2" pos="13" type="boolean"/>
942
		<bitfield name="CP_IB1" pos="14" type="boolean"/>
943
		<bitfield name="CP_RB" pos="15" type="boolean"/>
944
		<bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
945
		<bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
946
		<bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
947
		<bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
948
		<bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/>
949
		<bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
950
		<bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
951
		<bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
952
		<bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
953
		<bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
954
		<bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
955
	</bitset>
956

957
	<bitset name="A6XX_CP_INT">
958
		<bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
959
		<bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/>
960
		<bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>
961
		<bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/>
962
		<bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>
963
		<bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/>
964
		<bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/>
965
	</bitset>
966

967
	<reg32 offset="0x0800" name="CP_RB_BASE"/>
968
	<reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
969
	<reg32 offset="0x0802" name="CP_RB_CNTL"/>
970
	<reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
971
	<reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
972
	<reg32 offset="0x0806" name="CP_RB_RPTR"/>
973
	<reg32 offset="0x0807" name="CP_RB_WPTR"/>
974
	<reg32 offset="0x0808" name="CP_SQE_CNTL"/>
975
	<reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
976
		<bitfield name="IFPC" pos="0" type="boolean"/>
977
	</reg32>
978
	<reg32 offset="0x0821" name="CP_HW_FAULT"/>
979
	<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
980
	<reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
981
	<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
982
	<reg32 offset="0x0840" name="CP_MISC_CNTL"/>
983
	<reg32 offset="0x0844" name="CP_APRIV_CNTL"/>
984
	<!-- all the threshold values seem to be in units of quad-dwords: -->
985
	<reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
986
		<doc>
987
			b0..7 seems to contain the size of buffered by not yet processed
988
			RB level cmdstream.. it's possible that it is a low threshold
989
			and b8..15 is a high threshold?
990

991
			b16..23 identifies where IB1 data starts (and RB data ends?)
992

993
			b24..31 identifies where IB2 data starts (and IB1 data ends)
994
		</doc>
995
		<bitfield name="RB_LO" low="0" high="7" shr="2"/>
996
		<bitfield name="RB_HI" low="8" high="15" shr="2"/>
997
		<bitfield name="IB1_START" low="16" high="23" shr="2"/>
998
		<bitfield name="IB2_START" low="24" high="31" shr="2"/>
999
	</reg32>
1000
	<reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
1001
		<doc>
1002
			low bits identify where CP_SET_DRAW_STATE stateobj
1003
			processing starts (and IB2 data ends). I'm guessing
1004
			b8 is part of this since (from downstream kgsl):
1005

1006
				/* ROQ sizes are twice as big on a640/a680 than on a630 */
1007
				if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
1008
					kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
1009
					kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
1010
				} ...
1011
		</doc>
1012
		<bitfield name="SDS_START" low="0" high="8" shr="2"/>
1013
		<!-- total ROQ size: -->
1014
		<bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
1015
	</reg32>
1016
	<reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
1017
	<reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
1018
	<reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1019
	<reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
1020
	<reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
1021

1022
	<array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
1023
		<reg32 offset="0x0" name="REG" type="uint"/>
1024
	</array>
1025
	<array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
1026
		<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
1027
	</array>
1028

1029
	<reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
1030
	<reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
1031
	<reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
1032
	<reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
1033
	<reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
1034
	<reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
1035
	<reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
1036
	<reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
1037
	<reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
1038
	<array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/>
1039
	<reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
1040
	<reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
1041
	<reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
1042
	<reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
1043
	<reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
1044
	<reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
1045
	<reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
1046
	<reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
1047
	<reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
1048
	<reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
1049
	<reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
1050
	<reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
1051
	<reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
1052
	<reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
1053
	<reg32 offset="0x0928" name="CP_IB1_BASE"/>
1054
	<reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
1055
	<reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
1056
	<reg32 offset="0x092B" name="CP_IB2_BASE"/>
1057
	<reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
1058
	<reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
1059
	<!-- SDS == CP_SET_DRAW_STATE: -->
1060
	<reg32 offset="0x092e" name="CP_SDS_BASE"/>
1061
	<reg32 offset="0x092f" name="CP_SDS_BASE_HI"/>
1062
	<reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/>
1063
	<!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->
1064
	<reg32 offset="0x0931" name="CP_MRB_BASE"/>
1065
	<reg32 offset="0x0932" name="CP_MRB_BASE_HI"/>
1066
	<reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/>
1067
	<!--
1068
	VSD == Visibility Stream Decode
1069
	This is used by CP to read the draw stream and skip empty draws
1070
	-->
1071
	<reg32 offset="0x0934" name="CP_VSD_BASE"/>
1072
	<reg32 offset="0x0935" name="CP_VSD_BASE_HI"/>
1073
	<reg32 offset="0x0946" name="CP_MRB_DWORDS"/>
1074
	<reg32 offset="0x0947" name="CP_VSD_DWORDS"/>
1075
	<!--
1076
	There are probably similar registers for RB and SDS, teasing out SDS will
1077
	take a slightly better test case..
1078
	 -->
1079
	<reg32 offset="0x0949" name="CP_CSQ_IB1_STAT">
1080
		<doc>number of remaining dwords incl current dword being consumed?</doc>
1081
		<bitfield name="REM" low="16" high="31"/>
1082
	</reg32>
1083
	<reg32 offset="0x094a" name="CP_CSQ_IB2_STAT">
1084
		<doc>number of remaining dwords incl current dword being consumed?</doc>
1085
		<bitfield name="REM" low="16" high="31"/>
1086
	</reg32>
1087
	<reg32 offset="0x094c" name="CP_MRQ_MRB_STAT">
1088
		<doc>number of dwords that have already been read but haven't been consumed by $addr</doc>
1089
		<bitfield name="REM" low="16" high="31"/>
1090
	</reg32>
1091
	<reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
1092
	<reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
1093
	<reg32 offset="0x098D" name="CP_AHB_CNTL"/>
1094
	<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
1095
	<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
1096
	<reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
1097
	<reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>
1098
	<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1099
	<reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
1100
	<reg32 offset="0x0210" name="RBBM_STATUS">
1101
		<bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/>
1102
		<bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/>
1103
		<bitfield pos="21" name="HLSQ_BUSY" type="boolean"/>
1104
		<bitfield pos="20" name="VSC_BUSY" type="boolean"/>
1105
		<bitfield pos="19" name="TPL1_BUSY" type="boolean"/>
1106
		<bitfield pos="18" name="SP_BUSY" type="boolean"/>
1107
		<bitfield pos="17" name="UCHE_BUSY" type="boolean"/>
1108
		<bitfield pos="16" name="VPC_BUSY" type="boolean"/>
1109
		<bitfield pos="15" name="VFD_BUSY" type="boolean"/>
1110
		<bitfield pos="14" name="TESS_BUSY" type="boolean"/>
1111
		<bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/>
1112
		<bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/>
1113
		<bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/>
1114
		<bitfield pos="10" name="LRZ_BUSY" type="boolean"/>
1115
		<bitfield pos="9"  name="A2D_BUSY" type="boolean"/>
1116
		<bitfield pos="8"  name="CCU_BUSY" type="boolean"/>
1117
		<bitfield pos="7"  name="RB_BUSY" type="boolean"/>
1118
		<bitfield pos="6"  name="RAS_BUSY" type="boolean"/>
1119
		<bitfield pos="5"  name="TSE_BUSY" type="boolean"/>
1120
		<bitfield pos="4"  name="VBIF_BUSY" type="boolean"/>
1121
		<bitfield pos="3"  name="GFX_DBGC_BUSY" type="boolean"/>
1122
		<bitfield pos="2"  name="CP_BUSY" type="boolean"/>
1123
		<bitfield pos="1"  name="CP_AHB_BUSY_CP_MASTER" type="boolean"/>
1124
		<bitfield pos="0"  name="CP_AHB_BUSY_CX_MASTER" type="boolean"/>
1125
	</reg32>
1126
	<reg32 offset="0x0213" name="RBBM_STATUS3">
1127
		<bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
1128
	</reg32>
1129
	<reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
1130
	<array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14"/>
1131
	<array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4"/>
1132
	<array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8"/>
1133
	<array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8"/>
1134
	<array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6"/>
1135
	<array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6"/>
1136
	<array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5"/>
1137
	<array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4"/>
1138
	<array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4"/>
1139
	<array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12"/>
1140
	<array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12"/>
1141
	<array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24"/>
1142
	<array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8"/>
1143
	<array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2"/>
1144
	<array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4"/>
1145
	<array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4"/>
1146
	<reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
1147
	<reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
1148
	<reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
1149
	<reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
1150
	<reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
1151
	<reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1152
	<reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1153
	<array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/>
1154
	<reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1155
	<reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1156

1157
	<!---
1158
	    This block of registers aren't tied to perf counters. They
1159
	    count various geometry stats, for example number of
1160
	    vertices in, number of primnitives assembled etc.
1161
	-->
1162

1163
	<reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/>  <!-- vs vertices in -->
1164
	<reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
1165
	<reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/>  <!-- vs primitives out -->
1166
	<reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
1167
	<reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/>  <!-- hs vertices in -->
1168
	<reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
1169
	<reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/>  <!-- hs patches out -->
1170
	<reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
1171
	<reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/>  <!-- dss vertices in -->
1172
	<reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
1173
	<reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/>  <!-- ds primitives out -->
1174
	<reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
1175
	<reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/>  <!-- gs primitives in -->
1176
	<reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
1177
	<reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/>  <!-- gs primitives out -->
1178
	<reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
1179
	<reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/>  <!-- gs primitives out -->
1180
	<reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
1181
	<reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/>  <!-- raster primitives in -->
1182
	<reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
1183
	<reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
1184
	<reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
1185

1186
	<reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
1187
	<reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1188
	<reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1189
	<reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1190
	<reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
1191
	<reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1192
	<reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
1193
	<reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
1194
	<reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">
1195
		<bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>
1196
	</reg32>
1197
	<reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
1198
	<reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/>
1199
	<reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
1200
	<reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
1201
	<reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
1202
	<reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
1203
	<reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1204
	<reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1205
	<reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
1206
	<reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
1207
	<reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
1208
	<reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
1209
	<reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
1210
	<reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
1211
	<reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
1212
	<reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
1213
	<reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
1214
	<reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
1215
	<reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
1216
	<reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
1217
	<reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
1218
	<reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
1219
	<reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
1220
	<reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
1221
	<reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
1222
	<reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
1223
	<reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
1224
	<reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
1225
	<reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
1226
	<reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
1227
	<reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
1228
	<reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
1229
	<reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
1230
	<reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
1231
	<reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
1232
	<reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
1233
	<reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
1234
	<reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
1235
	<reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
1236
	<reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
1237
	<reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
1238
	<reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
1239
	<reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
1240
	<reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
1241
	<reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
1242
	<reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
1243
	<reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
1244
	<reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
1245
	<reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
1246
	<reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
1247
	<reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
1248
	<reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
1249
	<reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
1250
	<reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
1251
	<reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
1252
	<reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
1253
	<reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
1254
	<reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
1255
	<reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
1256
	<reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
1257
	<reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
1258
	<reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
1259
	<reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
1260
	<reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
1261
	<reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
1262
	<reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
1263
	<reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
1264
	<reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
1265
	<reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
1266
	<reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
1267
	<reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
1268
	<reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
1269
	<reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
1270
	<reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
1271
	<reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
1272
	<reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
1273
	<reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
1274
	<reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
1275
	<reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
1276
	<reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
1277
	<reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
1278
	<reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
1279
	<reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
1280
	<reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
1281
	<reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
1282
	<reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1283
	<reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1284
	<reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1285
	<reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1286
	<reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
1287
	<reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
1288
	<reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
1289
	<reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
1290
	<reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1291
	<reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1292
	<reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1293
	<reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
1294
	<reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
1295
	<reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
1296
	<reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
1297
	<reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
1298
	<reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
1299
	<reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
1300
	<reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
1301
	<reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
1302
	<reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
1303
	<reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
1304
	<reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
1305
	<reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
1306
	<reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
1307
	<reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
1308
	<reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
1309
	<reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
1310
	<reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1311
	<reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/>
1312
	<reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/>
1313
	<reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/>
1314
	<reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/>
1315

1316
	<reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
1317
	<reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
1318
	<reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
1319
	<reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
1320
		<bitfield high="7" low="0" name="PING_INDEX"/>
1321
		<bitfield high="15" low="8" name="PING_BLK_SEL"/>
1322
	</reg32>
1323
	<reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
1324
		<bitfield high="5" low="0" name="TRACEEN"/>
1325
		<bitfield high="14" low="12" name="GRANU"/>
1326
		<bitfield high="31" low="28" name="SEGT"/>
1327
	</reg32>
1328
	<reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
1329
		<bitfield high="27" low="24" name="ENABLE"/>
1330
	</reg32>
1331
	<reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
1332
	<reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
1333
	<reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
1334
	<reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
1335
	<reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
1336
	<reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
1337
	<reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
1338
	<reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
1339
	<reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
1340
		<bitfield high="3" low="0" name="BYTEL0"/>
1341
		<bitfield high="7" low="4" name="BYTEL1"/>
1342
		<bitfield high="11" low="8" name="BYTEL2"/>
1343
		<bitfield high="15" low="12" name="BYTEL3"/>
1344
		<bitfield high="19" low="16" name="BYTEL4"/>
1345
		<bitfield high="23" low="20" name="BYTEL5"/>
1346
		<bitfield high="27" low="24" name="BYTEL6"/>
1347
		<bitfield high="31" low="28" name="BYTEL7"/>
1348
	</reg32>
1349
	<reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
1350
		<bitfield high="3" low="0" name="BYTEL8"/>
1351
		<bitfield high="7" low="4" name="BYTEL9"/>
1352
		<bitfield high="11" low="8" name="BYTEL10"/>
1353
		<bitfield high="15" low="12" name="BYTEL11"/>
1354
		<bitfield high="19" low="16" name="BYTEL12"/>
1355
		<bitfield high="23" low="20" name="BYTEL13"/>
1356
		<bitfield high="27" low="24" name="BYTEL14"/>
1357
		<bitfield high="31" low="28" name="BYTEL15"/>
1358
	</reg32>
1359
	<reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
1360
	<reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
1361
	<array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/>
1362
	<reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1363
	<reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1364
	<reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1365
	<reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1366
	<reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
1367
	<reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
1368
	<reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
1369
	<reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
1370
	<reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
1371
	<reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
1372
	<reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
1373
	<reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
1374
	<reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
1375
	<reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
1376
	<reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
1377
	<reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1378
	<reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
1379
		<bitfield high="7" low="0" name="PERFSEL"/>
1380
	</reg32>
1381
	<array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
1382
	<reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/>
1383

1384
	<reg32 offset="0x3000" name="VBIF_VERSION"/>
1385
	<reg32 offset="0x3001" name="VBIF_CLKON">
1386
		<bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/>
1387
	</reg32>
1388
	<reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1389
	<reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1390
	<reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1391
	<reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1392
	<reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1393
	<reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
1394
		<bitfield low="0" high="3" name="DATA_SEL"/>
1395
	</reg32>
1396
	<reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1397
	<reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
1398
		<bitfield low="0" high="8" name="DATA_SEL"/>
1399
	</reg32>
1400
	<reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1401
	<reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1402
	<reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1403
	<reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1404
	<reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1405
	<reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1406
	<reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1407
	<reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1408
	<reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1409
	<reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1410
	<reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1411
	<reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1412
	<reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1413
	<reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1414
	<reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1415
	<reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1416
	<reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1417
	<reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1418
	<reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1419
	<reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1420
	<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1421
	<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1422

1423
	<reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
1424
	<reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
1425
	<reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
1426
	<reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
1427
	<reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
1428
	<reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
1429
	<reg32 offset="0x3c45" name="GBIF_HALT"/>
1430
	<reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
1431
	<reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
1432
	<reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
1433
	<reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
1434
	<reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
1435
	<reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
1436
	<reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
1437
	<reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
1438
	<reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
1439
	<reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
1440
	<reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
1441
	<reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
1442
	<reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
1443
	<reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
1444
	<reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
1445
	<reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
1446
	<reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
1447
	<reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
1448

1449
	<reg32 offset="0x0c02" name="VSC_BIN_SIZE">
1450
		<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1451
		<bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
1452
	</reg32>
1453
	<reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress"/>
1454
	<reg32 offset="0x0c06" name="VSC_BIN_COUNT">
1455
		<bitfield name="NX" low="1" high="10" type="uint"/>
1456
		<bitfield name="NY" low="11" high="20" type="uint"/>
1457
	</reg32>
1458
	<array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32">
1459
		<reg32 offset="0x0" name="REG">
1460
			<doc>
1461
				Configures the mapping between VSC_PIPE buffer and
1462
				bin, X/Y specify the bin index in the horiz/vert
1463
				direction (0,0 is upper left, 0,1 is leftmost bin
1464
				on second row, and so on).  W/H specify the number
1465
				of bins assigned to this VSC_PIPE in the horiz/vert
1466
				dimension.
1467
			</doc>
1468
			<bitfield name="X" low="0" high="9" type="uint"/>
1469
			<bitfield name="Y" low="10" high="19" type="uint"/>
1470
			<bitfield name="W" low="20" high="25" type="uint"/>
1471
			<bitfield name="H" low="26" high="31" type="uint"/>
1472
		</reg32>
1473
	</array>
1474
	<!--
1475
	HW binning primitive & draw streams, which enable draws and primitives
1476
	within a draw to be skipped in the main tile pass.  See:
1477
	https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
1478

1479
	Compared to a5xx and earlier, we just program the address of the first
1480
	stream and hw adds (pipe_num * VSC_*_STRM_PITCH)
1481

1482
	LIMIT is set to PITCH - 64, to make room for a bit of overflow
1483
	 -->
1484
	<reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress"/>
1485
	<reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH"/>
1486
	<reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT"/>
1487
	<reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress"/>
1488
	<reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH"/>
1489
	<reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT"/>
1490

1491
	<array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
1492
		<doc>
1493
			Seems to be a bitmap of which tiles mapped to the VSC
1494
			pipe contain geometry.
1495

1496
			I suppose we can connect a maximum of 32 tiles to a
1497
			single VSC pipe.
1498
		</doc>
1499
		<reg32 offset="0x0" name="REG"/>
1500
	</array>
1501

1502
	<array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32">
1503
		<doc>
1504
			Has the size of data written to corresponding VSC_PRIM_STRM
1505
			buffer.
1506
		</doc>
1507
		<reg32 offset="0x0" name="REG"/>
1508
	</array>
1509

1510
	<array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32">
1511
		<doc>
1512
			Has the size of data written to corresponding VSC pipe, ie.
1513
			same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI
1514
		</doc>
1515
		<reg32 offset="0x0" name="REG"/>
1516
	</array>
1517

1518
	<!-- always 0x03200000 ? -->
1519
	<reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
1520

1521
	<!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
1522
	<bitset name="a6xx_reg_xy" inline="yes">
1523
		<bitfield name="X" low="0" high="13" type="uint"/>
1524
		<bitfield name="Y" low="16" high="29" type="uint"/>
1525
	</bitset>
1526

1527
	<reg32 offset="0x8000" name="GRAS_CL_CNTL">
1528
		<bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
1529
		<bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
1530
		<bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
1531
		<!-- set with depthClampEnable, not clear what it does -->
1532
		<bitfield name="UNK5" pos="5" type="boolean"/>
1533
		<!-- controls near z clip behavior (set for vulkan) -->
1534
		<bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
1535
		<!-- guess based on a3xx and meaning of bits 8 and 9
1536
		     if the guess is right then this is related to point sprite clipping -->
1537
		<bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
1538
		<bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
1539
		<bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
1540
	</reg32>
1541

1542
	<bitset name="a6xx_gras_xs_cl_cntl" inline="yes">
1543
		<bitfield name="CLIP_MASK" low="0" high="7"/>
1544
		<bitfield name="CULL_MASK" low="8" high="15"/>
1545
	</bitset>
1546
	<reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1547
	<reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1548
	<reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1549
	<reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint"/>
1550

1551
	<reg32 offset="0x8005" name="GRAS_CNTL">
1552
		<!-- see also RB_RENDER_CONTROL0 -->
1553
		<bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
1554
		<!-- b1 set for interpolateAtCentroid() -->
1555
		<bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
1556
		<!-- b2 set instead of b0 when running in per-sample mode -->
1557
		<bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
1558
		<!--
1559
		b3 set for interpolateAt{Offset,Sample}() if not in per-sample
1560
		mode, and frag_face
1561
		 -->
1562
		<bitfield name="SIZE" pos="3" type="boolean"/>
1563
		<bitfield name="UNK4" pos="4" type="boolean"/>
1564
		<!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
1565
		<bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
1566
		<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
1567
	</reg32>
1568
	<reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1569
		<bitfield name="HORZ" low="0" high="8" type="uint"/>
1570
		<bitfield name="VERT" low="10" high="18" type="uint"/>
1571
	</reg32>
1572
	<!-- 0x8006-0x800f invalid -->
1573
	<array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16">
1574
		<reg32 offset="0" name="XOFFSET" type="float"/>
1575
		<reg32 offset="1" name="XSCALE" type="float"/>
1576
		<reg32 offset="2" name="YOFFSET" type="float"/>
1577
		<reg32 offset="3" name="YSCALE" type="float"/>
1578
		<reg32 offset="4" name="ZOFFSET" type="float"/>
1579
		<reg32 offset="5" name="ZSCALE" type="float"/>
1580
	</array>
1581
	<array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16">
1582
		<reg32 offset="0" name="MIN" type="float"/>
1583
		<reg32 offset="1" name="MAX" type="float"/>
1584
	</array>
1585

1586
	<reg32 offset="0x8090" name="GRAS_SU_CNTL">
1587
		<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1588
		<bitfield name="CULL_BACK" pos="1" type="boolean"/>
1589
		<bitfield name="FRONT_CW" pos="2" type="boolean"/>
1590
		<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1591
		<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1592
		<bitfield name="UNK12" pos="12"/>
1593
		<bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1594
		<bitfield name="UNK15" low="15" high="16"/>
1595
		<!--
1596
		This is set by the blob when multiview is enabled, but doesn't seem
1597
		to do anything.
1598
		-->
1599
		<bitfield name="UNK17" pos="17" type="boolean"/>
1600
		<bitfield name="MULTIVIEW_ENABLE" pos="18" type="boolean"/>
1601
		<bitfield name="UNK19" low="19" high="22"/>
1602
	</reg32>
1603
	<reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
1604
		<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1605
		<bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1606
	</reg32>
1607
	<reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4"/>
1608
	<!-- 0x8093 invalid -->
1609
	<reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1610
		<bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
1611
	</reg32>
1612
	<reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1613
	<reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1614
	<reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1615
	<!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1616
	<reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1617
		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
1618
		<bitfield name="UNK3" pos="3"/>
1619
	</reg32>
1620

1621
	<reg32 offset="0x8099" name="GRAS_UNKNOWN_8099" low="0" high="5"/>
1622
	<reg32 offset="0x809a" name="GRAS_UNKNOWN_809A" low="0" high="1"/>
1623

1624
	<bitset name="a6xx_gras_layer_cntl" inline="yes">
1625
		<bitfield name="WRITES_LAYER" pos="0" type="boolean"/>
1626
		<bitfield name="WRITES_VIEW" pos="1" type="boolean"/>
1627
	</bitset>
1628
	<reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1629
	<reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1630
	<reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1631
	<!-- 0x809e/0x809f invalid -->
1632
	<reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0" low="0" high="12"/>
1633
	<reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
1634
		<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
1635
		<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
1636
		<bitfield name="BINNING_PASS" pos="18" type="boolean"/>
1637
		<bitfield name="UNK19" pos="19"/>
1638
		<bitfield name="UNK20" pos="20"/>
1639
		<bitfield name="USE_VIZ" pos="21" type="boolean"/>
1640
		<bitfield name="UNK22" low="22" high="27"/>
1641
	</reg32>
1642

1643
	<reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
1644
		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1645
		<bitfield name="UNK2" pos="2"/>
1646
		<bitfield name="UNK3" pos="3"/>
1647
	</reg32>
1648
	<reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
1649
		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1650
		<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1651
	</reg32>
1652

1653
	<bitset name="a6xx_sample_config" inline="yes">
1654
		<bitfield name="UNK0" pos="0"/>
1655
		<bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
1656
	</bitset>
1657

1658
	<bitset name="a6xx_sample_locations" inline="yes">
1659
		<bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
1660
		<bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
1661
		<bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
1662
		<bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
1663
		<bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
1664
		<bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
1665
		<bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
1666
		<bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
1667
	</bitset>
1668

1669
	<reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config"/>
1670
	<reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
1671
	<reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
1672
	<!-- 0x80a7-0x80ae invalid -->
1673
	<reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0"/>
1674

1675
	<bitset name="a6xx_scissor_xy" inline="yes">
1676
		<bitfield name="X" low="0" high="15" type="uint"/>
1677
		<bitfield name="Y" low="16" high="31" type="uint"/>
1678
	</bitset>
1679
	<array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16">
1680
		<reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
1681
		<reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
1682
	</array>
1683
	<array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16">
1684
		<reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
1685
		<reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
1686
	</array>
1687

1688
	<reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy"/>
1689
	<reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy"/>
1690
	<!-- 0x80f2-0x80ff invalid -->
1691

1692
	<reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
1693
		<!--
1694
		These bits seems to mostly fit.. but wouldn't hurt to have a 2nd
1695
		look when we get around to enabling lrz
1696
		 -->
1697
		<bitfield name="ENABLE" pos="0" type="boolean"/>
1698
		<doc>LRZ write also disabled for blend/etc.</doc>
1699
		<bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
1700
		<doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
1701
		<bitfield name="GREATER" pos="2" type="boolean"/>
1702
		<bitfield name="FC_ENABLE" pos="3" type="boolean"/>
1703
		<!-- set when depth-test + depth-write enabled -->
1704
		<bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
1705
		<bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/>
1706
		<bitfield name="UNK6" low="6" high="9"/>
1707
	</reg32>
1708
	<reg32 offset="0x8101" name="GRAS_UNKNOWN_8101" low="0" high="2"/>
1709
	<reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
1710
		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
1711
	</reg32>
1712
	<reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress"/>
1713
	<reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
1714
		<!-- TODO: fix the shr fields -->
1715
		<bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>
1716
		<bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/>
1717
	</reg32>
1718

1719
	<!--
1720
	The LRZ "fast clear" buffer is initialized to zero's by blob, and
1721
	read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set.  It appears
1722
	to store 1b/block.  It appears that '0' means block has original
1723
	depth clear value, and '1' means that the corresponding block in
1724
	LRZ has been modified.  Ignoring alignment/padding, the size is
1725
	given by the formula:
1726

1727
		// calculate LRZ size from depth size:
1728
		if (nr_samples == 4) {
1729
			width *= 2;
1730
			height *= 2;
1731
		} else if (nr_samples == 2) {
1732
			height *= 2;
1733
		}
1734

1735
		lrz_width = div_round_up(width, 8);
1736
		lrz_heigh = div_round_up(height, 8);
1737

1738
		// calculate # of blocks:
1739
		nblocksx = div_round_up(lrz_width, 16);
1740
		nblocksy = div_round_up(lrz_height, 4);
1741

1742
		// fast-clear buffer is 1bit/block:
1743
		fc_sz = div_round_up(nblocksx * nblocksy, 8);
1744

1745
	In practice the blob seems to switch off FC_ENABLE once the size
1746
	increases beyond 1 page.  Not sure if that is an actual limit or
1747
	not.
1748
	 -->
1749
	<reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress"/>
1750
	<!-- 0x8108 invalid -->
1751
	<reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
1752
		<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
1753
	</reg32>
1754
	<reg32 offset="0x810a" name="GRAS_UNKNOWN_810A">
1755
		<bitfield name="UNK0" low="0" high="10" type="uint"/>
1756
		<bitfield name="UNK16" low="16" high="26" type="uint"/>
1757
		<bitfield name="UNK28" low="28" high="31" type="uint"/>
1758
	</reg32>
1759

1760
	<!-- 0x810b-0x810f invalid -->
1761

1762
	<reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1"/>
1763

1764
	<!-- 0x8111-0x83ff invalid -->
1765

1766
	<enum name="a6xx_rotation">
1767
		<value value="0x0" name="ROTATE_0"/>
1768
		<value value="0x1" name="ROTATE_90"/>
1769
		<value value="0x2" name="ROTATE_180"/>
1770
		<value value="0x3" name="ROTATE_270"/>
1771
		<value value="0x4" name="ROTATE_HFLIP"/>
1772
		<value value="0x5" name="ROTATE_VFLIP"/>
1773
	</enum>
1774

1775
	<bitset name="a6xx_2d_blit_cntl" inline="yes">
1776
		<bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
1777
		<bitfield name="UNK3" low="3" high="6"/>
1778
		<bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
1779
		<bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
1780
		<bitfield name="SCISSOR" pos="16" type="boolean"/>
1781
		<bitfield name="UNK17" low="17" high="18"/>
1782
		<!-- required when blitting D24S8/D24X8 -->
1783
		<bitfield name="D24S8" pos="19" type="boolean"/>
1784
		<!-- some sort of channel mask, disabled channels are set to zero ? -->
1785
		<bitfield name="MASK" low="20" high="23"/>
1786
		<bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
1787
		<bitfield name="UNK29" pos="29"/>
1788
	</bitset>
1789

1790
	<reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
1791
	<!-- note: the low 8 bits for src coords are valid, probably fixed point
1792
	     it would be a bit weird though, since we subtract 1 from BR coords
1793
	     apparently signed, gallium driver uses negative coords and it works?
1794
	 -->
1795
	<reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int"/>
1796
	<reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int"/>
1797
	<reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int"/>
1798
	<reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int"/>
1799
	<reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy"/>
1800
	<reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy"/>
1801
	<reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/>
1802
	<reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/>
1803
	<reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/>
1804
	<reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy"/>
1805
	<reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy"/>
1806
	<!-- 0x840c-0x85ff invalid -->
1807

1808
	<!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
1809
	<reg32 offset="0x8600" name="GRAS_UNKNOWN_8600" low="0" high="12" />
1810
	<reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
1811
	<array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/>
1812
	<array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/>
1813
	<array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/>
1814

1815
	<!-- note 0x8620-0x87ff are not all invalid
1816
	(in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords)
1817
	-->
1818

1819
	<!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
1820
	<reg32 offset="0x8800" name="RB_BIN_CONTROL">
1821
		<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
1822
		<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
1823
		<bitfield name="BINNING_PASS" pos="18" type="boolean"/>
1824
		<bitfield name="UNK19" pos="19"/>
1825
		<bitfield name="UNK20" pos="20"/>
1826
		<bitfield name="USE_VIZ" pos="21" type="boolean"/>
1827
		<bitfield name="UNK22" low="22" high="26"/>
1828
	</reg32>
1829
	<reg32 offset="0x8801" name="RB_RENDER_CNTL">
1830
		<bitfield name="UNK3" pos="3" type="boolean"/>
1831
		<!-- always set: ?? -->
1832
		<bitfield name="UNK4" pos="4" type="boolean"/>
1833
		<bitfield name="UNK5" low="5" high="6"/>
1834
		<!-- set during binning pass: -->
1835
		<bitfield name="BINNING" pos="7" type="boolean"/>
1836
		<bitfield name="UNK8" low="8" high="12"/>
1837
		<!-- bit seems to be set whenever depth buffer enabled: -->
1838
		<bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
1839
		<!-- bitmask of MRTs using UBWC flag buffer: -->
1840
		<bitfield name="FLAG_MRTS" low="16" high="23"/>
1841
	</reg32>
1842
	<reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
1843
		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1844
		<bitfield name="UNK2" pos="2"/>
1845
		<bitfield name="UNK3" pos="3"/>
1846
	</reg32>
1847
	<reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
1848
		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1849
		<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1850
	</reg32>
1851

1852
	<reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config"/>
1853
	<reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
1854
	<reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
1855
	<!-- 0x8807-0x8808 invalid -->
1856
	<!--
1857
	note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
1858
	name comes from kernel and is probably right)
1859
	 -->
1860
	<reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
1861
		<!-- see also GRAS_CNTL -->
1862
		<bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
1863
		<!-- b1 set for interpolateAtCentroid() -->
1864
		<bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
1865
		<!-- b2 set instead of b0 when running in per-sample mode -->
1866
		<bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
1867
		<!--
1868
		b3 set for interpolateAt{Offset,Sample}() if not in per-sample
1869
		mode, and frag_face
1870
		 -->
1871
		<bitfield name="SIZE" pos="3" type="boolean"/>
1872
		<bitfield name="UNK4" pos="4" type="boolean"/>
1873
		<!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
1874
		<bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
1875
		<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
1876
		<bitfield name="UNK10" pos="10" type="boolean"/>
1877
	</reg32>
1878
	<reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
1879
		<!-- enable bits for various FS sysvalue regs: -->
1880
		<bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
1881
		<bitfield name="UNK1" pos="1" type="boolean"/>
1882
		<bitfield name="FACENESS" pos="2" type="boolean"/>
1883
		<bitfield name="SAMPLEID" pos="3" type="boolean"/>
1884
		<!-- b4 and b5 set in per-sample mode: -->
1885
		<bitfield name="UNK4" pos="4" type="boolean"/>
1886
		<bitfield name="UNK5" pos="5" type="boolean"/>
1887
		<bitfield name="SIZE" pos="6" type="boolean"/>
1888
		<bitfield name="UNK7" pos="7" type="boolean"/>
1889
		<bitfield name="UNK8" pos="8" type="boolean"/>
1890
	</reg32>
1891

1892
	<reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
1893
		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
1894
		<bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
1895
		<bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
1896
		<bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/>
1897
	</reg32>
1898
	<reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
1899
		<bitfield name="MRT" low="0" high="3" type="uint"/>
1900
	</reg32>
1901
	<reg32 offset="0x880d" name="RB_RENDER_COMPONENTS">
1902
		<bitfield name="RT0" low="0" high="3"/>
1903
		<bitfield name="RT1" low="4" high="7"/>
1904
		<bitfield name="RT2" low="8" high="11"/>
1905
		<bitfield name="RT3" low="12" high="15"/>
1906
		<bitfield name="RT4" low="16" high="19"/>
1907
		<bitfield name="RT5" low="20" high="23"/>
1908
		<bitfield name="RT6" low="24" high="27"/>
1909
		<bitfield name="RT7" low="28" high="31"/>
1910
	</reg32>
1911
	<reg32 offset="0x880e" name="RB_DITHER_CNTL">
1912
		<bitfield name="DITHER_MODE_MRT0" low="0"  high="1"  type="adreno_rb_dither_mode"/>
1913
		<bitfield name="DITHER_MODE_MRT1" low="2"  high="3"  type="adreno_rb_dither_mode"/>
1914
		<bitfield name="DITHER_MODE_MRT2" low="4"  high="5"  type="adreno_rb_dither_mode"/>
1915
		<bitfield name="DITHER_MODE_MRT3" low="6"  high="7"  type="adreno_rb_dither_mode"/>
1916
		<bitfield name="DITHER_MODE_MRT4" low="8"  high="9"  type="adreno_rb_dither_mode"/>
1917
		<bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
1918
		<bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/>
1919
		<bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
1920
	</reg32>
1921
	<reg32 offset="0x880f" name="RB_SRGB_CNTL">
1922
		<!-- Same as SP_SRGB_CNTL -->
1923
		<bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
1924
		<bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
1925
		<bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
1926
		<bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
1927
		<bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
1928
		<bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
1929
		<bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
1930
		<bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
1931
	</reg32>
1932

1933
	<reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
1934
		<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
1935
	</reg32>
1936
	<reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6"/>
1937
	<!-- 0x8812-0x8817 invalid -->
1938
	<!-- always 0x0 ? -->
1939
	<reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6"/>
1940
	<!-- 0x8819-0x881e all 32 bits -->
1941
	<reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
1942
	<reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
1943
	<reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
1944
	<reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
1945
	<reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
1946
	<reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>
1947
	<!-- 0x881f invalid -->
1948
	<array offset="0x8820" name="RB_MRT" stride="8" length="8">
1949
		<reg32 offset="0x0" name="CONTROL">
1950
			<bitfield name="BLEND" pos="0" type="boolean"/>
1951
			<bitfield name="BLEND2" pos="1" type="boolean"/>
1952
			<bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
1953
			<bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
1954
			<bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
1955
		</reg32>
1956
		<reg32 offset="0x1" name="BLEND_CONTROL">
1957
			<bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
1958
			<bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
1959
			<bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
1960
			<bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
1961
			<bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
1962
			<bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
1963
		</reg32>
1964
		<reg32 offset="0x2" name="BUF_INFO">
1965
			<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
1966
			<bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
1967
			<bitfield name="UNK10" pos="10"/>
1968
			<bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
1969
		</reg32>
1970
		<!--
1971
		at least in gmem, things seem to be aligned to pitch of 64..
1972
		maybe an artifact of tiled format used in gmem?
1973
		 -->
1974
		<reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/>
1975
		<reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/>
1976
		<!--
1977
		Compared to a5xx and before, we configure both a GMEM base and
1978
		external base.  Not sure if this is to facilitate GMEM save/
1979
		restore for context switch, or just to simplify state setup to
1980
		not have to care about GMEM vs BYPASS mode.
1981
		 -->
1982
		<!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
1983
		<reg64 offset="0x5" name="BASE" type="waddress" align="1"/>
1984

1985
		<reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/>
1986
	</array>
1987

1988
	<reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
1989
	<reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/>
1990
	<reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/>
1991
	<reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/>
1992
	<reg32 offset="0x8864" name="RB_ALPHA_CONTROL">
1993
		<bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
1994
		<bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
1995
		<bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
1996
	</reg32>
1997
	<reg32 offset="0x8865" name="RB_BLEND_CNTL">
1998
		<!-- per-mrt enable bit -->
1999
		<bitfield name="ENABLE_BLEND" low="0" high="7"/>
2000
		<bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2001
		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
2002
		<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2003
		<bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/>
2004
		<bitfield name="SAMPLE_MASK" low="16" high="31"/>
2005
	</reg32>
2006
	<!-- 0x8866-0x886f invalid -->
2007
	<reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
2008
		<bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
2009
	</reg32>
2010

2011
	<reg32 offset="0x8871" name="RB_DEPTH_CNTL">
2012
		<bitfield name="Z_ENABLE" pos="0" type="boolean"/>
2013
		<bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2014
		<bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2015
		<bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
2016
		<doc>
2017
		Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
2018
		also set when Z_BOUNDS_ENABLE is set
2019
		</doc>
2020
		<bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
2021
		<bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>
2022
	</reg32>
2023
	<!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2024
	<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
2025
		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2026
		<bitfield name="UNK3" low="3" high="4"/>
2027
	</reg32>
2028
	<reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint"/>
2029
	<reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint"/>
2030
	<reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64"/>
2031
	<reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
2032

2033
	<reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float"/>
2034
	<reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float"/>
2035
	<!-- 0x887a-0x887f invalid -->
2036
	<reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
2037
		<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2038
		<bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2039
		<!--
2040
			set for stencil operations that require read from stencil
2041
			buffer, but not for example for stencil clear (which does
2042
			not require read).. so guessing this is analogous to
2043
			READ_DEST_ENABLE for color buffer..
2044
		 -->
2045
		<bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2046
		<bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2047
		<bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2048
		<bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2049
		<bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2050
		<bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2051
		<bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2052
		<bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2053
		<bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2054
	</reg32>
2055
	<reg32 offset="0x8881" name="RB_STENCIL_INFO">
2056
		<bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2057
		<bitfield name="UNK1" pos="1" type="boolean"/>
2058
	</reg32>
2059
	<reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint"/>
2060
	<reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint"/>
2061
	<reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64"/>
2062
	<reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
2063
	<reg32 offset="0x8887" name="RB_STENCILREF">
2064
		<bitfield name="REF" low="0" high="7"/>
2065
		<bitfield name="BFREF" low="8" high="15"/>
2066
	</reg32>
2067
	<reg32 offset="0x8888" name="RB_STENCILMASK">
2068
		<bitfield name="MASK" low="0" high="7"/>
2069
		<bitfield name="BFMASK" low="8" high="15"/>
2070
	</reg32>
2071
	<reg32 offset="0x8889" name="RB_STENCILWRMASK">
2072
		<bitfield name="WRMASK" low="0" high="7"/>
2073
		<bitfield name="BFWRMASK" low="8" high="15"/>
2074
	</reg32>
2075
	<!-- 0x888a-0x888f invalid -->
2076
	<reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy"/>
2077
	<reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
2078
		<bitfield name="UNK0" pos="0" type="boolean"/>
2079
		<bitfield name="COPY" pos="1" type="boolean"/>
2080
	</reg32>
2081
	<!-- 0x8892-0x8897 invalid -->
2082
	<reg32 offset="0x8898" name="RB_LRZ_CNTL">
2083
		<bitfield name="ENABLE" pos="0" type="boolean"/>
2084
	</reg32>
2085
	<!-- 0x8899-0x88bf invalid -->
2086
	<!-- clamps depth value for depth test/write -->
2087
	<reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float"/>
2088
	<reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float"/>
2089
	<!-- 0x88c2-0x88cf invalid-->
2090
	<reg32 offset="0x88d0" name="RB_UNKNOWN_88D0">
2091
		<bitfield name="UNK0" low="0" high="12"/>
2092
		<bitfield name="UNK16" low="16" high="26"/>
2093
	</reg32>
2094
	<reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy"/>
2095
	<reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy"/>
2096
	<!-- weird to duplicate other regs from same block?? -->
2097
	<reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
2098
		<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
2099
		<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
2100
	</reg32>
2101
	<reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy"/>
2102
	<reg32 offset="0x88d5" name="RB_MSAA_CNTL">
2103
		<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2104
	</reg32>
2105
	<reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12"/>
2106
	<!-- s/DST_FORMAT/DST_INFO/ probably: -->
2107
	<reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
2108
		<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
2109
		<bitfield name="FLAGS" pos="2" type="boolean"/>
2110
		<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2111
		<bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
2112
		<bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
2113
		<bitfield name="UNK15" pos="15" type="boolean"/>
2114
	</reg32>
2115
	<reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64"/>
2116
	<reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
2117
	<!-- array-pitch is size of layer -->
2118
	<reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/>
2119
	<reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64"/>
2120
	<reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
2121
		<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2122
		<bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
2123
	</reg32>
2124

2125
	<reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
2126
	<reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/>
2127
	<reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/>
2128
	<reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/>
2129

2130
	<!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2131
	<reg32 offset="0x88e3" name="RB_BLIT_INFO">
2132
		<bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear?  But also color restore? -->
2133
		<bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2134
		<bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging -->
2135
		<bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2136
		<doc>
2137
			For clearing depth/stencil
2138
				1 - depth
2139
				2 - stencil
2140
				3 - depth+stencil
2141
			For clearing color buffer:
2142
				then probably a component mask, I always see 0xf
2143
		</doc>
2144
		<bitfield name="CLEAR_MASK" low="4" high="7"/>
2145
		<bitfield name="UNK8" low="8" high="9"/>
2146
		<bitfield name="UNK12" low="12" high="15"/>
2147
	</reg32>
2148
	<!-- 0x88e4-0x88ef invalid -->
2149
	<!-- always 0x0 ? -->
2150
	<reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11"/>
2151
	<!-- could be for separate stencil? (or may not be a flag buffer at all) -->
2152
	<reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/>
2153
	<reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH">
2154
		<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2155
		<bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/>
2156
	</reg32>
2157
	<reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>
2158
	<!-- 0x88f5-0x88ff invalid -->
2159
	<reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64"/>
2160
	<reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2161
		<bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>
2162
		<!-- TODO: actually part of array pitch -->
2163
		<bitfield name="UNK8" low="8" high="10"/>
2164
		<bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
2165
	</reg32>
2166
	<array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
2167
		<reg64 offset="0" name="ADDR" type="waddress" align="64"/>
2168
		<reg32 offset="2" name="PITCH">
2169
			<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2170
			<bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/>
2171
		</reg32>
2172
	</array>
2173
	<!-- 0x891b-0x8926 invalid -->
2174
	<reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16"/>
2175
	<!-- 0x8929-0x89ff invalid -->
2176

2177
	<!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
2178

2179
	<reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2180
	<reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31"/>
2181

2182
	<bitset name="a6xx_2d_surf_info" inline="yes">
2183
		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2184
		<bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2185
		<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2186
		<bitfield name="FLAGS" pos="12" type="boolean"/>
2187
		<bitfield name="SRGB" pos="13" type="boolean"/>
2188
		<!-- the rest is only for src -->
2189
		<bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
2190
		<bitfield name="FILTER" pos="16" type="boolean"/>
2191
		<bitfield name="UNK17" pos="17" type="boolean"/>
2192
		<bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
2193
		<bitfield name="UNK19" pos="19" type="boolean"/>
2194
		<bitfield name="UNK20" pos="20" type="boolean"/>
2195
		<bitfield name="UNK21" pos="21" type="boolean"/>
2196
		<bitfield name="UNK22" pos="22" type="boolean"/>
2197
		<bitfield name="UNK23" low="23" high="26"/>
2198
		<bitfield name="UNK28" pos="28" type="boolean"/>
2199
	</bitset>
2200

2201
	<!-- 0x8c02-0x8c16 invalid -->
2202
	<!-- TODO: RB_2D_DST_INFO has 17 valid bits (doesn't match a6xx_2d_surf_info) -->
2203
	<reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
2204
	<reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64"/>
2205
	<reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
2206
	<!-- this is a guess but seems likely (for NV12/IYUV): -->
2207
	<reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64"/>
2208
	<reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint"/>
2209
	<reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64"/>
2210

2211
	<reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64"/>
2212
	<reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint"/>
2213
	<!-- this is a guess but seems likely (for NV12 with UBWC): -->
2214
	<reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64"/>
2215
	<reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint"/>
2216

2217
	<!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->
2218
	<!-- unlike a5xx, these are per channel values rather than packed -->
2219
	<reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/>
2220
	<reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/>
2221
	<reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/>
2222
	<reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/>
2223
	<!-- 0x8c34-0x8dff invalid -->
2224

2225
	<!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
2226
	<reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/>
2227
	<!-- 0x8e00-0x8e03 invalid -->
2228
	<reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/> <!-- TODO: valid mask 0xfffffeff -->
2229
	<reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
2230
	<!-- 0x8e06 invalid -->
2231
	<reg32 offset="0x8e07" name="RB_CCU_CNTL">
2232
		<!-- GMEM offset of CCU color cache
2233
			CCU depth cache starts at zero, so this should be the size
2234
			of the depth cache for direct rendering
2235
			for GMEM rendering, we set it to GMEM size minus the minimum
2236
			CCU color cache size. CCU color cache will be needed in some
2237
			resolve cases, and in those cases we need to reserve the end
2238
			of GMEM for color cache.
2239
		-->
2240
		<bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
2241
		<bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path -->
2242
		<bitfield name="UNK2" pos="2" type="boolean"/> <!-- sometimes set with GMEM? -->
2243
		<!--TODO: valid mask 0xfffffc1f -->
2244
	</reg32>
2245
	<reg32 offset="0x8e08" name="RB_NC_MODE_CNTL">
2246
		<bitfield name="MODE" pos="0" type="boolean"/>
2247
		<bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
2248
		<bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
2249
		<bitfield name="AMSBC" pos="4" type="boolean"/>
2250
		<bitfield name="UPPER_BIT" pos="10" type="uint"/>
2251
		<bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/>
2252
		<bitfield name="UNK12" low="12" high="13"/>
2253
	</reg32>
2254
	<!-- 0x8e09-0x8e0f invalid -->
2255
	<array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/>
2256
	<array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/>
2257
	<!-- 0x8e1d-0x8e1f invalid -->
2258
	<!-- 0x8e20-0x8e25 more perfcntr sel? -->
2259
	<!-- 0x8e26-0x8e27 invalid -->
2260
	<reg32 offset="0x8e28" name="RB_UNKNOWN_8E28" low="0" high="10"/>
2261
	<!-- 0x8e29-0x8e2b invalid -->
2262
	<array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>
2263
	<reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
2264
	<reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
2265
	<!-- 0x8e3e-0x8e4f invalid -->
2266
	<!-- GMEM save/restore for preemption: -->
2267
	<reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/>
2268
	<!-- address for GMEM save/restore? -->
2269
	<reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/>
2270
	<!-- 0x8e53-0x8e7f invalid -->
2271
	<!-- 0x8e80-0x8e83 are valid -->
2272
	<!-- 0x8e84-0x90ff invalid -->
2273

2274
	<!-- 0x9000-0x90ff invalid -->
2275

2276
	<!-- something to do with geometry shader: -->
2277
	<reg32 offset="0x9100" name="VPC_UNKNOWN_9100" low="0" high="7"/>
2278

2279
	<bitset name="a6xx_vpc_xs_clip_cntl" inline="yes">
2280
		<bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
2281
		<!-- there can be up to 8 total clip/cull distance outputs,
2282
		     but apparenly VPC can only deal with vec4, so when there are
2283
		     more than 4 outputs a second location needs to be programmed
2284
		-->
2285
		<bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/>
2286
		<bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/>
2287
	</bitset>
2288
	<reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
2289
	<reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
2290
	<reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
2291

2292
	<bitset name="a6xx_vpc_xs_layer_cntl" inline="yes">
2293
		<bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
2294
		<bitfield name="VIEWLOC" low="8" high="15" type="uint"/>
2295
	</bitset>
2296

2297
	<reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
2298
	<reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
2299
	<reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
2300

2301
	<reg32 offset="0x9107" name="VPC_UNKNOWN_9107">
2302
		<!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused -->
2303
		<bitfield name="RASTER_DISCARD" pos="0" type="boolean"/>
2304
		<bitfield name="UNK2" pos="2" type="boolean"/>
2305
	</reg32>
2306
	<reg32 offset="0x9108" name="VPC_POLYGON_MODE">
2307
		<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
2308
	</reg32>
2309
	<!-- 0x9109-0x91ff invalid -->
2310
	<array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
2311
		<reg32 offset="0x0" name="MODE"/>
2312
	</array>
2313
	<array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2314
		<reg32 offset="0x0" name="MODE"/>
2315
	</array>
2316

2317
	<!-- always 0x0 -->
2318
	<reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31"/>
2319
	<reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31"/>
2320

2321
	<array offset="0x9212" name="VPC_VAR" stride="1" length="4">
2322
		<!-- one bit per varying component: -->
2323
		<reg32 offset="0" name="DISABLE"/>
2324
	</array>
2325

2326
	<reg32 offset="0x9216" name="VPC_SO_CNTL">
2327
		<!--
2328
			Choose which DWORD to write to. There is an array of
2329
			(4 * 64) DWORD's, dumped in the devcoredump at
2330
			HLSQ_INST_RAM dword 0x400. Each DWORD corresponds to a
2331
			(VPC location, stream) pair like so:
2332

2333
			location 0, stream 0
2334
			location 2, stream 0
2335
			...
2336
			location 126, stream 0
2337
			location 0, stream 1
2338
			location 2, stream 1
2339
			...
2340
			location 126, stream 1
2341
			location 0, stream 2
2342
			...
2343

2344
			When EmitStreamVertex(N) happens, the HW goes to DWORD
2345
			64 * N and then "executes" the next 64 DWORD's.
2346

2347
			This field is auto-incremented when VPC_SO_PROG is
2348
			written to.
2349
		-->
2350
		<bitfield name="ADDR" low="0" high="7" type="hex"/>
2351
		<!-- clear all A_EN and B_EN bits for all DWORD's -->
2352
		<bitfield name="RESET" pos="16" type="boolean"/>
2353
	</reg32>
2354
	<!-- special register, write multiple times to load SO program (not readable) -->
2355
	<reg32 offset="0x9217" name="VPC_SO_PROG">
2356
		<bitfield name="A_BUF" low="0" high="1" type="uint"/>
2357
		<bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
2358
		<bitfield name="A_EN" pos="11" type="boolean"/>
2359
		<bitfield name="B_BUF" low="12" high="13" type="uint"/>
2360
		<bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
2361
		<bitfield name="B_EN" pos="23" type="boolean"/>
2362
	</reg32>
2363

2364
	<reg64 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32"/>
2365

2366
	<array offset="0x921a" name="VPC_SO" stride="7" length="4">
2367
		<reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
2368
		<reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
2369
		<reg32 offset="3" name="NCOMP" low="0" high="9"/>  <!-- component count -->
2370
		<reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>
2371
		<reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/>
2372
	</array>
2373

2374
	<reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT">
2375
		<bitfield name="INVERT" pos="0" type="boolean"/>
2376
	</reg32>
2377
	<!-- 0x9237-0x92ff invalid -->
2378
	<!-- always 0x0 ? -->
2379
	<reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2"/>
2380

2381
	<bitset name="a6xx_vpc_xs_pack" inline="yes">
2382
		<doc>
2383
			num of varyings plus four for gl_Position (plus one if gl_PointSize)
2384
			plus # of transform-feedback (streamout) varyings if using the
2385
			hw streamout (rather than stg instructions in shader)
2386
		</doc>
2387
		<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2388
		<bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
2389
		<bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2390
		<bitfield name="EXTRAPOS" low="24" high="27" type="uint">
2391
			<doc>
2392
				The number of extra copies of POSITION, i.e.
2393
				number of views minus one when multi-position
2394
				output is enabled, otherwise 0.
2395
			</doc>
2396
		</bitfield>
2397
	</bitset>
2398
	<reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack"/>
2399
	<reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack"/>
2400
	<reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack"/>
2401

2402
	<reg32 offset="0x9304" name="VPC_CNTL_0">
2403
		<bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
2404
		<!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
2405
		<bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/>
2406
		<bitfield name="VARYING" pos="16" type="boolean"/>
2407
		<bitfield name="VIEWIDLOC" low="24" high="31" type="uint">
2408
			<doc>
2409
				This VPC location will be overwritten with
2410
				ViewID when multiview is enabled. It's used when
2411
				fragment shaders read ViewID. It's only
2412
				strictly required for multi-position output,
2413
				where the same VS invocation is used for all the
2414
				views at once, but it can be used when multi-pos
2415
				output is disabled too, to avoid having to pass
2416
				ViewID through the VS.
2417
			</doc>
2418
		</bitfield>
2419
	</reg32>
2420

2421
	<reg32 offset="0x9305" name="VPC_SO_STREAM_CNTL">
2422
		<!--
2423
		It's offset by 1, and 0 means "disabled"
2424
		-->
2425
		<bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/>
2426
		<bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/>
2427
		<bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/>
2428
		<bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/>
2429
		<bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
2430
	</reg32>
2431
	<reg32 offset="0x9306" name="VPC_SO_DISABLE">
2432
		<bitfield name="DISABLE" pos="0" type="boolean"/>
2433
	</reg32>
2434
	<!-- 0x9307-0x95ff invalid -->
2435

2436
	<!-- TODO: 0x9600-0x97ff range -->
2437
	<reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -->
2438
	<reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
2439
	<reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0"/> <!-- always 0x0 ? -->
2440
	<reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>
2441
	<array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6"/>
2442
	<!-- 0x960a-0x9623 invalid -->
2443
	<!-- TODO: regs from 0x9624-0x963a -->
2444
	<!-- 0x963b-0x97ff invalid -->
2445

2446
	<reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint"/>
2447

2448
	<!-- always 0x0 ? -->
2449
	<reg32 offset="0x9801" name="PC_HS_INPUT_SIZE">
2450
		<bitfield name="SIZE" low="0" high="10"/>
2451
		<bitfield name="UNK13" pos="13"/>
2452
	</reg32>
2453

2454
	<enum name="a6xx_tess_spacing">
2455
		<value value="0x0" name="TESS_EQUAL"/>
2456
		<value value="0x2" name="TESS_FRACTIONAL_ODD"/>
2457
		<value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
2458
	</enum>
2459
	<enum name="a6xx_tess_output">
2460
		<value value="0x0" name="TESS_POINTS"/>
2461
		<value value="0x1" name="TESS_LINES"/>
2462
		<value value="0x2" name="TESS_CW_TRIS"/>
2463
		<value value="0x3" name="TESS_CCW_TRIS"/>
2464
	</enum>
2465
	<reg32 offset="0x9802" name="PC_TESS_CNTL">
2466
		<bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
2467
		<bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
2468
	</reg32>
2469

2470
	<reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint"/>
2471
	<reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7"/>
2472

2473
	<!-- always 0x1 ? -->
2474
	<reg32 offset="0x9805" name="PC_UNKNOWN_9805" low="0" high="2"/>
2475

2476
	<!-- probably a mirror of VFD_CONTROL_6 -->
2477
	<reg32 offset="0x9806" name="PC_PRIMID_PASSTHRU" pos="0" type="boolean"/>
2478
	<!-- 0x980b-0x983f invalid -->
2479

2480
	<!-- 0x9840 - 0x9842 are not readable -->
2481
	<reg32 offset="0x9840" name="PC_DRAW_CMD">
2482
		<bitfield name="STATE_ID" low="0" high="7"/>
2483
	</reg32>
2484

2485
	<reg32 offset="0x9841" name="PC_DISPATCH_CMD">
2486
		<bitfield name="STATE_ID" low="0" high="7"/>
2487
	</reg32>
2488

2489
	<reg32 offset="0x9842" name="PC_EVENT_CMD">
2490
		<!-- I think only the low bit is actually used? -->
2491
		<bitfield name="STATE_ID" low="16" high="23"/>
2492
		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
2493
	</reg32>
2494

2495
	<!--
2496
		0x9880 written in a lot of places by SQE, same value gets written
2497
		to control reg 0x12a.  Set by CP_SET_MARKER, so lets name it after
2498
		that
2499
	 -->
2500
	<reg32 offset="0x9880" name="PC_MARKER"/>
2501

2502
	<!-- 0x9843-0x997f invalid -->
2503

2504
	<reg32 offset="0x9981" name="PC_POLYGON_MODE">
2505
		<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
2506
	</reg32>
2507

2508
	<reg32 offset="0x9980" name="PC_RASTER_CNTL">
2509
		<!-- which stream to send to GRAS -->
2510
		<bitfield name="STREAM" low="0" high="1" type="uint"/>
2511
		<!-- discard primitives before rasterization -->
2512
		<bitfield name="DISCARD" pos="2" type="boolean"/>
2513
	</reg32>
2514

2515
	<!-- 0x9982-0x9aff invalid -->
2516

2517
	<reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
2518
		<bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
2519
		<!-- maybe?  b1 seems always set, so just assume it is for now: -->
2520
		<bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
2521
		<bitfield name="TESS_UPPER_LEFT_DOMAIN_ORIGIN" pos="2" type="boolean"/>
2522
		<bitfield name="UNK3" pos="3" type="boolean"/>
2523
	</reg32>
2524

2525
	<bitset name="a6xx_xs_out_cntl" inline="yes">
2526
		<doc>
2527
			num of varyings plus four for gl_Position (plus one if gl_PointSize)
2528
			plus # of transform-feedback (streamout) varyings if using the
2529
			hw streamout (rather than stg instructions in shader)
2530
		</doc>
2531
		<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2532
		<bitfield name="PSIZE" pos="8" type="boolean"/>
2533
		<bitfield name="LAYER" pos="9" type="boolean"/>
2534
		<bitfield name="VIEW" pos="10" type="boolean"/>
2535
		<!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->
2536
		<bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
2537
		<bitfield name="CLIP_MASK" low="16" high="23" type="uint"/>
2538
	</bitset>
2539

2540
	<reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
2541
	<reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
2542
	<reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3" pos="11"/>
2543
	<reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
2544

2545
	<reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
2546
		<doc>
2547
		  geometry shader
2548
		</doc>
2549
		<!-- TODO: first 16 bits are valid so something is wrong or missing here -->
2550
		<bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
2551
		<bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
2552
		<bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
2553
		<bitfield name="UNK18" pos="18"/>
2554
	</reg32>
2555

2556
	<reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
2557
		<doc>
2558
		  size in vec4s of per-primitive storage for gs. TODO: not actually in VPC
2559
		</doc>
2560
		<bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/>
2561
	</reg32>
2562

2563
	<bitset name="a6xx_multiview_cntl" inline="yes">
2564
		<bitfield name="ENABLE" pos="0" type="boolean"/>
2565
		<bitfield name="DISABLEMULTIPOS" pos="1" type="boolean">
2566
			<doc>
2567
				Multi-position output lets the last geometry
2568
				stage shader write multiple copies of
2569
				gl_Position. If disabled then the VS is run once
2570
				for each view, and ViewID is passed as a
2571
				register to the VS.
2572
			</doc>
2573
		</bitfield>
2574
		<bitfield name="VIEWS" low="2" high="6" type="uint"/>
2575
	</bitset>
2576

2577
	<reg32 offset="0x9b07" name="PC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl"/>
2578
	<!-- mask of enabled views, doesn't exist on A630 -->
2579
	<reg32 offset="0x9b08" name="PC_MULTIVIEW_MASK" type="hex" low="0" high="15"/>
2580
	<!-- 0x9b09-0x9bff invalid -->
2581
	<reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">
2582
		<!-- special register (but note first 8 bits can be written/read) -->
2583
		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
2584
		<bitfield name="STATE_ID" low="8" high="15"/>
2585
	</reg32>
2586
	<!-- 0x9c01-0x9dff invalid -->
2587
	<!-- TODO: 0x9e00-0xa000 range incomplete -->
2588
	<reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
2589
	<reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
2590
	<reg64 offset="0x9e04" name="PC_DRAW_INDX_BASE"/>
2591
	<reg32 offset="0x9e06" name="PC_DRAW_FIRST_INDX" type="uint"/>
2592
	<reg32 offset="0x9e07" name="PC_DRAW_MAX_INDICES" type="uint"/>
2593
	<reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" type="waddress" align="32"/>
2594

2595
	<reg32 offset="0x9e0b" name="PC_DRAW_INITIATOR" type="vgt_draw_initiator_a4xx">
2596
		<doc>
2597
			Possibly not really "initiating" the draw but the layout is similar
2598
			to VGT_DRAW_INITIATOR on older gens
2599
		</doc>
2600
	</reg32>
2601
	<reg32 offset="0x9e0c" name="PC_DRAW_NUM_INSTANCES" type="uint"/>
2602
	<reg32 offset="0x9e0d" name="PC_DRAW_NUM_INDICES" type="uint"/>
2603

2604
	<!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
2605
	<reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
2606
		<bitfield name="UNK0" low="0" high="15"/>
2607
		<bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
2608
		<bitfield name="VSC_N" low="22" high="26" type="uint"/>
2609
	</reg32>
2610
	<reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/>
2611
	<reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/>
2612

2613
	<reg32 offset="0x9e1c" name="PC_VISIBILITY_OVERRIDE">
2614
		<doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc>
2615
		<bitfield name="OVERRIDE" pos="0" type="boolean"/>
2616
	</reg32>
2617

2618
	<array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8"/>
2619

2620
	<!-- always 0x0 -->
2621
	<reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
2622

2623
	<reg32 offset="0xa000" name="VFD_CONTROL_0">
2624
		<bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
2625
		<bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>
2626
	</reg32>
2627
	<reg32 offset="0xa001" name="VFD_CONTROL_1">
2628
		<bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
2629
		<bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
2630
		<bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
2631
		<!-- only used for VS in non-multi-position-output case -->
2632
		<bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/>
2633
	</reg32>
2634
	<reg32 offset="0xa002" name="VFD_CONTROL_2">
2635
		<bitfield name="REGID_HSPATCHID" low="0" high="7" type="a3xx_regid"/>
2636
		<bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
2637
	</reg32>
2638
	<reg32 offset="0xa003" name="VFD_CONTROL_3">
2639
		<bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/>
2640
		<bitfield name="REGID_DSPATCHID" low="8" high="15" type="a3xx_regid"/>
2641
		<bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
2642
		<bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
2643
	</reg32>
2644
	<reg32 offset="0xa004" name="VFD_CONTROL_4">
2645
		<bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/>
2646
	</reg32>
2647
	<reg32 offset="0xa005" name="VFD_CONTROL_5">
2648
		<bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
2649
		<bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/>
2650
	</reg32>
2651
	<reg32 offset="0xa006" name="VFD_CONTROL_6">
2652
		<!--
2653
			True if gl_PrimitiveID is read via the FS and there is
2654
			no matching write from the GS, and therefore it needs to
2655
			be passed through via fixed-function logic.
2656
		-->
2657
		<bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
2658
	</reg32>
2659

2660
	<reg32 offset="0xa007" name="VFD_MODE_CNTL">
2661
		<bitfield name="BINNING_PASS" pos="0" type="boolean"/>
2662
		<bitfield name="UNK1" pos="1" type="boolean"/>
2663
		<bitfield name="UNK2" pos="2" type="boolean"/>
2664
	</reg32>
2665

2666
	<reg32 offset="0xa008" name="VFD_MULTIVIEW_CNTL" type="a6xx_multiview_cntl"/>
2667
	<reg32 offset="0xa009" name="VFD_ADD_OFFSET">
2668
		<!-- add VFD_INDEX_OFFSET to REGID4VTX -->
2669
		<bitfield name="VERTEX" pos="0" type="boolean"/>
2670
		<!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
2671
		<bitfield name="INSTANCE" pos="1" type="boolean"/>
2672
	</reg32>
2673

2674
	<reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
2675
	<reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
2676
	<array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
2677
		<reg64 offset="0x0" name="BASE" type="address" align="1"/>
2678
		<reg32 offset="0x2" name="SIZE" type="uint"/>
2679
		<reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/>
2680
	</array>
2681
	<array offset="0xa090" name="VFD_DECODE" stride="2" length="32">
2682
		<reg32 offset="0x0" name="INSTR">
2683
			<!-- IDX and byte OFFSET into VFD_FETCH -->
2684
			<bitfield name="IDX" low="0" high="4" type="uint"/>
2685
			<bitfield name="OFFSET" low="5" high="16"/>
2686
			<bitfield name="INSTANCED" pos="17" type="boolean"/>
2687
			<bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
2688
			<bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
2689
			<bitfield name="UNK30" pos="30" type="boolean"/>
2690
			<bitfield name="FLOAT" pos="31" type="boolean"/>
2691
		</reg32>
2692
		<reg32 offset="0x1" name="STEP_RATE" type="uint"/>
2693
	</array>
2694
	<array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32">
2695
		<reg32 offset="0x0" name="INSTR">
2696
			<bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
2697
			<bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
2698
		</reg32>
2699
	</array>
2700

2701
	<!-- 0 on 618, 1 on 630/640, 2 on a650? (SP count - 1) ? -->
2702
	<reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8" low="0" high="2"/>
2703

2704
	<!--
2705
	Note: this seems to always be paired with another bit in another
2706
	block.
2707
	-->
2708
	<enum name="a6xx_threadsize">
2709
		<value value="0" name="THREAD64"/>
2710
		<value value="1" name="THREAD128"/>
2711
	</enum>
2712
	<reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
2713
	<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8"/>
2714

2715
	<bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
2716
		<!-- if set to SINGLE, only use 1 concurrent wave on each SP -->
2717
		<bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
2718
		<!--
2719
		When b31 set we just see FULLREGFOOTPRINT set.  The pattern of
2720
		used registers is a bit odd too:
2721
			- used (half): 0-15 68-179 (cnt=128, max=179)
2722
			- used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
2723
		whereas we usually see a (mostly) contiguous range of regs used.  But if
2724
		I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
2725
		then:
2726
			- used (merged): 0-191 (cnt=192, max=191)
2727
		So I think if b31 is set, then the half precision registers overlap
2728
		the full precision registers.  (Which seems like a pretty sensible
2729
		feature, actually I'm not sure when you *wouldn't* want to use that,
2730
		since it gives register allocation more flexibility)
2731
		 -->
2732
		<bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
2733
		<bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
2734
		<!-- could it be a low bit of branchstack? -->
2735
		<bitfield name="UNK13" pos="13" type="boolean"/>
2736
		<!-- seems to be nesting level for flow control:.. -->
2737
		<bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
2738
	</bitset>
2739

2740
	<bitset name="a6xx_sp_xs_config" inline="yes">
2741
		<!--
2742
		Each of these are set if the given resource type is used
2743
		with the Vulkan/bindless binding model.
2744
		-->
2745
		<bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
2746
		<bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
2747
		<bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
2748
		<bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
2749

2750
		<bitfield name="ENABLED" pos="8" type="boolean"/>
2751
		<!--
2752
		number of textures and samplers.. these might be swapped, with GL I
2753
		always see the same value for both.
2754
		 -->
2755
		<bitfield name="NTEX" low="9" high="16" type="uint"/>
2756
		<bitfield name="NSAMP" low="17" high="21" type="uint"/>
2757
		<bitfield name="NIBO" low="22" high="28" type="uint"/>
2758
	</bitset>
2759

2760
	<bitset name="a6xx_sp_xs_prim_cntl" inline="yes">
2761
		<!-- # of VS outputs including pos/psize -->
2762
		<bitfield name="OUT" low="0" high="5" type="uint"/>
2763
		<!-- FLAGS_REGID only for GS -->
2764
		<bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
2765
	</bitset>
2766

2767
	<reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
2768
		<bitfield name="MERGEDREGS" pos="20" type="boolean"/>
2769
		<!-- ??? (blob has it set) -->
2770
		<bitfield name="UNK21" pos="21" type="boolean"/>
2771
	</reg32>
2772
	<!-- bitmask of true/false conditions for VS brac.N instructions,
2773
	     bit N corresponds to brac.N -->
2774
	<reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex"/>
2775
	<!-- # of VS outputs including pos/psize -->
2776
	<reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl"/>
2777
	<array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
2778
		<reg32 offset="0x0" name="REG">
2779
			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2780
			<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2781
			<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2782
			<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2783
		</reg32>
2784
	</array>
2785
	<!--
2786
	Starting with a5xx, position/psize outputs from shader end up in the
2787
	SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
2788
	the last entries too, except when gl_PointCoord is used, blob inserts
2789
	an extra varying after, but with a lower OUTLOC position.  If present,
2790
	psize is last, preceded by position.
2791
	 -->
2792
	<array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
2793
		<reg32 offset="0x0" name="REG">
2794
			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2795
			<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2796
			<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2797
			<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2798
		</reg32>
2799
	</array>
2800

2801
	<bitset name="a6xx_sp_xs_pvt_mem_param" inline="yes">
2802
		<bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9">
2803
			<doc>The size of memory that ldp/stp can address.</doc>
2804
		</bitfield>
2805
		<bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31">
2806
                        <doc>
2807
				Seems to be the same as a3xx. The maximum stack
2808
				size in units of 4 calls, so a call depth of 7
2809
				would result in a value of 2.
2810
				TODO: What's the actual size per call, i.e. the
2811
				size of the PC? a3xx docs say it's 16 bits
2812
				there, but the length register now takes 28 bits
2813
				so it's probably been bumped to 32 bits.
2814
                        </doc>
2815
		</bitfield>
2816
	</bitset>
2817

2818
	<bitset name="a6xx_sp_xs_pvt_mem_size" inline="yes">
2819
		<bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/>
2820
		<bitfield name="PERWAVEMEMLAYOUT" pos="31" type="boolean">
2821
			<doc>
2822
				There are four indices used to compute the
2823
				private memory location for an access:
2824

2825
				- stp/ldp offset
2826
				- fiber id
2827
				- wavefront id (a swizzled version of what "getwid" returns)
2828
				- SP ID (the same as what "getspid" returns)
2829

2830
				The stride for the SP ID is always set by
2831
				TOTALPVTMEMSIZE. In the per-wave layout, the
2832
				indices are used in this order:
2833

2834
				- offset % 4 (offset within dword)
2835
				- fiber id
2836
				- offset / 4
2837
				- wavefront id
2838
				- SP ID
2839

2840
				and the stride for the wavefront ID is
2841
				MEMSIZEPERITEM, multiplied by 128 (fibers per
2842
				wavefront). In the per-fiber layout, the indices
2843
				are used in this order:
2844

2845
				- offset
2846
				- fiber id % 4
2847
				- wavefront id
2848
				- fiber id / 4
2849
				- SP ID
2850

2851
				and the stride for the fiber id/wavefront id
2852
				combo is MEMSIZEPERITEM.
2853

2854
				Note: Accesses of more than 1 dword do not work
2855
				with per-fiber layout. The blob will fall back
2856
				to per-wave instead.
2857
			</doc>
2858
		</bitfield>
2859
	</bitset>
2860

2861
	<bitset name="a6xx_sp_xs_pvt_mem_hw_stack_offset" inline="yes">
2862
		<doc>
2863
			This seems to be be the equivalent of HWSTACKOFFSET in
2864
			a3xx. The ldp/stp offset formula above isn't affected by
2865
			HWSTACKSIZEPERTHREAD at all, so the HW return address
2866
			stack seems to be after all the normal per-SP private
2867
			memory.
2868
		</doc>
2869
		<bitfield name="OFFSET" low="0" high="18" shr="11"/>
2870
	</bitset>
2871

2872
	<reg32 offset="0xa81b" name="SP_VS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
2873
	<reg64 offset="0xa81c" name="SP_VS_OBJ_START" type="address" align="32"/>
2874
	<reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
2875
	<reg64 offset="0xa81f" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32"/>
2876
	<reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
2877
	<reg32 offset="0xa822" name="SP_VS_TEX_COUNT" low="0" high="7" type="uint"/>
2878
	<reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/>
2879
	<reg32 offset="0xa824" name="SP_VS_INSTRLEN" low="0" high="27" type="uint"/>
2880
	<reg32 offset="0xa825" name="SP_VS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
2881

2882
	<reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
2883
		<!--
2884
		There is no mergedregs bit, that comes from the previous stage (VS).
2885
		No idea what this bit does here.
2886
		-->
2887
		<bitfield name="UNK20" pos="20" type="boolean"/>
2888
	</reg32>
2889
	<!--
2890
	Total size of local storage in dwords divided by the wave size.
2891
	The maximum value is 64. With the wave size being always 64 for HS,
2892
	the maximum size of local storage should be:
2893
	 64 (wavesize) * 64 (SP_HS_WAVE_INPUT_SIZE) * 4 = 16k
2894
	-->
2895
	<reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint"/>
2896
	<reg32 offset="0xa832" name="SP_HS_BRANCH_COND" type="hex"/>
2897

2898
	<!-- TODO: exact same layout as 0xa81b-0xa825 -->
2899
	<reg32 offset="0xa833" name="SP_HS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
2900
	<reg64 offset="0xa834" name="SP_HS_OBJ_START" type="address" align="32"/>
2901
	<reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
2902
	<reg64 offset="0xa837" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32"/>
2903
	<reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
2904
	<reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" low="0" high="7" type="uint"/>
2905
	<reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/>
2906
	<reg32 offset="0xa83c" name="SP_HS_INSTRLEN" low="0" high="27" type="uint"/>
2907
	<reg32 offset="0xa83d" name="SP_HS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
2908

2909
	<reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
2910
		<bitfield name="MERGEDREGS" pos="20" type="boolean"/>
2911
	</reg32>
2912
	<reg32 offset="0xa841" name="SP_DS_BRANCH_COND" type="hex"/>
2913

2914
	<!-- TODO: exact same layout as 0xa802-0xa81a -->
2915
	<reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl"/>
2916
	<array offset="0xa843" name="SP_DS_OUT" stride="1" length="16">
2917
		<reg32 offset="0x0" name="REG">
2918
			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2919
			<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2920
			<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2921
			<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2922
		</reg32>
2923
	</array>
2924
	<array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8">
2925
		<reg32 offset="0x0" name="REG">
2926
			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2927
			<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2928
			<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2929
			<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2930
		</reg32>
2931
	</array>
2932

2933
	<!-- TODO: exact same layout as 0xa81b-0xa825 -->
2934
	<reg32 offset="0xa85b" name="SP_DS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
2935
	<reg64 offset="0xa85c" name="SP_DS_OBJ_START" type="address" align="32"/>
2936
	<reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
2937
	<reg64 offset="0xa85f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32"/>
2938
	<reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
2939
	<reg32 offset="0xa862" name="SP_DS_TEX_COUNT" low="0" high="7" type="uint"/>
2940
	<reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/>
2941
	<reg32 offset="0xa864" name="SP_DS_INSTRLEN" low="0" high="27" type="uint"/>
2942
	<reg32 offset="0xa865" name="SP_DS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
2943

2944
	<reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
2945
		<!--
2946
		There is no mergedregs bit, that comes from the previous stage (VS/DS).
2947
		No idea what this bit does here.
2948
		-->
2949
		<bitfield name="UNK20" pos="20" type="boolean"/>
2950
	</reg32>
2951
	<reg32 offset="0xa871" name="SP_GS_PRIM_SIZE" low="0" high="7" type="uint">
2952
		<doc>
2953
			Normally the size of the output of the last stage in
2954
			dwords. It should be programmed as follows:
2955

2956
			size less than 63    - size
2957
			size of 63 (?) or 64 - 63
2958
			size greater than 64 - 64
2959

2960
			What to program when the size is 61-63 is a guess, but
2961
			both the blob and ir3 align the size to 4 dword's so it
2962
			doesn't matter in practice.
2963
		</doc>
2964
	</reg32>
2965
	<reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex"/>
2966

2967
	<!-- TODO: exact same layout as 0xa802-0xa81a -->
2968
	<reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl"/>
2969
	<array offset="0xa874" name="SP_GS_OUT" stride="1" length="16">
2970
		<reg32 offset="0x0" name="REG">
2971
			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2972
			<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2973
			<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2974
			<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2975
		</reg32>
2976
	</array>
2977

2978
	<array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8">
2979
		<reg32 offset="0x0" name="REG">
2980
			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2981
			<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2982
			<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2983
			<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2984
		</reg32>
2985
	</array>
2986

2987
	<!-- TODO: exact same layout as 0xa81b-0xa825 -->
2988
	<reg32 offset="0xa88c" name="SP_GS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
2989
	<reg64 offset="0xa88d" name="SP_GS_OBJ_START" type="address" align="32"/>
2990
	<reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
2991
	<reg64 offset="0xa890" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32"/>
2992
	<reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
2993
	<reg32 offset="0xa893" name="SP_GS_TEX_COUNT" low="0" high="7" type="uint"/>
2994
	<reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/>
2995
	<reg32 offset="0xa895" name="SP_GS_INSTRLEN" low="0" high="27" type="uint"/>
2996
	<reg32 offset="0xa896" name="SP_GS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
2997

2998
	<reg64 offset="0xa8a0" name="SP_VS_TEX_SAMP" type="address" align="16"/>
2999
	<reg64 offset="0xa8a2" name="SP_HS_TEX_SAMP" type="address" align="16"/>
3000
	<reg64 offset="0xa8a4" name="SP_DS_TEX_SAMP" type="address" align="16"/>
3001
	<reg64 offset="0xa8a6" name="SP_GS_TEX_SAMP" type="address" align="16"/>
3002
	<reg64 offset="0xa8a8" name="SP_VS_TEX_CONST" type="address" align="64"/>
3003
	<reg64 offset="0xa8aa" name="SP_HS_TEX_CONST" type="address" align="64"/>
3004
	<reg64 offset="0xa8ac" name="SP_DS_TEX_CONST" type="address" align="64"/>
3005
	<reg64 offset="0xa8ae" name="SP_GS_TEX_CONST" type="address" align="64"/>
3006

3007
	<!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 -->
3008

3009
	<reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
3010
		<bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>
3011
		<bitfield name="UNK21" pos="21" type="boolean"/>
3012
		<bitfield name="VARYING" pos="22" type="boolean"/>
3013
		<bitfield name="DIFF_FINE" pos="23" type="boolean"/>
3014
		<!-- note: vk blob uses bit24 -->
3015
		<bitfield name="UNK24" pos="24" type="boolean"/>
3016
		<bitfield name="UNK25" pos="25" type="boolean"/>
3017
		<bitfield name="PIXLODENABLE" pos="26" type="boolean"/>
3018
		<bitfield name="UNK27" low="27" high="28"/>
3019
		<bitfield name="MERGEDREGS" pos="31" type="boolean"/>
3020
	</reg32>
3021
	<reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex"/>
3022
	<reg32 offset="0xa982" name="SP_FS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
3023
	<reg64 offset="0xa983" name="SP_FS_OBJ_START" type="address" align="32"/>
3024
	<reg32 offset="0xa985" name="SP_FS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
3025
	<reg64 offset="0xa986" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32"/>
3026
	<reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
3027

3028
	<reg32 offset="0xa989" name="SP_BLEND_CNTL">
3029
		<!-- per-mrt enable bit -->
3030
		<bitfield name="ENABLE_BLEND" low="0" high="7"/>
3031
		<bitfield name="UNK8" pos="8" type="boolean"/>
3032
		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
3033
		<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
3034
	</reg32>
3035
	<reg32 offset="0xa98a" name="SP_SRGB_CNTL">
3036
		<!-- Same as RB_SRGB_CNTL -->
3037
		<bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
3038
		<bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
3039
		<bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
3040
		<bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
3041
		<bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
3042
		<bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
3043
		<bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
3044
		<bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
3045
	</reg32>
3046
	<reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS">
3047
		<bitfield name="RT0" low="0" high="3"/>
3048
		<bitfield name="RT1" low="4" high="7"/>
3049
		<bitfield name="RT2" low="8" high="11"/>
3050
		<bitfield name="RT3" low="12" high="15"/>
3051
		<bitfield name="RT4" low="16" high="19"/>
3052
		<bitfield name="RT5" low="20" high="23"/>
3053
		<bitfield name="RT6" low="24" high="27"/>
3054
		<bitfield name="RT7" low="28" high="31"/>
3055
	</reg32>
3056
	<reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0">
3057
		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
3058
		<bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
3059
		<bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
3060
		<bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/>
3061
	</reg32>
3062
	<reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
3063
		<bitfield name="MRT" low="0" high="3" type="uint"/>
3064
	</reg32>
3065

3066
	<array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
3067
		<doc>per MRT</doc>
3068
		<reg32 offset="0x0" name="REG">
3069
			<bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
3070
			<bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
3071
		</reg32>
3072
	</array>
3073

3074
	<array offset="0xa996" name="SP_FS_MRT" stride="1" length="8">
3075
		<reg32 offset="0" name="REG">
3076
			<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3077
			<bitfield name="COLOR_SINT" pos="8" type="boolean"/>
3078
			<bitfield name="COLOR_UINT" pos="9" type="boolean"/>
3079
			<bitfield name="UNK10" pos="10" type="boolean"/>
3080
		</reg32>
3081
	</array>
3082

3083
	<reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL">
3084
		<!-- unknown bits 0x7fc0 always set -->
3085
		<bitfield name="COUNT" low="0" high="2" type="uint"/>
3086
		<!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? -->
3087
		<bitfield name="UNK3" pos="3" type="boolean"/>
3088
		<bitfield name="UNK4" low="4" high="11" type="a3xx_regid"/>
3089
		<bitfield name="UNK12" low="12" high="14"/>
3090
	</reg32>
3091
	<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4">
3092
		<reg32 offset="0" name="CMD">
3093
			<bitfield name="SRC" low="0" high="6" type="uint"/>
3094
			<bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
3095
			<bitfield name="TEX_ID" low="11" high="15" type="uint"/>
3096
			<bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
3097
			<bitfield name="WRMASK" low="22" high="25" type="hex"/>
3098
			<bitfield name="HALF" pos="26" type="boolean"/>
3099
			<!--
3100
			CMD seems always 0x4??  3d, textureProj, textureLod seem to
3101
			skip pre-fetch.. TODO test texelFetch
3102
                        CMD is 0x6 when the Vulkan mode is enabled, and
3103
                        TEX_ID/SAMP_ID refer to the descriptor sets while the
3104
                        indices come from SP_FS_BINDLESS_PREFETCH[n]
3105
			 -->
3106
			<bitfield name="CMD" low="27" high="31"/>
3107
		</reg32>
3108
	</array>
3109
	<array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4">
3110
		<reg32 offset="0" name="CMD">
3111
			<bitfield name="SAMP_ID" low="0" high="15" type="uint"/>
3112
			<bitfield name="TEX_ID" low="16" high="31" type="uint"/>
3113
		</reg32>
3114
	</array>
3115
	<reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" low="0" high="7" type="uint"/>
3116
	<reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" /> <!-- always 0x0 ? -->
3117
	<reg32 offset="0xa9a9" name="SP_FS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
3118

3119
	<!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS -->
3120

3121

3122

3123

3124
	<reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0">
3125
		<bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>
3126
		<!-- seems to make SP use less concurrent threads when possible? -->
3127
		<bitfield name="UNK21" pos="21" type="boolean"/>
3128
		<!-- has a small impact on performance, not clear what it does -->
3129
		<bitfield name="UNK22" pos="22" type="boolean"/>
3130
		<!-- creates a separate prolog-only thread? -->
3131
		<bitfield name="SEPARATEPROLOG" pos="23" type="boolean"/>
3132
		<bitfield name="MERGEDREGS" pos="31" type="boolean"/>
3133
	</reg32>
3134

3135
	<!-- set for compute shaders -->
3136
	<reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1">
3137
		<bitfield name="SHARED_SIZE" low="0" high="4" type="uint">
3138
			<doc>
3139
				If 0 - all 32k of shared storage is enabled, otherwise
3140
				(SHARED_SIZE + 1) * 1k is enabled.
3141
				The ldl/stl offset seems to be rewritten to 0 when it is beyond
3142
				this limit. This is different from ldlw/stlw, which wraps at
3143
				64k (and has 36k of storage on A640 - reads between 36k-64k
3144
				always return 0)
3145
			</doc>
3146
		</bitfield>
3147
		<bitfield name="UNK5" pos="5" type="boolean"/>
3148
		<!-- always 1 ? -->
3149
		<bitfield name="UNK6" pos="6" type="boolean"/>
3150
	</reg32>
3151
	<reg32 offset="0xa9b2" name="SP_CS_BRANCH_COND" type="hex"/>
3152
	<reg32 offset="0xa9b3" name="SP_CS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
3153
	<reg64 offset="0xa9b4" name="SP_CS_OBJ_START" type="address" align="32"/>
3154
	<reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
3155
	<reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_ADDR" align="32"/>
3156
	<reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
3157
	<reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" low="0" high="7" type="uint"/>
3158
	<reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/>
3159
	<reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" low="0" high="27" type="uint"/>
3160
	<reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/>
3161

3162
	<!-- TODO: two 64kb aligned addresses at a9d0/a9d2 -->
3163

3164
	<reg64 offset="0xa9e0" name="SP_FS_TEX_SAMP" type="address" align="16"/>
3165
	<reg64 offset="0xa9e2" name="SP_CS_TEX_SAMP" type="address" align="16"/>
3166
	<reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64"/>
3167
	<reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64"/>
3168

3169
	<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5">
3170
		<!-- TODO: probably align=64 with 6 flags bits in the low bits ? -->
3171
		<reg64 offset="0" name="ADDR" type="address"/>
3172
	</array>
3173

3174
	<!--
3175
	IBO state for compute shader:
3176
	 -->
3177
	<reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/>
3178
	<reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/>
3179

3180
	<reg32 offset="0xab00" name="SP_MODE_CONTROL">
3181
	  <!--
3182
	  When set, half register loads from the constant file will
3183
	  load a 32-bit value (so hc0.y loads the same value as c0.y)
3184
	  and implicitly convert it to 16b (f2f16, or u2u16, based on
3185
	  operand type).  When unset, half register loads from the
3186
	  constant file will load 16 bits from the packed constant
3187
	  file (so hc0.y loads the top 16 bits of the value of c0.x)
3188
	  -->
3189
		<bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/>
3190
		<bitfield name="UNK1" pos="1" type="boolean"/> <!-- never set by VK blob -->
3191
		<bitfield name="UNK2" pos="2" type="boolean"/> <!-- always set by VK blob -->
3192
		<bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS -->
3193
	</reg32>
3194

3195
	<reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
3196
	<reg32 offset="0xab05" name="SP_FS_INSTRLEN" low="0" high="27" type="uint"/>
3197

3198
	<array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5">
3199
		<!-- TODO: probably align=64 with 6 flags bits in the low bits? -->
3200
		<reg64 offset="0" name="ADDR" type="address"/>
3201
	</array>
3202

3203
	<!--
3204
	Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
3205
	instructions VS/HS/DS/GS/FS.  See SP_CS_IBO_* for compute shaders.
3206
	 -->
3207
	<reg64 offset="0xab1a" name="SP_IBO" type="address" align="16"/>
3208
	<reg32 offset="0xab20" name="SP_IBO_COUNT" low="0" high="6" type="uint"/>
3209

3210
	<reg32 offset="0xacc0" name="SP_2D_DST_FORMAT">
3211
		<bitfield name="NORM" pos="0" type="boolean"/>
3212
		<bitfield name="SINT" pos="1" type="boolean"/>
3213
		<bitfield name="UINT" pos="2" type="boolean"/>
3214
		<!-- looks like HW only cares about the base type of this format,
3215
		     which matches the ifmt? -->
3216
		<bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>
3217
		<!-- set when ifmt is R2D_UNORM8_SRGB -->
3218
		<bitfield name="SRGB" pos="11" type="boolean"/>
3219
		<!-- some sort of channel mask, not sure what it is for -->
3220
		<bitfield name="MASK" low="12" high="15"/>
3221
	</reg32>
3222

3223
	<reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/>
3224
	<reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
3225
	<reg32 offset="0xae02" name="SP_NC_MODE_CNTL">
3226
		<!-- TODO: valid bits 0x3c3f, see kernel -->
3227
	</reg32>
3228
	<reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/>
3229
	<reg32 offset="0xae04" name="SP_FLOAT_CNTL">
3230
		<bitfield name="F16_NO_INF" pos="3" type="boolean"/>
3231
	</reg32>
3232

3233
	<reg32 offset="0xae0f" name="SP_PERFCTR_ENABLE">
3234
		<!-- some perfcntrs are affected by a per-stage enable bit
3235
		     (PERF_SP_ALU_WORKING_CYCLES for example)
3236
		     TODO: verify position of HS/DS/GS bits -->
3237
		<bitfield name="VS" pos="0" type="boolean"/>
3238
		<bitfield name="HS" pos="1" type="boolean"/>
3239
		<bitfield name="DS" pos="2" type="boolean"/>
3240
		<bitfield name="GS" pos="3" type="boolean"/>
3241
		<bitfield name="FS" pos="4" type="boolean"/>
3242
		<bitfield name="CS" pos="5" type="boolean"/>
3243
	</reg32>
3244
	<array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/>
3245
	<!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
3246
	<!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
3247

3248
	<!--
3249
	The downstream kernel calls the debug cluster of registers
3250
	"a6xx_sp_ps_tp_cluster" but this actually specifies the border
3251
	color base for compute shaders.
3252
	-->
3253
	<reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128"/>
3254
	<reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2"/>
3255
	<reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23"/>
3256

3257
	<reg32 offset="0xb190" name="SP_UNKNOWN_B190"/>
3258
	<reg32 offset="0xb191" name="SP_UNKNOWN_B191"/>
3259

3260
	<!-- could be all the stuff below here is actually TPL1?? -->
3261

3262
	<reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL">
3263
		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3264
		<bitfield name="UNK2" low="2" high="3"/>
3265
	</reg32>
3266
	<reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL">
3267
		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3268
		<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
3269
	</reg32>
3270

3271
	<!-- looks to work in the same way as a5xx: -->
3272
	<reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128"/>
3273
	<reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config"/>
3274
	<reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
3275
	<reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
3276
	<reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="a6xx_reg_xy"/>
3277
	<reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309" low="0" high="7" type="uint"/>
3278

3279
	<!--
3280
	Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
3281
	badly named or the functionality moved in a6xx.  But downstream kernel
3282
	calls this "a6xx_sp_ps_tp_2d_cluster"
3283
	 -->
3284
	<reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info"/>
3285
	<reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE">
3286
		<bitfield name="WIDTH" low="0" high="14" type="uint"/>
3287
		<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3288
	</reg32>
3289
	<reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="address" align="16"/>
3290
	<reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
3291
		<bitfield name="UNK0" low="0" high="8"/>
3292
		<bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>
3293
	</reg32>
3294

3295
	<!-- planes for NV12, etc. (TODO: not tested) -->
3296
	<reg64 offset="0xb4c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16"/>
3297
	<reg32 offset="0xb4c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint"/>
3298
	<reg64 offset="0xb4c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16"/>
3299

3300
	<reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16"/>
3301
	<reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint"/>
3302

3303
	<reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31"/>
3304
	<reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31"/>
3305
	<reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30"/>
3306
	<reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29"/>
3307
	<reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy"/>
3308

3309
	<!-- always 0x100000 or 0x1000000? -->
3310
	<reg32 offset="0xb600" name="TPL1_UNKNOWN_B600" low="0" high="25"/>
3311
	<reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
3312
	<reg32 offset="0xb602" name="TPL1_UNKNOWN_B602" low="0" high="7" type="uint"/>
3313
	<reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL">
3314
		<bitfield name="MODE" pos="0" type="boolean"/>
3315
		<bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
3316
		<bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
3317
		<bitfield name="UPPER_BIT" pos="4" type="uint"/>
3318
		<bitfield name="UNK6" low="6" high="7"/>
3319
	</reg32>
3320
	<reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint"/> <!-- always 0x0 or 0x44 ? -->
3321
	<reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29"/>
3322
	<reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29"/>
3323
	<reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29"/>
3324
	<reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29"/>
3325
	<reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29"/>
3326
	<array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12"/>
3327

3328
	<!-- TODO: 4 more perfcntr sel at 0xb620 ? -->
3329

3330
	<bitset name="a6xx_hlsq_xs_cntl" inline="yes">
3331
		<bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
3332
		<bitfield name="ENABLED" pos="8" type="boolean"/>
3333
	</bitset>
3334

3335
	<reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3336
	<reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3337
	<reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3338
	<reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3339

3340
	<reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/>
3341
	<reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR" align="16" type="address"/>
3342
	<reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/>
3343

3344
	<reg32 offset="0xb980" name="HLSQ_FS_CNTL_0">
3345
		<!-- must match SP_FS_CTRL -->
3346
		<bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/>
3347
		<bitfield name="VARYINGS" pos="1" type="boolean"/>
3348
		<bitfield name="UNK2" low="2" high="11"/>
3349
	</reg32>
3350
	<reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean"/> <!-- never used by blob -->
3351

3352
	<reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2">
3353
		<!-- TODO: have test cases with either 0x3 or 0x7 -->
3354
	</reg32>
3355
	<reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG">
3356
		<bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
3357
		<!-- SAMPLEID is loaded into a half-precision register: -->
3358
		<bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
3359
		<bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
3360
		<!--
3361
		SIZE is the "size" of the primitive, ie. what the i/j coords need
3362
		to be divided by to scale to a single fragment.  It is probably
3363
		the longer of the two lines that form the tri (ie v0v1 and v0v2)?
3364
		 -->
3365
		<bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/>
3366
	</reg32>
3367
	<reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
3368
		<!-- register loaded with position (bary.f) -->
3369
		<bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
3370
		<bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
3371
		<bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
3372
		<bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
3373
	</reg32>
3374
	<reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
3375
		<bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
3376
		<bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
3377
		<bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
3378
		<bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
3379
	</reg32>
3380
	<reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
3381
		<bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/>
3382
		<bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/>
3383
	</reg32>
3384
	<reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3385

3386
	<!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
3387
	<reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0">
3388
		<bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
3389
		<!-- localsize is value minus one: -->
3390
		<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
3391
		<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
3392
		<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
3393
	</reg32>
3394
	<reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1">
3395
		<bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
3396
	</reg32>
3397
	<reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2">
3398
		<bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
3399
	</reg32>
3400
	<reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3">
3401
		<bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
3402
	</reg32>
3403
	<reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4">
3404
		<bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
3405
	</reg32>
3406
	<reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5">
3407
		<bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
3408
	</reg32>
3409
	<reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6">
3410
		<bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
3411
	</reg32>
3412
	<reg32 offset="0xb997" name="HLSQ_CS_CNTL_0">
3413
		<!-- these are all vec3. first 3 need to be high regs
3414
		     WGSIZECONSTID is the local size (from HLSQ_CS_NDRANGE_0)
3415
		     WGOFFSETCONSTID is WGIDCONSTID*WGSIZECONSTID
3416
		-->
3417
		<bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
3418
		<bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>
3419
		<bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>
3420
		<bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
3421
	</reg32>
3422
	<reg32 offset="0xb998" name="HLSQ_CS_CNTL_1">
3423
		<!-- gl_LocalInvocationIndex -->
3424
		<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
3425
		<!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
3426
		     one of those 6 "SP cores" -->
3427
		<bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/>
3428
		<!-- Must match SP_CS_CTRL -->
3429
		<bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
3430
		<!-- 1 thread per wave (ignored if bit9 set) -->
3431
		<bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/>
3432
	</reg32>
3433
	<!--note: vulkan blob doesn't use these -->
3434
	<reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/>
3435
	<reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
3436
	<reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>
3437

3438
	<reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/>
3439
	<reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR" align="16" type="address"/>
3440
	<reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/>
3441

3442
	<!-- mirror of SP_CS_BINDLESS_BASE -->
3443
	<array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5">
3444
		<!-- 64 alignment, 2 low bits for unknown flags (always 0x3 when enabled?) -->
3445
		<reg64 offset="0" name="ADDR" type="waddress"/>
3446
	</array>
3447

3448
	<reg32 offset="0xbb00" name="HLSQ_DRAW_CMD">
3449
		<bitfield name="STATE_ID" low="0" high="7"/>
3450
	</reg32>
3451

3452
	<reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD">
3453
		<bitfield name="STATE_ID" low="0" high="7"/>
3454
	</reg32>
3455

3456
	<reg32 offset="0xbb02" name="HLSQ_EVENT_CMD">
3457
		<!-- I think only the low bit is actually used? -->
3458
		<bitfield name="STATE_ID" low="16" high="23"/>
3459
		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
3460
	</reg32>
3461

3462
	<reg32 offset="0xbb08" name="HLSQ_INVALIDATE_CMD">
3463
		<doc>
3464
			This register clears pending loads queued up by
3465
			CP_LOAD_STATE6. Each bit resets a particular kind(s) of
3466
			CP_LOAD_STATE6.
3467
		</doc>
3468

3469
		<!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
3470
		<bitfield name="VS_STATE" pos="0" type="boolean"/>
3471
		<bitfield name="HS_STATE" pos="1" type="boolean"/>
3472
		<bitfield name="DS_STATE" pos="2" type="boolean"/>
3473
		<bitfield name="GS_STATE" pos="3" type="boolean"/>
3474
		<bitfield name="FS_STATE" pos="4" type="boolean"/>
3475
		<bitfield name="CS_STATE" pos="5" type="boolean"/>
3476

3477
		<bitfield name="CS_IBO" pos="6" type="boolean"/>
3478
		<bitfield name="GFX_IBO" pos="7" type="boolean"/>
3479

3480
		<!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 -->
3481
		<bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/>
3482
		<bitfield name="GFX_SHARED_CONST" pos="8" type="boolean"/>
3483

3484
		<!-- SS6_BINDLESS: one bit per bindless base -->
3485
		<bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/>
3486
		<bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/>
3487
	</reg32>
3488

3489
	<reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3490

3491
	<reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS">
3492
		<doc>
3493
			Shared constants are intended to be used for Vulkan push
3494
			constants. When enabled, 8 vec4's are reserved in the FS
3495
			const pool and 16 in the geometry const pool although
3496
			only 8 are actually used (why?) and they are mapped to
3497
			c504-c511 in each stage. Both VS and FS shared consts
3498
			are written using ST6_CONSTANTS/SB6_IBO, so that both
3499
			the geometry and FS shared consts can be written at once
3500
			by using CP_LOAD_STATE6 rather than
3501
			CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition
3502
			DST_OFF and NUM_UNIT are in units of dwords instead of
3503
			vec4's.
3504

3505
			There is also a separate shared constant pool for CS,
3506
			which is loaded through CP_LOAD_STATE6_FRAG with
3507
			ST6_UBO/ST6_IBO. However the only real difference for CS
3508
			is the dword units.
3509
		</doc>
3510
		<bitfield name="ENABLE" pos="0" type="boolean"/>
3511
	</reg32>
3512

3513
	<!-- mirror of SP_BINDLESS_BASE -->
3514
	<array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5">
3515
		<!-- align 64 with two LSB for unknown flags (always 0x3 enabled) -->
3516
		<reg64 offset="0" name="ADDR" type="address"/>
3517
	</array>
3518

3519
	<reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD">
3520
		<bitfield name="STATE_ID" low="8" high="15"/>
3521
		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
3522
	</reg32>
3523

3524
	<reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/> <!-- all bits valid except bit 29 -->
3525
	<reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6"/>
3526
	<reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/>
3527
	<reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
3528
	<reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/>
3529
	<array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/>
3530

3531
	<!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
3532

3533
	<!--
3534
		These special registers signal the beginning/end of an event
3535
		sequence. The sequence used internally for an event looks like:
3536
		- write EVENT_CMD pipe register
3537
		- write CP_EVENT_START
3538
		- write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD
3539
		- write PC_EVENT_CMD with event or PC_DRAW_CMD
3540
		- write HLSQ_EVENT_CMD(CONTEXT_DONE)
3541
		- write PC_EVENT_CMD(CONTEXT_DONE)
3542
		- write CP_EVENT_END
3543
		Writing to CP_EVENT_END seems to actually trigger the context roll
3544
	-->
3545
	<reg32 offset="0xd600" name="CP_EVENT_START">
3546
		<bitfield name="STATE_ID" low="0" high="7"/>
3547
	</reg32>
3548
	<reg32 offset="0xd601" name="CP_EVENT_END">
3549
		<bitfield name="STATE_ID" low="0" high="7"/>
3550
	</reg32>
3551
	<reg32 offset="0xd700" name="CP_2D_EVENT_START">
3552
		<bitfield name="STATE_ID" low="0" high="7"/>
3553
	</reg32>
3554
	<reg32 offset="0xd701" name="CP_2D_EVENT_END">
3555
		<bitfield name="STATE_ID" low="0" high="7"/>
3556
	</reg32>
3557
</domain>
3558

3559
<!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
3560
<domain name="A6XX_TEX_SAMP" width="32">
3561
	<doc>Texture sampler dwords</doc>
3562
	<enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
3563
		<value name="A6XX_TEX_NEAREST" value="0"/>
3564
		<value name="A6XX_TEX_LINEAR" value="1"/>
3565
		<value name="A6XX_TEX_ANISO" value="2"/>
3566
		<value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
3567
	</enum>
3568
	<enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
3569
		<value name="A6XX_TEX_REPEAT" value="0"/>
3570
		<value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
3571
		<value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
3572
		<value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
3573
		<value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
3574
	</enum>
3575
	<enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
3576
		<value name="A6XX_TEX_ANISO_1" value="0"/>
3577
		<value name="A6XX_TEX_ANISO_2" value="1"/>
3578
		<value name="A6XX_TEX_ANISO_4" value="2"/>
3579
		<value name="A6XX_TEX_ANISO_8" value="3"/>
3580
		<value name="A6XX_TEX_ANISO_16" value="4"/>
3581
	</enum>
3582
	<enum name="a6xx_reduction_mode">
3583
		<value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>
3584
		<value name="A6XX_REDUCTION_MODE_MIN" value="1"/>
3585
		<value name="A6XX_REDUCTION_MODE_MAX" value="2"/>
3586
	</enum>
3587

3588
	<reg32 offset="0" name="0">
3589
		<bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
3590
		<bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
3591
		<bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
3592
		<bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
3593
		<bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
3594
		<bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
3595
		<bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
3596
		<bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
3597
	</reg32>
3598
	<reg32 offset="1" name="1">
3599
		<!-- bit 0 always set with vulkan? -->
3600
		<bitfield name="UNK0" pos="0" type="boolean"/>
3601
		<bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
3602
		<bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
3603
		<bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
3604
		<bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
3605
		<bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
3606
		<bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
3607
	</reg32>
3608
	<reg32 offset="2" name="2">
3609
		<bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
3610
		<bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/>
3611
		<bitfield name="BCOLOR" low="7" high="31"/>
3612
	</reg32>
3613
	<reg32 offset="3" name="3"/>
3614
</domain>
3615

3616
<domain name="A6XX_TEX_CONST" width="32">
3617
	<doc>Texture constant dwords</doc>
3618
	<enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
3619
		<value name="A6XX_TEX_X" value="0"/>
3620
		<value name="A6XX_TEX_Y" value="1"/>
3621
		<value name="A6XX_TEX_Z" value="2"/>
3622
		<value name="A6XX_TEX_W" value="3"/>
3623
		<value name="A6XX_TEX_ZERO" value="4"/>
3624
		<value name="A6XX_TEX_ONE" value="5"/>
3625
	</enum>
3626
	<enum name="a6xx_tex_type"> <!-- same as a4xx? -->
3627
		<value name="A6XX_TEX_1D" value="0"/>
3628
		<value name="A6XX_TEX_2D" value="1"/>
3629
		<value name="A6XX_TEX_CUBE" value="2"/>
3630
		<value name="A6XX_TEX_3D" value="3"/>
3631
	</enum>
3632
	<reg32 offset="0" name="0">
3633
		<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3634
		<bitfield name="SRGB" pos="2" type="boolean"/>
3635
		<bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
3636
		<bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
3637
		<bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
3638
		<bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
3639
		<bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
3640
		<!-- overlaps with MIPLVLS -->
3641
		<bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/>
3642
		<bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/>
3643
		<bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
3644
		<bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3645
		<bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
3646
	</reg32>
3647
	<reg32 offset="1" name="1">
3648
		<bitfield name="WIDTH" low="0" high="14" type="uint"/>
3649
		<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3650
	</reg32>
3651
	<reg32 offset="2" name="2">
3652
		<!--
3653
		b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3654
		of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3655

3656
		b31 is probably the 'BUFFER' bit.. it is the one that changes
3657
		behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
3658
		 -->
3659
		<bitfield name="UNK4" pos="4" type="boolean"/>
3660
                <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
3661
		<bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
3662
		<doc>Pitch in bytes (so actually stride)</doc>
3663
		<bitfield name="PITCH" low="7" high="28" type="uint"/>
3664
		<bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3665
		<bitfield name="UNK31" pos="31" type="boolean"/>
3666
	</reg32>
3667
	<reg32 offset="3" name="3">
3668
		<!--
3669
		ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3670
		for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3671
		layer size at the point that it stops being reduced moving to
3672
		higher (smaller) mipmap levels
3673
		 -->
3674
		<bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3675
		<bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
3676
		<!--
3677
		by default levels with w < 16 are linear
3678
		TILE_ALL makes all levels have tiling
3679
		seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
3680
		 -->
3681
		<bitfield name="TILE_ALL" pos="27" type="boolean"/>
3682
		<bitfield name="FLAG" pos="28" type="boolean"/>
3683
	</reg32>
3684
	<!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
3685
	     the address of the non-flag base buffer is determined automatically,
3686
	     and must follow the flag buffer
3687
	 -->
3688
	<reg32 offset="4" name="4">
3689
		<bitfield name="BASE_LO" low="5" high="31" shr="5"/>
3690
	</reg32>
3691
	<reg32 offset="5" name="5">
3692
		<bitfield name="BASE_HI" low="0" high="16"/>
3693
		<bitfield name="DEPTH" low="17" high="29" type="uint"/>
3694
	</reg32>
3695
	<reg32 offset="6" name="6">
3696
		<!-- pitch for plane 2 / plane 3 -->
3697
		<bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/>
3698
	</reg32>
3699
	<!-- 7/8 is plane 2 address for planar formats -->
3700
	<reg32 offset="7" name="7">
3701
		<bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
3702
	</reg32>
3703
	<reg32 offset="8" name="8">
3704
		<bitfield name="FLAG_HI" low="0" high="16"/>
3705
	</reg32>
3706
	<!-- 9/10 is plane 3 address for planar formats -->
3707
	<reg32 offset="9" name="9">
3708
		<bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3709
	</reg32>
3710
	<reg32 offset="10" name="10">
3711
		<bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3712
		<!-- log2 size of the first level, required for mipmapping -->
3713
		<bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
3714
		<bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
3715
	</reg32>
3716
	<reg32 offset="11" name="11"/>
3717
	<reg32 offset="12" name="12"/>
3718
	<reg32 offset="13" name="13"/>
3719
	<reg32 offset="14" name="14"/>
3720
	<reg32 offset="15" name="15"/>
3721
</domain>
3722

3723
<!--
3724
Note the "SSBO" state blocks are actually used for both images and SSBOs,
3725
naming is just because I r/e'd SSBOs first.  I should probably come up
3726
with a better name.
3727
-->
3728
<domain name="A6XX_IBO" width="32">
3729
	<reg32 offset="0" name="0">
3730
		<!--
3731
		NOTE: same position as in TEX_CONST state.. I don't see other bits
3732
		used but if they are good chance position is same as TEX_CONST
3733
		 -->
3734
		<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3735
		<bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
3736
	</reg32>
3737
	<reg32 offset="1" name="1">
3738
		<bitfield name="WIDTH" low="0" high="14" type="uint"/>
3739
		<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3740
	</reg32>
3741
	<reg32 offset="2" name="2">
3742
		<!--
3743
		b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3744
		of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3745
		 -->
3746
		<bitfield name="UNK4" pos="4" type="boolean"/>
3747
		<doc>Pitch in bytes (so actually stride)</doc>
3748
		<bitfield name="PITCH" low="7" high="28" type="uint"/>
3749
		<bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3750
		<bitfield name="UNK31" pos="31" type="boolean"/>
3751
	</reg32>
3752
	<reg32 offset="3" name="3">
3753
		<!--
3754
		ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3755
		for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3756
		layer size at the point that it stops being reduced moving to
3757
		higher (smaller) mipmap levels
3758
		 -->
3759
		<bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3760
		<bitfield name="UNK27" pos="27" type="boolean"/>
3761
		<bitfield name="FLAG" pos="28" type="boolean"/>
3762
	</reg32>
3763
	<reg32 offset="4" name="4">
3764
		<bitfield name="BASE_LO" low="0" high="31"/>
3765
	</reg32>
3766
	<reg32 offset="5" name="5">
3767
		<bitfield name="BASE_HI" low="0" high="16"/>
3768
		<bitfield name="DEPTH" low="17" high="29" type="uint"/>
3769
	</reg32>
3770
	<reg32 offset="6" name="6">
3771
	</reg32>
3772
	<reg32 offset="7" name="7">
3773
	</reg32>
3774
	<reg32 offset="8" name="8">
3775
	</reg32>
3776
	<reg32 offset="9" name="9">
3777
		<bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3778
	</reg32>
3779
	<reg32 offset="10" name="10">
3780
		<!--
3781
		I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
3782
		don't seem to be particularly sensible... or needed for UBWC to work
3783
		 -->
3784
		<bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3785
	</reg32>
3786
</domain>
3787

3788
<domain name="A6XX_UBO" width="32">
3789
	<reg32 offset="0" name="0">
3790
		<bitfield name="BASE_LO" low="0" high="31"/>
3791
	</reg32>
3792
	<reg32 offset="1" name="1">
3793
		<bitfield name="BASE_HI" low="0" high="16"/>
3794
		<bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
3795
	</reg32>
3796
</domain>
3797

3798
<domain name="A6XX_PDC" width="32">
3799
	<reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
3800
	<reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
3801
	<reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
3802
	<reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
3803
	<reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
3804
	<reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
3805
	<reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
3806
	<reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
3807
	<reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
3808
	<reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
3809
	<reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
3810
	<reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
3811
	<reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
3812
	<reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
3813
	<reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
3814
	<reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
3815
	<reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
3816
	<reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
3817
	<reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
3818
	<reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
3819
	<reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
3820
	<reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
3821
	<reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
3822
	<reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
3823
	<reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
3824
	<reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
3825
</domain>
3826

3827
<domain name="A6XX_PDC_GPU_SEQ" width="32">
3828
	<reg32 offset="0x0" name="MEM_0"/>
3829
</domain>
3830

3831
<domain name="A6XX_CX_DBGC" width="32">
3832
	<reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
3833
		<bitfield high="7" low="0" name="PING_INDEX"/>
3834
		<bitfield high="15" low="8" name="PING_BLK_SEL"/>
3835
	</reg32>
3836
	<reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
3837
	<reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
3838
	<reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
3839
	<reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
3840
		<bitfield high="5" low="0" name="TRACEEN"/>
3841
		<bitfield high="14" low="12" name="GRANU"/>
3842
		<bitfield high="31" low="28" name="SEGT"/>
3843
	</reg32>
3844
	<reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
3845
		<bitfield high="27" low="24" name="ENABLE"/>
3846
	</reg32>
3847
	<reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
3848
	<reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
3849
	<reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
3850
	<reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
3851
	<reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
3852
	<reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
3853
	<reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
3854
	<reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
3855
	<reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
3856
		<bitfield high="3" low="0" name="BYTEL0"/>
3857
		<bitfield high="7" low="4" name="BYTEL1"/>
3858
		<bitfield high="11" low="8" name="BYTEL2"/>
3859
		<bitfield high="15" low="12" name="BYTEL3"/>
3860
		<bitfield high="19" low="16" name="BYTEL4"/>
3861
		<bitfield high="23" low="20" name="BYTEL5"/>
3862
		<bitfield high="27" low="24" name="BYTEL6"/>
3863
		<bitfield high="31" low="28" name="BYTEL7"/>
3864
	</reg32>
3865
	<reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
3866
		<bitfield high="3" low="0" name="BYTEL8"/>
3867
		<bitfield high="7" low="4" name="BYTEL9"/>
3868
		<bitfield high="11" low="8" name="BYTEL10"/>
3869
		<bitfield high="15" low="12" name="BYTEL11"/>
3870
		<bitfield high="19" low="16" name="BYTEL12"/>
3871
		<bitfield high="23" low="20" name="BYTEL13"/>
3872
		<bitfield high="27" low="24" name="BYTEL14"/>
3873
		<bitfield high="31" low="28" name="BYTEL15"/>
3874
	</reg32>
3875

3876
	<reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
3877
	<reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
3878
</domain>
3879

3880
<domain name="A6XX_CX_MISC" width="32">
3881
	<reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
3882
	<reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
3883
</domain>
3884

3885
</database>
3886

3887
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