CoCalc -- adreno

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/freedreno/registers/adreno/adreno_pm4.xml
⁸³⁶² views
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<?xml version="1.0" encoding="UTF-8"?>
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<database xmlns="http://nouveau.freedesktop.org/"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
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<enum name="vgt_event_type">
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	<value name="VS_DEALLOC" value="0"/>
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	<value name="PS_DEALLOC" value="1"/>
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	<value name="VS_DONE_TS" value="2"/>
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	<value name="PS_DONE_TS" value="3"/>
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	<value name="CACHE_FLUSH_TS" value="4"/>
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	<value name="CONTEXT_DONE" value="5"/>
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	<value name="CACHE_FLUSH" value="6"/>
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	<value name="VIZQUERY_START" value="7" varset="chip" variants="A2XX"/>
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	<value name="HLSQ_FLUSH" value="7" varset="chip" variants="A3XX-A4XX"/>
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	<value name="VIZQUERY_END" value="8" varset="chip" variants="A2XX"/>
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	<value name="SC_WAIT_WC" value="9" varset="chip" variants="A2XX"/>
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	<value name="WRITE_PRIMITIVE_COUNTS" value="9" varset="chip" variants="A6XX"/>
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	<value name="START_PRIMITIVE_CTRS" value="11" varset="chip" variants="A6XX"/>
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	<value name="STOP_PRIMITIVE_CTRS" value="12" varset="chip" variants="A6XX"/>
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	<value name="RST_PIX_CNT" value="13"/>
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	<value name="RST_VTX_CNT" value="14"/>
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	<value name="TILE_FLUSH" value="15"/>
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	<value name="STAT_EVENT" value="16"/>
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	<value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" varset="chip" variants="A2XX-A4XX"/>
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	<value name="ZPASS_DONE" value="21"/>
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	<value name="CACHE_FLUSH_AND_INV_EVENT" value="22" varset="chip" variants="A2XX"/>
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	<value name="RB_DONE_TS" value="22" varset="chip" variants="A3XX-"/>
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	<value name="PERFCOUNTER_START" value="23" varset="chip" variants="A2XX-A4XX"/>
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	<value name="PERFCOUNTER_STOP" value="24" varset="chip" variants="A2XX-A4XX"/>
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	<value name="VS_FETCH_DONE" value="27"/>
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	<value name="FACENESS_FLUSH" value="28" varset="chip" variants="A2XX-A4XX"/>
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	<!-- a5xx events -->
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	<value name="WT_DONE_TS" value="8" varset="chip" variants="A5XX-"/>
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	<value name="FLUSH_SO_0" value="17" varset="chip" variants="A5XX-"/>
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	<value name="FLUSH_SO_1" value="18" varset="chip" variants="A5XX-"/>
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	<value name="FLUSH_SO_2" value="19" varset="chip" variants="A5XX-"/>
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	<value name="FLUSH_SO_3" value="20" varset="chip" variants="A5XX-"/>
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	<value name="PC_CCU_INVALIDATE_DEPTH" value="24" varset="chip" variants="A5XX-"/>
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	<value name="PC_CCU_INVALIDATE_COLOR" value="25" varset="chip" variants="A5XX-"/>
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	<value name="PC_CCU_RESOLVE_TS" value="26" varset="chip" variants="A6XX"/>
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	<value name="PC_CCU_FLUSH_DEPTH_TS" value="28" varset="chip" variants="A5XX-"/>
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	<value name="PC_CCU_FLUSH_COLOR_TS" value="29" varset="chip" variants="A5XX-"/>
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	<value name="BLIT" value="30" varset="chip" variants="A5XX-"/>
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	<value name="UNK_25" value="37" varset="chip" variants="A5XX"/>
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	<value name="LRZ_FLUSH" value="38" varset="chip" variants="A5XX-"/>
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	<value name="BLIT_OP_FILL_2D" value="39" varset="chip" variants="A5XX-"/>
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	<value name="BLIT_OP_COPY_2D" value="40" varset="chip" variants="A5XX-"/>
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	<value name="BLIT_OP_SCALE_2D" value="42" varset="chip" variants="A5XX-"/>
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	<value name="CONTEXT_DONE_2D" value="43" varset="chip" variants="A5XX-"/>
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	<value name="UNK_2C" value="44" varset="chip" variants="A5XX-"/>
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	<value name="UNK_2D" value="45" varset="chip" variants="A5XX-"/>
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	<!-- a6xx events -->
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	<value name="CACHE_INVALIDATE" value="49" varset="chip" variants="A6XX"/>
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</enum>
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<enum name="pc_di_primtype">
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	<value name="DI_PT_NONE" value="0"/>
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	<!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
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	<value name="DI_PT_POINTLIST_PSIZE" value="1"/>
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	<value name="DI_PT_LINELIST" value="2"/>
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	<value name="DI_PT_LINESTRIP" value="3"/>
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	<value name="DI_PT_TRILIST" value="4"/>
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	<value name="DI_PT_TRIFAN" value="5"/>
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	<value name="DI_PT_TRISTRIP" value="6"/>
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	<value name="DI_PT_LINELOOP" value="7"/>  <!-- a22x, a3xx -->
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	<value name="DI_PT_RECTLIST" value="8"/>
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	<value name="DI_PT_POINTLIST" value="9"/>
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	<value name="DI_PT_LINE_ADJ" value="0xa"/>
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	<value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
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	<value name="DI_PT_TRI_ADJ" value="0xc"/>
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	<value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
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	<value name="DI_PT_PATCHES0" value="0x1f"/>
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	<value name="DI_PT_PATCHES1" value="0x20"/>
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	<value name="DI_PT_PATCHES2" value="0x21"/>
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	<value name="DI_PT_PATCHES3" value="0x22"/>
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	<value name="DI_PT_PATCHES4" value="0x23"/>
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	<value name="DI_PT_PATCHES5" value="0x24"/>
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	<value name="DI_PT_PATCHES6" value="0x25"/>
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	<value name="DI_PT_PATCHES7" value="0x26"/>
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	<value name="DI_PT_PATCHES8" value="0x27"/>
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	<value name="DI_PT_PATCHES9" value="0x28"/>
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	<value name="DI_PT_PATCHES10" value="0x29"/>
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	<value name="DI_PT_PATCHES11" value="0x2a"/>
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	<value name="DI_PT_PATCHES12" value="0x2b"/>
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	<value name="DI_PT_PATCHES13" value="0x2c"/>
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	<value name="DI_PT_PATCHES14" value="0x2d"/>
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	<value name="DI_PT_PATCHES15" value="0x2e"/>
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	<value name="DI_PT_PATCHES16" value="0x2f"/>
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	<value name="DI_PT_PATCHES17" value="0x30"/>
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	<value name="DI_PT_PATCHES18" value="0x31"/>
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	<value name="DI_PT_PATCHES19" value="0x32"/>
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	<value name="DI_PT_PATCHES20" value="0x33"/>
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	<value name="DI_PT_PATCHES21" value="0x34"/>
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	<value name="DI_PT_PATCHES22" value="0x35"/>
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	<value name="DI_PT_PATCHES23" value="0x36"/>
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	<value name="DI_PT_PATCHES24" value="0x37"/>
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	<value name="DI_PT_PATCHES25" value="0x38"/>
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	<value name="DI_PT_PATCHES26" value="0x39"/>
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	<value name="DI_PT_PATCHES27" value="0x3a"/>
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	<value name="DI_PT_PATCHES28" value="0x3b"/>
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	<value name="DI_PT_PATCHES29" value="0x3c"/>
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	<value name="DI_PT_PATCHES30" value="0x3d"/>
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	<value name="DI_PT_PATCHES31" value="0x3e"/>
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</enum>
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<enum name="pc_di_src_sel">
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	<value name="DI_SRC_SEL_DMA" value="0"/>
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	<value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
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	<value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
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	<value name="DI_SRC_SEL_AUTO_XFB" value="3"/>
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</enum>
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<enum name="pc_di_face_cull_sel">
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	<value name="DI_FACE_CULL_NONE" value="0"/>
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	<value name="DI_FACE_CULL_FETCH" value="1"/>
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	<value name="DI_FACE_BACKFACE_CULL" value="2"/>
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	<value name="DI_FACE_FRONTFACE_CULL" value="3"/>
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</enum>
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<enum name="pc_di_index_size">
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	<value name="INDEX_SIZE_IGN" value="0"/>
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	<value name="INDEX_SIZE_16_BIT" value="0"/>
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	<value name="INDEX_SIZE_32_BIT" value="1"/>
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	<value name="INDEX_SIZE_8_BIT" value="2"/>
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	<value name="INDEX_SIZE_INVALID"/>
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</enum>
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<enum name="pc_di_vis_cull_mode">
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	<value name="IGNORE_VISIBILITY" value="0"/>
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	<value name="USE_VISIBILITY" value="1"/>
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</enum>
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<enum name="adreno_pm4_packet_type">
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	<value name="CP_TYPE0_PKT" value="0x00000000"/>
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	<value name="CP_TYPE1_PKT" value="0x40000000"/>
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	<value name="CP_TYPE2_PKT" value="0x80000000"/>
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	<value name="CP_TYPE3_PKT" value="0xc0000000"/>
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	<value name="CP_TYPE4_PKT" value="0x40000000"/>
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	<value name="CP_TYPE7_PKT" value="0x70000000"/>
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</enum>
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<!--
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   Note that in some cases, the same packet id is recycled on a later
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   generation, so variants attribute is used to distinguish.   They
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   may not be completely accurate, we would probably have to analyze
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   the pfp and me/pm4 firmware to verify the packet is actually
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   handled on a particular generation.  But it is at least enough to
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   disambiguate the packet-id's that were re-used for different
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   packets starting with a5xx.
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 -->
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<enum name="adreno_pm4_type3_packets">
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	<doc>initialize CP's micro-engine</doc>
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	<value name="CP_ME_INIT" value="0x48"/>
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	<doc>skip N 32-bit words to get to the next packet</doc>
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	<value name="CP_NOP" value="0x10"/>
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	<doc>
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		indirect buffer dispatch.  prefetch parser uses this packet
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		type to determine whether to pre-fetch the IB
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	</doc>
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	<value name="CP_PREEMPT_ENABLE" value="0x1c"/>
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	<value name="CP_PREEMPT_TOKEN" value="0x1e"/>
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	<value name="CP_INDIRECT_BUFFER" value="0x3f"/>
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	<doc>
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		Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to
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		another buffer at the same level. Must be at the end of IB, and
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		doesn't work with draw state IB's.
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	</doc>
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	<value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" varset="chip" variants="A5XX-"/>
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	<doc>indirect buffer dispatch.  same as IB, but init is pipelined</doc>
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	<value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
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	<doc>wait for the IDLE state of the engine</doc>
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	<value name="CP_WAIT_FOR_IDLE" value="0x26"/>
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	<doc>wait until a register or memory location is a specific value</doc>
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	<value name="CP_WAIT_REG_MEM" value="0x3c"/>
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	<doc>wait until a register location is equal to a specific value</doc>
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	<value name="CP_WAIT_REG_EQ" value="0x52"/>
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	<doc>wait until a register location is >= a specific value</doc>
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	<value name="CP_WAIT_REG_GTE" value="0x53" varset="chip" variants="A2XX-A4XX"/>
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	<doc>wait until a read completes</doc>
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	<value name="CP_WAIT_UNTIL_READ" value="0x5c" varset="chip" variants="A2XX-A4XX"/>
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	<doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
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	<value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/>
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	<doc>register read/modify/write</doc>
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	<value name="CP_REG_RMW" value="0x21"/>
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	<doc>Set binning configuration registers</doc>
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	<value name="CP_SET_BIN_DATA" value="0x2f" varset="chip" variants="A2XX-A4XX"/>
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	<value name="CP_SET_BIN_DATA5" value="0x2f" varset="chip" variants="A5XX-"/>
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	<doc>reads register in chip and writes to memory</doc>
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	<value name="CP_REG_TO_MEM" value="0x3e"/>
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	<doc>write N 32-bit words to memory</doc>
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	<value name="CP_MEM_WRITE" value="0x3d"/>
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	<doc>write CP_PROG_COUNTER value to memory</doc>
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	<value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
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	<doc>conditional execution of a sequence of packets</doc>
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	<value name="CP_COND_EXEC" value="0x44"/>
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	<doc>conditional write to memory or register</doc>
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	<value name="CP_COND_WRITE" value="0x45" varset="chip" variants="A2XX-A4XX"/>
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	<value name="CP_COND_WRITE5" value="0x45" varset="chip" variants="A5XX-"/>
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	<doc>generate an event that creates a write to memory when completed</doc>
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	<value name="CP_EVENT_WRITE" value="0x46"/>
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	<doc>generate a VS|PS_done event</doc>
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	<value name="CP_EVENT_WRITE_SHD" value="0x58"/>
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	<doc>generate a cache flush done event</doc>
208
	<value name="CP_EVENT_WRITE_CFL" value="0x59"/>
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	<doc>generate a z_pass done event</doc>
210
	<value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
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	<doc>
212
		not sure the real name, but this seems to be what is used for
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		opencl, instead of CP_DRAW_INDX..
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	</doc>
215
	<value name="CP_RUN_OPENCL" value="0x31"/>
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	<doc>initiate fetch of index buffer and draw</doc>
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	<value name="CP_DRAW_INDX" value="0x22"/>
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	<doc>draw using supplied indices in packet</doc>
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	<value name="CP_DRAW_INDX_2" value="0x36" varset="chip" variants="A2XX-A4XX"/>  <!-- this is something different on a6xx and unused on a5xx -->
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	<doc>initiate fetch of index buffer and binIDs and draw</doc>
221
	<value name="CP_DRAW_INDX_BIN" value="0x34" varset="chip" variants="A2XX-A4XX"/>
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	<doc>initiate fetch of bin IDs and draw using supplied indices</doc>
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	<value name="CP_DRAW_INDX_2_BIN" value="0x35" varset="chip" variants="A2XX-A4XX"/>
224
	<doc>begin/end initiator for viz query extent processing</doc>
225
	<value name="CP_VIZ_QUERY" value="0x23" varset="chip" variants="A2XX-A4XX"/>
226
	<doc>fetch state sub-blocks and initiate shader code DMAs</doc>
227
	<value name="CP_SET_STATE" value="0x25"/>
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	<doc>load constant into chip and to memory</doc>
229
	<value name="CP_SET_CONSTANT" value="0x2d"/>
230
	<doc>load sequencer instruction memory (pointer-based)</doc>
231
	<value name="CP_IM_LOAD" value="0x27"/>
232
	<doc>load sequencer instruction memory (code embedded in packet)</doc>
233
	<value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
234
	<doc>load constants from a location in memory</doc>
235
	<value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" varset="chip" variants="A2XX"/>
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	<doc>selective invalidation of state pointers</doc>
237
	<value name="CP_INVALIDATE_STATE" value="0x3b"/>
238
	<doc>dynamically changes shader instruction memory partition</doc>
239
	<value name="CP_SET_SHADER_BASES" value="0x4a" varset="chip" variants="A2XX-A4XX"/>
240
	<doc>sets the 64-bit BIN_MASK register in the PFP</doc>
241
	<value name="CP_SET_BIN_MASK" value="0x50" varset="chip" variants="A2XX-A4XX"/>
242
	<doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
243
	<value name="CP_SET_BIN_SELECT" value="0x51"/>
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	<doc>updates the current context, if needed</doc>
245
	<value name="CP_CONTEXT_UPDATE" value="0x5e"/>
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	<doc>generate interrupt from the command stream</doc>
247
	<value name="CP_INTERRUPT" value="0x40"/>
248
	<doc>copy sequencer instruction memory to system memory</doc>
249
	<value name="CP_IM_STORE" value="0x2c" varset="chip" variants="A2XX"/>
250

251
	<!-- For a20x -->
252
<!-- TODO handle variants..
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	<doc>
254
		Program an offset that will added to the BIN_BASE value of
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		the 3D_DRAW_INDX_BIN packet
256
	</doc>
257
	<value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
258
 -->
259

260
	<!-- for a22x -->
261
	<doc>
262
		sets draw initiator flags register in PFP, gets bitwise-ORed into
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		every draw initiator
264
	</doc>
265
	<value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
266
	<doc>sets the register protection mode</doc>
267
	<value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
268

269
	<value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
270

271
	<!-- for a3xx -->
272
	<doc>load high level sequencer command</doc>
273
	<value name="CP_LOAD_STATE" value="0x30" varset="chip" variants="A3XX"/>
274
	<value name="CP_LOAD_STATE4" value="0x30" varset="chip" variants="A4XX-A5XX"/>
275
	<doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
276
	<value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
277
	<doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
278
	<value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" varset="chip" variants="A3XX"/>
279
	<doc>Load a buffer with pre-fetch enabled</doc>
280
	<value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" varset="chip" variants="A5XX"/>
281
	<doc>Set bin (?)</doc>
282
	<value name="CP_SET_BIN" value="0x4c" varset="chip" variants="A2XX"/>
283

284
	<doc>test 2 memory locations to dword values specified</doc>
285
	<value name="CP_TEST_TWO_MEMS" value="0x71"/>
286

287
	<doc>Write register, ignoring context state for context sensitive registers</doc>
288
	<value name="CP_REG_WR_NO_CTXT" value="0x78"/>
289

290
	<doc>Record the real-time when this packet is processed by PFP</doc>
291
	<value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
292

293
	<!-- Used to switch GPU between secure and non-secure modes -->
294
	<value name="CP_SET_SECURE_MODE" value="0x66"/>
295

296
	<doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
297
	<value name="CP_WAIT_FOR_ME" value="0x13"/>
298

299
	<!-- for a4xx -->
300
	<doc>
301
		Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
302
		groups of registers.  Looks like it can be used to create state
303
		objects in GPU memory, and on state change only emit pointer
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		(via CP_SET_DRAW_STATE), which should be nice for reducing CPU
305
		overhead:
306

307
		(A4x) save PM4 stream pointers to execute upon a visible draw
308
	</doc>
309
	<value name="CP_SET_DRAW_STATE" value="0x43" varset="chip" variants="A4XX-"/>
310
	<value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
311
	<value name="CP_DRAW_INDIRECT" value="0x28" varset="chip" variants="A4XX-"/>
312
	<value name="CP_DRAW_INDX_INDIRECT" value="0x29" varset="chip" variants="A4XX-"/>
313
	<value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" varset="chip" variants="A6XX"/>
314
	<value name="CP_DRAW_AUTO" value="0x24"/>
315

316
	<doc>
317
		Enable or disable predication globally. Also resets the
318
		predicate to "passing" and the local bit to enabled when
319
		enabling global predication.
320
	</doc>
321
	<value name="CP_DRAW_PRED_ENABLE_GLOBAL" value="0x19"/>
322

323
	<doc>
324
		Enable or disable predication locally. Unlike globally enabling
325
		predication, this packet doesn't touch any other state.
326
		Predication only happens when enabled globally and locally and a
327
		predicate has been set. This should be used for internal draws
328
		which aren't supposed to use the predication state:
329

330
		CP_DRAW_PRED_ENABLE_LOCAL(0)
331
		... do draw...
332
		CP_DRAW_PRED_ENABLE_LOCAL(1)
333
	</doc>
334
	<value name="CP_DRAW_PRED_ENABLE_LOCAL" value="0x1a"/>
335

336
	<doc>
337
		Latch a draw predicate into the internal register.
338
	</doc>
339
	<value name="CP_DRAW_PRED_SET" value="0x4e"/>
340

341
	<doc>
342
		for A4xx
343
		Write to register with address that does not fit into type-0 pkt
344
	</doc>
345
	<value name="CP_WIDE_REG_WRITE" value="0x74" varset="chip" variants="A4XX"/>
346

347
	<doc>copy from ME scratch RAM to a register</doc>
348
	<value name="CP_SCRATCH_TO_REG" value="0x4d"/>
349

350
	<doc>Copy from REG to ME scratch RAM</doc>
351
	<value name="CP_REG_TO_SCRATCH" value="0x4a"/>
352

353
	<doc>Wait for memory writes to complete</doc>
354
	<value name="CP_WAIT_MEM_WRITES" value="0x12"/>
355

356
	<doc>Conditional execution based on register comparison</doc>
357
	<value name="CP_COND_REG_EXEC" value="0x47"/>
358

359
	<doc>Memory to REG copy</doc>
360
	<value name="CP_MEM_TO_REG" value="0x42"/>
361

362
	<value name="CP_EXEC_CS_INDIRECT" value="0x41" varset="chip" variants="A4XX-"/>
363
	<value name="CP_EXEC_CS" value="0x33"/>
364

365
	<doc>
366
		for a5xx
367
	</doc>
368
	<value name="CP_PERFCOUNTER_ACTION" value="0x50" varset="chip" variants="A5XX"/>
369
	<!-- switches SMMU pagetable, used on a5xx+ only -->
370
	<value name="CP_SMMU_TABLE_UPDATE" value="0x53" varset="chip" variants="A5XX-"/>
371
	<!-- for a6xx -->
372
	<doc>Tells CP the current mode of GPU operation</doc>
373
	<value name="CP_SET_MARKER" value="0x65" varset="chip" variants="A6XX"/>
374
	<doc>Instruct CP to set a few internal CP registers</doc>
375
	<value name="CP_SET_PSEUDO_REG" value="0x56" varset="chip" variants="A6XX"/>
376
	<!--
377
	pairs of regid and value.. seems to be used to program some TF
378
	related regs:
379
	 -->
380
	<value name="CP_CONTEXT_REG_BUNCH" value="0x5c" varset="chip" variants="A5XX-"/>
381
	<!-- A5XX Enable yield in RB only -->
382
	<value name="CP_YIELD_ENABLE" value="0x1c" varset="chip" variants="A5XX"/>
383
	<value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" varset="chip" variants="A5XX-"/>
384
	<value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" varset="chip" variants="A5XX-"/>
385
	<value name="CP_SET_SUBDRAW_SIZE" value="0x35" varset="chip" variants="A5XX-"/>
386
	<value name="CP_WHERE_AM_I" value="0x62" varset="chip" variants="A5XX-"/>
387
	<value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" varset="chip" variants="A5XX-"/>
388
	<!-- Enable/Disable/Defer A5x global preemption model -->
389
	<value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" varset="chip" variants="A5XX"/>
390
	<!-- Enable/Disable A5x local preemption model -->
391
	<value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" varset="chip" variants="A5XX"/>
392
	<!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
393
	<value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" varset="chip" variants="A5XX"/>
394
	<!-- Inform CP about current render mode (needed for a5xx preemption) -->
395
	<value name="CP_SET_RENDER_MODE" value="0x6c" varset="chip" variants="A5XX"/>
396
	<value name="CP_COMPUTE_CHECKPOINT" value="0x6e" varset="chip" variants="A5XX"/>
397
	<!-- check if this works on earlier.. -->
398
	<value name="CP_MEM_TO_MEM" value="0x73" varset="chip" variants="A5XX-"/>
399
	<value name="CP_BLIT" value="0x2c" varset="chip" variants="A5XX-"/>
400

401
	<!-- Test specified bit in specified register and set predicate -->
402
	<value name="CP_REG_TEST" value="0x39" varset="chip" variants="A5XX-"/>
403

404
	<!--
405
	Seems to set the mode flags which control which CP_SET_DRAW_STATE
406
	packets are executed, based on their ENABLE_MASK values
407
	
408
	CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
409
	packets w/ ENABLE_MASK & 0x6 to execute immediately
410
	 -->
411
	<value name="CP_SET_MODE" value="0x63" varset="chip" variants="A6XX"/>
412

413
	<!--
414
	Seems like there are now separate blocks of state for VS vs FS/CS
415
	(probably these amounts to geometry vs fragments so that geometry
416
	stage of the pipeline for next draw can start while fragment stage
417
	of current draw is still running.  The format of the payload of the
418
	packets is the same, the only difference is the offsets of the regs
419
	the firmware code that handles the packet writes.
420

421
	Note that for CL, starting with a6xx, the preferred # of local
422
	threads is no longer the same as the max, implying that the shader
423
	core can now run warps from unrelated shaders (ie.
424
	CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
425
	CL_KERNEL_WORK_GROUP_SIZE)
426
	 -->
427
	<value name="CP_LOAD_STATE6_GEOM" value="0x32" varset="chip" variants="A6XX"/>
428
	<value name="CP_LOAD_STATE6_FRAG" value="0x34" varset="chip" variants="A6XX"/>
429
	<!--
430
	Note: For IBO state (Image/SSBOs) which have shared state across
431
	shader stages, for 3d pipeline CP_LOAD_STATE6 is used.  But for
432
	compute shaders, CP_LOAD_STATE6_FRAG is used.  Possibly they are
433
	interchangable.
434
	 -->
435
	<value name="CP_LOAD_STATE6" value="0x36" varset="chip" variants="A6XX"/>
436

437
	<!-- internal packets: -->
438
	<value name="IN_IB_PREFETCH_END" value="0x17" varset="chip" variants="A2XX"/>
439
	<value name="IN_SUBBLK_PREFETCH" value="0x1f" varset="chip" variants="A2XX"/>
440
	<value name="IN_INSTR_PREFETCH" value="0x20" varset="chip" variants="A2XX"/>
441
	<value name="IN_INSTR_MATCH" value="0x47" varset="chip" variants="A2XX"/>
442
	<value name="IN_CONST_PREFETCH" value="0x49" varset="chip" variants="A2XX"/>
443
	<value name="IN_INCR_UPDT_STATE" value="0x55" varset="chip" variants="A2XX"/>
444
	<value name="IN_INCR_UPDT_CONST" value="0x56" varset="chip" variants="A2XX"/>
445
	<value name="IN_INCR_UPDT_INSTR" value="0x57" varset="chip" variants="A2XX"/>
446

447
	<!-- jmptable entry used to handle type4 packet on a5xx+: -->
448
	<value name="PKT4" value="0x04" varset="chip" variants="A5XX-"/>
449

450
	<!-- TODO do these exist on A5xx? -->
451
	<value name="CP_SCRATCH_WRITE" value="0x4c" varset="chip" variants="A6XX"/>
452
	<value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" varset="chip" variants="A6XX"/>
453
	<value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" varset="chip" variants="A6XX"/>
454
	<value name="CP_WAIT_MEM_GTE" value="0x14" varset="chip" variants="A6XX"/>
455
	<value name="CP_WAIT_TWO_REGS" value="0x70" varset="chip" variants="A6XX"/>
456
	<value name="CP_MEMCPY" value="0x75" varset="chip" variants="A6XX"/>
457
	<value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" varset="chip" variants="A6XX"/>
458
	<value name="CP_SET_CTXSWITCH_IB" value="0x55" varset="chip" variants="A6XX"/>
459

460
	<!--
461
	Seems to always have the payload:
462
	  00000002 00008801 00004010
463
	or:
464
	  00000002 00008801 00004090
465
	or:
466
	  00000002 00008801 00000010
467
	  00000002 00008801 00010010
468
	  00000002 00008801 00d64010
469
	  ...
470
	Note set for compute shaders..
471
	Is 0x8801 a register offset?
472
	This appears to be a special sort of register write packet
473
	more or less, but the firmware has some special handling..
474
	Seems like it intercepts/modifies certain register offsets,
475
	but others are treated like a normal PKT4 reg write.  I
476
	guess there are some registers that the fw controls certain
477
	bits.
478
	 -->
479
	<value name="CP_REG_WRITE" value="0x6d" varset="chip" variants="A6XX"/>
480

481
</enum>
482

483

484
<domain name="CP_LOAD_STATE" width="32">
485
	<doc>Load state, a3xx (and later?)</doc>
486
	<enum name="adreno_state_block">
487
		<value name="SB_VERT_TEX" value="0"/>
488
		<value name="SB_VERT_MIPADDR" value="1"/>
489
		<value name="SB_FRAG_TEX" value="2"/>
490
		<value name="SB_FRAG_MIPADDR" value="3"/>
491
		<value name="SB_VERT_SHADER" value="4"/>
492
		<value name="SB_GEOM_SHADER" value="5"/>
493
		<value name="SB_FRAG_SHADER" value="6"/>
494
		<value name="SB_COMPUTE_SHADER" value="7"/>
495
	</enum>
496
	<enum name="adreno_state_type">
497
		<value name="ST_SHADER" value="0"/>
498
		<value name="ST_CONSTANTS" value="1"/>
499
	</enum>
500
	<enum name="adreno_state_src">
501
		<value name="SS_DIRECT" value="0">
502
			<doc>inline with the CP_LOAD_STATE packet</doc>
503
		</value>
504
		<value name="SS_INVALID_ALL_IC" value="2"/>
505
		<value name="SS_INVALID_PART_IC" value="3"/>
506
		<value name="SS_INDIRECT" value="4">
507
			<doc>in buffer pointed to by EXT_SRC_ADDR</doc>
508
		</value>
509
		<value name="SS_INDIRECT_TCM" value="5"/>
510
		<value name="SS_INDIRECT_STM" value="6"/>
511
	</enum>
512
	<reg32 offset="0" name="0">
513
		<bitfield name="DST_OFF" low="0" high="15" type="uint"/>
514
		<bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
515
		<bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
516
		<bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
517
	</reg32>
518
	<reg32 offset="1" name="1">
519
		<bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
520
		<bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
521
	</reg32>
522
</domain>
523

524
<domain name="CP_LOAD_STATE4" width="32" varset="chip">
525
	<doc>Load state, a4xx+</doc>
526
	<enum name="a4xx_state_block">
527
		<!--
528
		unknown: 0x7 and 0xf <- seen in compute shader
529

530
		STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
531
		Seen in some GL shaders.  Payload is NUM_UNIT dwords, and it contains
532
		the gpuaddr of the following shader constants block.  DST_OFF seems
533
		to specify which shader stage:
534

535
		    16 -> vert
536
		    36 -> tcs
537
		    56 -> tes
538
		    76 -> geom
539
		    96 -> frag
540

541
		Example:
542

543
opcode: CP_LOAD_STATE4 (30) (12 dwords)
544
        { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
545
        { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
546
        { EXT_SRC_ADDR_HI = 0 }
547
                        0000: c0264100 00000000 00000000 00000000
548
                0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
549

550
opcode: CP_LOAD_STATE4 (30) (4 dwords)
551
        { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
552
        { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
553
        { EXT_SRC_ADDR_HI = 0 }
554
                        0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
555
                        0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
556
                        0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
557

558
		STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader.  NUM_UNITS * 2 dwords.
559

560
		 -->
561
		<value name="SB4_VS_TEX"    value="0x0"/>
562
		<value name="SB4_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
563
		<value name="SB4_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
564
		<value name="SB4_GS_TEX"    value="0x3"/>
565
		<value name="SB4_FS_TEX"    value="0x4"/>
566
		<value name="SB4_CS_TEX"    value="0x5"/>
567
		<value name="SB4_VS_SHADER" value="0x8"/>
568
		<value name="SB4_HS_SHADER" value="0x9"/>
569
		<value name="SB4_DS_SHADER" value="0xa"/>
570
		<value name="SB4_GS_SHADER" value="0xb"/>
571
		<value name="SB4_FS_SHADER" value="0xc"/>
572
		<value name="SB4_CS_SHADER" value="0xd"/>
573
		<!--
574
		for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
575
		STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
576

577
		Compute has it's own dedicated SSBO state, it seems, but the rest
578
		of the stages share state
579
		 -->
580
		<value name="SB4_SSBO"   value="0xe"/>
581
		<value name="SB4_CS_SSBO"   value="0xf"/>
582
	</enum>
583
	<enum name="a4xx_state_type">
584
		<value name="ST4_SHADER" value="0"/>
585
		<value name="ST4_CONSTANTS" value="1"/>
586
		<value name="ST4_UBO" value="2"/>
587
	</enum>
588
	<enum name="a4xx_state_src">
589
		<value name="SS4_DIRECT" value="0"/>
590
		<value name="SS4_INDIRECT" value="2"/>
591
	</enum>
592
	<reg32 offset="0" name="0">
593
		<bitfield name="DST_OFF" low="0" high="13" type="uint"/>
594
		<bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
595
		<bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
596
		<bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
597
	</reg32>
598
	<reg32 offset="1" name="1">
599
		<bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
600
		<bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
601
	</reg32>
602
	<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
603
		<bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
604
	</reg32>
605
</domain>
606

607
<!-- looks basically same CP_LOAD_STATE4 -->
608
<domain name="CP_LOAD_STATE6" width="32" varset="chip">
609
	<doc>Load state, a6xx+</doc>
610
	<enum name="a6xx_state_block">
611
		<value name="SB6_VS_TEX"    value="0x0"/>
612
		<value name="SB6_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
613
		<value name="SB6_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
614
		<value name="SB6_GS_TEX"    value="0x3"/>
615
		<value name="SB6_FS_TEX"    value="0x4"/>
616
		<value name="SB6_CS_TEX"    value="0x5"/>
617
		<value name="SB6_VS_SHADER" value="0x8"/>
618
		<value name="SB6_HS_SHADER" value="0x9"/>
619
		<value name="SB6_DS_SHADER" value="0xa"/>
620
		<value name="SB6_GS_SHADER" value="0xb"/>
621
		<value name="SB6_FS_SHADER" value="0xc"/>
622
		<value name="SB6_CS_SHADER" value="0xd"/>
623
		<value name="SB6_IBO"       value="0xe"/>
624
		<value name="SB6_CS_IBO"    value="0xf"/>
625
	</enum>
626
	<enum name="a6xx_state_type">
627
		<value name="ST6_SHADER" value="0"/>
628
		<value name="ST6_CONSTANTS" value="1"/>
629
		<value name="ST6_UBO" value="2"/>
630
		<value name="ST6_IBO" value="3"/>
631
	</enum>
632
	<enum name="a6xx_state_src">
633
		<value name="SS6_DIRECT" value="0"/>
634
		<value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? -->
635
		<value name="SS6_INDIRECT" value="2"/>
636
		<doc>
637
		SS6_UBO used by the a6xx vulkan blob with tesselation constants
638
		in this case, EXT_SRC_ADDR is (ubo_id shl 16 | offset)
639
		to load constants from a UBO loaded with DST_OFF = 14 and offset 0,
640
		EXT_SRC_ADDR = 0xe0000
641
		(offset is a guess, should be in bytes given that maxUniformBufferRange=64k)
642
		</doc>
643
		<value name="SS6_UBO" value="3"/>
644
	</enum>
645
	<reg32 offset="0" name="0">
646
		<bitfield name="DST_OFF" low="0" high="13" type="uint"/>
647
		<bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
648
		<bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
649
		<bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
650
		<bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
651
	</reg32>
652
	<reg32 offset="1" name="1">
653
		<bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
654
	</reg32>
655
	<reg32 offset="2" name="2">
656
		<bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
657
	</reg32>
658
	<reg64 offset="1" name="EXT_SRC_ADDR" type="address"/>
659
</domain>
660

661
<bitset name="vgt_draw_initiator" inline="yes">
662
	<bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
663
	<bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
664
	<bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
665
	<bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
666
	<bitfield name="NOT_EOP" pos="12" type="boolean"/>
667
	<bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
668
	<bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
669
	<bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
670
</bitset>
671

672
<!-- changed on a4xx: -->
673
<enum name="a4xx_index_size">
674
	<value name="INDEX4_SIZE_8_BIT" value="0"/>
675
	<value name="INDEX4_SIZE_16_BIT" value="1"/>
676
	<value name="INDEX4_SIZE_32_BIT" value="2"/>
677
</enum>
678

679
<enum name="a6xx_patch_type">
680
  <value name="TESS_QUADS" value="0"/>
681
  <value name="TESS_TRIANGLES" value="1"/>
682
  <value name="TESS_ISOLINES" value="2"/>
683
</enum>
684

685
<bitset name="vgt_draw_initiator_a4xx" inline="yes">
686
	<!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
687
	<bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
688
	<bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
689
	<bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
690
	<bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
691
	<bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
692
	<bitfield name="GS_ENABLE" pos="16" type="boolean"/>
693
	<bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
694
</bitset>
695

696
<domain name="CP_DRAW_INDX" width="32">
697
	<reg32 offset="0" name="0">
698
		<bitfield name="VIZ_QUERY" low="0" high="31"/>
699
	</reg32>
700
	<reg32 offset="1" name="1" type="vgt_draw_initiator"/>
701
	<reg32 offset="2" name="2">
702
		<bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
703
	</reg32>
704
	<reg32 offset="3" name="3">
705
		<bitfield name="INDX_BASE" low="0" high="31"/>
706
	</reg32>
707
	<reg32 offset="4" name="4">
708
		<bitfield name="INDX_SIZE" low="0" high="31"/>
709
	</reg32>
710
</domain>
711

712
<domain name="CP_DRAW_INDX_2" width="32">
713
	<reg32 offset="0" name="0">
714
		<bitfield name="VIZ_QUERY" low="0" high="31"/>
715
	</reg32>
716
	<reg32 offset="1" name="1" type="vgt_draw_initiator"/>
717
	<reg32 offset="2" name="2">
718
		<bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
719
	</reg32>
720
	<!-- followed by NUM_INDICES indices.. -->
721
</domain>
722

723
<domain name="CP_DRAW_INDX_OFFSET" width="32">
724
	<reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
725
	<reg32 offset="1" name="1">
726
		<bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
727
	</reg32>
728
	<reg32 offset="2" name="2">
729
		<bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
730
	</reg32>
731
	<reg32 offset="3" name="3">
732
		<bitfield name="FIRST_INDX" low="0" high="31"/>
733
	</reg32>
734

735
	<stripe varset="chip" variants="A5XX-">
736
		<reg32 offset="4" name="4">
737
			<bitfield name="INDX_BASE_LO" low="0" high="31"/>
738
		</reg32>
739
		<reg32 offset="5" name="5">
740
			<bitfield name="INDX_BASE_HI" low="0" high="31"/>
741
		</reg32>
742
		<reg64 offset="4" name="INDX_BASE" type="address"/>
743
		<reg32 offset="6" name="6">
744
			<!-- max # of elements in index buffer -->
745
			<bitfield name="MAX_INDICES" low="0" high="31"/>
746
		</reg32>
747
	</stripe>
748

749
	<reg32 offset="4" name="4">
750
		<bitfield name="INDX_BASE" low="0" high="31" type="address"/>
751
	</reg32>
752

753
	<reg32 offset="5" name="5">
754
		<bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
755
	</reg32>
756
</domain>
757

758
<domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
759
	<reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
760
	<stripe varset="chip" variants="A4XX">
761
		<reg32 offset="1" name="1">
762
			<bitfield name="INDIRECT" low="0" high="31"/>
763
		</reg32>
764
	</stripe>
765
	<stripe varset="chip" variants="A5XX-">
766
		<reg32 offset="1" name="1">
767
			<bitfield name="INDIRECT_LO" low="0" high="31"/>
768
		</reg32>
769
		<reg32 offset="2" name="2">
770
			<bitfield name="INDIRECT_HI" low="0" high="31"/>
771
		</reg32>
772
		<reg64 offset="1" name="INDIRECT" type="address"/>
773
	</stripe>
774
</domain>
775

776
<domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
777
	<reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
778
	<stripe varset="chip" variants="A4XX">
779
		<reg32 offset="1" name="1">
780
			<bitfield name="INDX_BASE" low="0" high="31"/>
781
		</reg32>
782
		<reg32 offset="2" name="2">
783
			<!-- max # of bytes in index buffer -->
784
			<bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
785
		</reg32>
786
		<reg32 offset="3" name="3">
787
			<bitfield name="INDIRECT" low="0" high="31"/>
788
		</reg32>
789
	</stripe>
790
	<stripe varset="chip" variants="A5XX-">
791
		<reg32 offset="1" name="1">
792
			<bitfield name="INDX_BASE_LO" low="0" high="31"/>
793
		</reg32>
794
		<reg32 offset="2" name="2">
795
			<bitfield name="INDX_BASE_HI" low="0" high="31"/>
796
		</reg32>
797
		<reg64 offset="1" name="INDX_BASE" type="address"/>
798
		<reg32 offset="3" name="3">
799
			<!-- max # of elements in index buffer -->
800
			<bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
801
		</reg32>
802
		<reg32 offset="4" name="4">
803
			<bitfield name="INDIRECT_LO" low="0" high="31"/>
804
		</reg32>
805
		<reg32 offset="5" name="5">
806
			<bitfield name="INDIRECT_HI" low="0" high="31"/>
807
		</reg32>
808
		<reg64 offset="4" name="INDIRECT" type="address"/>
809
	</stripe>
810
</domain>
811

812
<domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-">
813
	<enum name="a6xx_draw_indirect_opcode">
814
		<value name="INDIRECT_OP_NORMAL"  value="0x2"/>
815
		<value name="INDIRECT_OP_INDEXED" value="0x4"/>
816
		<value name="INDIRECT_OP_INDIRECT_COUNT" value="0x6"/>
817
		<value name="INDIRECT_OP_INDIRECT_COUNT_INDEXED" value="0x7"/>
818
	</enum>
819
	<reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
820
	<reg32 offset="1" name="1">
821
		<bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode" addvariant="yes"/>
822
		<doc>
823
		DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will
824
		be updated for each draw to {draw_id, first_vertex, first_instance, 0}
825
		value of 0 disables it
826
		</doc>
827
		<bitfield name="DST_OFF" low="8" high="21" type="hex"/>
828
	</reg32>
829
	<reg32 offset="2" name="DRAW_COUNT" type="uint"/>
830
	<stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_NORMAL">
831
		<reg64 offset="3" name="INDIRECT" type="address"/>
832
		<reg32 offset="5" name="STRIDE" type="uint"/>
833
	</stripe>
834
	<stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDEXED" prefix="INDEXED">
835
		<reg64 offset="3" name="INDEX" type="address"/>
836
		<reg32 offset="5" name="MAX_INDICES" type="uint"/>
837
		<reg64 offset="6" name="INDIRECT" type="address"/>
838
		<reg32 offset="8" name="STRIDE" type="uint"/>
839
	</stripe>
840
	<stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT" prefix="INDIRECT">
841
		<reg64 offset="3" name="INDIRECT" type="address"/>
842
		<reg64 offset="5" name="INDIRECT_COUNT" type="address"/>
843
		<reg32 offset="7" name="STRIDE" type="uint"/>
844
	</stripe>
845
	<stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT_INDEXED" prefix="INDIRECT_INDEXED">
846
		<reg64 offset="3" name="INDEX" type="address"/>
847
		<reg32 offset="5" name="MAX_INDICES" type="uint"/>
848
		<reg64 offset="6" name="INDIRECT" type="address"/>
849
		<reg64 offset="8" name="INDIRECT_COUNT" type="address"/>
850
		<reg32 offset="10" name="STRIDE" type="uint"/>
851
	</stripe>
852
</domain>
853

854
<domain name="CP_DRAW_PRED_ENABLE_GLOBAL" width="32" varset="chip">
855
	<reg32 offset="0" name="0">
856
		<bitfield name="ENABLE" pos="0" type="boolean"/>
857
	</reg32>
858
</domain>
859

860
<domain name="CP_DRAW_PRED_ENABLE_LOCAL" width="32" varset="chip">
861
	<reg32 offset="0" name="0">
862
		<bitfield name="ENABLE" pos="0" type="boolean"/>
863
	</reg32>
864
</domain>
865

866
<domain name="CP_DRAW_PRED_SET" width="32" varset="chip">
867
	<enum name="cp_draw_pred_src">
868
		<!--
869
			Sources 1-4 seem to be about combining reading
870
			SO/primitive queries and setting the predicate, which is
871
			a DX11-specific optimization (since in DX11 you can only
872
			predicate on the result of queries).
873
		-->
874
		<value name="PRED_SRC_MEM" value="5">
875
			<doc>
876
				Read a 64-bit value at the given address and
877
				test if it equals/doesn't equal 0.
878
			</doc>
879
		</value>
880
	</enum>
881
	<enum name="cp_draw_pred_test">
882
		<value name="NE_0_PASS" value="0"/>
883
		<value name="EQ_0_PASS" value="1"/>
884
	</enum>
885
	<reg32 offset="0" name="0">
886
		<bitfield name="SRC" low="4" high="7" type="cp_draw_pred_src"/>
887
		<bitfield name="TEST" pos="8" type="cp_draw_pred_test"/>
888
	</reg32>
889
	<reg64 offset="1" name="MEM_ADDR" type="address"/>
890
</domain>
891

892
<domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
893
	<array offset="0" stride="3" length="100">
894
		<reg32 offset="0" name="0">
895
			<bitfield name="COUNT" low="0" high="15" type="uint"/>
896
			<bitfield name="DIRTY" pos="16" type="boolean"/>
897
			<bitfield name="DISABLE" pos="17" type="boolean"/>
898
			<bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
899
			<bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
900
			<bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/>
901
			<bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/>
902
			<bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/>
903
			<bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
904
		</reg32>
905
		<reg32 offset="1" name="1">
906
			<bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
907
		</reg32>
908
		<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
909
			<bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
910
		</reg32>
911
	</array>
912
</domain>
913

914
<domain name="CP_SET_BIN" width="32">
915
	<doc>value at offset 0 always seems to be 0x00000000..</doc>
916
	<reg32 offset="0" name="0"/>
917
	<reg32 offset="1" name="1">
918
		<bitfield name="X1" low="0" high="15" type="uint"/>
919
		<bitfield name="Y1" low="16" high="31" type="uint"/>
920
	</reg32>
921
	<reg32 offset="2" name="2">
922
		<bitfield name="X2" low="0" high="15" type="uint"/>
923
		<bitfield name="Y2" low="16" high="31" type="uint"/>
924
	</reg32>
925
</domain>
926

927
<domain name="CP_SET_BIN_DATA" width="32">
928
	<reg32 offset="0" name="0">
929
		<!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
930
		<bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
931
	</reg32>
932
	<reg32 offset="1" name="1">
933
		<!-- seesm to correspond to VSC_SIZE_ADDRESS -->
934
		<bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
935
	</reg32>
936
</domain>
937

938
<domain name="CP_SET_BIN_DATA5" width="32">
939
	<reg32 offset="0" name="0">
940
		<!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
941
		<bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
942
		<!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
943
		<bitfield name="VSC_N" low="22" high="26" type="uint"/>
944
	</reg32>
945
	<!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
946
	<reg32 offset="1" name="1">
947
		<bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
948
	</reg32>
949
	<reg32 offset="2" name="2">
950
		<bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
951
	</reg32>
952
	<!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
953
	<reg32 offset="3" name="3">
954
		<bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
955
	</reg32>
956
	<reg32 offset="4" name="4">
957
		<bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
958
	</reg32>
959
	<!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
960
	<reg32 offset="5" name="5">
961
		<bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
962
	</reg32>
963
	<reg32 offset="6" name="6">
964
		<bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
965
	</reg32>
966
</domain>
967

968
<domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
969
	<doc>
970
                Like CP_SET_BIN_DATA5, but set the pointers as offsets from the
971
                pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful
972
                for Vulkan where these values aren't known when the command
973
                stream is recorded.
974
	</doc>
975
	<reg32 offset="0" name="0">
976
		<!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
977
		<bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
978
		<!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
979
		<bitfield name="VSC_N" low="22" high="26" type="uint"/>
980
	</reg32>
981
	<!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
982
	<reg32 offset="1" name="1">
983
		<bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
984
	</reg32>
985
	<!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
986
	<reg32 offset="2" name="2">
987
		<bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
988
	</reg32>
989
	<!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
990
	<reg32 offset="3" name="3">
991
		<bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
992
	</reg32>
993
</domain>
994

995
<domain name="CP_REG_RMW" width="32">
996
	<doc>
997
                Modifies DST_REG using two sources that can either be registers
998
                or immediates. If SRC1_ADD is set, then do the following:
999

1000
			$dst = (($dst &amp; $src0) rot $rotate) + $src1
1001

1002
		Otherwise:
1003

1004
			$dst = (($dst &amp; $src0) rot $rotate) | $src1
1005

1006
		Here "rot" means rotate left.
1007
	</doc>
1008
	<reg32 offset="0" name="0">
1009
		<bitfield name="DST_REG" low="0" high="17" type="hex"/>
1010
		<bitfield name="ROTATE" low="24" high="28" type="uint"/>
1011
		<bitfield name="SRC1_ADD" pos="29" type="boolean"/>
1012
		<bitfield name="SRC1_IS_REG" pos="30" type="boolean"/>
1013
		<bitfield name="SRC0_IS_REG" pos="31" type="boolean"/>
1014
	</reg32>
1015
	<reg32 offset="1" name="1">
1016
		<bitfield name="SRC0" low="0" high="31" type="uint"/>
1017
	</reg32>
1018
	<reg32 offset="2" name="2">
1019
		<bitfield name="SRC1" low="0" high="31" type="uint"/>
1020
	</reg32>
1021
</domain>
1022

1023
<domain name="CP_REG_TO_MEM" width="32">
1024
	<reg32 offset="0" name="0">
1025
		<bitfield name="REG" low="0" high="17" type="hex"/>
1026
		<!-- number of registers/dwords copied is max(CNT, 1). -->
1027
		<bitfield name="CNT" low="18" high="29" type="uint"/>
1028
		<bitfield name="64B" pos="30" type="boolean"/>
1029
		<bitfield name="ACCUMULATE" pos="31" type="boolean"/>
1030
	</reg32>
1031
	<reg32 offset="1" name="1">
1032
		<bitfield name="DEST" low="0" high="31"/>
1033
	</reg32>
1034
	<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1035
		<bitfield name="DEST_HI" low="0" high="31"/>
1036
	</reg32>
1037
</domain>
1038

1039
<domain name="CP_REG_TO_MEM_OFFSET_REG" width="32">
1040
	<doc>
1041
                Like CP_REG_TO_MEM, but the memory address to write to can be
1042
                offsetted using either one or two registers or scratch
1043
                registers.
1044
	</doc>
1045
	<reg32 offset="0" name="0">
1046
		<bitfield name="REG" low="0" high="17" type="hex"/>
1047
		<!-- number of registers/dwords copied is max(CNT, 1). -->
1048
		<bitfield name="CNT" low="18" high="29" type="uint"/>
1049
		<bitfield name="64B" pos="30" type="boolean"/>
1050
		<bitfield name="ACCUMULATE" pos="31" type="boolean"/>
1051
	</reg32>
1052
	<reg32 offset="1" name="1">
1053
		<bitfield name="DEST" low="0" high="31"/>
1054
	</reg32>
1055
	<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1056
		<bitfield name="DEST_HI" low="0" high="31"/>
1057
	</reg32>
1058
	<reg32 offset="3" name="3">
1059
		<bitfield name="OFFSET0" low="0" high="17" type="hex"/>
1060
		<bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/>
1061
	</reg32>
1062
	<!-- followed by an optional identical OFFSET1 dword -->
1063
</domain>
1064

1065
<domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32">
1066
	<doc>
1067
                Like CP_REG_TO_MEM, but the memory address to write to can be
1068
                offsetted using a DWORD in memory.
1069
	</doc>
1070
	<reg32 offset="0" name="0">
1071
		<bitfield name="REG" low="0" high="17" type="hex"/>
1072
		<!-- number of registers/dwords copied is max(CNT, 1). -->
1073
		<bitfield name="CNT" low="18" high="29" type="uint"/>
1074
		<bitfield name="64B" pos="30" type="boolean"/>
1075
		<bitfield name="ACCUMULATE" pos="31" type="boolean"/>
1076
	</reg32>
1077
	<reg32 offset="1" name="1">
1078
		<bitfield name="DEST" low="0" high="31"/>
1079
	</reg32>
1080
	<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1081
		<bitfield name="DEST_HI" low="0" high="31"/>
1082
	</reg32>
1083
	<reg32 offset="3" name="3">
1084
		<bitfield name="OFFSET_LO" low="0" high="31" type="hex"/>
1085
	</reg32>
1086
	<reg32 offset="4" name="4">
1087
		<bitfield name="OFFSET_HI" low="0" high="31" type="hex"/>
1088
	</reg32>
1089
</domain>
1090

1091
<domain name="CP_MEM_TO_REG" width="32">
1092
	<reg32 offset="0" name="0">
1093
		<bitfield name="REG" low="0" high="17" type="hex"/>
1094
		<!-- number of registers/dwords copied is max(CNT, 1). -->
1095
		<bitfield name="CNT" low="19" high="29" type="uint"/>
1096
		<!-- shift each DWORD left by 2 while copying -->
1097
		<bitfield name="SHIFT_BY_2" pos="30" type="boolean"/>
1098
		<!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
1099
		<bitfield name="UNK31" pos="31" type="boolean"/>
1100
	</reg32>
1101
	<reg32 offset="1" name="1">
1102
		<bitfield name="SRC" low="0" high="31"/>
1103
	</reg32>
1104
	<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1105
		<bitfield name="SRC_HI" low="0" high="31"/>
1106
	</reg32>
1107
</domain>
1108

1109
<domain name="CP_MEM_TO_MEM" width="32">
1110
	<reg32 offset="0" name="0">
1111
		<!--
1112
		not sure how many src operands we have, but the low
1113
		bits negate the n'th src argument.
1114
		 -->
1115
		<bitfield name="NEG_A" pos="0" type="boolean"/>
1116
		<bitfield name="NEG_B" pos="1" type="boolean"/>
1117
		<bitfield name="NEG_C" pos="2" type="boolean"/>
1118

1119
		<!-- if set treat src/dst as 64bit values -->
1120
		<bitfield name="DOUBLE" pos="29" type="boolean"/>
1121
		<!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
1122
		<bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/>
1123
		<!-- some other kind of wait -->
1124
		<bitfield name="UNK31" pos="31" type="boolean"/>
1125
	</reg32>
1126
	<!--
1127
	followed by sequence of addresses.. the first is the
1128
	destination and the rest are N src addresses which are
1129
	summed (after being negated if NEG_x bit set) allowing
1130
	to do things like 'result += end - start' (which turns
1131
	out to be useful for queries and accumulating results
1132
	across multiple tiles)
1133
	 -->
1134
</domain>
1135

1136
<domain name="CP_MEMCPY" width="32">
1137
	<reg32 offset="0" name="0">
1138
		<bitfield name="DWORDS" low="0" high="31" type="uint"/>
1139
	</reg32>
1140
	<reg32 offset="1" name="1">
1141
		<bitfield name="SRC_LO" low="0" high="31" type="hex"/>
1142
	</reg32>
1143
	<reg32 offset="2" name="2">
1144
		<bitfield name="SRC_HI" low="0" high="31" type="hex"/>
1145
	</reg32>
1146
	<reg32 offset="3" name="3">
1147
		<bitfield name="DST_LO" low="0" high="31" type="hex"/>
1148
	</reg32>
1149
	<reg32 offset="4" name="4">
1150
		<bitfield name="DST_HI" low="0" high="31" type="hex"/>
1151
	</reg32>
1152
</domain>
1153

1154
<domain name="CP_REG_TO_SCRATCH" width="32">
1155
	<reg32 offset="0" name="0">
1156
		<bitfield name="REG" low="0" high="17" type="hex"/>
1157
		<bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1158
		<!-- number of registers/dwords copied is CNT + 1. -->
1159
		<bitfield name="CNT" low="24" high="26" type="uint"/>
1160
	</reg32>
1161
</domain>
1162

1163
<domain name="CP_SCRATCH_TO_REG" width="32">
1164
	<reg32 offset="0" name="0">
1165
		<bitfield name="REG" low="0" high="17" type="hex"/>
1166
		<!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
1167
		<bitfield name="UNK18" pos="18" type="boolean"/>
1168
		<bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1169
		<!-- number of registers/dwords copied is CNT + 1. -->
1170
		<bitfield name="CNT" low="24" high="26" type="uint"/>
1171
	</reg32>
1172
</domain>
1173

1174
<domain name="CP_SCRATCH_WRITE" width="32">
1175
	<reg32 offset="0" name="0">
1176
		<bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1177
	</reg32>
1178
	<!-- followed by one or more DWORDs to write to scratch registers -->
1179
</domain>
1180

1181
<domain name="CP_MEM_WRITE" width="32">
1182
	<reg32 offset="0" name="0">
1183
		<bitfield name="ADDR_LO" low="0" high="31"/>
1184
	</reg32>
1185
	<reg32 offset="1" name="1">
1186
		<bitfield name="ADDR_HI" low="0" high="31"/>
1187
	</reg32>
1188
	<!-- followed by the DWORDs to write -->
1189
</domain>
1190

1191
<enum name="cp_cond_function">
1192
	<value value="0" name="WRITE_ALWAYS"/>
1193
	<value value="1" name="WRITE_LT"/>
1194
	<value value="2" name="WRITE_LE"/>
1195
	<value value="3" name="WRITE_EQ"/>
1196
	<value value="4" name="WRITE_NE"/>
1197
	<value value="5" name="WRITE_GE"/>
1198
	<value value="6" name="WRITE_GT"/>
1199
</enum>
1200

1201
<domain name="CP_COND_WRITE" width="32">
1202
	<reg32 offset="0" name="0">
1203
		<bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1204
		<bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1205
		<bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1206
	</reg32>
1207
	<reg32 offset="1" name="1">
1208
		<bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
1209
	</reg32>
1210
	<reg32 offset="2" name="2">
1211
		<bitfield name="REF" low="0" high="31"/>
1212
	</reg32>
1213
	<reg32 offset="3" name="3">
1214
		<bitfield name="MASK" low="0" high="31"/>
1215
	</reg32>
1216
	<reg32 offset="4" name="4">
1217
		<bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
1218
	</reg32>
1219
	<reg32 offset="5" name="5">
1220
		<bitfield name="WRITE_DATA" low="0" high="31"/>
1221
	</reg32>
1222
</domain>
1223

1224
<domain name="CP_COND_WRITE5" width="32">
1225
	<reg32 offset="0" name="0">
1226
		<bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1227
		<bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1228
                <!-- if both POLL_MEMORY and POLL_SCRATCH are false, it polls a register at POLL_ADDR_LO instead. -->
1229
		<bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1230
		<bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
1231
		<bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1232
	</reg32>
1233
	<reg32 offset="1" name="1">
1234
		<bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1235
	</reg32>
1236
	<reg32 offset="2" name="2">
1237
		<bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1238
	</reg32>
1239
	<reg32 offset="3" name="3">
1240
		<bitfield name="REF" low="0" high="31"/>
1241
	</reg32>
1242
	<reg32 offset="4" name="4">
1243
		<bitfield name="MASK" low="0" high="31"/>
1244
	</reg32>
1245
	<reg32 offset="5" name="5">
1246
		<bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
1247
	</reg32>
1248
	<reg32 offset="6" name="6">
1249
		<bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
1250
	</reg32>
1251
	<reg32 offset="7" name="7">
1252
		<bitfield name="WRITE_DATA" low="0" high="31"/>
1253
	</reg32>
1254
</domain>
1255

1256
<domain name="CP_WAIT_MEM_GTE" width="32">
1257
        <doc>
1258
                Wait until a memory value is greater than or equal to the
1259
                reference, using signed comparison.
1260
	</doc>
1261
	<reg32 offset="0" name="0">
1262
		<!-- Reserved for flags, presumably? Unused in FW -->
1263
		<bitfield name="RESERVED" low="0" high="31" type="hex"/>
1264
	</reg32>
1265
	<reg32 offset="1" name="1">
1266
		<bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1267
	</reg32>
1268
	<reg32 offset="2" name="2">
1269
		<bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1270
	</reg32>
1271
	<reg32 offset="3" name="3">
1272
		<bitfield name="REF" low="0" high="31"/>
1273
	</reg32>
1274
</domain>
1275

1276
<domain name="CP_WAIT_REG_MEM" width="32">
1277
        <doc>
1278
                This uses the same internal comparison as CP_COND_WRITE,
1279
                but waits until the comparison is true instead. It busy-loops in
1280
                the CP for the given number of cycles before trying again.
1281
	</doc>
1282
	<reg32 offset="0" name="0">
1283
		<bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1284
		<bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1285
		<bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1286
		<bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
1287
		<bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1288
	</reg32>
1289
	<reg32 offset="1" name="1">
1290
		<bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1291
	</reg32>
1292
	<reg32 offset="2" name="2">
1293
		<bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1294
	</reg32>
1295
	<reg32 offset="3" name="3">
1296
		<bitfield name="REF" low="0" high="31"/>
1297
	</reg32>
1298
	<reg32 offset="4" name="4">
1299
		<bitfield name="MASK" low="0" high="31"/>
1300
	</reg32>
1301
	<reg32 offset="5" name="5">
1302
		<bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/>
1303
	</reg32>
1304
</domain>
1305

1306
<domain name="CP_WAIT_TWO_REGS" width="32">
1307
	<doc>
1308
		Waits for REG0 to not be 0 or REG1 to not equal REF
1309
	</doc>
1310
	<reg32 offset="0" name="0">
1311
		<bitfield name="REG0" low="0" high="17" type="hex"/>
1312
	</reg32>
1313
	<reg32 offset="1" name="1">
1314
		<bitfield name="REG1" low="0" high="17" type="hex"/>
1315
	</reg32>
1316
	<reg32 offset="2" name="2">
1317
		<bitfield name="REF" low="0" high="31" type="uint"/>
1318
	</reg32>
1319
</domain>
1320

1321
<domain name="CP_DISPATCH_COMPUTE" width="32">
1322
	<reg32 offset="0" name="0"/>
1323
	<reg32 offset="1" name="1">
1324
		<bitfield name="X" low="0" high="31"/>
1325
	</reg32>
1326
	<reg32 offset="2" name="2">
1327
		<bitfield name="Y" low="0" high="31"/>
1328
	</reg32>
1329
	<reg32 offset="3" name="3">
1330
		<bitfield name="Z" low="0" high="31"/>
1331
	</reg32>
1332
</domain>
1333

1334
<domain name="CP_SET_RENDER_MODE" width="32">
1335
	<enum name="render_mode_cmd">
1336
		<value value="1" name="BYPASS"/>
1337
		<value value="2" name="BINNING"/>
1338
		<value value="3" name="GMEM"/>
1339
		<value value="5" name="BLIT2D"/>
1340
		<!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
1341
		<value value="7" name="BLIT2DSCALE"/>
1342
		<!-- 8 set before going back to BYPASS exiting 2D -->
1343
		<value value="8" name="END2D"/>
1344
	</enum>
1345
	<reg32 offset="0" name="0">
1346
		<bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
1347
		<!--
1348
		normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
1349
		0x21xx range.. possibly (at least some) a5xx variants have a
1350
		2d core?
1351
		 -->
1352
	</reg32>
1353
	<!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1354
	<reg32 offset="1" name="1">
1355
		<bitfield name="ADDR_0_LO" low="0" high="31"/>
1356
	</reg32>
1357
	<reg32 offset="2" name="2">
1358
		<bitfield name="ADDR_0_HI" low="0" high="31"/>
1359
	</reg32>
1360
	<reg32 offset="3" name="3">
1361
		<!--
1362
		set when in GMEM.. maybe indicates GMEM contents need to be
1363
		preserved on ctx switch?
1364
		 -->
1365
		<bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
1366
		<bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
1367
	</reg32>
1368
	<reg32 offset="4" name="4"/>
1369
	<!-- second buffer looks like some cmdstream.. length in dwords: -->
1370
	<reg32 offset="5" name="5">
1371
		<bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1372
	</reg32>
1373
	<reg32 offset="6" name="6">
1374
		<bitfield name="ADDR_1_LO" low="0" high="31"/>
1375
	</reg32>
1376
	<reg32 offset="7" name="7">
1377
		<bitfield name="ADDR_1_HI" low="0" high="31"/>
1378
	</reg32>
1379
</domain>
1380

1381
<!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
1382
<domain name="CP_COMPUTE_CHECKPOINT" width="32">
1383
	<!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1384
	<reg32 offset="0" name="0">
1385
		<bitfield name="ADDR_0_LO" low="0" high="31"/>
1386
	</reg32>
1387
	<reg32 offset="1" name="1">
1388
		<bitfield name="ADDR_0_HI" low="0" high="31"/>
1389
	</reg32>
1390
	<reg32 offset="2" name="2">
1391
	</reg32>
1392
	<!-- second buffer looks like some cmdstream.. length in dwords: -->
1393
	<reg32 offset="3" name="3">
1394
		<bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1395
	</reg32>
1396
	<reg32 offset="4" name="4"/>
1397
	<reg32 offset="5" name="5">
1398
		<bitfield name="ADDR_1_LO" low="0" high="31"/>
1399
	</reg32>
1400
	<reg32 offset="6" name="6">
1401
		<bitfield name="ADDR_1_HI" low="0" high="31"/>
1402
	</reg32>
1403
	<reg32 offset="7" name="7"/>
1404
</domain>
1405

1406
<domain name="CP_PERFCOUNTER_ACTION" width="32">
1407
	<reg32 offset="0" name="0">
1408
	</reg32>
1409
	<reg32 offset="1" name="1">
1410
		<bitfield name="ADDR_0_LO" low="0" high="31"/>
1411
	</reg32>
1412
	<reg32 offset="2" name="2">
1413
		<bitfield name="ADDR_0_HI" low="0" high="31"/>
1414
	</reg32>
1415
</domain>
1416

1417
<domain name="CP_EVENT_WRITE" width="32">
1418
	<reg32 offset="0" name="0">
1419
		<bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1420
		<!-- when set, write back timestamp instead of value from packet: -->
1421
		<bitfield name="TIMESTAMP" pos="30" type="boolean"/>
1422
		<bitfield name="IRQ" pos="31" type="boolean"/>
1423
	</reg32>
1424
	<!--
1425
	TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
1426
	context switch?
1427
	 -->
1428
	<reg32 offset="1" name="1">
1429
		<bitfield name="ADDR_0_LO" low="0" high="31"/>
1430
	</reg32>
1431
	<reg32 offset="2" name="2">
1432
		<bitfield name="ADDR_0_HI" low="0" high="31"/>
1433
	</reg32>
1434
	<reg32 offset="3" name="3">
1435
		<!-- ??? -->
1436
	</reg32>
1437
</domain>
1438

1439
<domain name="CP_BLIT" width="32">
1440
	<enum name="cp_blit_cmd">
1441
		<value value="0" name="BLIT_OP_FILL"/>
1442
		<value value="1" name="BLIT_OP_COPY"/>
1443
		<value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1444
	</enum>
1445
	<reg32 offset="0" name="0">
1446
		<bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1447
	</reg32>
1448
	<reg32 offset="1" name="1">
1449
		<bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1450
		<bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1451
	</reg32>
1452
	<reg32 offset="2" name="2">
1453
		<bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1454
		<bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1455
	</reg32>
1456
	<reg32 offset="3" name="3">
1457
		<bitfield name="DST_X1" low="0" high="13" type="uint"/>
1458
		<bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1459
	</reg32>
1460
	<reg32 offset="4" name="4">
1461
		<bitfield name="DST_X2" low="0" high="13" type="uint"/>
1462
		<bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1463
	</reg32>
1464
</domain>
1465

1466
<domain name="CP_EXEC_CS" width="32">
1467
	<reg32 offset="0" name="0">
1468
	</reg32>
1469
	<reg32 offset="1" name="1">
1470
		<bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1471
	</reg32>
1472
	<reg32 offset="2" name="2">
1473
		<bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1474
	</reg32>
1475
	<reg32 offset="3" name="3">
1476
		<bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1477
	</reg32>
1478
</domain>
1479

1480
<domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1481
	<reg32 offset="0" name="0">
1482
	</reg32>
1483
	<stripe varset="chip" variants="A4XX">
1484
		<reg32 offset="1" name="1">
1485
			<bitfield name="ADDR" low="0" high="31"/>
1486
		</reg32>
1487
		<reg32 offset="2" name="2">
1488
			<!-- localsize is value minus one: -->
1489
			<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1490
			<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1491
			<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1492
		</reg32>
1493
	</stripe>
1494
	<stripe varset="chip" variants="A5XX-">
1495
		<reg32 offset="1" name="1">
1496
			<bitfield name="ADDR_LO" low="0" high="31"/>
1497
		</reg32>
1498
		<reg32 offset="2" name="2">
1499
			<bitfield name="ADDR_HI" low="0" high="31"/>
1500
		</reg32>
1501
		<reg32 offset="3" name="3">
1502
			<!-- localsize is value minus one: -->
1503
			<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1504
			<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1505
			<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1506
		</reg32>
1507
	</stripe>
1508
</domain>
1509

1510
<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1511
	<doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
1512
	<enum name="a6xx_render_mode">
1513
		<value value="1" name="RM6_BYPASS"/>
1514
		<value value="2" name="RM6_BINNING"/>
1515
		<value value="4" name="RM6_GMEM"/>
1516
		<value value="5" name="RM6_ENDVIS"/>
1517
		<value value="6" name="RM6_RESOLVE"/>
1518
		<value value="7" name="RM6_YIELD"/>
1519
		<value value="8" name="RM6_COMPUTE"/>
1520
		<value value="0xc" name="RM6_BLIT2DSCALE"/>  <!-- no-op (at least on current sqe fw) -->
1521

1522
		<!--
1523
			These values come from a6xx_set_marker() in the
1524
			downstream kernel, and they can only be set by the kernel
1525
		-->
1526
		<value value="0xd" name="RM6_IB1LIST_START"/>
1527
		<value value="0xe" name="RM6_IB1LIST_END"/>
1528
		<!-- IFPC - inter-frame power collapse -->
1529
		<value value="0x100" name="RM6_IFPC_ENABLE"/>
1530
		<value value="0x101" name="RM6_IFPC_DISABLE"/>
1531
	</enum>
1532
	<reg32 offset="0" name="0">
1533
		<!--
1534
			NOTE: blob driver and some versions of freedreno/turnip set
1535
			b4, which is unused (at least by current sqe fw), but interferes
1536
			with parsing if we extend the size of the bitfield to include
1537
			b8 (only sent by kernel mode driver).  Really, the way the
1538
			parsing works in the firmware, only b0-b3 are considered, but
1539
			if b8 is set, the low bits are interpreted differently.  To
1540
			model this, without getting confused by spurious b4, this is
1541
			described as two overlapping bitfields:
1542
		 -->
1543
		<bitfield name="MODE" low="0" high="8" type="a6xx_render_mode"/>
1544
		<bitfield name="MARKER" low="0" high="3" type="a6xx_render_mode"/>
1545
	</reg32>
1546
</domain>
1547

1548
<domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1549
	<doc>Set internal CP registers, used to indicate context save data addresses</doc>
1550
	<enum name="pseudo_reg">
1551
		<value value="0" name="SMMU_INFO"/>
1552
		<value value="1" name="NON_SECURE_SAVE_ADDR"/>
1553
		<value value="2" name="SECURE_SAVE_ADDR"/>
1554
		<value value="3" name="NON_PRIV_SAVE_ADDR"/>
1555
		<value value="4" name="COUNTER"/>
1556
	</enum>
1557
	<array offset="0" stride="3" length="100">
1558
		<reg32 offset="0" name="0">
1559
			<bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/>
1560
		</reg32>
1561
		<reg32 offset="1" name="1">
1562
			<bitfield name="LO" low="0" high="31"/>
1563
		</reg32>
1564
		<reg32 offset="2" name="2">
1565
			<bitfield name="HI" low="0" high="31"/>
1566
		</reg32>
1567
	</array>
1568
</domain>
1569

1570
<domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1571
	<doc>
1572
		Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
1573
		So:
1574

1575
			opcode: CP_REG_TEST (39) (2 dwords)
1576
			        { REG = 0xc10 | BIT = 0 }
1577
			               0000: 70b90001 00000c10
1578
			opcode: CP_COND_REG_EXEC (47) (3 dwords)
1579
			               0000: 70c70002 10000000 00000004
1580
			opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
1581

1582
		Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
1583
		offset 0x0c10 is 1
1584
	</doc>
1585
	<reg32 offset="0" name="0">
1586
		<!-- the register to test -->
1587
		<bitfield name="REG" low="0" high="17"/>
1588
		<!-- the bit to test -->
1589
		<bitfield name="BIT" low="20" high="24" type="uint"/>
1590
		<!-- execute CP_WAIT_FOR_ME beforehand -->
1591
		<bitfield name="WAIT_FOR_ME" pos="25" type="boolean"/>
1592
	</reg32>
1593
</domain>
1594

1595
<!-- I *think* this existed at least as far back as a4xx -->
1596
<domain name="CP_COND_REG_EXEC" width="32">
1597
	<enum name="compare_mode">
1598
		<!-- use the predicate bit set by CP_REG_TEST -->
1599
		<value value="1" name="PRED_TEST"/>
1600
		<!-- compare two registers directly for equality -->
1601
		<value value="2" name="REG_COMPARE"/>
1602
		<!-- test if certain render modes are set via CP_SET_MARKER -->
1603
		<value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/>
1604
	</enum>
1605
	<reg32 offset="0" name="0">
1606
		<bitfield name="REG0" low="0" high="17" type="hex"/>
1607

1608
		<!--
1609
			Note: these bits have the same meaning, and use the same
1610
			internal mechanism as the bits in CP_SET_DRAW_STATE.
1611
			When RENDER_MODE is selected, they're used as
1612
			a bitmask of which modes pass the test.
1613
		-->
1614

1615
		<!-- RM6_BINNING -->
1616
		<bitfield name="BINNING" pos="25" varset="chip" variants="A6XX-" type="boolean"/>
1617
		<!-- all others -->
1618
		<bitfield name="GMEM" pos="26" varset="chip" variants="A6XX-" type="boolean"/>
1619
		<!-- RM6_BYPASS -->
1620
		<bitfield name="SYSMEM" pos="27" varset="chip" variants="A6XX-" type="boolean"/>
1621

1622
		<bitfield name="MODE" low="28" high="31" type="compare_mode"/>
1623
	</reg32>
1624

1625
	<!-- in REG_COMPARE mode, there's an extra DWORD here with REG1 -->
1626

1627
	<reg32 offset="1" name="1">
1628
		<bitfield name="DWORDS" low="0" high="31" type="uint"/>
1629
	</reg32>
1630
</domain>
1631

1632
<domain name="CP_COND_EXEC" width="32">
1633
	<doc>
1634
                Executes the following DWORDs of commands if the dword at ADDR0
1635
                is not equal to 0 and the dword at ADDR1 is less than REF
1636
                (signed comparison).
1637
	</doc>
1638
	<reg32 offset="0" name="0">
1639
		<bitfield name="ADDR0_LO" low="0" high="31"/>
1640
	</reg32>
1641
	<reg32 offset="1" name="1">
1642
		<bitfield name="ADDR0_HI" low="0" high="31"/>
1643
	</reg32>
1644
	<reg32 offset="2" name="2">
1645
		<bitfield name="ADDR1_LO" low="0" high="31"/>
1646
	</reg32>
1647
	<reg32 offset="3" name="3">
1648
		<bitfield name="ADDR1_HI" low="0" high="31"/>
1649
	</reg32>
1650
	<reg32 offset="4" name="4">
1651
		<bitfield name="REF" low="0" high="31"/>
1652
	</reg32>
1653
	<reg32 offset="5" name="5">
1654
		<bitfield name="DWORDS" low="0" high="31" type="uint"/>
1655
	</reg32>
1656
</domain>
1657

1658
<domain name="CP_SET_CTXSWITCH_IB" width="32">
1659
	<doc>
1660
                Used by the userspace driver to set various IB's which are
1661
                executed during context save/restore for handling
1662
                state that isn't restored by the
1663
                context switch routine itself.
1664
	</doc>
1665
	<enum name="ctxswitch_ib">
1666
		<value name="RESTORE_IB" value="0">
1667
			<doc>Executed unconditionally when switching back to the context.</doc>
1668
		</value>
1669
		<value name="YIELD_RESTORE_IB" value="1">
1670
                        <doc>
1671
				Executed when switching back after switching
1672
				away during execution of
1673
				a CP_SET_MARKER packet with RM6_YIELD as the
1674
				payload *and* the normal save routine was
1675
				bypassed for a shorter one. I think this is
1676
				connected to the "skipsaverestore" bit set by
1677
				the kernel when preempting.
1678
			</doc>
1679
		</value>
1680
		<value name="SAVE_IB" value="2">
1681
                        <doc>
1682
				Executed when switching away from the context,
1683
				except for context switches initiated via
1684
				CP_YIELD.
1685
                        </doc>
1686
		</value>
1687
		<value name="RB_SAVE_IB" value="3">
1688
			<doc>
1689
				This can only be set by the RB (i.e. the kernel)
1690
				and executes with protected mode off, but
1691
				is otherwise similar to SAVE_IB.
1692
			</doc>
1693
		</value>
1694
	</enum>
1695
	<reg32 offset="0" name="0">
1696
		<bitfield name="ADDR_LO" low="0" high="31"/>
1697
	</reg32>
1698
	<reg32 offset="1" name="1">
1699
		<bitfield name="ADDR_HI" low="0" high="31"/>
1700
	</reg32>
1701
	<reg32 offset="2" name="2">
1702
		<bitfield name="DWORDS" low="0" high="19" type="uint"/>
1703
		<bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
1704
	</reg32>
1705
</domain>
1706

1707
<domain name="CP_REG_WRITE" width="32">
1708
	<enum name="reg_tracker">
1709
		<doc>
1710
			Keep shadow copies of these registers and only set them
1711
			when drawing, avoiding redundant writes:
1712
			- VPC_CNTL_0
1713
			- HLSQ_CONTROL_1_REG
1714
			- HLSQ_UNKNOWN_B980
1715
		</doc>
1716
		<value name="TRACK_CNTL_REG" value="0x1"/>
1717
		<doc>
1718
			Track RB_RENDER_CNTL, and insert a WFI in the following
1719
			situation:
1720
			- There is a write that disables binning
1721
			- There was a draw with binning left enabled, but in
1722
			  BYPASS mode
1723
			Presumably this is a hang workaround?
1724
		</doc>
1725
		<value name="TRACK_RENDER_CNTL" value="0x2"/>
1726
		<doc>
1727
			Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of
1728
			the data to write is 0. Used by the Vulkan blob with
1729
			PC_MULTIVIEW_CNTL, but this isn't predicated on particular
1730
			register(s) like the others.
1731
		</doc>
1732
		<value name="UNK_EVENT_WRITE" value="0x4"/>
1733
	</enum>
1734
	<reg32 offset="0" name="0">
1735
		<bitfield name="TRACKER" low="0" high="2" type="reg_tracker"/>
1736
	</reg32>
1737
</domain>
1738

1739
<domain name="CP_SMMU_TABLE_UPDATE" width="32">
1740
	<doc>
1741
		Note that the SMMU's definition of TTBRn can take different forms
1742
		depending on the pgtable format.  But a5xx+ only uses aarch64
1743
		format.
1744
	</doc>
1745
	<reg32 offset="0" name="0">
1746
		<bitfield name="TTBR0_LO" low="0" high="31"/>
1747
	</reg32>
1748
	<reg32 offset="1" name="1">
1749
		<bitfield name="TTBR0_HI" low="0" high="15"/>
1750
		<bitfield name="ASID" low="16" high="31"/>
1751
	</reg32>
1752
	<reg32 offset="2" name="2">
1753
		<doc>Unused, does not apply to aarch64 pgtable format</doc>
1754
		<bitfield name="CONTEXTIDR" low="0" high="31"/>
1755
	</reg32>
1756
	<reg32 offset="3" name="3">
1757
		<bitfield name="CONTEXTBANK" low="0" high="31"/>
1758
	</reg32>
1759
</domain>
1760

1761
</database>
1762

1763

1764
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