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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
 Path: blob/21.2-virgl/src/freedreno/registers/dsi/dsi.xml
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<?xml version="1.0" encoding="UTF-8"?>

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<database xmlns="http://nouveau.freedesktop.org/"

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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

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xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">

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<import file="freedreno_copyright.xml"/>

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<domain name="DSI" width="32">

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	<enum name="dsi_traffic_mode">

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		<value name="NON_BURST_SYNCH_PULSE" value="0"/>

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		<value name="NON_BURST_SYNCH_EVENT" value="1"/>

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		<value name="BURST_MODE" value="2"/>

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	</enum>

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	<enum name="dsi_vid_dst_format">

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		<value name="VID_DST_FORMAT_RGB565" value="0"/>

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		<value name="VID_DST_FORMAT_RGB666" value="1"/>

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		<value name="VID_DST_FORMAT_RGB666_LOOSE" value="2"/>

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		<value name="VID_DST_FORMAT_RGB888" value="3"/>

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	</enum>

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	<enum name="dsi_rgb_swap">

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		<value name="SWAP_RGB" value="0"/>

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		<value name="SWAP_RBG" value="1"/>

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		<value name="SWAP_BGR" value="2"/>

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		<value name="SWAP_BRG" value="3"/>

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		<value name="SWAP_GRB" value="4"/>

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		<value name="SWAP_GBR" value="5"/>

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	</enum>

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	<enum name="dsi_cmd_trigger">

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		<value name="TRIGGER_NONE" value="0"/>

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		<value name="TRIGGER_SEOF" value="1"/>

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		<value name="TRIGGER_TE" value="2"/>

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		<value name="TRIGGER_SW" value="4"/>

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		<value name="TRIGGER_SW_SEOF" value="5"/>

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		<value name="TRIGGER_SW_TE" value="6"/>

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	</enum>

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	<enum name="dsi_cmd_dst_format">

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		<value name="CMD_DST_FORMAT_RGB111" value="0"/>

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		<value name="CMD_DST_FORMAT_RGB332" value="3"/>

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		<value name="CMD_DST_FORMAT_RGB444" value="4"/>

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		<value name="CMD_DST_FORMAT_RGB565" value="6"/>

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		<value name="CMD_DST_FORMAT_RGB666" value="7"/>

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		<value name="CMD_DST_FORMAT_RGB888" value="8"/>

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	</enum>

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	<enum name="dsi_lane_swap">

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		<value name="LANE_SWAP_0123" value="0"/>

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		<value name="LANE_SWAP_3012" value="1"/>

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		<value name="LANE_SWAP_2301" value="2"/>

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		<value name="LANE_SWAP_1230" value="3"/>

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		<value name="LANE_SWAP_0321" value="4"/>

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		<value name="LANE_SWAP_1032" value="5"/>

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		<value name="LANE_SWAP_2103" value="6"/>

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		<value name="LANE_SWAP_3210" value="7"/>

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	</enum>

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	<bitset name="DSI_IRQ">

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		<bitfield name="CMD_DMA_DONE" pos="0" type="boolean"/>

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		<bitfield name="MASK_CMD_DMA_DONE" pos="1" type="boolean"/>

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		<bitfield name="CMD_MDP_DONE" pos="8" type="boolean"/>

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		<bitfield name="MASK_CMD_MDP_DONE" pos="9" type="boolean"/>

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		<bitfield name="VIDEO_DONE" pos="16" type="boolean"/>

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		<bitfield name="MASK_VIDEO_DONE" pos="17" type="boolean"/>

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		<bitfield name="BTA_DONE" pos="20" type="boolean"/>

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		<bitfield name="MASK_BTA_DONE" pos="21" type="boolean"/>

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		<bitfield name="ERROR" pos="24" type="boolean"/>

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		<bitfield name="MASK_ERROR" pos="25" type="boolean"/>

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	</bitset>

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	<reg32 offset="0x00000" name="6G_HW_VERSION">

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		<bitfield name="MAJOR" low="28" high="31" type="uint"/>

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		<bitfield name="MINOR" low="16" high="27" type="uint"/>

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		<bitfield name="STEP" low="0" high="15" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00000" name="CTRL">

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		<bitfield name="ENABLE" pos="0" type="boolean"/>

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		<bitfield name="VID_MODE_EN" pos="1" type="boolean"/>

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		<bitfield name="CMD_MODE_EN" pos="2" type="boolean"/>

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		<bitfield name="LANE0" pos="4" type="boolean"/>

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		<bitfield name="LANE1" pos="5" type="boolean"/>

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		<bitfield name="LANE2" pos="6" type="boolean"/>

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		<bitfield name="LANE3" pos="7" type="boolean"/>

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		<bitfield name="CLK_EN" pos="8" type="boolean"/>

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		<bitfield name="ECC_CHECK" pos="20" type="boolean"/>

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		<bitfield name="CRC_CHECK" pos="24" type="boolean"/>

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	</reg32>

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	<reg32 offset="0x00004" name="STATUS0">

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		<bitfield name="CMD_MODE_ENGINE_BUSY" pos="0" type="boolean"/>

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		<bitfield name="CMD_MODE_DMA_BUSY" pos="1" type="boolean"/>

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		<bitfield name="CMD_MODE_MDP_BUSY" pos="2" type="boolean"/>

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		<bitfield name="VIDEO_MODE_ENGINE_BUSY" pos="3" type="boolean"/>

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		<bitfield name="DSI_BUSY" pos="4" type="boolean"/>  <!-- see mipi_dsi_cmd_bta_sw_trigger() -->

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		<bitfield name="INTERLEAVE_OP_CONTENTION" pos="31" type="boolean"/>

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	</reg32>

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	<reg32 offset="0x00008" name="FIFO_STATUS">

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		<bitfield name="VIDEO_MDP_FIFO_OVERFLOW" pos="0" type="boolean"/>

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		<bitfield name="VIDEO_MDP_FIFO_UNDERFLOW" pos="3" type="boolean"/>

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		<bitfield name="CMD_MDP_FIFO_UNDERFLOW" pos="7" type="boolean"/>

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		<bitfield name="CMD_DMA_FIFO_RD_WATERMARK_REACH" pos="8" type="boolean"/>

99
		<bitfield name="CMD_DMA_FIFO_WR_WATERMARK_REACH" pos="9" type="boolean"/>

100
		<bitfield name="CMD_DMA_FIFO_UNDERFLOW" pos="10" type="boolean"/>

101
		<bitfield name="DLN0_LP_FIFO_EMPTY"     pos="12" type="boolean"/>

102
		<bitfield name="DLN0_LP_FIFO_FULL"      pos="13" type="boolean"/>

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		<bitfield name="DLN0_LP_FIFO_OVERFLOW"  pos="14" type="boolean"/>

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		<bitfield name="DLN0_HS_FIFO_EMPTY"     pos="16" type="boolean"/>

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		<bitfield name="DLN0_HS_FIFO_FULL"      pos="17" type="boolean"/>

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		<bitfield name="DLN0_HS_FIFO_OVERFLOW"  pos="18" type="boolean"/>

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		<bitfield name="DLN0_HS_FIFO_UNDERFLOW" pos="19" type="boolean"/>

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		<bitfield name="DLN1_HS_FIFO_EMPTY"     pos="20" type="boolean"/>

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		<bitfield name="DLN1_HS_FIFO_FULL"      pos="21" type="boolean"/>

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		<bitfield name="DLN1_HS_FIFO_OVERFLOW"  pos="22" type="boolean"/>

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		<bitfield name="DLN1_HS_FIFO_UNDERFLOW" pos="23" type="boolean"/>

112
		<bitfield name="DLN2_HS_FIFO_EMPTY"     pos="24" type="boolean"/>

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		<bitfield name="DLN2_HS_FIFO_FULL"      pos="25" type="boolean"/>

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		<bitfield name="DLN2_HS_FIFO_OVERFLOW"  pos="26" type="boolean"/>

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		<bitfield name="DLN2_HS_FIFO_UNDERFLOW" pos="27" type="boolean"/>

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		<bitfield name="DLN3_HS_FIFO_EMPTY"     pos="28" type="boolean"/>

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		<bitfield name="DLN3_HS_FIFO_FULL"      pos="29" type="boolean"/>

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		<bitfield name="DLN3_HS_FIFO_OVERFLOW"  pos="30" type="boolean"/>

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		<bitfield name="DLN3_HS_FIFO_UNDERFLOW" pos="31" type="boolean"/>

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	</reg32>

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	<reg32 offset="0x0000c" name="VID_CFG0">

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		<bitfield name="VIRT_CHANNEL" low="0" high="1" type="uint"/>  <!-- always zero? -->

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		<bitfield name="DST_FORMAT" low="4" high="5" type="dsi_vid_dst_format"/>

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		<bitfield name="TRAFFIC_MODE" low="8" high="9" type="dsi_traffic_mode"/>

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		<bitfield name="BLLP_POWER_STOP" pos="12" type="boolean"/>

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		<bitfield name="EOF_BLLP_POWER_STOP" pos="15" type="boolean"/>

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		<bitfield name="HSA_POWER_STOP" pos="16" type="boolean"/>

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		<bitfield name="HBP_POWER_STOP" pos="20" type="boolean"/>

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		<bitfield name="HFP_POWER_STOP" pos="24" type="boolean"/>

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		<bitfield name="PULSE_MODE_HSA_HE" pos="28" type="boolean"/>

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	</reg32>

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	<reg32 offset="0x0001c" name="VID_CFG1">

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		<bitfield name="R_SEL" pos="0" type="boolean"/>

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		<bitfield name="G_SEL" pos="4" type="boolean"/>

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		<bitfield name="B_SEL" pos="8" type="boolean"/>

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		<bitfield name="RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>

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	</reg32>

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	<reg32 offset="0x00020" name="ACTIVE_H">

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		<bitfield name="START" low="0" high="11" type="uint"/>

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		<bitfield name="END" low="16" high="27" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00024" name="ACTIVE_V">

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		<bitfield name="START" low="0" high="11" type="uint"/>

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		<bitfield name="END" low="16" high="27" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00028" name="TOTAL">

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		<bitfield name="H_TOTAL" low="0" high="11" type="uint"/>

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		<bitfield name="V_TOTAL" low="16" high="27" type="uint"/>

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	</reg32>

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	<reg32 offset="0x0002c" name="ACTIVE_HSYNC">

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		<bitfield name="START" low="0" high="11" type="uint"/>

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		<bitfield name="END" low="16" high="27" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00030" name="ACTIVE_VSYNC_HPOS">

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		<bitfield name="START" low="0" high="11" type="uint"/>

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		<bitfield name="END" low="16" high="27" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00034" name="ACTIVE_VSYNC_VPOS">

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		<bitfield name="START" low="0" high="11" type="uint"/>

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		<bitfield name="END" low="16" high="27" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00038" name="CMD_DMA_CTRL">

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		<bitfield name="BROADCAST_EN" pos="31" type="boolean"/>

165
		<bitfield name="FROM_FRAME_BUFFER" pos="28" type="boolean"/>

166
		<bitfield name="LOW_POWER" pos="26" type="boolean"/>

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	</reg32>

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	<reg32 offset="0x0003c" name="CMD_CFG0">

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		<bitfield name="DST_FORMAT" low="0" high="3" type="dsi_cmd_dst_format"/>

170
		<bitfield name="R_SEL" pos="4" type="boolean"/>

171
		<bitfield name="G_SEL" pos="8" type="boolean"/>

172
		<bitfield name="B_SEL" pos="12" type="boolean"/>

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		<bitfield name="INTERLEAVE_MAX" low="20" high="23" type="uint"/>

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		<bitfield name="RGB_SWAP" low="16" high="18" type="dsi_rgb_swap"/>

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	</reg32>

176
	<reg32 offset="0x00040" name="CMD_CFG1">

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		<bitfield name="WR_MEM_START" low="0" high="7" type="uint"/>

178
		<bitfield name="WR_MEM_CONTINUE" low="8" high="15" type="uint"/>

179
		<bitfield name="INSERT_DCS_COMMAND" pos="16" type="boolean"/>

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	</reg32>

181
	<reg32 offset="0x00044" name="DMA_BASE"/>

182
	<reg32 offset="0x00048" name="DMA_LEN"/>

183
	<reg32 offset="0x00054" name="CMD_MDP_STREAM0_CTRL">

184
		<bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>

185
		<bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>

186
		<bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>

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	</reg32>

188
	<reg32 offset="0x00058" name="CMD_MDP_STREAM0_TOTAL">

189
		<bitfield name="H_TOTAL" low="0" high="11" type="uint"/>

190
		<bitfield name="V_TOTAL" low="16" high="27" type="uint"/>

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	</reg32>

192
	<reg32 offset="0x0005c" name="CMD_MDP_STREAM1_CTRL">

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		<bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>

194
		<bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>

195
		<bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>

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	</reg32>

197
	<reg32 offset="0x00060" name="CMD_MDP_STREAM1_TOTAL">

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		<bitfield name="H_TOTAL" low="0" high="15" type="uint"/>

199
		<bitfield name="V_TOTAL" low="16" high="31" type="uint"/>

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	</reg32>

201
	<reg32 offset="0x00064" name="ACK_ERR_STATUS"/>

202
	<array offset="0x00068" name="RDBK" length="4" stride="4">

203
		<reg32 offset="0x0" name="DATA"/>

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	</array>

205
	<reg32 offset="0x00080" name="TRIG_CTRL">

206
		<bitfield name="DMA_TRIGGER" low="0" high="2" type="dsi_cmd_trigger"/>

207
		<bitfield name="MDP_TRIGGER" low="4" high="6" type="dsi_cmd_trigger"/>

208
		<bitfield name="STREAM" low="8" high="9" type="uint"/>

209
		<bitfield name="BLOCK_DMA_WITHIN_FRAME" pos="12" type="boolean"/>

210
		<bitfield name="TE" pos="31" type="boolean"/>

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	</reg32>

212
	<reg32 offset="0x0008c" name="TRIG_DMA"/>

213
	<reg32 offset="0x000b0" name="DLN0_PHY_ERR">

214
		<bitfield name="DLN0_ERR_ESC" pos="0" type="boolean"/>

215
		<bitfield name="DLN0_ERR_SYNC_ESC" pos="4" type="boolean"/>

216
		<bitfield name="DLN0_ERR_CONTROL" pos="8" type="boolean"/>

217
		<bitfield name="DLN0_ERR_CONTENTION_LP0" pos="12" type="boolean"/>

218
		<bitfield name="DLN0_ERR_CONTENTION_LP1" pos="16" type="boolean"/>

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	</reg32>

220
	<reg32 offset="0x000b4" name="LP_TIMER_CTRL">

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		<bitfield name="LP_RX_TO" low="0" high="15" type="uint"/>

222
		<bitfield name="BTA_TO" low="16" high="31" type="uint"/>

223
	</reg32>

224
	<reg32 offset="0x000b8" name="HS_TIMER_CTRL">

225
		<bitfield name="HS_TX_TO" low="0" high="15" type="uint"/>

226
		<bitfield name="TIMER_RESOLUTION" low="16" high="19" type="uint"/>

227
		<bitfield name="HS_TX_TO_STOP_EN" pos="28" type="boolean"/>

228
	</reg32>

229
	<reg32 offset="0x000bc" name="TIMEOUT_STATUS"/>

230
	<reg32 offset="0x000c0" name="CLKOUT_TIMING_CTRL">

231
		<bitfield name="T_CLK_PRE" low="0" high="5" type="uint"/>

232
		<bitfield name="T_CLK_POST" low="8" high="13" type="uint"/>

233
	</reg32>

234
	<reg32 offset="0x000c8" name="EOT_PACKET_CTRL">

235
		<bitfield name="TX_EOT_APPEND" pos="0" type="boolean"/>

236
		<bitfield name="RX_EOT_IGNORE" pos="4" type="boolean"/>

237
	</reg32>

238
	<reg32 offset="0x000a4" name="LANE_STATUS">

239
		<bitfield name="DLN0_STOPSTATE" pos="0" type="boolean"/>

240
		<bitfield name="DLN1_STOPSTATE" pos="1" type="boolean"/>

241
		<bitfield name="DLN2_STOPSTATE" pos="2" type="boolean"/>

242
		<bitfield name="DLN3_STOPSTATE" pos="3" type="boolean"/>

243
		<bitfield name="CLKLN_STOPSTATE" pos="4" type="boolean"/>

244
		<bitfield name="DLN0_ULPS_ACTIVE_NOT" pos="8" type="boolean"/>

245
		<bitfield name="DLN1_ULPS_ACTIVE_NOT" pos="9" type="boolean"/>

246
		<bitfield name="DLN2_ULPS_ACTIVE_NOT" pos="10" type="boolean"/>

247
		<bitfield name="DLN3_ULPS_ACTIVE_NOT" pos="11" type="boolean"/>

248
		<bitfield name="CLKLN_ULPS_ACTIVE_NOT" pos="12" type="boolean"/>

249
		<bitfield name="DLN0_DIRECTION" pos="16" type="boolean"/>

250
	</reg32>

251
	<reg32 offset="0x000a8" name="LANE_CTRL">

252
		<bitfield name="CLKLN_HS_FORCE_REQUEST" pos="28" type="boolean"/>

253
	</reg32>

254
	<reg32 offset="0x000ac" name="LANE_SWAP_CTRL">

255
		<bitfield name="DLN_SWAP_SEL" low="0" high="2" type="dsi_lane_swap"/>

256
	</reg32>

257
	<reg32 offset="0x00108" name="ERR_INT_MASK0"/>

258
	<reg32 offset="0x0010c" name="INTR_CTRL" type="DSI_IRQ"/>

259
	<reg32 offset="0x00114" name="RESET"/>

260
	<reg32 offset="0x00118" name="CLK_CTRL">

261
		<bitfield name="AHBS_HCLK_ON" pos="0" type="boolean"/>

262
		<bitfield name="AHBM_SCLK_ON" pos="1" type="boolean"/>

263
		<bitfield name="PCLK_ON" pos="2" type="boolean"/>

264
		<bitfield name="DSICLK_ON" pos="3" type="boolean"/>

265
		<bitfield name="BYTECLK_ON" pos="4" type="boolean"/>

266
		<bitfield name="ESCCLK_ON" pos="5" type="boolean"/>

267
		<bitfield name="FORCE_ON_DYN_AHBM_HCLK" pos="9" type="boolean"/>

268
	</reg32>

269
	<reg32 offset="0x0011c" name="CLK_STATUS">

270
		<bitfield name="DSI_AON_AHBM_HCLK_ACTIVE" pos="0" type="boolean"/>

271
		<bitfield name="DSI_DYN_AHBM_HCLK_ACTIVE" pos="1" type="boolean"/>

272
		<bitfield name="DSI_AON_AHBS_HCLK_ACTIVE" pos="2" type="boolean"/>

273
		<bitfield name="DSI_DYN_AHBS_HCLK_ACTIVE" pos="3" type="boolean"/>

274
		<bitfield name="DSI_AON_DSICLK_ACTIVE" pos="4" type="boolean"/>

275
		<bitfield name="DSI_DYN_DSICLK_ACTIVE" pos="5" type="boolean"/>

276
		<bitfield name="DSI_AON_BYTECLK_ACTIVE" pos="6" type="boolean"/>

277
		<bitfield name="DSI_DYN_BYTECLK_ACTIVE" pos="7" type="boolean"/>

278
		<bitfield name="DSI_AON_ESCCLK_ACTIVE" pos="8" type="boolean"/>

279
		<bitfield name="DSI_AON_PCLK_ACTIVE" pos="9" type="boolean"/>

280
		<bitfield name="DSI_DYN_PCLK_ACTIVE" pos="10" type="boolean"/>

281
		<bitfield name="DSI_DYN_CMD_PCLK_ACTIVE" pos="12" type="boolean"/>

282
		<bitfield name="DSI_CMD_PCLK_ACTIVE" pos="13" type="boolean"/>

283
		<bitfield name="DSI_VID_PCLK_ACTIVE" pos="14" type="boolean"/>

284
		<bitfield name="DSI_CAM_BIST_PCLK_ACT" pos="15" type="boolean"/>

285
		<bitfield name="PLL_UNLOCKED" pos="16" type="boolean"/>

286
	</reg32>

287
	<reg32 offset="0x00128" name="PHY_RESET">

288
		<bitfield name="RESET" pos="0" type="boolean"/>

289
	</reg32>

290
	<reg32 offset="0x0017c" name="T_CLK_PRE_EXTEND">

291
		<bitfield name="INC_BY_2_BYTECLK" pos="0" type="boolean"/>

292
	</reg32>

293
	<reg32 offset="0x001b4" name="CMD_MODE_MDP_CTRL2">

294
		<bitfield name="DST_FORMAT2" low="0" high="3" type="dsi_cmd_dst_format"/>

295
		<bitfield name="R_SEL" pos="4" type="boolean"/>

296
		<bitfield name="G_SEL" pos="5" type="boolean"/>

297
		<bitfield name="B_SEL" pos="6" type="boolean"/>

298
		<bitfield name="BYTE_MSB_LSB_FLIP" pos="7" type="boolean"/>

299
		<bitfield name="RGB_SWAP" low="8" high="10" type="dsi_rgb_swap"/>

300
		<bitfield name="INPUT_RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>

301
		<bitfield name="BURST_MODE" pos="16" type="boolean"/>

302
	</reg32>

303
	<reg32 offset="0x001b8" name="CMD_MODE_MDP_STREAM2_CTRL">

304
		<bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>

305
		<bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>

306
		<bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>

307
	</reg32>

308
	<reg32 offset="0x001d0" name="RDBK_DATA_CTRL">

309
		<bitfield name="COUNT" low="16" high="23" type="uint"/>

310
		<bitfield name="CLR" pos="0" type="boolean"/>

311
	</reg32>

312
	<reg32 offset="0x001f0" name="VERSION">

313
		<bitfield name="MAJOR" low="24" high="31" type="uint"/>

314
	</reg32>

315
	<reg32 offset="0x002d4" name="CPHY_MODE_CTRL"/>

316
</domain>

317


318
</database>

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