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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
 Path: blob/21.2-virgl/src/freedreno/registers/dsi/dsi_phy_10nm.xml
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<?xml version="1.0" encoding="UTF-8"?>

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<database xmlns="http://nouveau.freedesktop.org/"

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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

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xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">

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<import file="freedreno_copyright.xml"/>

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<domain name="DSI_10nm_PHY_CMN" width="32">

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	<reg32 offset="0x00000" name="REVISION_ID0"/>

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	<reg32 offset="0x00004" name="REVISION_ID1"/>

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	<reg32 offset="0x00008" name="REVISION_ID2"/>

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	<reg32 offset="0x0000c" name="REVISION_ID3"/>

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	<reg32 offset="0x00010" name="CLK_CFG0"/>

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	<reg32 offset="0x00014" name="CLK_CFG1"/>

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	<reg32 offset="0x00018" name="GLBL_CTRL"/>

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	<reg32 offset="0x0001c" name="RBUF_CTRL"/>

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	<reg32 offset="0x00020" name="VREG_CTRL"/>

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	<reg32 offset="0x00024" name="CTRL_0"/>

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	<reg32 offset="0x00028" name="CTRL_1"/>

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	<reg32 offset="0x0002c" name="CTRL_2"/>

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	<reg32 offset="0x00030" name="LANE_CFG0"/>

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	<reg32 offset="0x00034" name="LANE_CFG1"/>

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	<reg32 offset="0x00038" name="PLL_CNTRL"/>

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	<reg32 offset="0x00098" name="LANE_CTRL0"/>

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	<reg32 offset="0x0009c" name="LANE_CTRL1"/>

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	<reg32 offset="0x000a0" name="LANE_CTRL2"/>

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	<reg32 offset="0x000a4" name="LANE_CTRL3"/>

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	<reg32 offset="0x000a8" name="LANE_CTRL4"/>

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	<reg32 offset="0x000ac" name="TIMING_CTRL_0"/>

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	<reg32 offset="0x000b0" name="TIMING_CTRL_1"/>

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	<reg32 offset="0x000b4" name="TIMING_CTRL_2"/>

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	<reg32 offset="0x000b8" name="TIMING_CTRL_3"/>

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	<reg32 offset="0x000bc" name="TIMING_CTRL_4"/>

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	<reg32 offset="0x000c0" name="TIMING_CTRL_5"/>

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	<reg32 offset="0x000c4" name="TIMING_CTRL_6"/>

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	<reg32 offset="0x000c8" name="TIMING_CTRL_7"/>

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	<reg32 offset="0x000cc" name="TIMING_CTRL_8"/>

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	<reg32 offset="0x000d0" name="TIMING_CTRL_9"/>

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	<reg32 offset="0x000d4" name="TIMING_CTRL_10"/>

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	<reg32 offset="0x000d8" name="TIMING_CTRL_11"/>

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	<reg32 offset="0x000ec" name="PHY_STATUS"/>

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	<reg32 offset="0x000f4" name="LANE_STATUS0"/>

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	<reg32 offset="0x000f8" name="LANE_STATUS1"/>

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</domain>

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<domain name="DSI_10nm_PHY" width="32">

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	<array offset="0x00000" name="LN" length="5" stride="0x80">

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		<reg32 offset="0x00" name="CFG0"/>

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		<reg32 offset="0x04" name="CFG1"/>

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		<reg32 offset="0x08" name="CFG2"/>

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		<reg32 offset="0x0c" name="CFG3"/>

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		<reg32 offset="0x10" name="TEST_DATAPATH"/>

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		<reg32 offset="0x14" name="PIN_SWAP"/>

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		<reg32 offset="0x18" name="HSTX_STR_CTRL"/>

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		<reg32 offset="0x1c" name="OFFSET_TOP_CTRL"/>

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		<reg32 offset="0x20" name="OFFSET_BOT_CTRL"/>

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		<reg32 offset="0x24" name="LPTX_STR_CTRL"/>

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		<reg32 offset="0x28" name="LPRX_CTRL"/>

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		<reg32 offset="0x2c" name="TX_DCTRL"/>

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	</array>

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</domain>

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<domain name="DSI_10nm_PHY_PLL" width="32">

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	<reg32 offset="0x0000" name="ANALOG_CONTROLS_ONE"/>

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	<reg32 offset="0x0004" name="ANALOG_CONTROLS_TWO"/>

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	<reg32 offset="0x0010" name="ANALOG_CONTROLS_THREE"/>

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	<reg32 offset="0x001c" name="DSM_DIVIDER"/>

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	<reg32 offset="0x0020" name="FEEDBACK_DIVIDER"/>

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	<reg32 offset="0x0024" name="SYSTEM_MUXES"/>

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	<reg32 offset="0x002c" name="CMODE"/>

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	<reg32 offset="0x0030" name="CALIBRATION_SETTINGS"/>

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	<reg32 offset="0x0054" name="BAND_SEL_CAL_SETTINGS_THREE"/>

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	<reg32 offset="0x0064" name="FREQ_DETECT_SETTINGS_ONE"/>

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	<reg32 offset="0x007c" name="PFILT"/>

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	<reg32 offset="0x0080" name="IFILT"/>

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	<reg32 offset="0x0094" name="OUTDIV"/>

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	<reg32 offset="0x00a4" name="CORE_OVERRIDE"/>

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	<reg32 offset="0x00a8" name="CORE_INPUT_OVERRIDE"/>

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	<reg32 offset="0x00b4" name="PLL_DIGITAL_TIMERS_TWO"/>

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	<reg32 offset="0x00cc" name="DECIMAL_DIV_START_1"/>

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	<reg32 offset="0x00d0" name="FRAC_DIV_START_LOW_1"/>

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	<reg32 offset="0x00d4" name="FRAC_DIV_START_MID_1"/>

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	<reg32 offset="0x00d8" name="FRAC_DIV_START_HIGH_1"/>

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	<reg32 offset="0x010c" name="SSC_STEPSIZE_LOW_1"/>

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	<reg32 offset="0x0110" name="SSC_STEPSIZE_HIGH_1"/>

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	<reg32 offset="0x0114" name="SSC_DIV_PER_LOW_1"/>

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	<reg32 offset="0x0118" name="SSC_DIV_PER_HIGH_1"/>

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	<reg32 offset="0x011c" name="SSC_DIV_ADJPER_LOW_1"/>

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	<reg32 offset="0x0120" name="SSC_DIV_ADJPER_HIGH_1"/>

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	<reg32 offset="0x013c" name="SSC_CONTROL"/>

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	<reg32 offset="0x0140" name="PLL_OUTDIV_RATE"/>

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	<reg32 offset="0x0144" name="PLL_LOCKDET_RATE_1"/>

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	<reg32 offset="0x014c" name="PLL_PROP_GAIN_RATE_1"/>

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	<reg32 offset="0x0154" name="PLL_BAND_SET_RATE_1"/>

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	<reg32 offset="0x015c" name="PLL_INT_GAIN_IFILT_BAND_1"/>

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	<reg32 offset="0x0164" name="PLL_FL_INT_GAIN_PFILT_BAND_1"/>

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	<reg32 offset="0x0180" name="PLL_LOCK_OVERRIDE"/>

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	<reg32 offset="0x0184" name="PLL_LOCK_DELAY"/>

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	<reg32 offset="0x018c" name="CLOCK_INVERTERS"/>

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	<reg32 offset="0x01a0" name="COMMON_STATUS_ONE"/>

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</domain>

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</database>

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