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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
 Path: blob/21.2-virgl/src/freedreno/registers/dsi/dsi_phy_20nm.xml
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<?xml version="1.0" encoding="UTF-8"?>

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<database xmlns="http://nouveau.freedesktop.org/"

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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

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xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">

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<import file="freedreno_copyright.xml"/>

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<domain name="DSI_20nm_PHY" width="32">

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	<array offset="0x00000" name="LN" length="4" stride="0x40">

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		<reg32 offset="0x00" name="CFG_0"/>

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		<reg32 offset="0x04" name="CFG_1"/>

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		<reg32 offset="0x08" name="CFG_2"/>

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		<reg32 offset="0x0c" name="CFG_3"/>

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		<reg32 offset="0x10" name="CFG_4"/>

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		<reg32 offset="0x14" name="TEST_DATAPATH"/>

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		<reg32 offset="0x18" name="DEBUG_SEL"/>

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		<reg32 offset="0x1c" name="TEST_STR_0"/>

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		<reg32 offset="0x20" name="TEST_STR_1"/>

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	</array>

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	<reg32 offset="0x00100" name="LNCK_CFG_0"/>

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	<reg32 offset="0x00104" name="LNCK_CFG_1"/>

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	<reg32 offset="0x00108" name="LNCK_CFG_2"/>

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	<reg32 offset="0x0010c" name="LNCK_CFG_3"/>

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	<reg32 offset="0x00110" name="LNCK_CFG_4"/>

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	<reg32 offset="0x00114" name="LNCK_TEST_DATAPATH"/>

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	<reg32 offset="0x00118" name="LNCK_DEBUG_SEL"/>

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	<reg32 offset="0x0011c" name="LNCK_TEST_STR0"/>

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	<reg32 offset="0x00120" name="LNCK_TEST_STR1"/>

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	<reg32 offset="0x00140" name="TIMING_CTRL_0">

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		<bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00144" name="TIMING_CTRL_1">

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		<bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00148" name="TIMING_CTRL_2">

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		<bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>

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	</reg32>

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	<reg32 offset="0x0014c" name="TIMING_CTRL_3">

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		<bitfield name="CLK_ZERO_8" pos="0" type="boolean"/>

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	</reg32>

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	<reg32 offset="0x00150" name="TIMING_CTRL_4">

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		<bitfield name="HS_EXIT" low="0" high="7" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00154" name="TIMING_CTRL_5">

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		<bitfield name="HS_ZERO" low="0" high="7" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00158" name="TIMING_CTRL_6">

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		<bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>

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	</reg32>

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	<reg32 offset="0x0015c" name="TIMING_CTRL_7">

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		<bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00160" name="TIMING_CTRL_8">

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		<bitfield name="HS_RQST" low="0" high="7" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00164" name="TIMING_CTRL_9">

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		<bitfield name="TA_GO" low="0" high="2" type="uint"/>

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		<bitfield name="TA_SURE" low="4" high="6" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00168" name="TIMING_CTRL_10">

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		<bitfield name="TA_GET" low="0" high="2" type="uint"/>

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	</reg32>

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	<reg32 offset="0x0016c" name="TIMING_CTRL_11">

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		<bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>

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	</reg32>

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	<reg32 offset="0x00170" name="CTRL_0"/>

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	<reg32 offset="0x00174" name="CTRL_1"/>

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	<reg32 offset="0x00178" name="CTRL_2"/>

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	<reg32 offset="0x0017c" name="CTRL_3"/>

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	<reg32 offset="0x00180" name="CTRL_4"/>

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	<reg32 offset="0x00184" name="STRENGTH_0"/>

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	<reg32 offset="0x00188" name="STRENGTH_1"/>

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	<reg32 offset="0x001b4" name="BIST_CTRL_0"/>

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	<reg32 offset="0x001b8" name="BIST_CTRL_1"/>

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	<reg32 offset="0x001bc" name="BIST_CTRL_2"/>

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	<reg32 offset="0x001c0" name="BIST_CTRL_3"/>

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	<reg32 offset="0x001c4" name="BIST_CTRL_4"/>

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	<reg32 offset="0x001c8" name="BIST_CTRL_5"/>

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	<reg32 offset="0x001d4" name="GLBL_TEST_CTRL">

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		<bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/>

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	</reg32>

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	<reg32 offset="0x001dc" name="LDO_CNTRL"/>

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</domain>

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<domain name="DSI_20nm_PHY_REGULATOR" width="32">

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	<reg32 offset="0x00000" name="CTRL_0"/>

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	<reg32 offset="0x00004" name="CTRL_1"/>

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	<reg32 offset="0x00008" name="CTRL_2"/>

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	<reg32 offset="0x0000c" name="CTRL_3"/>

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	<reg32 offset="0x00010" name="CTRL_4"/>

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	<reg32 offset="0x00014" name="CTRL_5"/>

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	<reg32 offset="0x00018" name="CAL_PWR_CFG"/>

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</domain>

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</database>

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