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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/asahi/agx_state.h
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/*
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* Copyright 2021 Alyssa Rosenzweig
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* Copyright (C) 2019-2021 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef AGX_STATE_H
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#define AGX_STATE_H
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#include "gallium/include/pipe/p_context.h"
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#include "gallium/include/pipe/p_state.h"
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#include "gallium/include/pipe/p_screen.h"
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#include "gallium/auxiliary/util/u_blitter.h"
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#include "asahi/lib/agx_pack.h"
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#include "asahi/lib/agx_bo.h"
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#include "asahi/lib/agx_device.h"
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#include "asahi/lib/pool.h"
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#include "asahi/compiler/agx_compile.h"
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#include "compiler/nir/nir_lower_blend.h"
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#include "util/hash_table.h"
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#include "util/bitset.h"
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struct agx_streamout_target {
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struct pipe_stream_output_target base;
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uint32_t offset;
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};
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struct agx_streamout {
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struct pipe_stream_output_target *targets[PIPE_MAX_SO_BUFFERS];
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unsigned num_targets;
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};
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static inline struct agx_streamout_target *
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agx_so_target(struct pipe_stream_output_target *target)
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{
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return (struct agx_streamout_target *)target;
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}
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struct agx_compiled_shader {
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/* Mapped executable memory */
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struct agx_bo *bo;
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/* Varying descriptor (TODO: is this the right place?) */
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uint64_t varyings;
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/* Metadata returned from the compiler */
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struct agx_shader_info info;
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};
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struct agx_uncompiled_shader {
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struct pipe_shader_state base;
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struct nir_shader *nir;
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struct hash_table *variants;
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/* Set on VS, passed to FS for linkage */
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unsigned base_varying;
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};
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struct agx_stage {
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struct agx_uncompiled_shader *shader;
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uint32_t dirty;
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struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
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uint32_t cb_mask;
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/* Need full CSOs for u_blitter */
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struct agx_sampler_state *samplers[PIPE_MAX_SAMPLERS];
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struct agx_sampler_view *textures[PIPE_MAX_SHADER_SAMPLER_VIEWS];
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unsigned sampler_count, texture_count;
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};
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/* Uploaded scissor descriptors */
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struct agx_scissors {
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struct agx_bo *bo;
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unsigned count;
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};
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struct agx_batch {
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unsigned width, height, nr_cbufs;
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struct pipe_surface *cbufs[8];
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struct pipe_surface *zsbuf;
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/* PIPE_CLEAR_* bitmask */
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uint32_t clear, draw;
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float clear_color[4];
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/* Resource list requirements, represented as a bit set indexed by BO
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* handles (GEM handles on Linux, or IOGPU's equivalent on macOS) */
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BITSET_WORD bo_list[256];
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struct agx_pool pool, pipeline_pool;
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struct agx_bo *encoder;
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uint8_t *encoder_current;
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struct agx_scissors scissor;
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};
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struct agx_zsa {
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struct pipe_depth_stencil_alpha_state base;
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struct agx_rasterizer_face_packed front, back;
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};
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struct agx_blend {
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bool logicop_enable, blend_enable;
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union {
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nir_lower_blend_rt rt[8];
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unsigned logicop_func;
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};
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};
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struct asahi_shader_key {
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struct agx_shader_key base;
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struct agx_blend blend;
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unsigned nr_cbufs;
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enum pipe_format rt_formats[PIPE_MAX_COLOR_BUFS];
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};
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enum agx_dirty {
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AGX_DIRTY_VERTEX = BITFIELD_BIT(0),
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AGX_DIRTY_VIEWPORT = BITFIELD_BIT(1),
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AGX_DIRTY_SCISSOR = BITFIELD_BIT(2),
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};
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struct agx_context {
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struct pipe_context base;
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struct agx_compiled_shader *vs, *fs;
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uint32_t dirty;
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struct agx_batch *batch;
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struct pipe_vertex_buffer vertex_buffers[PIPE_MAX_ATTRIBS];
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uint32_t vb_mask;
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struct agx_stage stage[PIPE_SHADER_TYPES];
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struct agx_attribute *attributes;
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struct agx_rasterizer *rast;
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struct agx_zsa zs;
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struct agx_blend *blend;
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struct pipe_blend_color blend_color;
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struct pipe_viewport_state viewport;
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struct pipe_scissor_state scissor;
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struct pipe_stencil_ref stencil_ref;
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struct agx_streamout streamout;
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uint16_t sample_mask;
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struct pipe_framebuffer_state framebuffer;
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struct pipe_query *cond_query;
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bool cond_cond;
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enum pipe_render_cond_flag cond_mode;
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bool is_noop;
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uint8_t render_target[8][AGX_RENDER_TARGET_LENGTH];
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struct blitter_context *blitter;
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};
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static inline struct agx_context *
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agx_context(struct pipe_context *pctx)
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{
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return (struct agx_context *) pctx;
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}
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struct agx_rasterizer {
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struct pipe_rasterizer_state base;
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uint8_t cull[AGX_CULL_LENGTH];
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uint8_t line_width;
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};
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struct agx_query {
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unsigned query;
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};
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struct agx_sampler_state {
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struct pipe_sampler_state base;
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/* Prepared descriptor */
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struct agx_bo *desc;
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};
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struct agx_sampler_view {
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struct pipe_sampler_view base;
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/* Prepared descriptor */
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struct agx_bo *desc;
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};
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struct agx_screen {
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struct pipe_screen pscreen;
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struct agx_device dev;
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struct sw_winsys *winsys;
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};
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static inline struct agx_screen *
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agx_screen(struct pipe_screen *p)
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{
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return (struct agx_screen *)p;
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}
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static inline struct agx_device *
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agx_device(struct pipe_screen *p)
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{
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return &(agx_screen(p)->dev);
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}
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/* TODO: UABI, fake for macOS */
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#ifndef DRM_FORMAT_MOD_LINEAR
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#define DRM_FORMAT_MOD_LINEAR 1
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#endif
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#define DRM_FORMAT_MOD_APPLE_64X64_MORTON_ORDER (2)
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struct agx_resource {
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struct pipe_resource base;
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uint64_t modifier;
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/* Hardware backing */
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struct agx_bo *bo;
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/* Software backing (XXX) */
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struct sw_displaytarget *dt;
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unsigned dt_stride;
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BITSET_DECLARE(data_valid, PIPE_MAX_TEXTURE_LEVELS);
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struct {
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unsigned offset;
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unsigned line_stride;
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} slices[PIPE_MAX_TEXTURE_LEVELS];
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};
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static inline struct agx_resource *
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agx_resource(struct pipe_resource *pctx)
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{
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return (struct agx_resource *) pctx;
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}
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struct agx_transfer {
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struct pipe_transfer base;
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void *map;
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struct {
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struct pipe_resource *rsrc;
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struct pipe_box box;
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} staging;
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};
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static inline struct agx_transfer *
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agx_transfer(struct pipe_transfer *p)
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{
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return (struct agx_transfer *)p;
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}
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uint64_t
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agx_push_location(struct agx_context *ctx, struct agx_push push,
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enum pipe_shader_type stage);
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uint64_t
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agx_build_clear_pipeline(struct agx_context *ctx, uint32_t code, uint64_t clear_buf);
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uint64_t
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agx_build_store_pipeline(struct agx_context *ctx, uint32_t code,
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uint64_t render_target);
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uint64_t
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agx_build_reload_pipeline(struct agx_context *ctx, uint32_t code, struct pipe_surface *surf);
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/* Add a BO to a batch. This needs to be amortized O(1) since it's called in
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* hot paths. To achieve this we model BO lists by bit sets */
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static inline void
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agx_batch_add_bo(struct agx_batch *batch, struct agx_bo *bo)
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{
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if (unlikely(bo->handle > (sizeof(batch->bo_list) * 8)))
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unreachable("todo: growable");
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BITSET_SET(batch->bo_list, bo->handle);
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}
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/* Blit shaders */
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void agx_blit(struct pipe_context *pipe,
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const struct pipe_blit_info *info);
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void agx_internal_shaders(struct agx_device *dev);
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#endif
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