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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/asahi/magic.c
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/*
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* Copyright 2021 Alyssa Rosenzweig
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#
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#include <stdint.h>
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#include "agx_state.h"
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#include "magic.h"
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/* The structures managed in this file appear to be software defined (either in
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* the macOS kernel driver or in the AGX firmware) */
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/* Odd pattern */
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static uint64_t
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demo_unk6(struct agx_pool *pool)
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{
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struct agx_ptr ptr = agx_pool_alloc_aligned(pool, 0x4000 * sizeof(uint64_t), 64);
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uint64_t *buf = ptr.cpu;
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memset(buf, 0, sizeof(*buf));
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for (unsigned i = 1; i < 0x3ff; ++i)
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buf[i] = (i + 1);
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return ptr.gpu;
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}
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static uint64_t
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demo_zero(struct agx_pool *pool, unsigned count)
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{
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struct agx_ptr ptr = agx_pool_alloc_aligned(pool, count, 64);
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memset(ptr.cpu, 0, count);
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return ptr.gpu;
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}
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unsigned
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demo_cmdbuf(uint64_t *buf, size_t size,
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struct agx_pool *pool,
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uint64_t encoder_ptr,
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uint64_t encoder_id,
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uint64_t scissor_ptr,
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unsigned width, unsigned height,
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uint32_t pipeline_null,
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uint32_t pipeline_clear,
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uint32_t pipeline_store,
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uint64_t rt0,
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bool clear_pipeline_textures)
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{
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uint32_t *map = (uint32_t *) buf;
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memset(map, 0, 474 * 4);
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map[54] = 0x6b0003;
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map[55] = 0x3a0012;
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map[56] = 1;
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map[106] = 1;
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map[108] = 0x1c;
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map[112] = 0xffffffff;
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map[113] = 0xffffffff;
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map[114] = 0xffffffff;
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uint64_t unk_buffer = demo_zero(pool, 0x1000);
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uint64_t unk_buffer_2 = demo_zero(pool, 0x8000);
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// This is a pipeline bind
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map[156] = 0xffff8002 | (clear_pipeline_textures ? 0x210 : 0);
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map[158] = pipeline_clear | 0x4;
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map[163] = 0x12;
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map[164] = pipeline_store | 0x4;
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map[166] = scissor_ptr & 0xFFFFFFFF;
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map[167] = scissor_ptr >> 32;
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map[168] = unk_buffer & 0xFFFFFFFF;
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map[169] = unk_buffer >> 32;
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map[220] = 4;
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map[222] = 0xc000;
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map[224] = width;
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map[225] = height;
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map[226] = unk_buffer_2 & 0xFFFFFFFF;
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map[227] = unk_buffer_2 >> 32;
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float depth_clear = 1.0;
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uint8_t stencil_clear = 0;
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map[278] = fui(depth_clear);
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map[279] = (0x3 << 8) | stencil_clear;
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map[282] = 0x1000000;
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map[284] = 0xffffffff;
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map[285] = 0xffffffff;
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map[286] = 0xffffffff;
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map[298] = 0xffff8212;
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map[300] = pipeline_null | 0x4;
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map[305] = 0x12;
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map[306] = pipeline_store | 0x4;
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map[352] = 1;
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map[360] = 0x1c;
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map[362] = encoder_id;
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map[365] = 0xffffffff;
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map[366] = 1;
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uint64_t unk6 = demo_unk6(pool);
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map[370] = unk6 & 0xFFFFFFFF;
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map[371] = unk6 >> 32;
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map[374] = width;
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map[375] = height;
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map[376] = 1;
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map[377] = 8;
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map[378] = 8;
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map[393] = 8;
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map[394] = 32;
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map[395] = 32;
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map[396] = 1;
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unsigned offset_unk = (458 * 4);
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unsigned offset_attachments = (470 * 4);
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unsigned nr_attachments = 1;
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map[473] = nr_attachments;
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/* A single attachment follows, depth/stencil have their own attachments */
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agx_pack((map + (offset_attachments / 4) + 4), IOGPU_ATTACHMENT, cfg) {
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cfg.address = rt0;
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cfg.type = AGX_IOGPU_ATTACHMENT_TYPE_COLOUR;
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cfg.unk_1 = 0x80000000;
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cfg.unk_2 = 0x5;
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cfg.bytes_per_pixel = 4;
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cfg.percent = 100;
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}
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unsigned total_size = offset_attachments + (AGX_IOGPU_ATTACHMENT_LENGTH * nr_attachments) + 16;
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agx_pack(map, IOGPU_HEADER, cfg) {
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cfg.total_size = total_size;
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cfg.attachment_offset_1 = offset_attachments;
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cfg.attachment_offset_2 = offset_attachments;
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cfg.attachment_length = nr_attachments * AGX_IOGPU_ATTACHMENT_LENGTH;
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cfg.unknown_offset = offset_unk;
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cfg.encoder = encoder_ptr;
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}
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return total_size;
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}
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static struct agx_map_header
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demo_map_header(uint64_t cmdbuf_id, uint64_t encoder_id, unsigned cmdbuf_size, unsigned count)
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{
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return (struct agx_map_header) {
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.cmdbuf_id = cmdbuf_id,
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.unk2 = 0x1,
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.unk3 = 0x528, // 1320
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.encoder_id = encoder_id,
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.unk6 = 0x0,
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.cmdbuf_size = cmdbuf_size,
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/* +1 for the sentinel ending */
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.nr_entries = count + 1,
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.nr_handles = count + 1,
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.indices = {0x0b},
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};
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}
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void
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demo_mem_map(void *map, size_t size, unsigned *handles, unsigned count,
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uint64_t cmdbuf_id, uint64_t encoder_id, unsigned cmdbuf_size)
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{
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struct agx_map_header *header = map;
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struct agx_map_entry *entries = (struct agx_map_entry *) (((uint8_t *) map) + 0x40);
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struct agx_map_entry *end = (struct agx_map_entry *) (((uint8_t *) map) + size);
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/* Header precedes the entry */
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*header = demo_map_header(cmdbuf_id, encoder_id, cmdbuf_size, count);
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/* Add an entry for each BO mapped */
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for (unsigned i = 0; i < count; ++i) {
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assert((entries + i) < end);
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entries[i] = (struct agx_map_entry) {
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.unkAAA = 0x20,
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.unkBBB = 0x1,
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.unka = 0x1ffff,
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.indices = {handles[i]}
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};
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}
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/* Final entry is a sentinel */
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assert((entries + count) < end);
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entries[count] = (struct agx_map_entry) {
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.unkAAA = 0x40,
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.unkBBB = 0x1,
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.unka = 0x1ffff,
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};
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}
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