Path: blob/21.2-virgl/src/gallium/drivers/crocus/crocus_formats.c
4570 views
/*1* Copyright © 2017 Intel Corporation2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included11* in all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS14* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER17* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING18* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER19* DEALINGS IN THE SOFTWARE.20*/2122/**23* @file crocus_formats.c24*25* Converts Gallium formats (PIPE_FORMAT_*) to hardware ones (ISL_FORMAT_*).26* Provides information about which formats support what features.27*/2829#include "util/bitscan.h"30#include "util/macros.h"31#include "util/format/u_format.h"3233#include "crocus_resource.h"34#include "crocus_screen.h"3536static enum isl_format37crocus_isl_format_for_pipe_format(enum pipe_format pf)38{39static const enum isl_format table[PIPE_FORMAT_COUNT] = {40[0 ... PIPE_FORMAT_COUNT-1] = ISL_FORMAT_UNSUPPORTED,4142[PIPE_FORMAT_B8G8R8A8_UNORM] = ISL_FORMAT_B8G8R8A8_UNORM,43[PIPE_FORMAT_B8G8R8X8_UNORM] = ISL_FORMAT_B8G8R8X8_UNORM,44[PIPE_FORMAT_B5G5R5A1_UNORM] = ISL_FORMAT_B5G5R5A1_UNORM,45[PIPE_FORMAT_B4G4R4A4_UNORM] = ISL_FORMAT_B4G4R4A4_UNORM,46[PIPE_FORMAT_B5G6R5_UNORM] = ISL_FORMAT_B5G6R5_UNORM,47[PIPE_FORMAT_R10G10B10A2_UNORM] = ISL_FORMAT_R10G10B10A2_UNORM,4849[PIPE_FORMAT_Z16_UNORM] = ISL_FORMAT_R16_UNORM,50[PIPE_FORMAT_Z32_UNORM] = ISL_FORMAT_R32_UNORM,51[PIPE_FORMAT_Z32_FLOAT] = ISL_FORMAT_R32_FLOAT,5253/* We translate the combined depth/stencil formats to depth only here */54[PIPE_FORMAT_Z24_UNORM_S8_UINT] = ISL_FORMAT_R24_UNORM_X8_TYPELESS,55[PIPE_FORMAT_Z24X8_UNORM] = ISL_FORMAT_R24_UNORM_X8_TYPELESS,56[PIPE_FORMAT_Z32_FLOAT_S8X24_UINT] = ISL_FORMAT_R32_FLOAT,5758[PIPE_FORMAT_S8_UINT] = ISL_FORMAT_R8_UINT,59[PIPE_FORMAT_X24S8_UINT] = ISL_FORMAT_R8_UINT,60[PIPE_FORMAT_X32_S8X24_UINT] = ISL_FORMAT_R8_UINT,6162[PIPE_FORMAT_R64_FLOAT] = ISL_FORMAT_R64_FLOAT,63[PIPE_FORMAT_R64G64_FLOAT] = ISL_FORMAT_R64G64_FLOAT,64[PIPE_FORMAT_R64G64B64_FLOAT] = ISL_FORMAT_R64G64B64_FLOAT,65[PIPE_FORMAT_R64G64B64A64_FLOAT] = ISL_FORMAT_R64G64B64A64_FLOAT,66[PIPE_FORMAT_R32_FLOAT] = ISL_FORMAT_R32_FLOAT,67[PIPE_FORMAT_R32G32_FLOAT] = ISL_FORMAT_R32G32_FLOAT,68[PIPE_FORMAT_R32G32B32_FLOAT] = ISL_FORMAT_R32G32B32_FLOAT,69[PIPE_FORMAT_R32G32B32A32_FLOAT] = ISL_FORMAT_R32G32B32A32_FLOAT,70[PIPE_FORMAT_R32_UNORM] = ISL_FORMAT_R32_UNORM,71[PIPE_FORMAT_R32G32_UNORM] = ISL_FORMAT_R32G32_UNORM,72[PIPE_FORMAT_R32G32B32_UNORM] = ISL_FORMAT_R32G32B32_UNORM,73[PIPE_FORMAT_R32G32B32A32_UNORM] = ISL_FORMAT_R32G32B32A32_UNORM,74[PIPE_FORMAT_R32_USCALED] = ISL_FORMAT_R32_USCALED,75[PIPE_FORMAT_R32G32_USCALED] = ISL_FORMAT_R32G32_USCALED,76[PIPE_FORMAT_R32G32B32_USCALED] = ISL_FORMAT_R32G32B32_USCALED,77[PIPE_FORMAT_R32G32B32A32_USCALED] = ISL_FORMAT_R32G32B32A32_USCALED,78[PIPE_FORMAT_R32_SNORM] = ISL_FORMAT_R32_SNORM,79[PIPE_FORMAT_R32G32_SNORM] = ISL_FORMAT_R32G32_SNORM,80[PIPE_FORMAT_R32G32B32_SNORM] = ISL_FORMAT_R32G32B32_SNORM,81[PIPE_FORMAT_R32G32B32A32_SNORM] = ISL_FORMAT_R32G32B32A32_SNORM,82[PIPE_FORMAT_R32_SSCALED] = ISL_FORMAT_R32_SSCALED,83[PIPE_FORMAT_R32G32_SSCALED] = ISL_FORMAT_R32G32_SSCALED,84[PIPE_FORMAT_R32G32B32_SSCALED] = ISL_FORMAT_R32G32B32_SSCALED,85[PIPE_FORMAT_R32G32B32A32_SSCALED] = ISL_FORMAT_R32G32B32A32_SSCALED,86[PIPE_FORMAT_R16_UNORM] = ISL_FORMAT_R16_UNORM,87[PIPE_FORMAT_R16G16_UNORM] = ISL_FORMAT_R16G16_UNORM,88[PIPE_FORMAT_R16G16B16_UNORM] = ISL_FORMAT_R16G16B16_UNORM,89[PIPE_FORMAT_R16G16B16A16_UNORM] = ISL_FORMAT_R16G16B16A16_UNORM,90[PIPE_FORMAT_R16_USCALED] = ISL_FORMAT_R16_USCALED,91[PIPE_FORMAT_R16G16_USCALED] = ISL_FORMAT_R16G16_USCALED,92[PIPE_FORMAT_R16G16B16_USCALED] = ISL_FORMAT_R16G16B16_USCALED,93[PIPE_FORMAT_R16G16B16A16_USCALED] = ISL_FORMAT_R16G16B16A16_USCALED,94[PIPE_FORMAT_R16_SNORM] = ISL_FORMAT_R16_SNORM,95[PIPE_FORMAT_R16G16_SNORM] = ISL_FORMAT_R16G16_SNORM,96[PIPE_FORMAT_R16G16B16_SNORM] = ISL_FORMAT_R16G16B16_SNORM,97[PIPE_FORMAT_R16G16B16A16_SNORM] = ISL_FORMAT_R16G16B16A16_SNORM,98[PIPE_FORMAT_R16_SSCALED] = ISL_FORMAT_R16_SSCALED,99[PIPE_FORMAT_R16G16_SSCALED] = ISL_FORMAT_R16G16_SSCALED,100[PIPE_FORMAT_R16G16B16_SSCALED] = ISL_FORMAT_R16G16B16_SSCALED,101[PIPE_FORMAT_R16G16B16A16_SSCALED] = ISL_FORMAT_R16G16B16A16_SSCALED,102[PIPE_FORMAT_R8_UNORM] = ISL_FORMAT_R8_UNORM,103[PIPE_FORMAT_R8G8_UNORM] = ISL_FORMAT_R8G8_UNORM,104[PIPE_FORMAT_R8G8B8_UNORM] = ISL_FORMAT_R8G8B8_UNORM,105[PIPE_FORMAT_R8G8B8A8_UNORM] = ISL_FORMAT_R8G8B8A8_UNORM,106[PIPE_FORMAT_R8_USCALED] = ISL_FORMAT_R8_USCALED,107[PIPE_FORMAT_R8G8_USCALED] = ISL_FORMAT_R8G8_USCALED,108[PIPE_FORMAT_R8G8B8_USCALED] = ISL_FORMAT_R8G8B8_USCALED,109[PIPE_FORMAT_R8G8B8A8_USCALED] = ISL_FORMAT_R8G8B8A8_USCALED,110[PIPE_FORMAT_R8_SNORM] = ISL_FORMAT_R8_SNORM,111[PIPE_FORMAT_R8G8_SNORM] = ISL_FORMAT_R8G8_SNORM,112[PIPE_FORMAT_R8G8B8_SNORM] = ISL_FORMAT_R8G8B8_SNORM,113[PIPE_FORMAT_R8G8B8A8_SNORM] = ISL_FORMAT_R8G8B8A8_SNORM,114[PIPE_FORMAT_R8_SSCALED] = ISL_FORMAT_R8_SSCALED,115[PIPE_FORMAT_R8G8_SSCALED] = ISL_FORMAT_R8G8_SSCALED,116[PIPE_FORMAT_R8G8B8_SSCALED] = ISL_FORMAT_R8G8B8_SSCALED,117[PIPE_FORMAT_R8G8B8A8_SSCALED] = ISL_FORMAT_R8G8B8A8_SSCALED,118[PIPE_FORMAT_R32_FIXED] = ISL_FORMAT_R32_SFIXED,119[PIPE_FORMAT_R32G32_FIXED] = ISL_FORMAT_R32G32_SFIXED,120[PIPE_FORMAT_R32G32B32_FIXED] = ISL_FORMAT_R32G32B32_SFIXED,121[PIPE_FORMAT_R32G32B32A32_FIXED] = ISL_FORMAT_R32G32B32A32_SFIXED,122[PIPE_FORMAT_R16_FLOAT] = ISL_FORMAT_R16_FLOAT,123[PIPE_FORMAT_R16G16_FLOAT] = ISL_FORMAT_R16G16_FLOAT,124[PIPE_FORMAT_R16G16B16_FLOAT] = ISL_FORMAT_R16G16B16_FLOAT,125[PIPE_FORMAT_R16G16B16A16_FLOAT] = ISL_FORMAT_R16G16B16A16_FLOAT,126127[PIPE_FORMAT_R8G8B8_SRGB] = ISL_FORMAT_R8G8B8_UNORM_SRGB,128[PIPE_FORMAT_B8G8R8A8_SRGB] = ISL_FORMAT_B8G8R8A8_UNORM_SRGB,129[PIPE_FORMAT_B8G8R8X8_SRGB] = ISL_FORMAT_B8G8R8X8_UNORM_SRGB,130[PIPE_FORMAT_R8G8B8A8_SRGB] = ISL_FORMAT_R8G8B8A8_UNORM_SRGB,131132[PIPE_FORMAT_DXT1_RGB] = ISL_FORMAT_BC1_UNORM,133[PIPE_FORMAT_DXT1_RGBA] = ISL_FORMAT_BC1_UNORM,134[PIPE_FORMAT_DXT3_RGBA] = ISL_FORMAT_BC2_UNORM,135[PIPE_FORMAT_DXT5_RGBA] = ISL_FORMAT_BC3_UNORM,136137[PIPE_FORMAT_DXT1_SRGB] = ISL_FORMAT_BC1_UNORM_SRGB,138[PIPE_FORMAT_DXT1_SRGBA] = ISL_FORMAT_BC1_UNORM_SRGB,139[PIPE_FORMAT_DXT3_SRGBA] = ISL_FORMAT_BC2_UNORM_SRGB,140[PIPE_FORMAT_DXT5_SRGBA] = ISL_FORMAT_BC3_UNORM_SRGB,141142[PIPE_FORMAT_RGTC1_UNORM] = ISL_FORMAT_BC4_UNORM,143[PIPE_FORMAT_RGTC1_SNORM] = ISL_FORMAT_BC4_SNORM,144[PIPE_FORMAT_RGTC2_UNORM] = ISL_FORMAT_BC5_UNORM,145[PIPE_FORMAT_RGTC2_SNORM] = ISL_FORMAT_BC5_SNORM,146147[PIPE_FORMAT_R10G10B10A2_USCALED] = ISL_FORMAT_R10G10B10A2_USCALED,148[PIPE_FORMAT_R11G11B10_FLOAT] = ISL_FORMAT_R11G11B10_FLOAT,149[PIPE_FORMAT_R9G9B9E5_FLOAT] = ISL_FORMAT_R9G9B9E5_SHAREDEXP,150[PIPE_FORMAT_R1_UNORM] = ISL_FORMAT_R1_UNORM,151[PIPE_FORMAT_R10G10B10X2_USCALED] = ISL_FORMAT_R10G10B10X2_USCALED,152[PIPE_FORMAT_B10G10R10A2_UNORM] = ISL_FORMAT_B10G10R10A2_UNORM,153[PIPE_FORMAT_R8G8B8X8_UNORM] = ISL_FORMAT_R8G8B8X8_UNORM,154155[PIPE_FORMAT_I8_UNORM] = ISL_FORMAT_R8_UNORM,156[PIPE_FORMAT_I16_UNORM] = ISL_FORMAT_R16_UNORM,157[PIPE_FORMAT_I8_SNORM] = ISL_FORMAT_R8_SNORM,158[PIPE_FORMAT_I16_SNORM] = ISL_FORMAT_R16_SNORM,159[PIPE_FORMAT_I16_FLOAT] = ISL_FORMAT_R16_FLOAT,160[PIPE_FORMAT_I32_FLOAT] = ISL_FORMAT_R32_FLOAT,161162[PIPE_FORMAT_L8_UINT] = ISL_FORMAT_L8_UINT,163[PIPE_FORMAT_L8_UNORM] = ISL_FORMAT_L8_UNORM,164[PIPE_FORMAT_L8_SNORM] = ISL_FORMAT_R8_SNORM,165[PIPE_FORMAT_L8_SINT] = ISL_FORMAT_L8_SINT,166[PIPE_FORMAT_L16_UNORM] = ISL_FORMAT_L16_UNORM,167[PIPE_FORMAT_L16_SNORM] = ISL_FORMAT_R16_SNORM,168[PIPE_FORMAT_L16_FLOAT] = ISL_FORMAT_L16_FLOAT,169[PIPE_FORMAT_L32_FLOAT] = ISL_FORMAT_L32_FLOAT,170171[PIPE_FORMAT_A8_UNORM] = ISL_FORMAT_A8_UNORM,172[PIPE_FORMAT_A16_UNORM] = ISL_FORMAT_A16_UNORM,173[PIPE_FORMAT_A16_FLOAT] = ISL_FORMAT_A16_FLOAT,174[PIPE_FORMAT_A32_FLOAT] = ISL_FORMAT_A32_FLOAT,175176[PIPE_FORMAT_L8A8_UNORM] = ISL_FORMAT_L8A8_UNORM,177[PIPE_FORMAT_L16A16_UNORM] = ISL_FORMAT_L16A16_UNORM,178[PIPE_FORMAT_L16A16_FLOAT] = ISL_FORMAT_L16A16_FLOAT,179[PIPE_FORMAT_L32A32_FLOAT] = ISL_FORMAT_L32A32_FLOAT,180181/* Sadly, we have to use luminance[-alpha] formats for sRGB decoding. */182[PIPE_FORMAT_R8_SRGB] = ISL_FORMAT_L8_UNORM_SRGB,183[PIPE_FORMAT_L8_SRGB] = ISL_FORMAT_L8_UNORM_SRGB,184[PIPE_FORMAT_L8A8_SRGB] = ISL_FORMAT_L8A8_UNORM_SRGB,185186[PIPE_FORMAT_R10G10B10A2_SSCALED] = ISL_FORMAT_R10G10B10A2_SSCALED,187[PIPE_FORMAT_R10G10B10A2_SNORM] = ISL_FORMAT_R10G10B10A2_SNORM,188189[PIPE_FORMAT_B10G10R10A2_USCALED] = ISL_FORMAT_B10G10R10A2_USCALED,190[PIPE_FORMAT_B10G10R10A2_SSCALED] = ISL_FORMAT_B10G10R10A2_SSCALED,191[PIPE_FORMAT_B10G10R10A2_SNORM] = ISL_FORMAT_B10G10R10A2_SNORM,192193[PIPE_FORMAT_R8_UINT] = ISL_FORMAT_R8_UINT,194[PIPE_FORMAT_R8G8_UINT] = ISL_FORMAT_R8G8_UINT,195[PIPE_FORMAT_R8G8B8_UINT] = ISL_FORMAT_R8G8B8_UINT,196[PIPE_FORMAT_R8G8B8A8_UINT] = ISL_FORMAT_R8G8B8A8_UINT,197198[PIPE_FORMAT_R8_SINT] = ISL_FORMAT_R8_SINT,199[PIPE_FORMAT_R8G8_SINT] = ISL_FORMAT_R8G8_SINT,200[PIPE_FORMAT_R8G8B8_SINT] = ISL_FORMAT_R8G8B8_SINT,201[PIPE_FORMAT_R8G8B8A8_SINT] = ISL_FORMAT_R8G8B8A8_SINT,202203[PIPE_FORMAT_R16_UINT] = ISL_FORMAT_R16_UINT,204[PIPE_FORMAT_R16G16_UINT] = ISL_FORMAT_R16G16_UINT,205[PIPE_FORMAT_R16G16B16_UINT] = ISL_FORMAT_R16G16B16_UINT,206[PIPE_FORMAT_R16G16B16A16_UINT] = ISL_FORMAT_R16G16B16A16_UINT,207208[PIPE_FORMAT_R16_SINT] = ISL_FORMAT_R16_SINT,209[PIPE_FORMAT_R16G16_SINT] = ISL_FORMAT_R16G16_SINT,210[PIPE_FORMAT_R16G16B16_SINT] = ISL_FORMAT_R16G16B16_SINT,211[PIPE_FORMAT_R16G16B16A16_SINT] = ISL_FORMAT_R16G16B16A16_SINT,212213[PIPE_FORMAT_R32_UINT] = ISL_FORMAT_R32_UINT,214[PIPE_FORMAT_R32G32_UINT] = ISL_FORMAT_R32G32_UINT,215[PIPE_FORMAT_R32G32B32_UINT] = ISL_FORMAT_R32G32B32_UINT,216[PIPE_FORMAT_R32G32B32A32_UINT] = ISL_FORMAT_R32G32B32A32_UINT,217218[PIPE_FORMAT_R32_SINT] = ISL_FORMAT_R32_SINT,219[PIPE_FORMAT_R32G32_SINT] = ISL_FORMAT_R32G32_SINT,220[PIPE_FORMAT_R32G32B32_SINT] = ISL_FORMAT_R32G32B32_SINT,221[PIPE_FORMAT_R32G32B32A32_SINT] = ISL_FORMAT_R32G32B32A32_SINT,222223[PIPE_FORMAT_B10G10R10A2_UINT] = ISL_FORMAT_B10G10R10A2_UINT,224225[PIPE_FORMAT_ETC1_RGB8] = ISL_FORMAT_ETC1_RGB8,226227[PIPE_FORMAT_R8G8B8X8_SRGB] = ISL_FORMAT_R8G8B8X8_UNORM_SRGB,228[PIPE_FORMAT_B10G10R10X2_UNORM] = ISL_FORMAT_B10G10R10X2_UNORM,229[PIPE_FORMAT_R16G16B16X16_UNORM] = ISL_FORMAT_R16G16B16X16_UNORM,230[PIPE_FORMAT_R16G16B16X16_FLOAT] = ISL_FORMAT_R16G16B16X16_FLOAT,231[PIPE_FORMAT_R32G32B32X32_FLOAT] = ISL_FORMAT_R32G32B32X32_FLOAT,232233[PIPE_FORMAT_R10G10B10A2_UINT] = ISL_FORMAT_R10G10B10A2_UINT,234235[PIPE_FORMAT_B5G6R5_SRGB] = ISL_FORMAT_B5G6R5_UNORM_SRGB,236237[PIPE_FORMAT_BPTC_RGBA_UNORM] = ISL_FORMAT_BC7_UNORM,238[PIPE_FORMAT_BPTC_SRGBA] = ISL_FORMAT_BC7_UNORM_SRGB,239[PIPE_FORMAT_BPTC_RGB_FLOAT] = ISL_FORMAT_BC6H_SF16,240[PIPE_FORMAT_BPTC_RGB_UFLOAT] = ISL_FORMAT_BC6H_UF16,241242[PIPE_FORMAT_ETC2_RGB8] = ISL_FORMAT_ETC2_RGB8,243[PIPE_FORMAT_ETC2_SRGB8] = ISL_FORMAT_ETC2_SRGB8,244[PIPE_FORMAT_ETC2_RGB8A1] = ISL_FORMAT_ETC2_RGB8_PTA,245[PIPE_FORMAT_ETC2_SRGB8A1] = ISL_FORMAT_ETC2_SRGB8_PTA,246[PIPE_FORMAT_ETC2_RGBA8] = ISL_FORMAT_ETC2_EAC_RGBA8,247[PIPE_FORMAT_ETC2_SRGBA8] = ISL_FORMAT_ETC2_EAC_SRGB8_A8,248[PIPE_FORMAT_ETC2_R11_UNORM] = ISL_FORMAT_EAC_R11,249[PIPE_FORMAT_ETC2_R11_SNORM] = ISL_FORMAT_EAC_SIGNED_R11,250[PIPE_FORMAT_ETC2_RG11_UNORM] = ISL_FORMAT_EAC_RG11,251[PIPE_FORMAT_ETC2_RG11_SNORM] = ISL_FORMAT_EAC_SIGNED_RG11,252253[PIPE_FORMAT_FXT1_RGB] = ISL_FORMAT_FXT1,254[PIPE_FORMAT_FXT1_RGBA] = ISL_FORMAT_FXT1,255256[PIPE_FORMAT_ASTC_4x4] = ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16,257[PIPE_FORMAT_ASTC_5x4] = ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16,258[PIPE_FORMAT_ASTC_5x5] = ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16,259[PIPE_FORMAT_ASTC_6x5] = ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16,260[PIPE_FORMAT_ASTC_6x6] = ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16,261[PIPE_FORMAT_ASTC_8x5] = ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16,262[PIPE_FORMAT_ASTC_8x6] = ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16,263[PIPE_FORMAT_ASTC_8x8] = ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16,264[PIPE_FORMAT_ASTC_10x5] = ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16,265[PIPE_FORMAT_ASTC_10x6] = ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16,266[PIPE_FORMAT_ASTC_10x8] = ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16,267[PIPE_FORMAT_ASTC_10x10] = ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16,268[PIPE_FORMAT_ASTC_12x10] = ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16,269[PIPE_FORMAT_ASTC_12x12] = ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16,270271[PIPE_FORMAT_ASTC_4x4_SRGB] = ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB,272[PIPE_FORMAT_ASTC_5x4_SRGB] = ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB,273[PIPE_FORMAT_ASTC_5x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB,274[PIPE_FORMAT_ASTC_6x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB,275[PIPE_FORMAT_ASTC_6x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB,276[PIPE_FORMAT_ASTC_8x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB,277[PIPE_FORMAT_ASTC_8x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB,278[PIPE_FORMAT_ASTC_8x8_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB,279[PIPE_FORMAT_ASTC_10x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB,280[PIPE_FORMAT_ASTC_10x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB,281[PIPE_FORMAT_ASTC_10x8_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB,282[PIPE_FORMAT_ASTC_10x10_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB,283[PIPE_FORMAT_ASTC_12x10_SRGB] = ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB,284[PIPE_FORMAT_ASTC_12x12_SRGB] = ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB,285286[PIPE_FORMAT_A1B5G5R5_UNORM] = ISL_FORMAT_A1B5G5R5_UNORM,287288/* We support these so that we know the API expects no alpha channel.289* Otherwise, the state tracker would just give us a format with alpha290* and we wouldn't know to override the swizzle to 1.291*/292[PIPE_FORMAT_R16G16B16X16_UINT] = ISL_FORMAT_R16G16B16A16_UINT,293[PIPE_FORMAT_R16G16B16X16_SINT] = ISL_FORMAT_R16G16B16A16_SINT,294[PIPE_FORMAT_R32G32B32X32_UINT] = ISL_FORMAT_R32G32B32A32_UINT,295[PIPE_FORMAT_R32G32B32X32_SINT] = ISL_FORMAT_R32G32B32A32_SINT,296[PIPE_FORMAT_R10G10B10X2_SNORM] = ISL_FORMAT_R10G10B10A2_SNORM,297};298assert(pf < PIPE_FORMAT_COUNT);299return table[pf];300}301302static enum isl_format303get_render_format(enum pipe_format pformat, enum isl_format def_format)304{305switch (pformat) {306case PIPE_FORMAT_A16_UNORM: return ISL_FORMAT_R16_UNORM;307case PIPE_FORMAT_A16_FLOAT: return ISL_FORMAT_R16_FLOAT;308case PIPE_FORMAT_A32_FLOAT: return ISL_FORMAT_R32_FLOAT;309310case PIPE_FORMAT_I8_UNORM: return ISL_FORMAT_R8_UNORM;311case PIPE_FORMAT_I16_UNORM: return ISL_FORMAT_R16_UNORM;312case PIPE_FORMAT_I16_FLOAT: return ISL_FORMAT_R16_FLOAT;313case PIPE_FORMAT_I32_FLOAT: return ISL_FORMAT_R32_FLOAT;314315case PIPE_FORMAT_L8_UNORM: return ISL_FORMAT_R8_UNORM;316case PIPE_FORMAT_L8_UINT: return ISL_FORMAT_R8_UINT;317case PIPE_FORMAT_L8_SINT: return ISL_FORMAT_R8_SINT;318case PIPE_FORMAT_L16_UNORM: return ISL_FORMAT_R16_UNORM;319case PIPE_FORMAT_L16_FLOAT: return ISL_FORMAT_R16_FLOAT;320case PIPE_FORMAT_L32_FLOAT: return ISL_FORMAT_R32_FLOAT;321322case PIPE_FORMAT_L8A8_UNORM: return ISL_FORMAT_R8G8_UNORM;323case PIPE_FORMAT_L16A16_UNORM: return ISL_FORMAT_R16G16_UNORM;324case PIPE_FORMAT_L16A16_FLOAT: return ISL_FORMAT_R16G16_FLOAT;325case PIPE_FORMAT_L32A32_FLOAT: return ISL_FORMAT_R32G32_FLOAT;326327default:328return def_format;329}330}331332struct crocus_format_info333crocus_format_for_usage(const struct intel_device_info *devinfo,334enum pipe_format pformat,335isl_surf_usage_flags_t usage)336{337struct crocus_format_info info = { crocus_isl_format_for_pipe_format(pformat),338{ PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y, PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W } };339340if (info.fmt == ISL_FORMAT_UNSUPPORTED)341return info;342343if (pformat == PIPE_FORMAT_A8_UNORM) {344info.fmt = ISL_FORMAT_A8_UNORM;345}346347if (usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)348info.fmt = get_render_format(pformat, info.fmt);349if (devinfo->ver < 6) {350if (pformat == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)351info.fmt = ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS;352if (pformat == PIPE_FORMAT_X32_S8X24_UINT)353info.fmt = ISL_FORMAT_X32_TYPELESS_G8X24_UINT;354if (pformat == PIPE_FORMAT_X24S8_UINT)355info.fmt = ISL_FORMAT_X24_TYPELESS_G8_UINT;356}357358const struct isl_format_layout *fmtl = isl_format_get_layout(info.fmt);359360if (util_format_is_snorm(pformat)) {361if (util_format_is_intensity(pformat)) {362info.swizzles[0] = PIPE_SWIZZLE_X;363info.swizzles[1] = PIPE_SWIZZLE_X;364info.swizzles[2] = PIPE_SWIZZLE_X;365info.swizzles[3] = PIPE_SWIZZLE_X;366} else if (util_format_is_luminance(pformat)) {367info.swizzles[0] = PIPE_SWIZZLE_X;368info.swizzles[1] = PIPE_SWIZZLE_X;369info.swizzles[2] = PIPE_SWIZZLE_X;370info.swizzles[3] = PIPE_SWIZZLE_1;371} else if (util_format_is_luminance_alpha(pformat)) {372info.swizzles[0] = PIPE_SWIZZLE_X;373info.swizzles[1] = PIPE_SWIZZLE_X;374info.swizzles[2] = PIPE_SWIZZLE_X;375info.swizzles[3] = PIPE_SWIZZLE_Y;376} else if (util_format_is_alpha(pformat)) {377info.swizzles[0] = PIPE_SWIZZLE_0;378info.swizzles[1] = PIPE_SWIZZLE_0;379info.swizzles[2] = PIPE_SWIZZLE_0;380info.swizzles[3] = PIPE_SWIZZLE_X;381}382}383384/* When faking RGBX pipe formats with RGBA ISL formats, override alpha. */385if (!util_format_has_alpha(pformat) && fmtl->channels.a.type != ISL_VOID) {386info.swizzles[0] = PIPE_SWIZZLE_X;387info.swizzles[1] = PIPE_SWIZZLE_Y;388info.swizzles[2] = PIPE_SWIZZLE_Z;389info.swizzles[3] = PIPE_SWIZZLE_1;390}391392/* We choose RGBA over RGBX for rendering the hardware doesn't support393* rendering to RGBX. However, when this internal override is used on Gen9+,394* fast clears don't work correctly.395*396* i965 fixes this by pretending to not support RGBX formats, and the higher397* layers of Mesa pick the RGBA format instead. Gallium doesn't work that398* way, and might choose a different format, like BGRX instead of RGBX,399* which will also cause problems when sampling from a surface fast cleared400* as RGBX. So we always choose RGBA instead of RGBX explicitly401* here.402*/403if (isl_format_is_rgbx(info.fmt) &&404!isl_format_supports_rendering(devinfo, info.fmt) &&405(usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)) {406info.fmt = isl_format_rgbx_to_rgba(info.fmt);407info.swizzles[0] = PIPE_SWIZZLE_X;408info.swizzles[1] = PIPE_SWIZZLE_Y;409info.swizzles[2] = PIPE_SWIZZLE_Z;410info.swizzles[3] = PIPE_SWIZZLE_1;411}412413return info;414}415416/**417* The pscreen->is_format_supported() driver hook.418*419* Returns true if the given format is supported for the given usage420* (PIPE_BIND_*) and sample count.421*/422bool423crocus_is_format_supported(struct pipe_screen *pscreen,424enum pipe_format pformat,425enum pipe_texture_target target,426unsigned sample_count, unsigned storage_sample_count,427unsigned usage)428{429struct crocus_screen *screen = (struct crocus_screen *)pscreen;430const struct intel_device_info *devinfo = &screen->devinfo;431432if (!util_is_power_of_two_or_zero(sample_count))433return false;434if (devinfo->ver >= 7) {435if (sample_count > 8 || sample_count == 2)436return false;437} else if (devinfo->ver == 6) {438if (sample_count > 4 || sample_count == 2)439return false;440} else if (sample_count > 1) {441return false;442}443444if (pformat == PIPE_FORMAT_NONE)445return true;446447enum isl_format format = crocus_isl_format_for_pipe_format(pformat);448449if (format == ISL_FORMAT_UNSUPPORTED)450return false;451452/* no stencil texturing prior to haswell */453if (devinfo->verx10 < 75) {454if (pformat == PIPE_FORMAT_S8_UINT ||455pformat == PIPE_FORMAT_X24S8_UINT ||456pformat == PIPE_FORMAT_S8X24_UINT ||457pformat == PIPE_FORMAT_X32_S8X24_UINT)458return FALSE;459}460461const struct isl_format_layout *fmtl = isl_format_get_layout(format);462const bool is_integer = isl_format_has_int_channel(format);463bool supported = true;464465if (sample_count > 1)466supported &= isl_format_supports_multisampling(devinfo, format);467468if (usage & PIPE_BIND_DEPTH_STENCIL) {469bool depth_fmts = format == ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS ||470format == ISL_FORMAT_R32_FLOAT ||471format == ISL_FORMAT_R24_UNORM_X8_TYPELESS ||472format == ISL_FORMAT_R8_UINT;473474/* Z16 is disabled here as on pre-GEN8 it's slower. */475if (devinfo->ver == 8)476depth_fmts |= format == ISL_FORMAT_R16_UNORM;477supported &= depth_fmts;478}479480if (usage & PIPE_BIND_RENDER_TARGET) {481/* Alpha and luminance-alpha formats other than A8_UNORM are not482* renderable.483*484* For BLORP, we can apply the swizzle in the shader. But for485* general rendering, this would mean recompiling the shader, which486* we'd like to avoid doing. So we mark these formats non-renderable.487*488* We do support A8_UNORM as it's required and is renderable.489*/490if (pformat != PIPE_FORMAT_A8_UNORM &&491(util_format_is_alpha(pformat) ||492util_format_is_luminance_alpha(pformat)))493supported = false;494495enum isl_format rt_format = format;496497if (isl_format_is_rgbx(format) &&498!isl_format_supports_rendering(devinfo, format))499rt_format = isl_format_rgbx_to_rgba(format);500501supported &= isl_format_supports_rendering(devinfo, rt_format);502503if (!is_integer)504supported &= isl_format_supports_alpha_blending(devinfo, rt_format);505}506507if (usage & PIPE_BIND_SHADER_IMAGE) {508/* Dataport doesn't support compression, and we can't resolve an MCS509* compressed surface. (Buffer images may have sample count of 0.)510*/511supported &= sample_count == 0;512513supported &= isl_format_supports_typed_writes(devinfo, format);514supported &= isl_has_matching_typed_storage_image_format(devinfo, format);515}516517if (usage & PIPE_BIND_SAMPLER_VIEW) {518supported &= isl_format_supports_sampling(devinfo, format);519520/* disable Z16 unorm depth textures pre gen8 */521if (devinfo->ver < 8 && pformat == PIPE_FORMAT_Z16_UNORM)522supported = false;523524bool ignore_filtering = false;525526if (is_integer)527ignore_filtering = true;528529/* I said them, but I lied them. */530if (devinfo->ver < 5 && (format == ISL_FORMAT_R32G32B32A32_FLOAT ||531format == ISL_FORMAT_R24_UNORM_X8_TYPELESS ||532format == ISL_FORMAT_R32_FLOAT ||533format == ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS))534ignore_filtering = true;535if (!ignore_filtering)536supported &= isl_format_supports_filtering(devinfo, format);537538/* Don't advertise 3-component RGB formats for non-buffer textures.539* This ensures that they are renderable from an API perspective since540* the state tracker will fall back to RGBA or RGBX, which are541* renderable. We want to render internally for copies and blits,542* even if the application doesn't.543*544* Buffer textures don't need to be renderable, so we support real RGB.545* This is useful for PBO upload, and 32-bit RGB support is mandatory.546*/547if (target != PIPE_BUFFER)548supported &= fmtl->bpb != 24 && fmtl->bpb != 48 && fmtl->bpb != 96;549}550551if (usage & PIPE_BIND_VERTEX_BUFFER) {552supported &= isl_format_supports_vertex_fetch(devinfo, format);553554if (devinfo->verx10 < 75) {555/* W/A: Pre-Haswell, the hardware doesn't really support the formats556* we'd like to use here, so upload everything as UINT and fix it in557* the shader558*/559if (format == ISL_FORMAT_R10G10B10A2_UNORM ||560format == ISL_FORMAT_B10G10R10A2_UNORM ||561format == ISL_FORMAT_R10G10B10A2_SNORM ||562format == ISL_FORMAT_B10G10R10A2_SNORM ||563format == ISL_FORMAT_R10G10B10A2_USCALED ||564format == ISL_FORMAT_B10G10R10A2_USCALED ||565format == ISL_FORMAT_R10G10B10A2_SSCALED ||566format == ISL_FORMAT_B10G10R10A2_SSCALED)567supported = true;568569if (format == ISL_FORMAT_R8G8B8_SINT ||570format == ISL_FORMAT_R8G8B8_UINT ||571format == ISL_FORMAT_R16G16B16_SINT ||572format == ISL_FORMAT_R16G16B16_UINT)573supported = true;574}575}576577if (usage & PIPE_BIND_INDEX_BUFFER) {578supported &= format == ISL_FORMAT_R8_UINT ||579format == ISL_FORMAT_R16_UINT ||580format == ISL_FORMAT_R32_UINT;581}582583return supported;584}585586587