Path: blob/21.2-virgl/src/gallium/drivers/freedreno/a2xx/fd2_zsa.c
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/*1* Copyright (C) 2012 Rob Clark <[email protected]>2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,19* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE20* SOFTWARE.21*22* Authors:23* Rob Clark <[email protected]>24*/2526#include "pipe/p_state.h"27#include "util/u_memory.h"28#include "util/u_string.h"2930#include "fd2_context.h"31#include "fd2_util.h"32#include "fd2_zsa.h"3334void *35fd2_zsa_state_create(struct pipe_context *pctx,36const struct pipe_depth_stencil_alpha_state *cso)37{38struct fd2_zsa_stateobj *so;3940so = CALLOC_STRUCT(fd2_zsa_stateobj);41if (!so)42return NULL;4344so->base = *cso;4546so->rb_depthcontrol |=47A2XX_RB_DEPTHCONTROL_ZFUNC(cso->depth_func); /* maps 1:1 */4849if (cso->depth_enabled)50so->rb_depthcontrol |=51A2XX_RB_DEPTHCONTROL_Z_ENABLE |52COND(!cso->alpha_enabled, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);53if (cso->depth_writemask)54so->rb_depthcontrol |= A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE;5556if (cso->stencil[0].enabled) {57const struct pipe_stencil_state *s = &cso->stencil[0];5859so->rb_depthcontrol |=60A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE |61A2XX_RB_DEPTHCONTROL_STENCILFUNC(s->func) | /* maps 1:1 */62A2XX_RB_DEPTHCONTROL_STENCILFAIL(fd_stencil_op(s->fail_op)) |63A2XX_RB_DEPTHCONTROL_STENCILZPASS(fd_stencil_op(s->zpass_op)) |64A2XX_RB_DEPTHCONTROL_STENCILZFAIL(fd_stencil_op(s->zfail_op));65so->rb_stencilrefmask |=660xff000000 | /* ??? */67A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |68A2XX_RB_STENCILREFMASK_STENCILMASK(s->valuemask);6970if (cso->stencil[1].enabled) {71const struct pipe_stencil_state *bs = &cso->stencil[1];7273so->rb_depthcontrol |=74A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE |75A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(bs->func) | /* maps 1:1 */76A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(fd_stencil_op(bs->fail_op)) |77A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(fd_stencil_op(bs->zpass_op)) |78A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(fd_stencil_op(bs->zfail_op));79so->rb_stencilrefmask_bf |=800xff000000 | /* ??? */81A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(bs->writemask) |82A2XX_RB_STENCILREFMASK_STENCILMASK(bs->valuemask);83}84}8586if (cso->alpha_enabled) {87so->rb_colorcontrol = A2XX_RB_COLORCONTROL_ALPHA_FUNC(cso->alpha_func) |88A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE;89so->rb_alpha_ref = fui(cso->alpha_ref_value);90}9192return so;93}949596