Path: blob/21.2-virgl/src/gallium/drivers/freedreno/a3xx/fd3_zsa.c
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/*1* Copyright (C) 2013 Rob Clark <[email protected]>2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,19* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE20* SOFTWARE.21*22* Authors:23* Rob Clark <[email protected]>24*/2526#include "pipe/p_state.h"27#include "util/u_memory.h"28#include "util/u_string.h"2930#include "fd3_context.h"31#include "fd3_format.h"32#include "fd3_zsa.h"3334void *35fd3_zsa_state_create(struct pipe_context *pctx,36const struct pipe_depth_stencil_alpha_state *cso)37{38struct fd3_zsa_stateobj *so;3940so = CALLOC_STRUCT(fd3_zsa_stateobj);41if (!so)42return NULL;4344so->base = *cso;4546so->rb_depth_control |=47A3XX_RB_DEPTH_CONTROL_ZFUNC(cso->depth_func); /* maps 1:1 */4849if (cso->depth_enabled)50so->rb_depth_control |=51A3XX_RB_DEPTH_CONTROL_Z_ENABLE | A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE;5253if (cso->depth_writemask)54so->rb_depth_control |= A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE;5556if (cso->stencil[0].enabled) {57const struct pipe_stencil_state *s = &cso->stencil[0];5859so->rb_stencil_control |=60A3XX_RB_STENCIL_CONTROL_STENCIL_READ |61A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |62A3XX_RB_STENCIL_CONTROL_FUNC(s->func) | /* maps 1:1 */63A3XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |64A3XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |65A3XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));66so->rb_stencilrefmask |=670xff000000 | /* ??? */68A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |69A3XX_RB_STENCILREFMASK_STENCILMASK(s->valuemask);7071if (cso->stencil[1].enabled) {72const struct pipe_stencil_state *bs = &cso->stencil[1];7374so->rb_stencil_control |=75A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |76A3XX_RB_STENCIL_CONTROL_FUNC_BF(bs->func) | /* maps 1:1 */77A3XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) |78A3XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |79A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));80so->rb_stencilrefmask_bf |=810xff000000 | /* ??? */82A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(bs->writemask) |83A3XX_RB_STENCILREFMASK_STENCILMASK(bs->valuemask);84}85}8687if (cso->alpha_enabled) {88so->rb_render_control =89A3XX_RB_RENDER_CONTROL_ALPHA_TEST |90A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(cso->alpha_func);91so->rb_alpha_ref = A3XX_RB_ALPHA_REF_UINT(cso->alpha_ref_value * 255.0) |92A3XX_RB_ALPHA_REF_FLOAT(cso->alpha_ref_value);93so->rb_depth_control |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;94}9596return so;97}9899100