Path: blob/21.2-virgl/src/gallium/drivers/freedreno/a5xx/fd5_texture.c
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/*1* Copyright (C) 2016 Rob Clark <[email protected]>2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,19* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE20* SOFTWARE.21*22* Authors:23* Rob Clark <[email protected]>24*/2526#include "pipe/p_state.h"27#include "util/format/u_format.h"28#include "util/u_inlines.h"29#include "util/u_memory.h"30#include "util/u_string.h"3132#include "fd5_format.h"33#include "fd5_texture.h"3435static enum a5xx_tex_clamp36tex_clamp(unsigned wrap, bool *needs_border)37{38switch (wrap) {39case PIPE_TEX_WRAP_REPEAT:40return A5XX_TEX_REPEAT;41case PIPE_TEX_WRAP_CLAMP_TO_EDGE:42return A5XX_TEX_CLAMP_TO_EDGE;43case PIPE_TEX_WRAP_CLAMP_TO_BORDER:44*needs_border = true;45return A5XX_TEX_CLAMP_TO_BORDER;46case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:47/* only works for PoT.. need to emulate otherwise! */48return A5XX_TEX_MIRROR_CLAMP;49case PIPE_TEX_WRAP_MIRROR_REPEAT:50return A5XX_TEX_MIRROR_REPEAT;51case PIPE_TEX_WRAP_MIRROR_CLAMP:52case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:53/* these two we could perhaps emulate, but we currently54* just don't advertise PIPE_CAP_TEXTURE_MIRROR_CLAMP55*/56default:57DBG("invalid wrap: %u", wrap);58return 0;59}60}6162static enum a5xx_tex_filter63tex_filter(unsigned filter, bool aniso)64{65switch (filter) {66case PIPE_TEX_FILTER_NEAREST:67return A5XX_TEX_NEAREST;68case PIPE_TEX_FILTER_LINEAR:69return aniso ? A5XX_TEX_ANISO : A5XX_TEX_LINEAR;70default:71DBG("invalid filter: %u", filter);72return 0;73}74}7576static void *77fd5_sampler_state_create(struct pipe_context *pctx,78const struct pipe_sampler_state *cso)79{80struct fd5_sampler_stateobj *so = CALLOC_STRUCT(fd5_sampler_stateobj);81unsigned aniso = util_last_bit(MIN2(cso->max_anisotropy >> 1, 8));82bool miplinear = false;8384if (!so)85return NULL;8687so->base = *cso;8889if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR)90miplinear = true;9192so->needs_border = false;93so->texsamp0 =94COND(miplinear, A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR) |95A5XX_TEX_SAMP_0_XY_MAG(tex_filter(cso->mag_img_filter, aniso)) |96A5XX_TEX_SAMP_0_XY_MIN(tex_filter(cso->min_img_filter, aniso)) |97A5XX_TEX_SAMP_0_ANISO(aniso) |98A5XX_TEX_SAMP_0_WRAP_S(tex_clamp(cso->wrap_s, &so->needs_border)) |99A5XX_TEX_SAMP_0_WRAP_T(tex_clamp(cso->wrap_t, &so->needs_border)) |100A5XX_TEX_SAMP_0_WRAP_R(tex_clamp(cso->wrap_r, &so->needs_border));101102so->texsamp1 =103COND(!cso->seamless_cube_map, A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF) |104COND(!cso->normalized_coords, A5XX_TEX_SAMP_1_UNNORM_COORDS);105106so->texsamp0 |= A5XX_TEX_SAMP_0_LOD_BIAS(cso->lod_bias);107108if (cso->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {109so->texsamp1 |= A5XX_TEX_SAMP_1_MIN_LOD(cso->min_lod) |110A5XX_TEX_SAMP_1_MAX_LOD(cso->max_lod);111} else {112/* If we're not doing mipmap filtering, we still need a slightly > 0113* LOD clamp so the HW can decide between min and mag filtering of114* level 0.115*/116so->texsamp1 |= A5XX_TEX_SAMP_1_MIN_LOD(MIN2(cso->min_lod, 0.125)) |117A5XX_TEX_SAMP_1_MAX_LOD(MIN2(cso->max_lod, 0.125));118}119120if (cso->compare_mode)121so->texsamp1 |=122A5XX_TEX_SAMP_1_COMPARE_FUNC(cso->compare_func); /* maps 1:1 */123124return so;125}126127static bool128use_astc_srgb_workaround(struct pipe_context *pctx, enum pipe_format format)129{130return false; // TODO check if this is still needed on a5xx131}132133static struct pipe_sampler_view *134fd5_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,135const struct pipe_sampler_view *cso)136{137struct fd5_pipe_sampler_view *so = CALLOC_STRUCT(fd5_pipe_sampler_view);138struct fd_resource *rsc = fd_resource(prsc);139enum pipe_format format = cso->format;140unsigned lvl, layers = 0;141142if (!so)143return NULL;144145if (format == PIPE_FORMAT_X32_S8X24_UINT) {146rsc = rsc->stencil;147format = rsc->b.b.format;148}149150so->base = *cso;151pipe_reference(NULL, &prsc->reference);152so->base.texture = prsc;153so->base.reference.count = 1;154so->base.context = pctx;155156so->texconst0 = A5XX_TEX_CONST_0_FMT(fd5_pipe2tex(format)) |157A5XX_TEX_CONST_0_SAMPLES(fd_msaa_samples(prsc->nr_samples)) |158fd5_tex_swiz(format, cso->swizzle_r, cso->swizzle_g,159cso->swizzle_b, cso->swizzle_a);160161/* NOTE: since we sample z24s8 using 8888_UINT format, the swizzle162* we get isn't quite right. Use SWAP(XYZW) as a cheap and cheerful163* way to re-arrange things so stencil component is where the swiz164* expects.165*166* Note that gallium expects stencil sampler to return (s,s,s,s)167* which isn't quite true. To make that happen we'd have to massage168* the swizzle. But in practice only the .x component is used.169*/170if (format == PIPE_FORMAT_X24S8_UINT) {171so->texconst0 |= A5XX_TEX_CONST_0_SWAP(XYZW);172}173174if (util_format_is_srgb(format)) {175if (use_astc_srgb_workaround(pctx, format))176so->astc_srgb = true;177so->texconst0 |= A5XX_TEX_CONST_0_SRGB;178}179180if (cso->target == PIPE_BUFFER) {181unsigned elements = cso->u.buf.size / util_format_get_blocksize(format);182183lvl = 0;184so->texconst1 = A5XX_TEX_CONST_1_WIDTH(elements & MASK(15)) |185A5XX_TEX_CONST_1_HEIGHT(elements >> 15);186so->texconst2 = A5XX_TEX_CONST_2_UNK4 | A5XX_TEX_CONST_2_UNK31;187so->offset = cso->u.buf.offset;188} else {189unsigned miplevels;190191lvl = fd_sampler_first_level(cso);192miplevels = fd_sampler_last_level(cso) - lvl;193layers = cso->u.tex.last_layer - cso->u.tex.first_layer + 1;194195so->texconst0 |= A5XX_TEX_CONST_0_MIPLVLS(miplevels);196so->texconst1 = A5XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) |197A5XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));198so->texconst2 = A5XX_TEX_CONST_2_PITCHALIGN(rsc->layout.pitchalign - 6) |199A5XX_TEX_CONST_2_PITCH(fd_resource_pitch(rsc, lvl));200so->offset = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer);201}202203so->texconst2 |= A5XX_TEX_CONST_2_TYPE(fd5_tex_type(cso->target));204205switch (cso->target) {206case PIPE_TEXTURE_RECT:207case PIPE_TEXTURE_1D:208case PIPE_TEXTURE_2D:209so->texconst3 = A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);210so->texconst5 = A5XX_TEX_CONST_5_DEPTH(1);211break;212case PIPE_TEXTURE_1D_ARRAY:213case PIPE_TEXTURE_2D_ARRAY:214so->texconst3 = A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);215so->texconst5 = A5XX_TEX_CONST_5_DEPTH(layers);216break;217case PIPE_TEXTURE_CUBE:218case PIPE_TEXTURE_CUBE_ARRAY:219so->texconst3 = A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);220so->texconst5 = A5XX_TEX_CONST_5_DEPTH(layers / 6);221break;222case PIPE_TEXTURE_3D:223so->texconst3 =224A5XX_TEX_CONST_3_MIN_LAYERSZ(225fd_resource_slice(rsc, prsc->last_level)->size0) |226A5XX_TEX_CONST_3_ARRAY_PITCH(fd_resource_slice(rsc, lvl)->size0);227so->texconst5 = A5XX_TEX_CONST_5_DEPTH(u_minify(prsc->depth0, lvl));228break;229default:230so->texconst3 = 0x00000000;231break;232}233234return &so->base;235}236237static void238fd5_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader,239unsigned start, unsigned nr,240unsigned unbind_num_trailing_slots,241struct pipe_sampler_view **views)242{243struct fd_context *ctx = fd_context(pctx);244struct fd5_context *fd5_ctx = fd5_context(ctx);245uint16_t astc_srgb = 0;246unsigned i;247248for (i = 0; i < nr; i++) {249if (views[i]) {250struct fd5_pipe_sampler_view *view = fd5_pipe_sampler_view(views[i]);251if (view->astc_srgb)252astc_srgb |= (1 << i);253}254}255256fd_set_sampler_views(pctx, shader, start, nr, unbind_num_trailing_slots,257views);258259if (shader == PIPE_SHADER_FRAGMENT) {260fd5_ctx->fastc_srgb = astc_srgb;261} else if (shader == PIPE_SHADER_VERTEX) {262fd5_ctx->vastc_srgb = astc_srgb;263}264}265266void267fd5_texture_init(struct pipe_context *pctx)268{269pctx->create_sampler_state = fd5_sampler_state_create;270pctx->bind_sampler_states = fd_sampler_states_bind;271pctx->create_sampler_view = fd5_sampler_view_create;272pctx->set_sampler_views = fd5_set_sampler_views;273}274275276