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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/freedreno/a5xx/fd5_zsa.c
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/*
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* Copyright (C) 2016 Rob Clark <[email protected]>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <[email protected]>
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*/
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#include "pipe/p_state.h"
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#include "util/u_memory.h"
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#include "util/u_string.h"
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#include "fd5_context.h"
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#include "fd5_format.h"
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#include "fd5_zsa.h"
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void *
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fd5_zsa_state_create(struct pipe_context *pctx,
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const struct pipe_depth_stencil_alpha_state *cso)
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{
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struct fd5_zsa_stateobj *so;
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so = CALLOC_STRUCT(fd5_zsa_stateobj);
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if (!so)
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return NULL;
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so->base = *cso;
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switch (cso->depth_func) {
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case PIPE_FUNC_LESS:
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case PIPE_FUNC_LEQUAL:
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so->gras_lrz_cntl = A5XX_GRAS_LRZ_CNTL_ENABLE;
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break;
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case PIPE_FUNC_GREATER:
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case PIPE_FUNC_GEQUAL:
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so->gras_lrz_cntl =
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A5XX_GRAS_LRZ_CNTL_ENABLE | A5XX_GRAS_LRZ_CNTL_GREATER;
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break;
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default:
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/* LRZ not enabled */
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so->gras_lrz_cntl = 0;
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break;
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}
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if (!(cso->stencil->enabled || cso->alpha_enabled || !cso->depth_writemask))
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so->lrz_write = true;
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so->rb_depth_cntl |=
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A5XX_RB_DEPTH_CNTL_ZFUNC(cso->depth_func); /* maps 1:1 */
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if (cso->depth_enabled)
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so->rb_depth_cntl |=
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A5XX_RB_DEPTH_CNTL_Z_ENABLE | A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
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if (cso->depth_writemask)
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so->rb_depth_cntl |= A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
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if (cso->stencil[0].enabled) {
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const struct pipe_stencil_state *s = &cso->stencil[0];
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so->rb_stencil_control |=
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A5XX_RB_STENCIL_CONTROL_STENCIL_READ |
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A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
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A5XX_RB_STENCIL_CONTROL_FUNC(s->func) | /* maps 1:1 */
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A5XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |
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A5XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |
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A5XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));
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so->rb_stencilrefmask |=
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A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |
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A5XX_RB_STENCILREFMASK_STENCILMASK(s->valuemask);
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if (cso->stencil[1].enabled) {
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const struct pipe_stencil_state *bs = &cso->stencil[1];
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so->rb_stencil_control |=
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A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
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A5XX_RB_STENCIL_CONTROL_FUNC_BF(bs->func) | /* maps 1:1 */
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A5XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) |
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A5XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |
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A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));
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so->rb_stencilrefmask_bf |=
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A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(bs->writemask) |
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A5XX_RB_STENCILREFMASK_BF_STENCILMASK(bs->valuemask);
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}
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}
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if (cso->alpha_enabled) {
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uint32_t ref = cso->alpha_ref_value * 255.0;
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so->rb_alpha_control =
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A5XX_RB_ALPHA_CONTROL_ALPHA_TEST |
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A5XX_RB_ALPHA_CONTROL_ALPHA_REF(ref) |
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A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(cso->alpha_func);
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// so->rb_depth_control |=
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// A5XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
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}
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return so;
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}
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