Path: blob/21.2-virgl/src/gallium/drivers/freedreno/a5xx/fd5_zsa.c
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/*1* Copyright (C) 2016 Rob Clark <[email protected]>2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,19* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE20* SOFTWARE.21*22* Authors:23* Rob Clark <[email protected]>24*/2526#include "pipe/p_state.h"27#include "util/u_memory.h"28#include "util/u_string.h"2930#include "fd5_context.h"31#include "fd5_format.h"32#include "fd5_zsa.h"3334void *35fd5_zsa_state_create(struct pipe_context *pctx,36const struct pipe_depth_stencil_alpha_state *cso)37{38struct fd5_zsa_stateobj *so;3940so = CALLOC_STRUCT(fd5_zsa_stateobj);41if (!so)42return NULL;4344so->base = *cso;4546switch (cso->depth_func) {47case PIPE_FUNC_LESS:48case PIPE_FUNC_LEQUAL:49so->gras_lrz_cntl = A5XX_GRAS_LRZ_CNTL_ENABLE;50break;5152case PIPE_FUNC_GREATER:53case PIPE_FUNC_GEQUAL:54so->gras_lrz_cntl =55A5XX_GRAS_LRZ_CNTL_ENABLE | A5XX_GRAS_LRZ_CNTL_GREATER;56break;5758default:59/* LRZ not enabled */60so->gras_lrz_cntl = 0;61break;62}6364if (!(cso->stencil->enabled || cso->alpha_enabled || !cso->depth_writemask))65so->lrz_write = true;6667so->rb_depth_cntl |=68A5XX_RB_DEPTH_CNTL_ZFUNC(cso->depth_func); /* maps 1:1 */6970if (cso->depth_enabled)71so->rb_depth_cntl |=72A5XX_RB_DEPTH_CNTL_Z_ENABLE | A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;7374if (cso->depth_writemask)75so->rb_depth_cntl |= A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;7677if (cso->stencil[0].enabled) {78const struct pipe_stencil_state *s = &cso->stencil[0];7980so->rb_stencil_control |=81A5XX_RB_STENCIL_CONTROL_STENCIL_READ |82A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |83A5XX_RB_STENCIL_CONTROL_FUNC(s->func) | /* maps 1:1 */84A5XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |85A5XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |86A5XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));87so->rb_stencilrefmask |=88A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |89A5XX_RB_STENCILREFMASK_STENCILMASK(s->valuemask);9091if (cso->stencil[1].enabled) {92const struct pipe_stencil_state *bs = &cso->stencil[1];9394so->rb_stencil_control |=95A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |96A5XX_RB_STENCIL_CONTROL_FUNC_BF(bs->func) | /* maps 1:1 */97A5XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) |98A5XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |99A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));100so->rb_stencilrefmask_bf |=101A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(bs->writemask) |102A5XX_RB_STENCILREFMASK_BF_STENCILMASK(bs->valuemask);103}104}105106if (cso->alpha_enabled) {107uint32_t ref = cso->alpha_ref_value * 255.0;108so->rb_alpha_control =109A5XX_RB_ALPHA_CONTROL_ALPHA_TEST |110A5XX_RB_ALPHA_CONTROL_ALPHA_REF(ref) |111A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(cso->alpha_func);112// so->rb_depth_control |=113// A5XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;114}115116return so;117}118119120