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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/freedreno/a6xx/fd6_texture.c
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/*
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* Copyright (C) 2016 Rob Clark <[email protected]>
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* Copyright © 2018 Google, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <[email protected]>
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*/
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#include "pipe/p_state.h"
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#include "util/format/u_format.h"
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#include "util/hash_table.h"
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#include "util/u_inlines.h"
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#include "util/u_memory.h"
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#include "util/u_string.h"
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#include "fd6_emit.h"
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#include "fd6_format.h"
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#include "fd6_resource.h"
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#include "fd6_texture.h"
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static void
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remove_tex_entry(struct fd6_context *fd6_ctx, struct hash_entry *entry)
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{
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struct fd6_texture_state *tex = entry->data;
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_mesa_hash_table_remove(fd6_ctx->tex_cache, entry);
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fd6_texture_state_reference(&tex, NULL);
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}
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static enum a6xx_tex_clamp
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tex_clamp(unsigned wrap, bool *needs_border)
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{
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switch (wrap) {
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case PIPE_TEX_WRAP_REPEAT:
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return A6XX_TEX_REPEAT;
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case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
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return A6XX_TEX_CLAMP_TO_EDGE;
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case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
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*needs_border = true;
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return A6XX_TEX_CLAMP_TO_BORDER;
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case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
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/* only works for PoT.. need to emulate otherwise! */
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return A6XX_TEX_MIRROR_CLAMP;
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case PIPE_TEX_WRAP_MIRROR_REPEAT:
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return A6XX_TEX_MIRROR_REPEAT;
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case PIPE_TEX_WRAP_MIRROR_CLAMP:
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case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
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/* these two we could perhaps emulate, but we currently
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* just don't advertise PIPE_CAP_TEXTURE_MIRROR_CLAMP
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*/
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default:
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DBG("invalid wrap: %u", wrap);
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return 0;
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}
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}
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static enum a6xx_tex_filter
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tex_filter(unsigned filter, bool aniso)
77
{
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switch (filter) {
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case PIPE_TEX_FILTER_NEAREST:
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return A6XX_TEX_NEAREST;
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case PIPE_TEX_FILTER_LINEAR:
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return aniso ? A6XX_TEX_ANISO : A6XX_TEX_LINEAR;
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default:
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DBG("invalid filter: %u", filter);
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return 0;
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}
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}
88
89
static void *
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fd6_sampler_state_create(struct pipe_context *pctx,
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const struct pipe_sampler_state *cso)
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{
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struct fd6_sampler_stateobj *so = CALLOC_STRUCT(fd6_sampler_stateobj);
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unsigned aniso = util_last_bit(MIN2(cso->max_anisotropy >> 1, 8));
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bool miplinear = false;
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if (!so)
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return NULL;
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so->base = *cso;
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so->seqno = ++fd6_context(fd_context(pctx))->tex_seqno;
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if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR)
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miplinear = true;
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so->needs_border = false;
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so->texsamp0 =
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COND(miplinear, A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR) |
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A6XX_TEX_SAMP_0_XY_MAG(tex_filter(cso->mag_img_filter, aniso)) |
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A6XX_TEX_SAMP_0_XY_MIN(tex_filter(cso->min_img_filter, aniso)) |
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A6XX_TEX_SAMP_0_ANISO(aniso) |
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A6XX_TEX_SAMP_0_WRAP_S(tex_clamp(cso->wrap_s, &so->needs_border)) |
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A6XX_TEX_SAMP_0_WRAP_T(tex_clamp(cso->wrap_t, &so->needs_border)) |
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A6XX_TEX_SAMP_0_WRAP_R(tex_clamp(cso->wrap_r, &so->needs_border));
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so->texsamp1 =
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COND(cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE,
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A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR) |
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COND(!cso->seamless_cube_map, A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF) |
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COND(!cso->normalized_coords, A6XX_TEX_SAMP_1_UNNORM_COORDS);
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so->texsamp0 |= A6XX_TEX_SAMP_0_LOD_BIAS(cso->lod_bias);
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so->texsamp1 |= A6XX_TEX_SAMP_1_MIN_LOD(cso->min_lod) |
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A6XX_TEX_SAMP_1_MAX_LOD(cso->max_lod);
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126
if (cso->compare_mode)
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so->texsamp1 |=
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A6XX_TEX_SAMP_1_COMPARE_FUNC(cso->compare_func); /* maps 1:1 */
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return so;
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}
132
133
static void
134
fd6_sampler_state_delete(struct pipe_context *pctx, void *hwcso)
135
{
136
struct fd_context *ctx = fd_context(pctx);
137
struct fd6_context *fd6_ctx = fd6_context(ctx);
138
struct fd6_sampler_stateobj *samp = hwcso;
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140
fd_screen_lock(ctx->screen);
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hash_table_foreach (fd6_ctx->tex_cache, entry) {
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struct fd6_texture_state *state = entry->data;
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145
for (unsigned i = 0; i < ARRAY_SIZE(state->key.samp); i++) {
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if (samp->seqno == state->key.samp[i].seqno) {
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remove_tex_entry(fd6_ctx, entry);
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break;
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}
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}
151
}
152
153
fd_screen_unlock(ctx->screen);
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free(hwcso);
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}
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static struct pipe_sampler_view *
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fd6_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
160
const struct pipe_sampler_view *cso)
161
{
162
struct fd6_pipe_sampler_view *so = CALLOC_STRUCT(fd6_pipe_sampler_view);
163
164
if (!so)
165
return NULL;
166
167
so->base = *cso;
168
pipe_reference(NULL, &prsc->reference);
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so->base.texture = prsc;
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so->base.reference.count = 1;
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so->base.context = pctx;
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so->needs_validate = true;
173
174
return &so->base;
175
}
176
177
static void
178
fd6_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader,
179
unsigned start, unsigned nr,
180
unsigned unbind_num_trailing_slots,
181
struct pipe_sampler_view **views) in_dt
182
{
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struct fd_context *ctx = fd_context(pctx);
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185
fd_set_sampler_views(pctx, shader, start, nr, unbind_num_trailing_slots,
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views);
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188
if (!views)
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return;
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for (unsigned i = 0; i < nr; i++) {
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struct fd6_pipe_sampler_view *so = fd6_pipe_sampler_view(views[i]);
193
194
if (!(so && so->needs_validate))
195
continue;
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struct fd_resource *rsc = fd_resource(so->base.texture);
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fd6_validate_format(ctx, rsc, so->base.format);
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fd6_sampler_view_update(ctx, so);
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so->needs_validate = false;
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}
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}
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206
void
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fd6_sampler_view_update(struct fd_context *ctx,
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struct fd6_pipe_sampler_view *so)
209
{
210
const struct pipe_sampler_view *cso = &so->base;
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struct pipe_resource *prsc = cso->texture;
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struct fd_resource *rsc = fd_resource(prsc);
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enum pipe_format format = cso->format;
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bool ubwc_enabled = false;
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unsigned lvl, layers = 0;
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217
fd6_validate_format(ctx, rsc, cso->format);
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if (format == PIPE_FORMAT_X32_S8X24_UINT) {
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rsc = rsc->stencil;
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format = rsc->b.b.format;
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}
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so->seqno = ++fd6_context(ctx)->tex_seqno;
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so->ptr1 = rsc;
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so->rsc_seqno = rsc->seqno;
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if (cso->target == PIPE_BUFFER) {
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unsigned elements = cso->u.buf.size / util_format_get_blocksize(format);
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lvl = 0;
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so->texconst1 = A6XX_TEX_CONST_1_WIDTH(elements & MASK(15)) |
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A6XX_TEX_CONST_1_HEIGHT(elements >> 15);
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so->texconst2 = A6XX_TEX_CONST_2_UNK4 | A6XX_TEX_CONST_2_UNK31;
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so->offset1 = cso->u.buf.offset;
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} else {
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unsigned miplevels;
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lvl = fd_sampler_first_level(cso);
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miplevels = fd_sampler_last_level(cso) - lvl;
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layers = cso->u.tex.last_layer - cso->u.tex.first_layer + 1;
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so->texconst0 |= A6XX_TEX_CONST_0_MIPLVLS(miplevels);
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so->texconst1 = A6XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) |
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A6XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));
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so->texconst2 = A6XX_TEX_CONST_2_PITCHALIGN(rsc->layout.pitchalign - 6) |
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A6XX_TEX_CONST_2_PITCH(fd_resource_pitch(rsc, lvl));
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249
ubwc_enabled = fd_resource_ubwc_enabled(rsc, lvl);
250
251
if (rsc->b.b.format == PIPE_FORMAT_R8_G8B8_420_UNORM) {
252
struct fd_resource *next = fd_resource(rsc->b.b.next);
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/* In case of biplanar R8_G8B8, the UBWC metadata address in
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* dwords 7 and 8, is instead the pointer to the second plane.
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*/
257
so->ptr2 = next;
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so->texconst6 =
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A6XX_TEX_CONST_6_PLANE_PITCH(fd_resource_pitch(next, lvl));
260
261
if (ubwc_enabled) {
262
/* Further, if using UBWC with R8_G8B8, we only point to the
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* UBWC header and the color data is expected to follow immediately.
264
*/
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so->offset1 =
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fd_resource_ubwc_offset(rsc, lvl, cso->u.tex.first_layer);
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so->offset2 =
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fd_resource_ubwc_offset(next, lvl, cso->u.tex.first_layer);
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} else {
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so->offset1 = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer);
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so->offset2 = fd_resource_offset(next, lvl, cso->u.tex.first_layer);
272
}
273
} else {
274
so->offset1 = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer);
275
if (ubwc_enabled) {
276
so->ptr2 = rsc;
277
so->offset2 =
278
fd_resource_ubwc_offset(rsc, lvl, cso->u.tex.first_layer);
279
}
280
}
281
}
282
283
so->texconst0 |=
284
fd6_tex_const_0(prsc, lvl, cso->format, cso->swizzle_r, cso->swizzle_g,
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cso->swizzle_b, cso->swizzle_a);
286
287
so->texconst2 |= A6XX_TEX_CONST_2_TYPE(fd6_tex_type(cso->target));
288
289
switch (cso->target) {
290
case PIPE_TEXTURE_RECT:
291
case PIPE_TEXTURE_1D:
292
case PIPE_TEXTURE_2D:
293
so->texconst3 = A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
294
so->texconst5 = A6XX_TEX_CONST_5_DEPTH(1);
295
break;
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case PIPE_TEXTURE_1D_ARRAY:
297
case PIPE_TEXTURE_2D_ARRAY:
298
so->texconst3 = A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
299
so->texconst5 = A6XX_TEX_CONST_5_DEPTH(layers);
300
break;
301
case PIPE_TEXTURE_CUBE:
302
case PIPE_TEXTURE_CUBE_ARRAY:
303
so->texconst3 = A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
304
so->texconst5 = A6XX_TEX_CONST_5_DEPTH(layers / 6);
305
break;
306
case PIPE_TEXTURE_3D:
307
so->texconst3 =
308
A6XX_TEX_CONST_3_MIN_LAYERSZ(
309
fd_resource_slice(rsc, prsc->last_level)->size0) |
310
A6XX_TEX_CONST_3_ARRAY_PITCH(fd_resource_slice(rsc, lvl)->size0);
311
so->texconst5 = A6XX_TEX_CONST_5_DEPTH(u_minify(prsc->depth0, lvl));
312
break;
313
default:
314
break;
315
}
316
317
if (rsc->layout.tile_all)
318
so->texconst3 |= A6XX_TEX_CONST_3_TILE_ALL;
319
320
if (ubwc_enabled) {
321
uint32_t block_width, block_height;
322
fdl6_get_ubwc_blockwidth(&rsc->layout, &block_width, &block_height);
323
324
so->texconst3 |= A6XX_TEX_CONST_3_FLAG;
325
so->texconst9 |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(
326
rsc->layout.ubwc_layer_size >> 2);
327
so->texconst10 |=
328
A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(
329
fdl_ubwc_pitch(&rsc->layout, lvl)) |
330
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(util_logbase2_ceil(
331
DIV_ROUND_UP(u_minify(prsc->width0, lvl), block_width))) |
332
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(util_logbase2_ceil(
333
DIV_ROUND_UP(u_minify(prsc->height0, lvl), block_height)));
334
}
335
}
336
337
/* NOTE this can be called in either driver thread or frontend thread
338
* depending on where the last unref comes from
339
*/
340
static void
341
fd6_sampler_view_destroy(struct pipe_context *pctx,
342
struct pipe_sampler_view *_view)
343
{
344
struct fd_context *ctx = fd_context(pctx);
345
struct fd6_context *fd6_ctx = fd6_context(ctx);
346
struct fd6_pipe_sampler_view *view = fd6_pipe_sampler_view(_view);
347
348
fd_screen_lock(ctx->screen);
349
350
hash_table_foreach (fd6_ctx->tex_cache, entry) {
351
struct fd6_texture_state *state = entry->data;
352
353
for (unsigned i = 0; i < ARRAY_SIZE(state->key.view); i++) {
354
if (view->seqno == state->key.view[i].seqno) {
355
remove_tex_entry(fd6_ctx, entry);
356
break;
357
}
358
}
359
}
360
361
fd_screen_unlock(ctx->screen);
362
363
pipe_resource_reference(&view->base.texture, NULL);
364
365
free(view);
366
}
367
368
static uint32_t
369
key_hash(const void *_key)
370
{
371
const struct fd6_texture_key *key = _key;
372
return XXH32(key, sizeof(*key), 0);
373
}
374
375
static bool
376
key_equals(const void *_a, const void *_b)
377
{
378
const struct fd6_texture_key *a = _a;
379
const struct fd6_texture_key *b = _b;
380
return memcmp(a, b, sizeof(struct fd6_texture_key)) == 0;
381
}
382
383
struct fd6_texture_state *
384
fd6_texture_state(struct fd_context *ctx, enum pipe_shader_type type,
385
struct fd_texture_stateobj *tex)
386
{
387
struct fd6_context *fd6_ctx = fd6_context(ctx);
388
struct fd6_texture_state *state = NULL;
389
struct fd6_texture_key key;
390
bool needs_border = false;
391
392
memset(&key, 0, sizeof(key));
393
394
for (unsigned i = 0; i < tex->num_textures; i++) {
395
if (!tex->textures[i])
396
continue;
397
398
struct fd6_pipe_sampler_view *view =
399
fd6_pipe_sampler_view(tex->textures[i]);
400
401
/* NOTE that if the backing rsc was uncompressed between the
402
* time that the CSO was originally created and now, the rsc
403
* seqno would have changed, so we don't have to worry about
404
* getting a bogus cache hit.
405
*/
406
key.view[i].rsc_seqno = fd_resource(view->base.texture)->seqno;
407
key.view[i].seqno = view->seqno;
408
}
409
410
for (unsigned i = 0; i < tex->num_samplers; i++) {
411
if (!tex->samplers[i])
412
continue;
413
414
struct fd6_sampler_stateobj *sampler =
415
fd6_sampler_stateobj(tex->samplers[i]);
416
417
key.samp[i].seqno = sampler->seqno;
418
419
needs_border |= sampler->needs_border;
420
}
421
422
key.type = type;
423
key.bcolor_offset = fd6_border_color_offset(ctx, type, tex);
424
425
uint32_t hash = key_hash(&key);
426
fd_screen_lock(ctx->screen);
427
struct hash_entry *entry =
428
_mesa_hash_table_search_pre_hashed(fd6_ctx->tex_cache, hash, &key);
429
430
if (entry) {
431
fd6_texture_state_reference(&state, entry->data);
432
goto out_unlock;
433
}
434
435
state = CALLOC_STRUCT(fd6_texture_state);
436
437
/* NOTE: one ref for tex_cache, and second ref for returned state: */
438
pipe_reference_init(&state->reference, 2);
439
state->key = key;
440
state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 32 * 4);
441
state->needs_border = needs_border;
442
443
fd6_emit_textures(ctx, state->stateobj, type, tex, key.bcolor_offset, NULL);
444
445
/* NOTE: uses copy of key in state obj, because pointer passed by caller
446
* is probably on the stack
447
*/
448
_mesa_hash_table_insert_pre_hashed(fd6_ctx->tex_cache, hash, &state->key,
449
state);
450
451
out_unlock:
452
fd_screen_unlock(ctx->screen);
453
return state;
454
}
455
456
void
457
__fd6_texture_state_describe(char *buf, const struct fd6_texture_state *tex)
458
{
459
sprintf(buf, "fd6_texture_state<%p>", tex);
460
}
461
462
void
463
__fd6_texture_state_destroy(struct fd6_texture_state *state)
464
{
465
fd_ringbuffer_del(state->stateobj);
466
free(state);
467
}
468
469
static void
470
fd6_rebind_resource(struct fd_context *ctx, struct fd_resource *rsc) assert_dt
471
{
472
fd_screen_assert_locked(ctx->screen);
473
474
if (!(rsc->dirty & FD_DIRTY_TEX))
475
return;
476
477
struct fd6_context *fd6_ctx = fd6_context(ctx);
478
479
hash_table_foreach (fd6_ctx->tex_cache, entry) {
480
struct fd6_texture_state *state = entry->data;
481
482
for (unsigned i = 0; i < ARRAY_SIZE(state->key.view); i++) {
483
if (rsc->seqno == state->key.view[i].rsc_seqno) {
484
remove_tex_entry(fd6_ctx, entry);
485
break;
486
}
487
}
488
}
489
}
490
491
void
492
fd6_texture_init(struct pipe_context *pctx) disable_thread_safety_analysis
493
{
494
struct fd_context *ctx = fd_context(pctx);
495
struct fd6_context *fd6_ctx = fd6_context(ctx);
496
497
pctx->create_sampler_state = fd6_sampler_state_create;
498
pctx->delete_sampler_state = fd6_sampler_state_delete;
499
pctx->bind_sampler_states = fd_sampler_states_bind;
500
501
pctx->create_sampler_view = fd6_sampler_view_create;
502
pctx->sampler_view_destroy = fd6_sampler_view_destroy;
503
pctx->set_sampler_views = fd6_set_sampler_views;
504
505
ctx->rebind_resource = fd6_rebind_resource;
506
507
fd6_ctx->tex_cache = _mesa_hash_table_create(NULL, key_hash, key_equals);
508
}
509
510
void
511
fd6_texture_fini(struct pipe_context *pctx)
512
{
513
struct fd_context *ctx = fd_context(pctx);
514
struct fd6_context *fd6_ctx = fd6_context(ctx);
515
516
fd_screen_lock(ctx->screen);
517
518
hash_table_foreach (fd6_ctx->tex_cache, entry) {
519
remove_tex_entry(fd6_ctx, entry);
520
}
521
522
fd_screen_unlock(ctx->screen);
523
524
ralloc_free(fd6_ctx->tex_cache);
525
}
526
527