Path: blob/21.2-virgl/src/gallium/drivers/i915/i915_debug_fp.c
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/**************************************************************************1*2* Copyright 2003 VMware, Inc.3* All Rights Reserved.4*5* Permission is hereby granted, free of charge, to any person obtaining a6* copy of this software and associated documentation files (the7* "Software"), to deal in the Software without restriction, including8* without limitation the rights to use, copy, modify, merge, publish,9* distribute, sub license, and/or sell copies of the Software, and to10* permit persons to whom the Software is furnished to do so, subject to11* the following conditions:12*13* The above copyright notice and this permission notice (including the14* next paragraph) shall be included in all copies or substantial portions15* of the Software.16*17* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS18* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF19* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.20* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR21* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,22* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE23* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.24*25**************************************************************************/2627#include "util/log.h"28#include "util/ralloc.h"29#include "util/u_debug.h"30#include "i915_debug.h"31#include "i915_debug_private.h"32#include "i915_reg.h"3334#define PRINTF ralloc_asprintf_append3536static const char *opcodes[0x20] = {37"NOP", "ADD", "MOV", "MUL", "MAD", "DP2ADD", "DP3", "DP4",38"FRC", "RCP", "RSQ", "EXP", "LOG", "CMP", "MIN", "MAX",39"FLR", "MOD", "TRC", "SGE", "SLT", "TEXLD", "TEXLDP", "TEXLDB",40"TEXKILL", "DCL", "0x1a", "0x1b", "0x1c", "0x1d", "0x1e", "0x1f",41};4243static const int args[0x20] = {440, /* 0 nop */452, /* 1 add */461, /* 2 mov */472, /* 3 m ul */483, /* 4 mad */493, /* 5 dp2add */502, /* 6 dp3 */512, /* 7 dp4 */521, /* 8 frc */531, /* 9 rcp */541, /* a rsq */551, /* b exp */561, /* c log */573, /* d cmp */582, /* e min */592, /* f max */601, /* 10 flr */611, /* 11 mod */621, /* 12 trc */632, /* 13 sge */642, /* 14 slt */651, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,66};6768static const char *regname[0x8] = {69"R", "T", "CONST", "S", "OC", "OD", "U", "UNKNOWN",70};7172static void73print_reg_type_nr(char **stream, unsigned type, unsigned nr)74{75switch (type) {76case REG_TYPE_T:77switch (nr) {78case T_DIFFUSE:79PRINTF(stream, "T_DIFFUSE");80return;81case T_SPECULAR:82PRINTF(stream, "T_SPECULAR");83return;84case T_FOG_W:85PRINTF(stream, "T_FOG_W");86return;87default:88PRINTF(stream, "T_TEX%d", nr);89return;90}91case REG_TYPE_OC:92if (nr == 0) {93PRINTF(stream, "oC");94return;95}96break;97case REG_TYPE_OD:98if (nr == 0) {99PRINTF(stream, "oD");100return;101}102break;103default:104break;105}106107PRINTF(stream, "%s[%d]", regname[type], nr);108}109110#define REG_SWIZZLE_MASK 0x7777111#define REG_NEGATE_MASK 0x8888112113#define REG_SWIZZLE_XYZW \114((SRC_X << A2_SRC2_CHANNEL_X_SHIFT) | (SRC_Y << A2_SRC2_CHANNEL_Y_SHIFT) | \115(SRC_Z << A2_SRC2_CHANNEL_Z_SHIFT) | (SRC_W << A2_SRC2_CHANNEL_W_SHIFT))116117static void118print_reg_neg_swizzle(char **stream, unsigned reg)119{120int i;121122if ((reg & REG_SWIZZLE_MASK) == REG_SWIZZLE_XYZW &&123(reg & REG_NEGATE_MASK) == 0)124return;125126PRINTF(stream, ".");127128for (i = 3; i >= 0; i--) {129if (reg & (1 << ((i * 4) + 3)))130PRINTF(stream, "-");131132switch ((reg >> (i * 4)) & 0x7) {133case 0:134PRINTF(stream, "x");135break;136case 1:137PRINTF(stream, "y");138break;139case 2:140PRINTF(stream, "z");141break;142case 3:143PRINTF(stream, "w");144break;145case 4:146PRINTF(stream, "0");147break;148case 5:149PRINTF(stream, "1");150break;151default:152PRINTF(stream, "?");153break;154}155}156}157158static void159print_src_reg(char **stream, unsigned dword)160{161unsigned nr = (dword >> A2_SRC2_NR_SHIFT) & REG_NR_MASK;162unsigned type = (dword >> A2_SRC2_TYPE_SHIFT) & REG_TYPE_MASK;163print_reg_type_nr(stream, type, nr);164print_reg_neg_swizzle(stream, dword);165}166167static void168print_dest_reg(char **stream, unsigned dword)169{170unsigned nr = (dword >> A0_DEST_NR_SHIFT) & REG_NR_MASK;171unsigned type = (dword >> A0_DEST_TYPE_SHIFT) & REG_TYPE_MASK;172print_reg_type_nr(stream, type, nr);173if ((dword & A0_DEST_CHANNEL_ALL) == A0_DEST_CHANNEL_ALL)174return;175PRINTF(stream, ".");176if (dword & A0_DEST_CHANNEL_X)177PRINTF(stream, "x");178if (dword & A0_DEST_CHANNEL_Y)179PRINTF(stream, "y");180if (dword & A0_DEST_CHANNEL_Z)181PRINTF(stream, "z");182if (dword & A0_DEST_CHANNEL_W)183PRINTF(stream, "w");184}185186#define GET_SRC0_REG(r0, r1) ((r0 << 14) | (r1 >> A1_SRC0_CHANNEL_W_SHIFT))187#define GET_SRC1_REG(r0, r1) ((r0 << 8) | (r1 >> A2_SRC1_CHANNEL_W_SHIFT))188#define GET_SRC2_REG(r) (r)189190static void191print_arith_op(char **stream, unsigned opcode, const unsigned *program)192{193if (opcode != A0_NOP) {194print_dest_reg(stream, program[0]);195if (program[0] & A0_DEST_SATURATE)196PRINTF(stream, " = SATURATE ");197else198PRINTF(stream, " = ");199}200201PRINTF(stream, "%s ", opcodes[opcode]);202203print_src_reg(stream, GET_SRC0_REG(program[0], program[1]));204if (args[opcode] == 1)205return;206207PRINTF(stream, ", ");208print_src_reg(stream, GET_SRC1_REG(program[1], program[2]));209if (args[opcode] == 2)210return;211212PRINTF(stream, ", ");213print_src_reg(stream, GET_SRC2_REG(program[2]));214return;215}216217static void218print_tex_op(char **stream, unsigned opcode, const unsigned *program)219{220print_dest_reg(stream, program[0] | A0_DEST_CHANNEL_ALL);221PRINTF(stream, " = ");222223PRINTF(stream, "%s ", opcodes[opcode]);224225PRINTF(stream, "S[%d],", program[0] & T0_SAMPLER_NR_MASK);226227print_reg_type_nr(stream,228(program[1] >> T1_ADDRESS_REG_TYPE_SHIFT) & REG_TYPE_MASK,229(program[1] >> T1_ADDRESS_REG_NR_SHIFT) & REG_NR_MASK);230}231232static void233print_texkil_op(char **stream, unsigned opcode, const unsigned *program)234{235PRINTF(stream, "TEXKIL ");236237print_reg_type_nr(stream,238(program[1] >> T1_ADDRESS_REG_TYPE_SHIFT) & REG_TYPE_MASK,239(program[1] >> T1_ADDRESS_REG_NR_SHIFT) & REG_NR_MASK);240}241242static void243print_dcl_op(char **stream, unsigned opcode, const unsigned *program)244{245unsigned type = (program[0] >> D0_TYPE_SHIFT) & REG_TYPE_MASK;246247PRINTF(stream, "%s ", opcodes[opcode]);248249unsigned dest_dword = program[0];250if (type == REG_TYPE_S)251dest_dword |= A0_DEST_CHANNEL_ALL;252print_dest_reg(stream, dest_dword);253254if (type == REG_TYPE_S) {255switch (program[0] & D0_SAMPLE_TYPE_MASK) {256case D0_SAMPLE_TYPE_2D:257PRINTF(stream, " 2D");258break;259case D0_SAMPLE_TYPE_VOLUME:260PRINTF(stream, " 3D");261break;262case D0_SAMPLE_TYPE_CUBE:263PRINTF(stream, " CUBE");264break;265default:266PRINTF(stream, " XXX bad type");267break;268}269}270}271272void273i915_disassemble_program(const unsigned *program, unsigned sz)274{275unsigned i;276277mesa_logi("\t\tBEGIN");278279assert((program[0] & 0x1ff) + 2 == sz);280281program++;282for (i = 1; i < sz; i += 3, program += 3) {283unsigned opcode = program[0] & (0x1f << 24);284285char *stream = ralloc_strdup(NULL, "");286if ((int)opcode >= A0_NOP && opcode <= A0_SLT)287print_arith_op(&stream, opcode >> 24, program);288else if (opcode >= T0_TEXLD && opcode < T0_TEXKILL)289print_tex_op(&stream, opcode >> 24, program);290else if (opcode == T0_TEXKILL)291print_texkil_op(&stream, opcode >> 24, program);292else if (opcode == D0_DCL)293print_dcl_op(&stream, opcode >> 24, program);294else295ralloc_asprintf_append(&stream, "\t\t Unknown opcode 0x%x\n", opcode);296297mesa_logi("\t\t %s ", stream);298ralloc_free(stream);299}300301mesa_logi("\t\tEND");302}303304305