Path: blob/21.2-virgl/src/gallium/drivers/i915/i915_fpc.h
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/**************************************************************************1*2* Copyright 2003 VMware, Inc.3* All Rights Reserved.4*5* Permission is hereby granted, free of charge, to any person obtaining a6* copy of this software and associated documentation files (the7* "Software"), to deal in the Software without restriction, including8* without limitation the rights to use, copy, modify, merge, publish,9* distribute, sub license, and/or sell copies of the Software, and to10* permit persons to whom the Software is furnished to do so, subject to11* the following conditions:12*13* The above copyright notice and this permission notice (including the14* next paragraph) shall be included in all copies or substantial portions15* of the Software.16*17* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS18* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF19* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.20* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR21* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,22* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE23* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.24*25**************************************************************************/2627#ifndef I915_FPC_H28#define I915_FPC_H2930#include "i915_context.h"31#include "i915_reg.h"3233#include "pipe/p_shader_tokens.h"3435#include "tgsi/tgsi_parse.h"3637#define I915_PROGRAM_SIZE 1923839/* Use those indices for pos/face routing, must be >= num of inputs */40#define I915_SEMANTIC_POS 10041#define I915_SEMANTIC_FACE 1014243/**44* Program translation state45*/46struct i915_fp_compile {47struct i915_fragment_shader *shader; /* the shader we're compiling */4849bool used_constants[I915_MAX_CONSTANT];5051/** maps TGSI immediate index to constant slot */52uint32_t num_immediates;53uint32_t immediates_map[I915_MAX_CONSTANT];54float immediates[I915_MAX_CONSTANT][4];5556bool first_instruction;5758uint32_t declarations[I915_PROGRAM_SIZE];59uint32_t program[I915_PROGRAM_SIZE];6061uint32_t *csr; /**< Cursor, points into program. */6263uint32_t *decl; /**< Cursor, points into declarations. */6465uint32_t decl_s; /**< flags for which s regs need to be decl'd */66uint32_t decl_t; /**< flags for which t regs need to be decl'd */6768uint32_t temp_flag; /**< Tracks temporary regs which are in use */69uint32_t utemp_flag; /**< Tracks TYPE_U temporary regs which are in use */7071uint32_t register_phases[I915_MAX_TEMPORARY];72uint32_t nr_tex_indirect;73uint32_t nr_tex_insn;74uint32_t nr_alu_insn;75uint32_t nr_decl_insn;7677bool log_program_errors;78bool error; /**< Set if i915_program_error() is called */79uint32_t NumNativeInstructions;80uint32_t NumNativeAluInstructions;81uint32_t NumNativeTexInstructions;82uint32_t NumNativeTexIndirections;83};8485/* Having zero and one in here makes the definition of swizzle a lot86* easier.87*/88#define UREG_TYPE_SHIFT 2989#define UREG_NR_SHIFT 2490#define UREG_CHANNEL_X_NEGATE_SHIFT 2391#define UREG_CHANNEL_X_SHIFT 2092#define UREG_CHANNEL_Y_NEGATE_SHIFT 1993#define UREG_CHANNEL_Y_SHIFT 1694#define UREG_CHANNEL_Z_NEGATE_SHIFT 1595#define UREG_CHANNEL_Z_SHIFT 1296#define UREG_CHANNEL_W_NEGATE_SHIFT 1197#define UREG_CHANNEL_W_SHIFT 898#define UREG_CHANNEL_ZERO_NEGATE_MBZ 599#define UREG_CHANNEL_ZERO_SHIFT 4100#define UREG_CHANNEL_ONE_NEGATE_MBZ 1101#define UREG_CHANNEL_ONE_SHIFT 0102103#define UREG_BAD 0xffffffff /* not a valid ureg */104105#define X SRC_X106#define Y SRC_Y107#define Z SRC_Z108#define W SRC_W109#define ZERO SRC_ZERO110#define ONE SRC_ONE111112/* Construct a ureg:113*/114#define UREG(type, nr) \115(((type) << UREG_TYPE_SHIFT) | ((nr) << UREG_NR_SHIFT) | \116(X << UREG_CHANNEL_X_SHIFT) | (Y << UREG_CHANNEL_Y_SHIFT) | \117(Z << UREG_CHANNEL_Z_SHIFT) | (W << UREG_CHANNEL_W_SHIFT) | \118(ZERO << UREG_CHANNEL_ZERO_SHIFT) | (ONE << UREG_CHANNEL_ONE_SHIFT))119120#define GET_CHANNEL_SRC(reg, channel) ((reg << (channel * 4)) & (0xf << 20))121#define CHANNEL_SRC(src, channel) (src >> (channel * 4))122123#define GET_UREG_TYPE(reg) (((reg) >> UREG_TYPE_SHIFT) & REG_TYPE_MASK)124#define GET_UREG_NR(reg) (((reg) >> UREG_NR_SHIFT) & REG_NR_MASK)125126#define UREG_XYZW_CHANNEL_MASK 0x00ffff00127128/* One neat thing about the UREG representation:129*/130static inline int131swizzle(int reg, uint32_t x, uint32_t y, uint32_t z, uint32_t w)132{133assert(x <= SRC_ONE);134assert(y <= SRC_ONE);135assert(z <= SRC_ONE);136assert(w <= SRC_ONE);137return ((reg & ~UREG_XYZW_CHANNEL_MASK) |138CHANNEL_SRC(GET_CHANNEL_SRC(reg, x), 0) |139CHANNEL_SRC(GET_CHANNEL_SRC(reg, y), 1) |140CHANNEL_SRC(GET_CHANNEL_SRC(reg, z), 2) |141CHANNEL_SRC(GET_CHANNEL_SRC(reg, w), 3));142}143144#define A0_DEST(reg) (((reg)&UREG_TYPE_NR_MASK) >> UREG_A0_DEST_SHIFT_LEFT)145#define D0_DEST(reg) (((reg)&UREG_TYPE_NR_MASK) >> UREG_A0_DEST_SHIFT_LEFT)146#define T0_DEST(reg) (((reg)&UREG_TYPE_NR_MASK) >> UREG_A0_DEST_SHIFT_LEFT)147#define A0_SRC0(reg) (((reg)&UREG_MASK) >> UREG_A0_SRC0_SHIFT_LEFT)148#define A1_SRC0(reg) (((reg)&UREG_MASK) << UREG_A1_SRC0_SHIFT_RIGHT)149#define A1_SRC1(reg) (((reg)&UREG_MASK) >> UREG_A1_SRC1_SHIFT_LEFT)150#define A2_SRC1(reg) (((reg)&UREG_MASK) << UREG_A2_SRC1_SHIFT_RIGHT)151#define A2_SRC2(reg) (((reg)&UREG_MASK) >> UREG_A2_SRC2_SHIFT_LEFT)152153/* These are special, and don't have swizzle/negate bits.154*/155#define T0_SAMPLER(reg) (GET_UREG_NR(reg) << T0_SAMPLER_NR_SHIFT)156#define T1_ADDRESS_REG(reg) \157((GET_UREG_NR(reg) << T1_ADDRESS_REG_NR_SHIFT) | \158(GET_UREG_TYPE(reg) << T1_ADDRESS_REG_TYPE_SHIFT))159160/* Macros for translating UREG's into the various register fields used161* by the I915 programmable unit.162*/163#define UREG_A0_DEST_SHIFT_LEFT (UREG_TYPE_SHIFT - A0_DEST_TYPE_SHIFT)164#define UREG_A0_SRC0_SHIFT_LEFT (UREG_TYPE_SHIFT - A0_SRC0_TYPE_SHIFT)165#define UREG_A1_SRC0_SHIFT_RIGHT \166(A1_SRC0_CHANNEL_W_SHIFT - UREG_CHANNEL_W_SHIFT)167#define UREG_A1_SRC1_SHIFT_LEFT (UREG_TYPE_SHIFT - A1_SRC1_TYPE_SHIFT)168#define UREG_A2_SRC1_SHIFT_RIGHT \169(A2_SRC1_CHANNEL_W_SHIFT - UREG_CHANNEL_W_SHIFT)170#define UREG_A2_SRC2_SHIFT_LEFT (UREG_TYPE_SHIFT - A2_SRC2_TYPE_SHIFT)171172#define UREG_MASK 0xffffff00173#define UREG_TYPE_NR_MASK \174((REG_TYPE_MASK << UREG_TYPE_SHIFT) | (REG_NR_MASK << UREG_NR_SHIFT))175176/***********************************************************************177* Public interface for the compiler178*/179extern void i915_translate_fragment_program(struct i915_context *i915,180struct i915_fragment_shader *fs);181182extern uint32_t i915_get_temp(struct i915_fp_compile *p);183extern uint32_t i915_get_utemp(struct i915_fp_compile *p);184extern void i915_release_utemps(struct i915_fp_compile *p);185186extern uint32_t i915_emit_texld(struct i915_fp_compile *p, uint32_t dest,187uint32_t destmask, uint32_t sampler,188uint32_t coord, uint32_t op,189uint32_t num_coord);190191extern uint32_t i915_emit_arith(struct i915_fp_compile *p, uint32_t op,192uint32_t dest, uint32_t mask, uint32_t saturate,193uint32_t src0, uint32_t src1, uint32_t src2);194195extern uint32_t i915_emit_decl(struct i915_fp_compile *p, uint32_t type,196uint32_t nr, uint32_t d0_flags);197198extern uint32_t i915_emit_const1f(struct i915_fp_compile *p, float c0);199200extern uint32_t i915_emit_const2f(struct i915_fp_compile *p, float c0,201float c1);202203extern uint32_t i915_emit_const4fv(struct i915_fp_compile *p, const float *c);204205extern uint32_t i915_emit_const4f(struct i915_fp_compile *p, float c0, float c1,206float c2, float c3);207208/*======================================================================209* i915_fpc_translate.c210*/211212extern void i915_program_error(struct i915_fp_compile *p, const char *msg, ...);213214/*======================================================================215* i915_fpc_optimize.c216*/217218struct i915_src_register {219unsigned File : 4; /* TGSI_FILE_ */220unsigned Indirect : 1; /* BOOL */221unsigned Dimension : 1; /* BOOL */222int Index : 16; /* SINT */223unsigned SwizzleX : 3; /* TGSI_SWIZZLE_ */224unsigned SwizzleY : 3; /* TGSI_SWIZZLE_ */225unsigned SwizzleZ : 3; /* TGSI_SWIZZLE_ */226unsigned SwizzleW : 3; /* TGSI_SWIZZLE_ */227unsigned Absolute : 1; /* BOOL */228unsigned Negate : 1; /* BOOL */229};230231/* Additional swizzle supported in i915 */232#define TGSI_SWIZZLE_ZERO 4233#define TGSI_SWIZZLE_ONE 5234235struct i915_dst_register {236unsigned File : 4; /* TGSI_FILE_ */237unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */238unsigned Indirect : 1; /* BOOL */239unsigned Dimension : 1; /* BOOL */240int Index : 16; /* SINT */241unsigned Padding : 6;242};243244struct i915_full_dst_register {245struct i915_dst_register Register;246/*247struct tgsi_ind_register Indirect;248struct tgsi_dimension Dimension;249struct tgsi_ind_register DimIndirect;250*/251};252253struct i915_full_src_register {254struct i915_src_register Register;255/*256struct tgsi_ind_register Indirect;257struct tgsi_dimension Dimension;258struct tgsi_ind_register DimIndirect;259*/260};261262struct i915_full_instruction {263struct tgsi_instruction Instruction;264/*265struct tgsi_instruction_label Label;266*/267struct tgsi_instruction_texture Texture;268struct i915_full_dst_register Dst[1];269struct i915_full_src_register Src[3];270};271272union i915_full_token {273struct tgsi_token Token;274struct tgsi_full_declaration FullDeclaration;275struct tgsi_full_immediate FullImmediate;276struct i915_full_instruction FullInstruction;277struct tgsi_full_property FullProperty;278};279280struct i915_token_list {281union i915_full_token *Tokens;282unsigned NumTokens;283};284285extern struct i915_token_list *i915_optimize(const struct tgsi_token *tokens);286287extern void i915_optimize_free(struct i915_token_list *tokens);288289extern uint32_t i915_num_coords(uint32_t tex);290291#endif292293294