Path: blob/21.2-virgl/src/gallium/drivers/i915/i915_state.c
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/**************************************************************************1*2* Copyright 2007 VMware, Inc.3* All Rights Reserved.4*5* Permission is hereby granted, free of charge, to any person obtaining a6* copy of this software and associated documentation files (the7* "Software"), to deal in the Software without restriction, including8* without limitation the rights to use, copy, modify, merge, publish,9* distribute, sub license, and/or sell copies of the Software, and to10* permit persons to whom the Software is furnished to do so, subject to11* the following conditions:12*13* The above copyright notice and this permission notice (including the14* next paragraph) shall be included in all copies or substantial portions15* of the Software.16*17* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS18* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF19* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.20* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR21* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,22* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE23* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.24*25**************************************************************************/2627/* Authors: Keith Whitwell <[email protected]>28*/2930#include "compiler/nir/nir_builder.h"31#include "draw/draw_context.h"32#include "nir/nir_to_tgsi.h"33#include "tgsi/tgsi_parse.h"34#include "util/u_helpers.h"35#include "util/u_inlines.h"36#include "util/u_math.h"37#include "util/u_memory.h"38#include "util/u_transfer.h"39#include "nir.h"4041#include "i915_context.h"42#include "i915_fpc.h"43#include "i915_reg.h"44#include "i915_resource.h"45#include "i915_state.h"46#include "i915_state_inlines.h"4748/* The i915 (and related graphics cores) do not support GL_CLAMP. The49* Intel drivers for "other operating systems" implement GL_CLAMP as50* GL_CLAMP_TO_EDGE, so the same is done here.51*/52static unsigned53translate_wrap_mode(unsigned wrap)54{55switch (wrap) {56case PIPE_TEX_WRAP_REPEAT:57return TEXCOORDMODE_WRAP;58case PIPE_TEX_WRAP_CLAMP:59return TEXCOORDMODE_CLAMP_EDGE; /* not quite correct */60case PIPE_TEX_WRAP_CLAMP_TO_EDGE:61return TEXCOORDMODE_CLAMP_EDGE;62case PIPE_TEX_WRAP_CLAMP_TO_BORDER:63return TEXCOORDMODE_CLAMP_BORDER;64case PIPE_TEX_WRAP_MIRROR_REPEAT:65return TEXCOORDMODE_MIRROR;66default:67return TEXCOORDMODE_WRAP;68}69}7071static unsigned72translate_img_filter(unsigned filter)73{74switch (filter) {75case PIPE_TEX_FILTER_NEAREST:76return FILTER_NEAREST;77case PIPE_TEX_FILTER_LINEAR:78return FILTER_LINEAR;79default:80assert(0);81return FILTER_NEAREST;82}83}8485static unsigned86translate_mip_filter(unsigned filter)87{88switch (filter) {89case PIPE_TEX_MIPFILTER_NONE:90return MIPFILTER_NONE;91case PIPE_TEX_MIPFILTER_NEAREST:92return MIPFILTER_NEAREST;93case PIPE_TEX_MIPFILTER_LINEAR:94return MIPFILTER_LINEAR;95default:96assert(0);97return MIPFILTER_NONE;98}99}100101static uint32_t102i915_remap_lis6_blend_dst_alpha(uint32_t lis6, uint32_t normal, uint32_t inv)103{104uint32_t src = (lis6 >> S6_CBUF_SRC_BLEND_FACT_SHIFT) & BLENDFACT_MASK;105lis6 &= ~SRC_BLND_FACT(BLENDFACT_MASK);106if (src == BLENDFACT_DST_ALPHA)107src = normal;108else if (src == BLENDFACT_INV_DST_ALPHA)109src = inv;110lis6 |= SRC_BLND_FACT(src);111112uint32_t dst = (lis6 >> S6_CBUF_DST_BLEND_FACT_SHIFT) & BLENDFACT_MASK;113lis6 &= ~DST_BLND_FACT(BLENDFACT_MASK);114if (dst == BLENDFACT_DST_ALPHA)115dst = normal;116else if (dst == BLENDFACT_INV_DST_ALPHA)117dst = inv;118lis6 |= DST_BLND_FACT(dst);119120return lis6;121}122123static uint32_t124i915_remap_iab_blend_dst_alpha(uint32_t iab, uint32_t normal, uint32_t inv)125{126uint32_t src = (iab >> IAB_SRC_FACTOR_SHIFT) & BLENDFACT_MASK;127iab &= ~SRC_BLND_FACT(BLENDFACT_MASK);128if (src == BLENDFACT_DST_ALPHA)129src = normal;130else if (src == BLENDFACT_INV_DST_ALPHA)131src = inv;132iab |= SRC_ABLND_FACT(src);133134uint32_t dst = (iab >> IAB_DST_FACTOR_SHIFT) & BLENDFACT_MASK;135iab &= ~DST_BLND_FACT(BLENDFACT_MASK);136if (dst == BLENDFACT_DST_ALPHA)137dst = normal;138else if (dst == BLENDFACT_INV_DST_ALPHA)139dst = inv;140iab |= DST_ABLND_FACT(dst);141142return iab;143}144145/* None of this state is actually used for anything yet.146*/147static void *148i915_create_blend_state(struct pipe_context *pipe,149const struct pipe_blend_state *blend)150{151struct i915_blend_state *cso_data = CALLOC_STRUCT(i915_blend_state);152153{154unsigned eqRGB = blend->rt[0].rgb_func;155unsigned srcRGB = blend->rt[0].rgb_src_factor;156unsigned dstRGB = blend->rt[0].rgb_dst_factor;157158unsigned eqA = blend->rt[0].alpha_func;159unsigned srcA = blend->rt[0].alpha_src_factor;160unsigned dstA = blend->rt[0].alpha_dst_factor;161162/* Special handling for MIN/MAX filter modes handled at163* frontend level.164*/165166if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {167168cso_data->iab = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |169IAB_MODIFY_ENABLE | IAB_ENABLE | IAB_MODIFY_FUNC |170IAB_MODIFY_SRC_FACTOR | IAB_MODIFY_DST_FACTOR |171SRC_ABLND_FACT(i915_translate_blend_factor(srcA)) |172DST_ABLND_FACT(i915_translate_blend_factor(dstA)) |173(i915_translate_blend_func(eqA) << IAB_FUNC_SHIFT));174} else {175cso_data->iab =176(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | IAB_MODIFY_ENABLE | 0);177}178}179180cso_data->modes4 |=181(_3DSTATE_MODES_4_CMD | ENABLE_LOGIC_OP_FUNC |182LOGIC_OP_FUNC(i915_translate_logic_op(blend->logicop_func)));183184if (blend->logicop_enable)185cso_data->LIS5 |= S5_LOGICOP_ENABLE;186187if (blend->dither)188cso_data->LIS5 |= S5_COLOR_DITHER_ENABLE;189190/* We potentially do some fixup at emission for non-BGRA targets */191if ((blend->rt[0].colormask & PIPE_MASK_R) == 0)192cso_data->LIS5 |= S5_WRITEDISABLE_RED;193194if ((blend->rt[0].colormask & PIPE_MASK_G) == 0)195cso_data->LIS5 |= S5_WRITEDISABLE_GREEN;196197if ((blend->rt[0].colormask & PIPE_MASK_B) == 0)198cso_data->LIS5 |= S5_WRITEDISABLE_BLUE;199200if ((blend->rt[0].colormask & PIPE_MASK_A) == 0)201cso_data->LIS5 |= S5_WRITEDISABLE_ALPHA;202203if (blend->rt[0].blend_enable) {204unsigned funcRGB = blend->rt[0].rgb_func;205unsigned srcRGB = blend->rt[0].rgb_src_factor;206unsigned dstRGB = blend->rt[0].rgb_dst_factor;207208cso_data->LIS6 |=209(S6_CBUF_BLEND_ENABLE |210SRC_BLND_FACT(i915_translate_blend_factor(srcRGB)) |211DST_BLND_FACT(i915_translate_blend_factor(dstRGB)) |212(i915_translate_blend_func(funcRGB) << S6_CBUF_BLEND_FUNC_SHIFT));213}214215cso_data->LIS6_alpha_in_g = i915_remap_lis6_blend_dst_alpha(216cso_data->LIS6, BLENDFACT_DST_COLR, BLENDFACT_INV_DST_COLR);217cso_data->LIS6_alpha_is_x = i915_remap_lis6_blend_dst_alpha(218cso_data->LIS6, BLENDFACT_ONE, BLENDFACT_ZERO);219220cso_data->iab_alpha_in_g = i915_remap_iab_blend_dst_alpha(221cso_data->iab, BLENDFACT_DST_COLR, BLENDFACT_INV_DST_COLR);222cso_data->iab_alpha_is_x = i915_remap_iab_blend_dst_alpha(223cso_data->iab, BLENDFACT_ONE, BLENDFACT_ZERO);224225return cso_data;226}227228static void229i915_bind_blend_state(struct pipe_context *pipe, void *blend)230{231struct i915_context *i915 = i915_context(pipe);232233if (i915->blend == blend)234return;235236i915->blend = (struct i915_blend_state *)blend;237238i915->dirty |= I915_NEW_BLEND;239}240241static void242i915_delete_blend_state(struct pipe_context *pipe, void *blend)243{244FREE(blend);245}246247static void248i915_set_blend_color(struct pipe_context *pipe,249const struct pipe_blend_color *blend_color)250{251struct i915_context *i915 = i915_context(pipe);252253if (!blend_color)254return;255256i915->blend_color = *blend_color;257258i915->dirty |= I915_NEW_BLEND;259}260261static void262i915_set_stencil_ref(struct pipe_context *pipe,263const struct pipe_stencil_ref stencil_ref)264{265struct i915_context *i915 = i915_context(pipe);266267i915->stencil_ref = stencil_ref;268269i915->dirty |= I915_NEW_DEPTH_STENCIL;270}271272static void *273i915_create_sampler_state(struct pipe_context *pipe,274const struct pipe_sampler_state *sampler)275{276struct i915_sampler_state *cso = CALLOC_STRUCT(i915_sampler_state);277const unsigned ws = sampler->wrap_s;278const unsigned wt = sampler->wrap_t;279const unsigned wr = sampler->wrap_r;280unsigned minFilt, magFilt;281unsigned mipFilt;282283cso->templ = *sampler;284285mipFilt = translate_mip_filter(sampler->min_mip_filter);286minFilt = translate_img_filter(sampler->min_img_filter);287magFilt = translate_img_filter(sampler->mag_img_filter);288289if (sampler->max_anisotropy > 1)290minFilt = magFilt = FILTER_ANISOTROPIC;291292if (sampler->max_anisotropy > 2) {293cso->state[0] |= SS2_MAX_ANISO_4;294}295296{297int b = (int)(sampler->lod_bias * 16.0);298b = CLAMP(b, -256, 255);299cso->state[0] |= ((b << SS2_LOD_BIAS_SHIFT) & SS2_LOD_BIAS_MASK);300}301302/* Shadow:303*/304if (sampler->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {305cso->state[0] |= (SS2_SHADOW_ENABLE | i915_translate_shadow_compare_func(306sampler->compare_func));307308minFilt = FILTER_4X4_FLAT;309magFilt = FILTER_4X4_FLAT;310}311312cso->state[0] |=313((minFilt << SS2_MIN_FILTER_SHIFT) | (mipFilt << SS2_MIP_FILTER_SHIFT) |314(magFilt << SS2_MAG_FILTER_SHIFT));315316cso->state[1] |= ((translate_wrap_mode(ws) << SS3_TCX_ADDR_MODE_SHIFT) |317(translate_wrap_mode(wt) << SS3_TCY_ADDR_MODE_SHIFT) |318(translate_wrap_mode(wr) << SS3_TCZ_ADDR_MODE_SHIFT));319320if (sampler->normalized_coords)321cso->state[1] |= SS3_NORMALIZED_COORDS;322323{324int minlod = (int)(16.0 * sampler->min_lod);325int maxlod = (int)(16.0 * sampler->max_lod);326minlod = CLAMP(minlod, 0, 16 * 11);327maxlod = CLAMP(maxlod, 0, 16 * 11);328329if (minlod > maxlod)330maxlod = minlod;331332cso->minlod = minlod;333cso->maxlod = maxlod;334}335336{337ubyte r = float_to_ubyte(sampler->border_color.f[0]);338ubyte g = float_to_ubyte(sampler->border_color.f[1]);339ubyte b = float_to_ubyte(sampler->border_color.f[2]);340ubyte a = float_to_ubyte(sampler->border_color.f[3]);341cso->state[2] = I915PACKCOLOR8888(r, g, b, a);342}343return cso;344}345346static void347i915_bind_sampler_states(struct pipe_context *pipe,348enum pipe_shader_type shader, unsigned start,349unsigned num, void **samplers)350{351if (shader != PIPE_SHADER_FRAGMENT) {352assert(num == 0);353return;354}355356struct i915_context *i915 = i915_context(pipe);357unsigned i;358359/* Check for no-op */360if (num == i915->num_samplers &&361!memcmp(i915->fragment_sampler + start, samplers, num * sizeof(void *)))362return;363364for (i = 0; i < num; ++i)365i915->fragment_sampler[i + start] = samplers[i];366367/* find highest non-null samplers[] entry */368{369unsigned j = MAX2(i915->num_samplers, start + num);370while (j > 0 && i915->fragment_sampler[j - 1] == NULL)371j--;372i915->num_samplers = j;373}374375i915->dirty |= I915_NEW_SAMPLER;376}377378static void379i915_delete_sampler_state(struct pipe_context *pipe, void *sampler)380{381FREE(sampler);382}383384/** XXX move someday? Or consolidate all these simple state setters385* into one file.386*/387388static uint32_t389i915_get_modes4_stencil(const struct pipe_stencil_state *stencil)390{391int testmask = stencil->valuemask & 0xff;392int writemask = stencil->writemask & 0xff;393394return (_3DSTATE_MODES_4_CMD | ENABLE_STENCIL_TEST_MASK |395STENCIL_TEST_MASK(testmask) | ENABLE_STENCIL_WRITE_MASK |396STENCIL_WRITE_MASK(writemask));397}398399static uint32_t400i915_get_lis5_stencil(const struct pipe_stencil_state *stencil)401{402int test = i915_translate_compare_func(stencil->func);403int fop = i915_translate_stencil_op(stencil->fail_op);404int dfop = i915_translate_stencil_op(stencil->zfail_op);405int dpop = i915_translate_stencil_op(stencil->zpass_op);406407return (S5_STENCIL_TEST_ENABLE | S5_STENCIL_WRITE_ENABLE |408(test << S5_STENCIL_TEST_FUNC_SHIFT) |409(fop << S5_STENCIL_FAIL_SHIFT) |410(dfop << S5_STENCIL_PASS_Z_FAIL_SHIFT) |411(dpop << S5_STENCIL_PASS_Z_PASS_SHIFT));412}413414static uint32_t415i915_get_bfo(const struct pipe_stencil_state *stencil)416{417int test = i915_translate_compare_func(stencil->func);418int fop = i915_translate_stencil_op(stencil->fail_op);419int dfop = i915_translate_stencil_op(stencil->zfail_op);420int dpop = i915_translate_stencil_op(stencil->zpass_op);421422return (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_FUNCS |423BFO_ENABLE_STENCIL_TWO_SIDE | BFO_ENABLE_STENCIL_REF |424BFO_STENCIL_TWO_SIDE | (test << BFO_STENCIL_TEST_SHIFT) |425(fop << BFO_STENCIL_FAIL_SHIFT) |426(dfop << BFO_STENCIL_PASS_Z_FAIL_SHIFT) |427(dpop << BFO_STENCIL_PASS_Z_PASS_SHIFT));428}429430static uint32_t431i915_get_bfm(const struct pipe_stencil_state *stencil)432{433return (_3DSTATE_BACKFACE_STENCIL_MASKS | BFM_ENABLE_STENCIL_TEST_MASK |434BFM_ENABLE_STENCIL_WRITE_MASK |435((stencil->valuemask & 0xff) << BFM_STENCIL_TEST_MASK_SHIFT) |436((stencil->writemask & 0xff) << BFM_STENCIL_WRITE_MASK_SHIFT));437}438439static void *440i915_create_depth_stencil_state(441struct pipe_context *pipe,442const struct pipe_depth_stencil_alpha_state *depth_stencil)443{444struct i915_depth_stencil_state *cso =445CALLOC_STRUCT(i915_depth_stencil_state);446447cso->stencil_modes4_cw = i915_get_modes4_stencil(&depth_stencil->stencil[0]);448cso->stencil_modes4_ccw =449i915_get_modes4_stencil(&depth_stencil->stencil[1]);450451if (depth_stencil->stencil[0].enabled) {452cso->stencil_LIS5_cw = i915_get_lis5_stencil(&depth_stencil->stencil[0]);453}454455if (depth_stencil->stencil[1].enabled) {456cso->bfo_cw[0] = i915_get_bfo(&depth_stencil->stencil[1]);457cso->bfo_cw[1] = i915_get_bfm(&depth_stencil->stencil[1]);458459/* Precompute the backface stencil settings if front winding order is460* reversed -- HW doesn't have a bit to flip it for us.461*/462cso->stencil_LIS5_ccw = i915_get_lis5_stencil(&depth_stencil->stencil[1]);463cso->bfo_ccw[0] = i915_get_bfo(&depth_stencil->stencil[0]);464cso->bfo_ccw[1] = i915_get_bfm(&depth_stencil->stencil[0]);465} else {466/* This actually disables two-side stencil: The bit set is a467* modify-enable bit to indicate we are changing the two-side468* setting. Then there is a symbolic zero to show that we are469* setting the flag to zero/off.470*/471cso->bfo_cw[0] = cso->bfo_ccw[0] =472(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);473cso->bfo_cw[1] = cso->bfo_ccw[1] = 0;474475cso->stencil_LIS5_ccw = cso->stencil_LIS5_cw;476}477478if (depth_stencil->depth_enabled) {479int func = i915_translate_compare_func(depth_stencil->depth_func);480481cso->depth_LIS6 |=482(S6_DEPTH_TEST_ENABLE | (func << S6_DEPTH_TEST_FUNC_SHIFT));483484if (depth_stencil->depth_writemask)485cso->depth_LIS6 |= S6_DEPTH_WRITE_ENABLE;486}487488if (depth_stencil->alpha_enabled) {489int test = i915_translate_compare_func(depth_stencil->alpha_func);490ubyte refByte = float_to_ubyte(depth_stencil->alpha_ref_value);491492cso->depth_LIS6 |=493(S6_ALPHA_TEST_ENABLE | (test << S6_ALPHA_TEST_FUNC_SHIFT) |494(((unsigned)refByte) << S6_ALPHA_REF_SHIFT));495}496497return cso;498}499500static void501i915_bind_depth_stencil_state(struct pipe_context *pipe, void *depth_stencil)502{503struct i915_context *i915 = i915_context(pipe);504505if (i915->depth_stencil == depth_stencil)506return;507508i915->depth_stencil = (const struct i915_depth_stencil_state *)depth_stencil;509510i915->dirty |= I915_NEW_DEPTH_STENCIL;511}512513static void514i915_delete_depth_stencil_state(struct pipe_context *pipe, void *depth_stencil)515{516FREE(depth_stencil);517}518519static void520i915_set_scissor_states(struct pipe_context *pipe, unsigned start_slot,521unsigned num_scissors,522const struct pipe_scissor_state *scissor)523{524struct i915_context *i915 = i915_context(pipe);525526memcpy(&i915->scissor, scissor, sizeof(*scissor));527i915->dirty |= I915_NEW_SCISSOR;528}529530static void531i915_set_polygon_stipple(struct pipe_context *pipe,532const struct pipe_poly_stipple *stipple)533{534}535536static void *537i915_create_fs_state(struct pipe_context *pipe,538const struct pipe_shader_state *templ)539{540struct i915_context *i915 = i915_context(pipe);541struct i915_fragment_shader *ifs = CALLOC_STRUCT(i915_fragment_shader);542if (!ifs)543return NULL;544545ifs->draw_data = draw_create_fragment_shader(i915->draw, templ);546547if (templ->type == PIPE_SHADER_IR_NIR) {548ifs->state.tokens = nir_to_tgsi(templ->ir.nir, pipe->screen);549} else {550assert(templ->type == PIPE_SHADER_IR_TGSI);551/* we need to keep a local copy of the tokens */552ifs->state.tokens = tgsi_dup_tokens(templ->tokens);553}554555ifs->state.type = PIPE_SHADER_IR_TGSI;556557tgsi_scan_shader(ifs->state.tokens, &ifs->info);558559/* The shader's compiled to i915 instructions here */560i915_translate_fragment_program(i915, ifs);561562return ifs;563}564565static void566i915_bind_fs_state(struct pipe_context *pipe, void *shader)567{568struct i915_context *i915 = i915_context(pipe);569570if (i915->fs == shader)571return;572573i915->fs = (struct i915_fragment_shader *)shader;574575draw_bind_fragment_shader(i915->draw,576(i915->fs ? i915->fs->draw_data : NULL));577578i915->dirty |= I915_NEW_FS;579}580581static void582i915_delete_fs_state(struct pipe_context *pipe, void *shader)583{584struct i915_fragment_shader *ifs = (struct i915_fragment_shader *)shader;585586FREE(ifs->program);587ifs->program = NULL;588FREE((struct tgsi_token *)ifs->state.tokens);589ifs->state.tokens = NULL;590591ifs->program_len = 0;592593FREE(ifs);594}595596static void *597i915_create_vs_state(struct pipe_context *pipe,598const struct pipe_shader_state *templ)599{600struct i915_context *i915 = i915_context(pipe);601602struct pipe_shader_state from_nir;603if (templ->type == PIPE_SHADER_IR_NIR) {604nir_shader *s = templ->ir.nir;605606NIR_PASS_V(s, nir_lower_point_size, 1.0, 255.0);607608/* The gallivm draw path doesn't support non-native-integers NIR shaders,609* st/mesa does native-integers for the screen as a whole rather than610* per-stage, and i915 FS can't do native integers. So, convert to TGSI,611* where the draw path *does* support non-native-integers.612*/613from_nir.type = PIPE_SHADER_IR_TGSI;614from_nir.tokens = nir_to_tgsi(s, pipe->screen);615templ = &from_nir;616}617618return draw_create_vertex_shader(i915->draw, templ);619}620621static void622i915_bind_vs_state(struct pipe_context *pipe, void *shader)623{624struct i915_context *i915 = i915_context(pipe);625626if (i915->vs == shader)627return;628629i915->vs = shader;630631/* just pass-through to draw module */632draw_bind_vertex_shader(i915->draw, (struct draw_vertex_shader *)shader);633634i915->dirty |= I915_NEW_VS;635}636637static void638i915_delete_vs_state(struct pipe_context *pipe, void *shader)639{640struct i915_context *i915 = i915_context(pipe);641642/* just pass-through to draw module */643draw_delete_vertex_shader(i915->draw, (struct draw_vertex_shader *)shader);644}645646static void647i915_set_constant_buffer(struct pipe_context *pipe,648enum pipe_shader_type shader, uint32_t index,649bool take_ownership,650const struct pipe_constant_buffer *cb)651{652struct i915_context *i915 = i915_context(pipe);653struct pipe_resource *buf = cb ? cb->buffer : NULL;654unsigned new_num = 0;655bool diff = true;656657/* XXX don't support geom shaders now */658if (shader == PIPE_SHADER_GEOMETRY)659return;660661if (cb && cb->user_buffer) {662buf = i915_user_buffer_create(pipe->screen, (void *)cb->user_buffer,663cb->buffer_size, PIPE_BIND_CONSTANT_BUFFER);664}665666/* if we have a new buffer compare it with the old one */667if (buf) {668struct i915_buffer *ibuf = i915_buffer(buf);669struct pipe_resource *old_buf = i915->constants[shader];670struct i915_buffer *old = old_buf ? i915_buffer(old_buf) : NULL;671unsigned old_num = i915->current.num_user_constants[shader];672673new_num = ibuf->b.width0 / 4 * sizeof(float);674675if (old_num == new_num) {676if (old_num == 0)677diff = false;678#if 0679/* XXX no point in running this code since st/mesa only uses user buffers */680/* Can't compare the buffer data since they are userbuffers */681else if (old && old->free_on_destroy)682diff = memcmp(old->data, ibuf->data, ibuf->b.width0);683#else684(void)old;685#endif686}687} else {688diff = i915->current.num_user_constants[shader] != 0;689}690691if (take_ownership) {692pipe_resource_reference(&i915->constants[shader], NULL);693i915->constants[shader] = buf;694} else {695pipe_resource_reference(&i915->constants[shader], buf);696}697i915->current.num_user_constants[shader] = new_num;698699if (diff)700i915->dirty |= shader == PIPE_SHADER_VERTEX ? I915_NEW_VS_CONSTANTS701: I915_NEW_FS_CONSTANTS;702703if (cb && cb->user_buffer) {704pipe_resource_reference(&buf, NULL);705}706}707708static void709i915_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,710unsigned start, unsigned num,711unsigned unbind_num_trailing_slots,712struct pipe_sampler_view **views)713{714if (shader != PIPE_SHADER_FRAGMENT) {715/* No support for VS samplers, because it would mean accessing the716* write-combined maps of the textures, which is very slow. VS samplers717* are not a required feature of GL2.1 or GLES2.718*/719assert(num == 0);720return;721}722struct i915_context *i915 = i915_context(pipe);723uint32_t i;724725assert(num <= PIPE_MAX_SAMPLERS);726727/* Check for no-op */728if (views && num == i915->num_fragment_sampler_views &&729!memcmp(i915->fragment_sampler_views, views,730num * sizeof(struct pipe_sampler_view *)))731return;732733for (i = 0; i < num; i++) {734pipe_sampler_view_reference(&i915->fragment_sampler_views[i], views[i]);735}736737for (i = num; i < i915->num_fragment_sampler_views; i++)738pipe_sampler_view_reference(&i915->fragment_sampler_views[i], NULL);739740i915->num_fragment_sampler_views = num;741742i915->dirty |= I915_NEW_SAMPLER_VIEW;743}744745struct pipe_sampler_view *746i915_create_sampler_view_custom(struct pipe_context *pipe,747struct pipe_resource *texture,748const struct pipe_sampler_view *templ,749unsigned width0, unsigned height0)750{751struct pipe_sampler_view *view = CALLOC_STRUCT(pipe_sampler_view);752753if (view) {754*view = *templ;755view->reference.count = 1;756view->texture = NULL;757pipe_resource_reference(&view->texture, texture);758view->context = pipe;759}760761return view;762}763764static struct pipe_sampler_view *765i915_create_sampler_view(struct pipe_context *pipe,766struct pipe_resource *texture,767const struct pipe_sampler_view *templ)768{769struct pipe_sampler_view *view = CALLOC_STRUCT(pipe_sampler_view);770771if (view) {772*view = *templ;773view->reference.count = 1;774view->texture = NULL;775pipe_resource_reference(&view->texture, texture);776view->context = pipe;777}778779return view;780}781782static void783i915_sampler_view_destroy(struct pipe_context *pipe,784struct pipe_sampler_view *view)785{786pipe_resource_reference(&view->texture, NULL);787FREE(view);788}789790static void791i915_set_framebuffer_state(struct pipe_context *pipe,792const struct pipe_framebuffer_state *fb)793{794struct i915_context *i915 = i915_context(pipe);795796i915->framebuffer.width = fb->width;797i915->framebuffer.height = fb->height;798i915->framebuffer.nr_cbufs = fb->nr_cbufs;799if (fb->nr_cbufs) {800pipe_surface_reference(&i915->framebuffer.cbufs[0], fb->cbufs[0]);801802struct i915_surface *surf = i915_surface(i915->framebuffer.cbufs[0]);803if (i915->current.fixup_swizzle != surf->oc_swizzle) {804i915->current.fixup_swizzle = surf->oc_swizzle;805memcpy(i915->current.color_swizzle, surf->color_swizzle,806sizeof(surf->color_swizzle));807i915->dirty |= I915_NEW_COLOR_SWIZZLE;808}809} else {810pipe_surface_reference(&i915->framebuffer.cbufs[0], NULL);811}812pipe_surface_reference(&i915->framebuffer.zsbuf, fb->zsbuf);813814i915->dirty |= I915_NEW_FRAMEBUFFER;815}816817static void818i915_set_clip_state(struct pipe_context *pipe,819const struct pipe_clip_state *clip)820{821struct i915_context *i915 = i915_context(pipe);822823i915->clip = *clip;824825draw_set_clip_state(i915->draw, clip);826827i915->dirty |= I915_NEW_CLIP;828}829830/* Called when gallium frontends notice changes to the viewport831* matrix:832*/833static void834i915_set_viewport_states(struct pipe_context *pipe, unsigned start_slot,835unsigned num_viewports,836const struct pipe_viewport_state *viewport)837{838struct i915_context *i915 = i915_context(pipe);839840i915->viewport = *viewport; /* struct copy */841842/* pass the viewport info to the draw module */843draw_set_viewport_states(i915->draw, start_slot, num_viewports,844&i915->viewport);845846i915->dirty |= I915_NEW_VIEWPORT;847}848849static void *850i915_create_rasterizer_state(struct pipe_context *pipe,851const struct pipe_rasterizer_state *rasterizer)852{853struct i915_rasterizer_state *cso = CALLOC_STRUCT(i915_rasterizer_state);854855cso->templ = *rasterizer;856cso->light_twoside = rasterizer->light_twoside;857cso->ds[0].u = _3DSTATE_DEPTH_OFFSET_SCALE;858cso->ds[1].f = rasterizer->offset_scale;859if (rasterizer->poly_stipple_enable) {860cso->st |= ST1_ENABLE;861}862863if (rasterizer->scissor)864cso->sc[0] = _3DSTATE_SCISSOR_ENABLE_CMD | ENABLE_SCISSOR_RECT;865else866cso->sc[0] = _3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT;867868switch (rasterizer->cull_face) {869case PIPE_FACE_NONE:870cso->LIS4 |= S4_CULLMODE_NONE;871break;872case PIPE_FACE_FRONT:873if (rasterizer->front_ccw)874cso->LIS4 |= S4_CULLMODE_CCW;875else876cso->LIS4 |= S4_CULLMODE_CW;877break;878case PIPE_FACE_BACK:879if (rasterizer->front_ccw)880cso->LIS4 |= S4_CULLMODE_CW;881else882cso->LIS4 |= S4_CULLMODE_CCW;883break;884case PIPE_FACE_FRONT_AND_BACK:885cso->LIS4 |= S4_CULLMODE_BOTH;886break;887}888889{890int line_width = CLAMP((int)(rasterizer->line_width * 2), 1, 0xf);891892cso->LIS4 |= line_width << S4_LINE_WIDTH_SHIFT;893894if (rasterizer->line_smooth)895cso->LIS4 |= S4_LINE_ANTIALIAS_ENABLE;896}897898{899int point_size = CLAMP((int)rasterizer->point_size, 1, 0xff);900901cso->LIS4 |= point_size << S4_POINT_WIDTH_SHIFT;902}903904if (rasterizer->flatshade) {905cso->LIS4 |=906(S4_FLATSHADE_ALPHA | S4_FLATSHADE_COLOR | S4_FLATSHADE_SPECULAR);907}908909if (!rasterizer->flatshade_first)910cso->LIS6 |= (2 << S6_TRISTRIP_PV_SHIFT);911912cso->LIS7 = fui(rasterizer->offset_units);913914return cso;915}916917static void918i915_bind_rasterizer_state(struct pipe_context *pipe, void *raster)919{920struct i915_context *i915 = i915_context(pipe);921922if (i915->rasterizer == raster)923return;924925i915->rasterizer = (struct i915_rasterizer_state *)raster;926927/* pass-through to draw module */928draw_set_rasterizer_state(929i915->draw, (i915->rasterizer ? &(i915->rasterizer->templ) : NULL),930raster);931932i915->dirty |= I915_NEW_RASTERIZER;933}934935static void936i915_delete_rasterizer_state(struct pipe_context *pipe, void *raster)937{938FREE(raster);939}940941static void942i915_set_vertex_buffers(struct pipe_context *pipe, unsigned start_slot,943unsigned count, unsigned unbind_num_trailing_slots,944bool take_ownership,945const struct pipe_vertex_buffer *buffers)946{947struct i915_context *i915 = i915_context(pipe);948struct draw_context *draw = i915->draw;949950util_set_vertex_buffers_count(i915->vertex_buffers, &i915->nr_vertex_buffers,951buffers, start_slot, count,952unbind_num_trailing_slots, take_ownership);953954/* pass-through to draw module */955draw_set_vertex_buffers(draw, start_slot, count, unbind_num_trailing_slots,956buffers);957}958959static void *960i915_create_vertex_elements_state(struct pipe_context *pipe, unsigned count,961const struct pipe_vertex_element *attribs)962{963struct i915_velems_state *velems;964assert(count <= PIPE_MAX_ATTRIBS);965velems =966(struct i915_velems_state *)MALLOC(sizeof(struct i915_velems_state));967if (velems) {968velems->count = count;969memcpy(velems->velem, attribs, sizeof(*attribs) * count);970}971return velems;972}973974static void975i915_bind_vertex_elements_state(struct pipe_context *pipe, void *velems)976{977struct i915_context *i915 = i915_context(pipe);978struct i915_velems_state *i915_velems = (struct i915_velems_state *)velems;979980if (i915->velems == velems)981return;982983i915->velems = velems;984985/* pass-through to draw module */986if (i915_velems) {987draw_set_vertex_elements(i915->draw, i915_velems->count,988i915_velems->velem);989}990}991992static void993i915_delete_vertex_elements_state(struct pipe_context *pipe, void *velems)994{995FREE(velems);996}997998static void999i915_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)1000{1001}10021003void1004i915_init_state_functions(struct i915_context *i915)1005{1006i915->base.create_blend_state = i915_create_blend_state;1007i915->base.bind_blend_state = i915_bind_blend_state;1008i915->base.delete_blend_state = i915_delete_blend_state;10091010i915->base.create_sampler_state = i915_create_sampler_state;1011i915->base.bind_sampler_states = i915_bind_sampler_states;1012i915->base.delete_sampler_state = i915_delete_sampler_state;10131014i915->base.create_depth_stencil_alpha_state =1015i915_create_depth_stencil_state;1016i915->base.bind_depth_stencil_alpha_state = i915_bind_depth_stencil_state;1017i915->base.delete_depth_stencil_alpha_state =1018i915_delete_depth_stencil_state;10191020i915->base.create_rasterizer_state = i915_create_rasterizer_state;1021i915->base.bind_rasterizer_state = i915_bind_rasterizer_state;1022i915->base.delete_rasterizer_state = i915_delete_rasterizer_state;1023i915->base.create_fs_state = i915_create_fs_state;1024i915->base.bind_fs_state = i915_bind_fs_state;1025i915->base.delete_fs_state = i915_delete_fs_state;1026i915->base.create_vs_state = i915_create_vs_state;1027i915->base.bind_vs_state = i915_bind_vs_state;1028i915->base.delete_vs_state = i915_delete_vs_state;1029i915->base.create_vertex_elements_state = i915_create_vertex_elements_state;1030i915->base.bind_vertex_elements_state = i915_bind_vertex_elements_state;1031i915->base.delete_vertex_elements_state = i915_delete_vertex_elements_state;10321033i915->base.set_blend_color = i915_set_blend_color;1034i915->base.set_stencil_ref = i915_set_stencil_ref;1035i915->base.set_clip_state = i915_set_clip_state;1036i915->base.set_sample_mask = i915_set_sample_mask;1037i915->base.set_constant_buffer = i915_set_constant_buffer;1038i915->base.set_framebuffer_state = i915_set_framebuffer_state;10391040i915->base.set_polygon_stipple = i915_set_polygon_stipple;1041i915->base.set_scissor_states = i915_set_scissor_states;1042i915->base.set_sampler_views = i915_set_sampler_views;1043i915->base.create_sampler_view = i915_create_sampler_view;1044i915->base.sampler_view_destroy = i915_sampler_view_destroy;1045i915->base.set_viewport_states = i915_set_viewport_states;1046i915->base.set_vertex_buffers = i915_set_vertex_buffers;1047}104810491050