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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/iris/iris_binder.c
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/*
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* Copyright © 2018 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/**
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* @file iris_binder.c
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*
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* Shader programs refer to most resources via integer handles. These are
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* indexes (BTIs) into a "Binding Table", which is simply a list of pointers
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* to SURFACE_STATE entries. Each shader stage has its own binding table,
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* set by the 3DSTATE_BINDING_TABLE_POINTERS_* commands. We stream out
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* binding tables dynamically, storing them in special BOs we call "binders."
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*
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* Unfortunately, the hardware designers made 3DSTATE_BINDING_TABLE_POINTERS
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* only accept a 16-bit pointer. This means that all binding tables have to
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* live within the 64kB range starting at Surface State Base Address. (The
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* actual SURFACE_STATE entries can live anywhere in the 4GB zone, as the
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* binding table entries are full 32-bit pointers.)
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*
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* To handle this, we split a 4GB region of VMA into two memory zones.
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* IRIS_MEMZONE_BINDER is a small region at the bottom able to hold a few
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* binder BOs. IRIS_MEMZONE_SURFACE contains the rest of the 4GB, and is
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* always at a higher address than the binders. This allows us to program
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* Surface State Base Address to the binder BO's address, and offset the
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* values in the binding table to account for the base not starting at the
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* beginning of the 4GB region.
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*
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* This does mean that we have to emit STATE_BASE_ADDRESS and stall when
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* we run out of space in the binder, which hopefully won't happen too often.
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*/
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#include <stdlib.h>
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#include "util/u_math.h"
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#include "iris_binder.h"
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#include "iris_bufmgr.h"
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#include "iris_context.h"
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#define BTP_ALIGNMENT 32
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/* Avoid using offset 0, tools consider it NULL */
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#define INIT_INSERT_POINT BTP_ALIGNMENT
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static bool
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binder_has_space(struct iris_binder *binder, unsigned size)
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{
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return binder->insert_point + size <= IRIS_BINDER_SIZE;
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}
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static void
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binder_realloc(struct iris_context *ice)
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{
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struct iris_screen *screen = (void *) ice->ctx.screen;
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struct iris_bufmgr *bufmgr = screen->bufmgr;
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struct iris_binder *binder = &ice->state.binder;
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uint64_t next_address = IRIS_MEMZONE_BINDER_START;
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if (binder->bo) {
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/* Place the new binder just after the old binder, unless we've hit the
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* end of the memory zone...then wrap around to the start again.
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*/
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next_address = binder->bo->gtt_offset + IRIS_BINDER_SIZE;
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if (next_address >= IRIS_MEMZONE_BINDLESS_START)
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next_address = IRIS_MEMZONE_BINDER_START;
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iris_bo_unreference(binder->bo);
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}
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binder->bo = iris_bo_alloc(bufmgr, "binder", IRIS_BINDER_SIZE, 1,
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IRIS_MEMZONE_BINDER, 0);
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binder->bo->gtt_offset = next_address;
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binder->map = iris_bo_map(NULL, binder->bo, MAP_WRITE);
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binder->insert_point = INIT_INSERT_POINT;
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/* Allocating a new binder requires changing Surface State Base Address,
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* which also invalidates all our previous binding tables - each entry
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* in those tables is an offset from the old base.
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*
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* We do this here so that iris_binder_reserve_3d correctly gets a new
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* larger total_size when making the updated reservation.
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*/
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ice->state.dirty |= IRIS_DIRTY_RENDER_BUFFER;
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ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
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}
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static uint32_t
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binder_insert(struct iris_binder *binder, unsigned size)
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{
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uint32_t offset = binder->insert_point;
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binder->insert_point = align(binder->insert_point + size, BTP_ALIGNMENT);
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return offset;
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}
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/**
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* Reserve a block of space in the binder, given the raw size in bytes.
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*/
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uint32_t
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iris_binder_reserve(struct iris_context *ice,
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unsigned size)
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{
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struct iris_binder *binder = &ice->state.binder;
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if (!binder_has_space(binder, size))
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binder_realloc(ice);
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assert(size > 0);
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return binder_insert(binder, size);
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}
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/**
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* Reserve and record binder space for 3D pipeline shader stages.
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*
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* Note that you must actually populate the new binding tables after
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* calling this command - the new area is uninitialized.
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*/
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void
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iris_binder_reserve_3d(struct iris_context *ice)
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{
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struct iris_compiled_shader **shaders = ice->shaders.prog;
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struct iris_binder *binder = &ice->state.binder;
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unsigned sizes[MESA_SHADER_STAGES] = {};
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unsigned total_size;
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/* If nothing is dirty, skip all this. */
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if (!(ice->state.dirty & IRIS_DIRTY_RENDER_BUFFER) &&
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!(ice->state.stage_dirty & IRIS_ALL_STAGE_DIRTY_BINDINGS_FOR_RENDER))
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return;
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/* Get the binding table sizes for each stage */
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for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
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if (!shaders[stage])
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continue;
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/* Round up the size so our next table has an aligned starting offset */
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sizes[stage] = align(shaders[stage]->bt.size_bytes, BTP_ALIGNMENT);
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}
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/* Make space for the new binding tables...this may take two tries. */
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while (true) {
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total_size = 0;
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for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
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if (ice->state.stage_dirty & (IRIS_STAGE_DIRTY_BINDINGS_VS << stage))
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total_size += sizes[stage];
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}
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assert(total_size < IRIS_BINDER_SIZE);
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if (total_size == 0)
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return;
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if (binder_has_space(binder, total_size))
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break;
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/* It didn't fit. Allocate a new buffer and try again. Note that
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* this will flag all bindings dirty, which may increase total_size
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* on the next iteration.
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*/
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binder_realloc(ice);
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}
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/* Assign space and record the new binding table offsets. */
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uint32_t offset = binder_insert(binder, total_size);
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for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
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if (ice->state.stage_dirty & (IRIS_STAGE_DIRTY_BINDINGS_VS << stage)) {
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binder->bt_offset[stage] = sizes[stage] > 0 ? offset : 0;
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iris_record_state_size(ice->state.sizes,
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binder->bo->gtt_offset + offset, sizes[stage]);
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offset += sizes[stage];
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}
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}
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}
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void
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iris_binder_reserve_compute(struct iris_context *ice)
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{
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if (!(ice->state.stage_dirty & IRIS_STAGE_DIRTY_BINDINGS_CS))
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return;
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struct iris_binder *binder = &ice->state.binder;
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struct iris_compiled_shader *shader =
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ice->shaders.prog[MESA_SHADER_COMPUTE];
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unsigned size = shader->bt.size_bytes;
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if (size == 0)
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return;
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binder->bt_offset[MESA_SHADER_COMPUTE] = iris_binder_reserve(ice, size);
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}
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void
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iris_init_binder(struct iris_context *ice)
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{
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memset(&ice->state.binder, 0, sizeof(struct iris_binder));
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binder_realloc(ice);
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}
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void
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iris_destroy_binder(struct iris_binder *binder)
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{
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iris_bo_unreference(binder->bo);
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}
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