Path: blob/21.2-virgl/src/gallium/drivers/iris/iris_formats.c
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/*1* Copyright © 2017 Intel Corporation2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included11* in all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS14* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER17* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING18* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER19* DEALINGS IN THE SOFTWARE.20*/2122/**23* @file iris_formats.c24*25* Converts Gallium formats (PIPE_FORMAT_*) to hardware ones (ISL_FORMAT_*).26* Provides information about which formats support what features.27*/2829#include "util/bitscan.h"30#include "util/macros.h"31#include "util/format/u_format.h"3233#include "iris_resource.h"34#include "iris_screen.h"3536struct iris_format_info37iris_format_for_usage(const struct intel_device_info *devinfo,38enum pipe_format pformat,39isl_surf_usage_flags_t usage)40{41enum isl_format format = isl_format_for_pipe_format(pformat);42struct isl_swizzle swizzle = ISL_SWIZZLE_IDENTITY;4344if (format == ISL_FORMAT_UNSUPPORTED)45return (struct iris_format_info) { .fmt = format, .swizzle = swizzle };4647const struct isl_format_layout *fmtl = isl_format_get_layout(format);4849if (!util_format_is_srgb(pformat)) {50if (util_format_is_intensity(pformat)) {51swizzle = ISL_SWIZZLE(RED, RED, RED, RED);52} else if (util_format_is_luminance(pformat)) {53swizzle = ISL_SWIZZLE(RED, RED, RED, ONE);54} else if (util_format_is_luminance_alpha(pformat)) {55swizzle = ISL_SWIZZLE(RED, RED, RED, GREEN);56} else if (util_format_is_alpha(pformat)) {57swizzle = ISL_SWIZZLE(ZERO, ZERO, ZERO, RED);58}59}6061/* When faking RGBX pipe formats with RGBA ISL formats, override alpha. */62if (!util_format_has_alpha(pformat) && fmtl->channels.a.type != ISL_VOID) {63swizzle = ISL_SWIZZLE(RED, GREEN, BLUE, ONE);64}6566if ((usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&67pformat == PIPE_FORMAT_A8_UNORM) {68/* Most of the hardware A/LA formats are not renderable, except69* for A8_UNORM. SURFACE_STATE's shader channel select fields70* cannot be used to swap RGB and A channels when rendering (as71* it could impact alpha blending), so we have to use the actual72* A8_UNORM format when rendering.73*/74format = ISL_FORMAT_A8_UNORM;75swizzle = ISL_SWIZZLE_IDENTITY;76}7778/* We choose RGBA over RGBX for rendering the hardware doesn't support79* rendering to RGBX. However, when this internal override is used on Gfx9+,80* fast clears don't work correctly.81*82* i965 fixes this by pretending to not support RGBX formats, and the higher83* layers of Mesa pick the RGBA format instead. Gallium doesn't work that84* way, and might choose a different format, like BGRX instead of RGBX,85* which will also cause problems when sampling from a surface fast cleared86* as RGBX. So we always choose RGBA instead of RGBX explicitly87* here.88*/89if (isl_format_is_rgbx(format) &&90!isl_format_supports_rendering(devinfo, format)) {91format = isl_format_rgbx_to_rgba(format);92swizzle = ISL_SWIZZLE(RED, GREEN, BLUE, ONE);93}9495return (struct iris_format_info) { .fmt = format, .swizzle = swizzle };96}9798/**99* The pscreen->is_format_supported() driver hook.100*101* Returns true if the given format is supported for the given usage102* (PIPE_BIND_*) and sample count.103*/104bool105iris_is_format_supported(struct pipe_screen *pscreen,106enum pipe_format pformat,107enum pipe_texture_target target,108unsigned sample_count,109unsigned storage_sample_count,110unsigned usage)111{112struct iris_screen *screen = (struct iris_screen *) pscreen;113const struct intel_device_info *devinfo = &screen->devinfo;114uint32_t max_samples = devinfo->ver == 8 ? 8 : 16;115116if (sample_count > max_samples ||117!util_is_power_of_two_or_zero(sample_count))118return false;119120if (pformat == PIPE_FORMAT_NONE)121return true;122123enum isl_format format = isl_format_for_pipe_format(pformat);124125if (format == ISL_FORMAT_UNSUPPORTED)126return false;127128const struct isl_format_layout *fmtl = isl_format_get_layout(format);129const bool is_integer = isl_format_has_int_channel(format);130bool supported = true;131132if (sample_count > 1)133supported &= isl_format_supports_multisampling(devinfo, format);134135if (usage & PIPE_BIND_DEPTH_STENCIL) {136supported &= format == ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS ||137format == ISL_FORMAT_R32_FLOAT ||138format == ISL_FORMAT_R24_UNORM_X8_TYPELESS ||139format == ISL_FORMAT_R16_UNORM ||140format == ISL_FORMAT_R8_UINT;141}142143if (usage & PIPE_BIND_RENDER_TARGET) {144/* Alpha and luminance-alpha formats other than A8_UNORM are not145* renderable. For texturing, we can use R or RG formats with146* shader channel selects (SCS) to swizzle the data into the correct147* channels. But for render targets, the hardware prohibits using148* SCS to move shader outputs between the RGB and A channels, as it149* would alter what data is used for alpha blending.150*151* For BLORP, we can apply the swizzle in the shader. But for152* general rendering, this would mean recompiling the shader, which153* we'd like to avoid doing. So we mark these formats non-renderable.154*155* We do support A8_UNORM as it's required and is renderable.156*/157if (pformat != PIPE_FORMAT_A8_UNORM &&158(util_format_is_alpha(pformat) ||159util_format_is_luminance_alpha(pformat)))160supported = false;161162enum isl_format rt_format = format;163164if (isl_format_is_rgbx(format) &&165!isl_format_supports_rendering(devinfo, format))166rt_format = isl_format_rgbx_to_rgba(format);167168supported &= isl_format_supports_rendering(devinfo, rt_format);169170if (!is_integer)171supported &= isl_format_supports_alpha_blending(devinfo, rt_format);172}173174if (usage & PIPE_BIND_SHADER_IMAGE) {175/* Dataport doesn't support compression, and we can't resolve an MCS176* compressed surface. (Buffer images may have sample count of 0.)177*/178supported &= sample_count == 0;179180supported &= isl_format_supports_typed_writes(devinfo, format);181supported &= isl_has_matching_typed_storage_image_format(devinfo, format);182}183184if (usage & PIPE_BIND_SAMPLER_VIEW) {185supported &= isl_format_supports_sampling(devinfo, format);186if (!is_integer)187supported &= isl_format_supports_filtering(devinfo, format);188189/* Don't advertise 3-component RGB formats for non-buffer textures.190* This ensures that they are renderable from an API perspective since191* gallium frontends will fall back to RGBA or RGBX, which are192* renderable. We want to render internally for copies and blits,193* even if the application doesn't.194*195* Buffer textures don't need to be renderable, so we support real RGB.196* This is useful for PBO upload, and 32-bit RGB support is mandatory.197*/198if (target != PIPE_BUFFER)199supported &= fmtl->bpb != 24 && fmtl->bpb != 48 && fmtl->bpb != 96;200}201202if (usage & PIPE_BIND_VERTEX_BUFFER)203supported &= isl_format_supports_vertex_fetch(devinfo, format);204205if (usage & PIPE_BIND_INDEX_BUFFER) {206supported &= format == ISL_FORMAT_R8_UINT ||207format == ISL_FORMAT_R16_UINT ||208format == ISL_FORMAT_R32_UINT;209}210211/* TODO: Support ASTC 5x5 on Gfx9 properly. This means implementing212* a complex sampler workaround (see i965's gfx9_apply_astc5x5_wa_flush).213* Without it, st/mesa will emulate ASTC 5x5 via uncompressed textures.214*/215if (devinfo->ver == 9 && (format == ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 ||216format == ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB))217return false;218219return supported;220}221222223224