Path: blob/21.2-virgl/src/gallium/drivers/iris/iris_genx_macros.h
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/*1* Copyright © 2019 Intel Corporation2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice shall be included11* in all copies or substantial portions of the Software.12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS14* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER17* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING18* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER19* DEALINGS IN THE SOFTWARE.20*/2122/**23* Macro and function definitions needed in order to use genxml.24*25* This should only be included in sources compiled per-generation.26*/2728#include "iris_batch.h"2930#define __gen_address_type struct iris_address31#define __gen_user_data struct iris_batch32#define __gen_combine_address iris_combine_address3334static inline void *35__gen_get_batch_dwords(struct iris_batch *batch, unsigned dwords)36{37return iris_get_command_space(batch, dwords * sizeof(uint32_t));38}3940static inline struct iris_address41__gen_address_offset(struct iris_address addr, uint64_t offset)42{43addr.offset += offset;44return addr;45}4647static uint64_t48__gen_combine_address(struct iris_batch *batch, void *location,49struct iris_address addr, uint32_t delta)50{51uint64_t result = addr.offset + delta;5253if (addr.bo) {54iris_use_pinned_bo(batch, addr.bo,55!iris_domain_is_read_only(addr.access), addr.access);56/* Assume this is a general address, not relative to a base. */57result += addr.bo->gtt_offset;58}5960return result;61}6263static inline struct iris_address64__gen_get_batch_address(struct iris_batch *batch, void *location)65{66unreachable("Not supported by iris");67}6869#define __gen_address_type struct iris_address70#define __gen_user_data struct iris_batch7172#define __genxml_cmd_length(cmd) cmd ## _length73#define __genxml_cmd_length_bias(cmd) cmd ## _length_bias74#define __genxml_cmd_header(cmd) cmd ## _header75#define __genxml_cmd_pack(cmd) cmd ## _pack76#define __genxml_reg_num(cmd) cmd ## _num7778#include "genxml/genX_pack.h"79#include "genxml/gen_macros.h"80#include "genxml/genX_bits.h"8182/* CS_GPR(15) is reserved for combining conditional rendering predicates83* with GL_ARB_indirect_parameters draw number predicates.84*/85#define MI_BUILDER_NUM_ALLOC_GPRS 1586#include "common/mi_builder.h"8788#define _iris_pack_command(batch, cmd, dst, name) \89for (struct cmd name = { __genxml_cmd_header(cmd) }, \90*_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \91({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \92_dst = NULL; \93}))9495#define iris_pack_command(cmd, dst, name) \96_iris_pack_command(NULL, cmd, dst, name)9798#define _iris_pack_state(batch, cmd, dst, name) \99for (struct cmd name = {}, \100*_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \101__genxml_cmd_pack(cmd)(batch, (void *)_dst, &name), \102_dst = NULL)103104#define iris_pack_state(cmd, dst, name) \105_iris_pack_state(NULL, cmd, dst, name)106107#define iris_emit_cmd(batch, cmd, name) \108_iris_pack_command(batch, cmd, __gen_get_batch_dwords(batch, __genxml_cmd_length(cmd)), name)109110#define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \111do { \112uint32_t *dw = __gen_get_batch_dwords(batch, num_dwords); \113for (uint32_t i = 0; i < num_dwords; i++) \114dw[i] = (dwords0)[i] | (dwords1)[i]; \115VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \116} while (0)117118#define iris_emit_reg(batch, reg, name) \119for (struct reg name = {}, *_cont = (struct reg *)1; _cont != NULL; \120({ \121uint32_t _dw[__genxml_cmd_length(reg)]; \122__genxml_cmd_pack(reg)(NULL, _dw, &name); \123for (unsigned i = 0; i < __genxml_cmd_length(reg); i++) { \124iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { \125lri.RegisterOffset = __genxml_reg_num(reg); \126lri.DataDWord = _dw[i]; \127} \128} \129_cont = NULL; \130}))131132133/**134* iris_address constructor helpers:135*136* When using these to construct a CSO, pass NULL for \p bo, and manually137* pin the BO later. Otherwise, genxml's address handling will add the138* BO to the current batch's validation list at CSO creation time, rather139* than at draw time as desired.140*/141142UNUSED static struct iris_address143ro_bo(struct iris_bo *bo, uint64_t offset)144{145return (struct iris_address) { .bo = bo, .offset = offset,146.access = IRIS_DOMAIN_OTHER_READ };147}148149UNUSED static struct iris_address150rw_bo(struct iris_bo *bo, uint64_t offset, enum iris_domain access)151{152return (struct iris_address) { .bo = bo, .offset = offset,153.access = access };154}155156157