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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/lima/ir/gp/codegen.h
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/*
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* Copyright (c) 2017 Lima Project
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* Copyright (c) 2013 Ben Brewer ([email protected])
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* Copyright (c) 2013 Connor Abbott ([email protected])
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef LIMA_IR_GP_CODEGEN_H
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#define LIMA_IR_GP_CODEGEN_H
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typedef enum {
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gpir_codegen_src_attrib_x = 0,
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gpir_codegen_src_attrib_y = 1,
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gpir_codegen_src_attrib_z = 2,
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gpir_codegen_src_attrib_w = 3,
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gpir_codegen_src_register_x = 4,
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gpir_codegen_src_register_y = 5,
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gpir_codegen_src_register_z = 6,
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gpir_codegen_src_register_w = 7,
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gpir_codegen_src_unknown_0 = 8,
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gpir_codegen_src_unknown_1 = 9,
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gpir_codegen_src_unknown_2 = 10,
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gpir_codegen_src_unknown_3 = 11,
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gpir_codegen_src_load_x = 12,
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gpir_codegen_src_load_y = 13,
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gpir_codegen_src_load_z = 14,
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gpir_codegen_src_load_w = 15,
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gpir_codegen_src_p1_acc_0 = 16,
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gpir_codegen_src_p1_acc_1 = 17,
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gpir_codegen_src_p1_mul_0 = 18,
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gpir_codegen_src_p1_mul_1 = 19,
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gpir_codegen_src_p1_pass = 20,
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gpir_codegen_src_unused = 21,
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gpir_codegen_src_ident = 22,
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gpir_codegen_src_p1_complex = 22,
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gpir_codegen_src_p2_pass = 23,
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gpir_codegen_src_p2_acc_0 = 24,
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gpir_codegen_src_p2_acc_1 = 25,
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gpir_codegen_src_p2_mul_0 = 26,
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gpir_codegen_src_p2_mul_1 = 27,
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gpir_codegen_src_p1_attrib_x = 28,
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gpir_codegen_src_p1_attrib_y = 29,
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gpir_codegen_src_p1_attrib_z = 30,
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gpir_codegen_src_p1_attrib_w = 31,
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} gpir_codegen_src;
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typedef enum {
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gpir_codegen_load_off_ld_addr_0 = 1,
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gpir_codegen_load_off_ld_addr_1 = 2,
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gpir_codegen_load_off_ld_addr_2 = 3,
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gpir_codegen_load_off_none = 7,
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} gpir_codegen_load_off;
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typedef enum {
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gpir_codegen_store_src_acc_0 = 0,
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gpir_codegen_store_src_acc_1 = 1,
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gpir_codegen_store_src_mul_0 = 2,
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gpir_codegen_store_src_mul_1 = 3,
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gpir_codegen_store_src_pass = 4,
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gpir_codegen_store_src_unknown = 5,
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gpir_codegen_store_src_complex = 6,
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gpir_codegen_store_src_none = 7,
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} gpir_codegen_store_src;
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typedef enum {
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gpir_codegen_acc_op_add = 0,
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gpir_codegen_acc_op_floor = 1,
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gpir_codegen_acc_op_sign = 2,
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gpir_codegen_acc_op_ge = 4,
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gpir_codegen_acc_op_lt = 5,
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gpir_codegen_acc_op_min = 6,
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gpir_codegen_acc_op_max = 7,
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} gpir_codegen_acc_op;
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typedef enum {
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gpir_codegen_complex_op_nop = 0,
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gpir_codegen_complex_op_exp2 = 2,
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gpir_codegen_complex_op_log2 = 3,
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gpir_codegen_complex_op_rsqrt = 4,
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gpir_codegen_complex_op_rcp = 5,
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gpir_codegen_complex_op_pass = 9,
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gpir_codegen_complex_op_temp_store_addr = 12,
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gpir_codegen_complex_op_temp_load_addr_0 = 13,
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gpir_codegen_complex_op_temp_load_addr_1 = 14,
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gpir_codegen_complex_op_temp_load_addr_2 = 15,
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} gpir_codegen_complex_op;
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typedef enum {
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gpir_codegen_mul_op_mul = 0,
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gpir_codegen_mul_op_complex1 = 1,
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gpir_codegen_mul_op_complex2 = 3,
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gpir_codegen_mul_op_select = 4,
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} gpir_codegen_mul_op;
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typedef enum {
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gpir_codegen_pass_op_pass = 2,
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gpir_codegen_pass_op_preexp2 = 4,
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gpir_codegen_pass_op_postlog2 = 5,
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gpir_codegen_pass_op_clamp = 6,
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} gpir_codegen_pass_op;
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typedef struct __attribute__((__packed__)) {
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gpir_codegen_src mul0_src0 : 5;
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gpir_codegen_src mul0_src1 : 5;
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gpir_codegen_src mul1_src0 : 5;
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gpir_codegen_src mul1_src1 : 5;
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bool mul0_neg : 1;
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bool mul1_neg : 1;
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gpir_codegen_src acc0_src0 : 5;
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gpir_codegen_src acc0_src1 : 5;
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gpir_codegen_src acc1_src0 : 5;
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gpir_codegen_src acc1_src1 : 5;
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bool acc0_src0_neg : 1;
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bool acc0_src1_neg : 1;
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bool acc1_src0_neg : 1;
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bool acc1_src1_neg : 1;
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unsigned load_addr : 9;
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gpir_codegen_load_off load_offset : 3;
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unsigned register0_addr : 4;
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bool register0_attribute : 1;
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unsigned register1_addr : 4;
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bool store0_temporary : 1;
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bool store1_temporary : 1;
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bool branch : 1;
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bool branch_target_lo : 1;
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gpir_codegen_store_src store0_src_x : 3;
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gpir_codegen_store_src store0_src_y : 3;
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gpir_codegen_store_src store1_src_z : 3;
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gpir_codegen_store_src store1_src_w : 3;
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gpir_codegen_acc_op acc_op : 3;
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gpir_codegen_complex_op complex_op : 4;
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unsigned store0_addr : 4;
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bool store0_varying : 1;
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unsigned store1_addr : 4;
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bool store1_varying : 1;
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gpir_codegen_mul_op mul_op : 3;
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gpir_codegen_pass_op pass_op : 3;
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gpir_codegen_src complex_src : 5;
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gpir_codegen_src pass_src : 5;
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unsigned unknown_1 : 4; /* 12: tmp_st, 13: branch */
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unsigned branch_target : 8;
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} gpir_codegen_instr;
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void gpir_disassemble_program(gpir_codegen_instr *code, unsigned num_instr);
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#endif
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