Path: blob/21.2-virgl/src/gallium/drivers/lima/ir/pp/codegen.h
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/*1* Copyright (c) 2017 Lima Project2* Copyright (c) 2013 Ben Brewer ([email protected])3* Copyright (c) 2013 Connor Abbott ([email protected])4*5* Permission is hereby granted, free of charge, to any person obtaining a6* copy of this software and associated documentation files (the "Software"),7* to deal in the Software without restriction, including without limitation8* the rights to use, copy, modify, merge, publish, distribute, sub license,9* and/or sell copies of the Software, and to permit persons to whom the10* Software is furnished to do so, subject to the following conditions:11*12* The above copyright notice and this permission notice (including the13* next paragraph) shall be included in all copies or substantial portions14* of the Software.15*16* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL19* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER20* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING21* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER22* DEALINGS IN THE SOFTWARE.23*24*/2526#ifndef LIMA_IR_PP_CODEGEN_H27#define LIMA_IR_PP_CODEGEN_H2829#include <stdint.h>30#include <stdbool.h>3132/* Control */3334typedef union __attribute__((__packed__)) {35struct __attribute__((__packed__)) {36unsigned count : 5;37bool stop : 1;38bool sync : 1;39unsigned fields : 12;40unsigned next_count : 6;41bool prefetch : 1;42unsigned unknown : 6;43};44uint32_t mask;45} ppir_codegen_ctrl;4647typedef enum {48ppir_codegen_field_shift_varying = 0,49ppir_codegen_field_shift_sampler = 1,50ppir_codegen_field_shift_uniform = 2,51ppir_codegen_field_shift_vec4_mul = 3,52ppir_codegen_field_shift_float_mul = 4,53ppir_codegen_field_shift_vec4_acc = 5,54ppir_codegen_field_shift_float_acc = 6,55ppir_codegen_field_shift_combine = 7,56ppir_codegen_field_shift_temp_write = 8,57ppir_codegen_field_shift_branch = 9,58ppir_codegen_field_shift_vec4_const_0 = 10,59ppir_codegen_field_shift_vec4_const_1 = 11,60ppir_codegen_field_shift_count = 12,61} ppir_codegen_field_shift;6263/* Data Inputs */6465typedef enum {66ppir_codegen_vec4_reg_frag_color = 0,67ppir_codegen_vec4_reg_constant0 = 12,68ppir_codegen_vec4_reg_constant1 = 13,69ppir_codegen_vec4_reg_texture = 14,70ppir_codegen_vec4_reg_uniform = 15,71ppir_codegen_vec4_reg_discard = 15,72} ppir_codegen_vec4_reg;7374typedef union __attribute__((__packed__)) {75struct __attribute__((__packed__)) {76unsigned perspective : 2;77unsigned source_type : 2;78unsigned unknown_0 : 1; /* = 0 */79unsigned alignment : 2;80unsigned unknown_1 : 3; /* = 00 0 */81unsigned offset_vector : 4;82unsigned unknown_2 : 2; /* = 00 */83unsigned offset_scalar : 2;84unsigned index : 6;85ppir_codegen_vec4_reg dest : 4;86unsigned mask : 4;87unsigned unknown_3 : 2; /* = 00 */88} imm;89struct __attribute__((__packed__)) {90unsigned perspective : 2;91unsigned source_type : 2; /* = 01 */92unsigned unknown_0 : 2; /* = 00 */93bool normalize : 1;94unsigned unknown_1 : 3;95ppir_codegen_vec4_reg source : 4;96bool negate : 1;97bool absolute : 1;98unsigned swizzle : 8;99ppir_codegen_vec4_reg dest : 4;100unsigned mask : 4;101unsigned unknown_2 : 2; /* = 00 */102} reg;103} ppir_codegen_field_varying;104105typedef enum {106ppir_codegen_sampler_type_2d = 0x00,107ppir_codegen_sampler_type_cube = 0x1F,108} ppir_codegen_sampler_type;109110typedef struct __attribute__((__packed__)) {111unsigned lod_bias : 6;112unsigned index_offset : 6;113unsigned unknown_0 : 5; /* = 00000 */114bool explicit_lod : 1;115bool lod_bias_en : 1;116unsigned unknown_1 : 5; /* = 00000 */117ppir_codegen_sampler_type type : 5;118bool offset_en : 1;119unsigned index : 12;120unsigned unknown_2 : 20; /* = 0011 1001 0000 0000 0001 */121} ppir_codegen_field_sampler;122123typedef enum {124ppir_codegen_uniform_src_uniform = 0,125ppir_codegen_uniform_src_temporary = 3,126} ppir_codegen_uniform_src;127128typedef struct __attribute__((__packed__)) {129ppir_codegen_uniform_src source : 2;130unsigned unknown_0 : 8; /* = 00 0000 00 */131unsigned alignment : 2; /* 00: float, 01: vec2, 10: vec4 */132unsigned unknown_1 : 6; /* = 00 0000 */133unsigned offset_reg : 6;134bool offset_en : 1;135unsigned index : 16;136} ppir_codegen_field_uniform;137138/* Vector Pipe */139140typedef enum {141ppir_codegen_vec4_mul_op_not = 0x08, /* Logical Not */142ppir_codegen_vec4_mul_op_and = 0x09, /* Logical AND */143ppir_codegen_vec4_mul_op_or = 0x0A, /* Logical OR */144ppir_codegen_vec4_mul_op_xor = 0x0B, /* Logical XOR */145ppir_codegen_vec4_mul_op_ne = 0x0C, /* Not Equal */146ppir_codegen_vec4_mul_op_gt = 0x0D, /* Great Than */147ppir_codegen_vec4_mul_op_ge = 0x0E, /* Great than or Equal */148ppir_codegen_vec4_mul_op_eq = 0x0F, /* Equal */149ppir_codegen_vec4_mul_op_min = 0x10, /* Minimum */150ppir_codegen_vec4_mul_op_max = 0x11, /* Maximum */151ppir_codegen_vec4_mul_op_mov = 0x1F, /* Passthrough, result = arg1 */152} ppir_codegen_vec4_mul_op;153154typedef enum {155ppir_codegen_outmod_none = 0,156ppir_codegen_outmod_clamp_fraction = 1,157ppir_codegen_outmod_clamp_positive = 2,158ppir_codegen_outmod_round = 3,159} ppir_codegen_outmod;160161typedef struct __attribute__((__packed__)) {162ppir_codegen_vec4_reg arg0_source : 4;163unsigned arg0_swizzle : 8;164bool arg0_absolute : 1;165bool arg0_negate : 1;166ppir_codegen_vec4_reg arg1_source : 4;167unsigned arg1_swizzle : 8;168bool arg1_absolute : 1;169bool arg1_negate : 1;170unsigned dest : 4;171unsigned mask : 4;172ppir_codegen_outmod dest_modifier : 2;173ppir_codegen_vec4_mul_op op : 5;174} ppir_codegen_field_vec4_mul;175176typedef enum {177ppir_codegen_vec4_acc_op_add = 0x00,178ppir_codegen_vec4_acc_op_fract = 0x04, /* Fract? */179ppir_codegen_vec4_acc_op_ne = 0x08, /* Not Equal */180ppir_codegen_vec4_acc_op_gt = 0x09, /* Great-Than */181ppir_codegen_vec4_acc_op_ge = 0x0A, /* Great-than or Equal */182ppir_codegen_vec4_acc_op_eq = 0x0B, /* Equal */183ppir_codegen_vec4_acc_op_floor = 0x0C,184ppir_codegen_vec4_acc_op_ceil = 0x0D,185ppir_codegen_vec4_acc_op_min = 0x0E,186ppir_codegen_vec4_acc_op_max = 0x0F,187ppir_codegen_vec4_acc_op_sum3 = 0x10, /* dest.xyzw = (arg0.x + arg0.y + arg0.z) */188ppir_codegen_vec4_acc_op_sum4 = 0x11, /* dest.xyzw = (arg0.x + arg0.y + arg0.z + arg0.w) */189ppir_codegen_vec4_acc_op_dFdx = 0x14,190ppir_codegen_vec4_acc_op_dFdy = 0x15,191ppir_codegen_vec4_acc_op_sel = 0x17, /* result = (^fmul ? arg0 : arg1) */192ppir_codegen_vec4_acc_op_mov = 0x1F, /* Passthrough, result = arg0 */193} ppir_codegen_vec4_acc_op;194195typedef struct __attribute__((__packed__)) {196ppir_codegen_vec4_reg arg0_source : 4;197unsigned arg0_swizzle : 8;198bool arg0_absolute : 1;199bool arg0_negate : 1;200ppir_codegen_vec4_reg arg1_source : 4;201unsigned arg1_swizzle : 8;202bool arg1_absolute : 1;203bool arg1_negate : 1;204unsigned dest : 4;205unsigned mask : 4;206ppir_codegen_outmod dest_modifier : 2;207ppir_codegen_vec4_acc_op op : 5;208bool mul_in : 1; /* whether to get arg0 from multiply unit below */209} ppir_codegen_field_vec4_acc;210211/* Float (Scalar) Pipe */212213typedef enum {214ppir_codegen_float_mul_op_not = 0x08, /* Logical Not */215ppir_codegen_float_mul_op_and = 0x09, /* Logical AND */216ppir_codegen_float_mul_op_or = 0x0A, /* Logical OR */217ppir_codegen_float_mul_op_xor = 0x0B, /* Logical XOR */218ppir_codegen_float_mul_op_ne = 0x0C, /* Not Equal */219ppir_codegen_float_mul_op_gt = 0x0D, /* Great Than */220ppir_codegen_float_mul_op_ge = 0x0E, /* great than or Equal */221ppir_codegen_float_mul_op_eq = 0x0F, /* Equal */222ppir_codegen_float_mul_op_min = 0x10, /* Minimum */223ppir_codegen_float_mul_op_max = 0x11, /* Maximum */224ppir_codegen_float_mul_op_mov = 0x1F, /* Passthrough, result = arg1 */225} ppir_codegen_float_mul_op;226227typedef struct __attribute__((__packed__)) {228unsigned arg0_source : 6;229bool arg0_absolute : 1;230bool arg0_negate : 1;231unsigned arg1_source : 6;232bool arg1_absolute : 1;233bool arg1_negate : 1;234unsigned dest : 6;235bool output_en : 1; /* Set to 0 when outputting directly to float_acc below. */236ppir_codegen_outmod dest_modifier : 2;237ppir_codegen_float_mul_op op : 5;238} ppir_codegen_field_float_mul;239240typedef enum {241ppir_codegen_float_acc_op_add = 0x00,242ppir_codegen_float_acc_op_fract = 0x04,243ppir_codegen_float_acc_op_ne = 0x08, /* Not Equal */244ppir_codegen_float_acc_op_gt = 0x09, /* Great-Than */245ppir_codegen_float_acc_op_ge = 0x0A, /* Great-than or Equal */246ppir_codegen_float_acc_op_eq = 0x0B, /* Equal */247ppir_codegen_float_acc_op_floor = 0x0C,248ppir_codegen_float_acc_op_ceil = 0x0D,249ppir_codegen_float_acc_op_min = 0x0E,250ppir_codegen_float_acc_op_max = 0x0F,251ppir_codegen_float_acc_op_dFdx = 0x14,252ppir_codegen_float_acc_op_dFdy = 0x15,253ppir_codegen_float_acc_op_sel = 0x17, /* result = (^fmul ? arg0 : arg1) */254ppir_codegen_float_acc_op_mov = 0x1F, /* Passthrough, result = arg1 */255} ppir_codegen_float_acc_op;256257typedef struct __attribute__((__packed__)) {258unsigned arg0_source : 6;259bool arg0_absolute : 1;260bool arg0_negate : 1;261unsigned arg1_source : 6;262bool arg1_absolute : 1;263bool arg1_negate : 1;264unsigned dest : 6;265bool output_en : 1; /* Always true */266ppir_codegen_outmod dest_modifier : 2;267ppir_codegen_float_acc_op op : 5;268bool mul_in : 1; /* Get arg1 from float_mul above. */269} ppir_codegen_field_float_acc;270271/* Temporary Write / Framebuffer Read */272273typedef union __attribute__((__packed__)) {274struct __attribute__((__packed__)) {275unsigned dest : 2; /* = 11 */276unsigned unknown_0 : 2; /* = 00 */277unsigned source : 6;278unsigned alignment : 2; /* 0: float, 1:vec2, 2: vec4 */279unsigned unknown_1 : 6; /* = 00 0000 */280unsigned offset_reg : 6;281bool offset_en : 1;282unsigned index : 16;283} temp_write;284struct __attribute__((__packed__)) {285bool source : 1; /* 0 = fb_depth, 1 = fb_color */286unsigned unknown_0 : 5; /* = 00 111 */287unsigned dest : 4;288unsigned unknown_1 : 31; /* = 0 0000 ... 10 */289} fb_read;290} ppir_codegen_field_temp_write;291292/* Result combiner */293294typedef enum {295ppir_codegen_combine_scalar_op_rcp = 0, /* Reciprocal */296ppir_codegen_combine_scalar_op_mov = 1, /* No Operation */297ppir_codegen_combine_scalar_op_sqrt = 2, /* Square-Root */298ppir_codegen_combine_scalar_op_rsqrt = 3, /* Inverse Square-Root */299ppir_codegen_combine_scalar_op_exp2 = 4, /* Binary Exponent */300ppir_codegen_combine_scalar_op_log2 = 5, /* Binary Logarithm */301ppir_codegen_combine_scalar_op_sin = 6, /* Sine (Scaled LUT) */302ppir_codegen_combine_scalar_op_cos = 7, /* Cosine (Scaled LUT) */303ppir_codegen_combine_scalar_op_atan = 8, /* Arc Tangent Part 1 */304ppir_codegen_combine_scalar_op_atan2 = 9, /* Arc Tangent 2 Part 1 */305} ppir_codegen_combine_scalar_op;306307typedef union __attribute__((__packed__)) {308struct __attribute__((__packed__)) {309bool dest_vec : 1;310bool arg1_en : 1;311ppir_codegen_combine_scalar_op op : 4;312bool arg1_absolute : 1;313bool arg1_negate : 1;314unsigned arg1_src : 6;315bool arg0_absolute : 1;316bool arg0_negate : 1;317unsigned arg0_src : 6;318ppir_codegen_outmod dest_modifier : 2;319unsigned dest : 6;320} scalar;321struct __attribute__((__packed__)) {322bool dest_vec : 1;323bool arg1_en : 1;324unsigned arg1_swizzle : 8;325unsigned arg1_source : 4;326unsigned padding_0 : 8;327unsigned mask : 4;328unsigned dest : 4;329} vector;330} ppir_codegen_field_combine;331332/* Branch/Control Flow */333334#define PPIR_CODEGEN_DISCARD_WORD0 0x007F0003335#define PPIR_CODEGEN_DISCARD_WORD1 0x00000000336#define PPIR_CODEGEN_DISCARD_WORD2 0x000337338typedef union __attribute__((__packed__)) {339struct __attribute__((__packed__)) {340unsigned unknown_0 : 4; /* = 0000 */341unsigned arg1_source : 6;342unsigned arg0_source : 6;343bool cond_gt : 1;344bool cond_eq : 1;345bool cond_lt : 1;346unsigned unknown_1 : 22; /* = 0 0000 0000 0000 0000 0000 0 */347signed target : 27;348unsigned next_count : 5;349} branch;350struct __attribute__((__packed__)) {351unsigned word0 : 32;352unsigned word1 : 32;353unsigned word2 : 9;354} discard;355} ppir_codegen_field_branch;356357void ppir_disassemble_instr(uint32_t *instr, unsigned offset);358359#endif360361362