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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/lima/lima_screen.c
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1
/*
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* Copyright (c) 2017-2019 Lima Project
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21
* DEALINGS IN THE SOFTWARE.
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*
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*/
24
25
#include <string.h>
26
27
#include "util/ralloc.h"
28
#include "util/u_debug.h"
29
#include "util/u_screen.h"
30
#include "renderonly/renderonly.h"
31
32
#include "drm-uapi/drm_fourcc.h"
33
#include "drm-uapi/lima_drm.h"
34
35
#include "lima_screen.h"
36
#include "lima_context.h"
37
#include "lima_resource.h"
38
#include "lima_program.h"
39
#include "lima_bo.h"
40
#include "lima_fence.h"
41
#include "lima_format.h"
42
#include "lima_disk_cache.h"
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#include "ir/lima_ir.h"
44
45
#include "xf86drm.h"
46
47
int lima_plb_max_blk = 0;
48
int lima_plb_pp_stream_cache_size = 0;
49
50
static void
51
lima_screen_destroy(struct pipe_screen *pscreen)
52
{
53
struct lima_screen *screen = lima_screen(pscreen);
54
55
slab_destroy_parent(&screen->transfer_pool);
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57
if (screen->ro)
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screen->ro->destroy(screen->ro);
59
60
if (screen->pp_buffer)
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lima_bo_unreference(screen->pp_buffer);
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63
lima_bo_cache_fini(screen);
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lima_bo_table_fini(screen);
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disk_cache_destroy(screen->disk_cache);
66
ralloc_free(screen);
67
}
68
69
static const char *
70
lima_screen_get_name(struct pipe_screen *pscreen)
71
{
72
struct lima_screen *screen = lima_screen(pscreen);
73
74
switch (screen->gpu_type) {
75
case DRM_LIMA_PARAM_GPU_ID_MALI400:
76
return "Mali400";
77
case DRM_LIMA_PARAM_GPU_ID_MALI450:
78
return "Mali450";
79
}
80
81
return NULL;
82
}
83
84
static const char *
85
lima_screen_get_vendor(struct pipe_screen *pscreen)
86
{
87
return "lima";
88
}
89
90
static const char *
91
lima_screen_get_device_vendor(struct pipe_screen *pscreen)
92
{
93
return "ARM";
94
}
95
96
static int
97
lima_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
98
{
99
switch (param) {
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case PIPE_CAP_NPOT_TEXTURES:
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case PIPE_CAP_BLEND_EQUATION_SEPARATE:
102
case PIPE_CAP_ACCELERATED:
103
case PIPE_CAP_UMA:
104
case PIPE_CAP_NATIVE_FENCE_FD:
105
case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
106
case PIPE_CAP_TEXTURE_SWIZZLE:
107
return 1;
108
109
/* Unimplemented, but for exporting OpenGL 2.0 */
110
case PIPE_CAP_OCCLUSION_QUERY:
111
case PIPE_CAP_POINT_SPRITE:
112
return 1;
113
114
/* not clear supported */
115
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
116
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
117
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
118
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
119
return 1;
120
121
case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
122
case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
123
case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
124
return 1;
125
126
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
127
return 1;
128
129
case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
130
return 1 << (LIMA_MAX_MIP_LEVELS - 1);
131
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
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case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
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return LIMA_MAX_MIP_LEVELS;
134
135
case PIPE_CAP_VENDOR_ID:
136
return 0x13B5;
137
138
case PIPE_CAP_VIDEO_MEMORY:
139
return 0;
140
141
case PIPE_CAP_PCI_GROUP:
142
case PIPE_CAP_PCI_BUS:
143
case PIPE_CAP_PCI_DEVICE:
144
case PIPE_CAP_PCI_FUNCTION:
145
return 0;
146
147
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
148
case PIPE_CAP_SHAREABLE_SHADERS:
149
return 0;
150
151
case PIPE_CAP_ALPHA_TEST:
152
return 1;
153
154
case PIPE_CAP_FLATSHADE:
155
case PIPE_CAP_TWO_SIDED_COLOR:
156
case PIPE_CAP_CLIP_PLANES:
157
return 0;
158
159
case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
160
return 1;
161
162
default:
163
return u_pipe_screen_get_param_defaults(pscreen, param);
164
}
165
}
166
167
static float
168
lima_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
169
{
170
switch (param) {
171
case PIPE_CAPF_MAX_LINE_WIDTH:
172
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
173
case PIPE_CAPF_MAX_POINT_WIDTH:
174
case PIPE_CAPF_MAX_POINT_WIDTH_AA:
175
return 100.0f;
176
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
177
return 16.0f;
178
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
179
return 15.0f;
180
181
default:
182
return 0.0f;
183
}
184
}
185
186
static int
187
get_vertex_shader_param(struct lima_screen *screen,
188
enum pipe_shader_cap param)
189
{
190
switch (param) {
191
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
192
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
193
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
194
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
195
return 16384; /* need investigate */
196
197
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
198
return 1024;
199
200
case PIPE_SHADER_CAP_MAX_INPUTS:
201
return 16; /* attributes */
202
203
case PIPE_SHADER_CAP_MAX_OUTPUTS:
204
return LIMA_MAX_VARYING_NUM; /* varying */
205
206
/* Mali-400 GP provides space for 304 vec4 uniforms, globals and
207
* temporary variables. */
208
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
209
return 304 * 4 * sizeof(float);
210
211
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
212
return 1;
213
214
case PIPE_SHADER_CAP_PREFERRED_IR:
215
return PIPE_SHADER_IR_NIR;
216
217
case PIPE_SHADER_CAP_MAX_TEMPS:
218
return 256; /* need investigate */
219
220
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
221
return 32;
222
223
default:
224
return 0;
225
}
226
}
227
228
static int
229
get_fragment_shader_param(struct lima_screen *screen,
230
enum pipe_shader_cap param)
231
{
232
switch (param) {
233
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
234
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
235
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
236
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
237
return 16384; /* need investigate */
238
239
case PIPE_SHADER_CAP_MAX_INPUTS:
240
return LIMA_MAX_VARYING_NUM - 1; /* varying, minus gl_Position */
241
242
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
243
return 1024;
244
245
/* The Mali-PP supports a uniform table up to size 32768 total.
246
* However, indirect access to an uniform only supports indices up
247
* to 8192 (a 2048 vec4 array). To prevent indices bigger than that,
248
* limit max const buffer size to 8192 for now. */
249
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
250
return 2048 * 4 * sizeof(float);
251
252
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
253
return 1;
254
255
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
256
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
257
return 16; /* need investigate */
258
259
case PIPE_SHADER_CAP_PREFERRED_IR:
260
return PIPE_SHADER_IR_NIR;
261
262
case PIPE_SHADER_CAP_MAX_TEMPS:
263
return 256; /* need investigate */
264
265
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
266
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
267
return 1;
268
269
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
270
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
271
return 0;
272
273
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
274
return 32;
275
276
default:
277
return 0;
278
}
279
}
280
281
static int
282
lima_screen_get_shader_param(struct pipe_screen *pscreen,
283
enum pipe_shader_type shader,
284
enum pipe_shader_cap param)
285
{
286
struct lima_screen *screen = lima_screen(pscreen);
287
288
switch (shader) {
289
case PIPE_SHADER_FRAGMENT:
290
return get_fragment_shader_param(screen, param);
291
case PIPE_SHADER_VERTEX:
292
return get_vertex_shader_param(screen, param);
293
294
default:
295
return 0;
296
}
297
}
298
299
static bool
300
lima_screen_is_format_supported(struct pipe_screen *pscreen,
301
enum pipe_format format,
302
enum pipe_texture_target target,
303
unsigned sample_count,
304
unsigned storage_sample_count,
305
unsigned usage)
306
{
307
switch (target) {
308
case PIPE_BUFFER:
309
case PIPE_TEXTURE_1D:
310
case PIPE_TEXTURE_2D:
311
case PIPE_TEXTURE_RECT:
312
case PIPE_TEXTURE_CUBE:
313
break;
314
default:
315
return false;
316
}
317
318
if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
319
return false;
320
321
/* be able to support 16, now limit to 4 */
322
if (sample_count > 1 && sample_count != 4)
323
return false;
324
325
if (usage & PIPE_BIND_RENDER_TARGET) {
326
if (!lima_format_pixel_supported(format))
327
return false;
328
329
/* multisample unsupported with half float target */
330
if (sample_count > 1 && util_format_is_float(format))
331
return false;
332
}
333
334
if (usage & PIPE_BIND_DEPTH_STENCIL) {
335
switch (format) {
336
case PIPE_FORMAT_Z16_UNORM:
337
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
338
case PIPE_FORMAT_Z24X8_UNORM:
339
break;
340
default:
341
return false;
342
}
343
}
344
345
if (usage & PIPE_BIND_VERTEX_BUFFER) {
346
switch (format) {
347
case PIPE_FORMAT_R32_FLOAT:
348
case PIPE_FORMAT_R32G32_FLOAT:
349
case PIPE_FORMAT_R32G32B32_FLOAT:
350
case PIPE_FORMAT_R32G32B32A32_FLOAT:
351
case PIPE_FORMAT_R32_FIXED:
352
case PIPE_FORMAT_R32G32_FIXED:
353
case PIPE_FORMAT_R32G32B32_FIXED:
354
case PIPE_FORMAT_R32G32B32A32_FIXED:
355
case PIPE_FORMAT_R16_FLOAT:
356
case PIPE_FORMAT_R16G16_FLOAT:
357
case PIPE_FORMAT_R16G16B16_FLOAT:
358
case PIPE_FORMAT_R16G16B16A16_FLOAT:
359
case PIPE_FORMAT_R32_UNORM:
360
case PIPE_FORMAT_R32G32_UNORM:
361
case PIPE_FORMAT_R32G32B32_UNORM:
362
case PIPE_FORMAT_R32G32B32A32_UNORM:
363
case PIPE_FORMAT_R32_SNORM:
364
case PIPE_FORMAT_R32G32_SNORM:
365
case PIPE_FORMAT_R32G32B32_SNORM:
366
case PIPE_FORMAT_R32G32B32A32_SNORM:
367
case PIPE_FORMAT_R32_USCALED:
368
case PIPE_FORMAT_R32G32_USCALED:
369
case PIPE_FORMAT_R32G32B32_USCALED:
370
case PIPE_FORMAT_R32G32B32A32_USCALED:
371
case PIPE_FORMAT_R32_SSCALED:
372
case PIPE_FORMAT_R32G32_SSCALED:
373
case PIPE_FORMAT_R32G32B32_SSCALED:
374
case PIPE_FORMAT_R32G32B32A32_SSCALED:
375
case PIPE_FORMAT_R16_UNORM:
376
case PIPE_FORMAT_R16G16_UNORM:
377
case PIPE_FORMAT_R16G16B16_UNORM:
378
case PIPE_FORMAT_R16G16B16A16_UNORM:
379
case PIPE_FORMAT_R16_SNORM:
380
case PIPE_FORMAT_R16G16_SNORM:
381
case PIPE_FORMAT_R16G16B16_SNORM:
382
case PIPE_FORMAT_R16G16B16A16_SNORM:
383
case PIPE_FORMAT_R16_USCALED:
384
case PIPE_FORMAT_R16G16_USCALED:
385
case PIPE_FORMAT_R16G16B16_USCALED:
386
case PIPE_FORMAT_R16G16B16A16_USCALED:
387
case PIPE_FORMAT_R16_SSCALED:
388
case PIPE_FORMAT_R16G16_SSCALED:
389
case PIPE_FORMAT_R16G16B16_SSCALED:
390
case PIPE_FORMAT_R16G16B16A16_SSCALED:
391
case PIPE_FORMAT_R8_UNORM:
392
case PIPE_FORMAT_R8G8_UNORM:
393
case PIPE_FORMAT_R8G8B8_UNORM:
394
case PIPE_FORMAT_R8G8B8A8_UNORM:
395
case PIPE_FORMAT_R8_SNORM:
396
case PIPE_FORMAT_R8G8_SNORM:
397
case PIPE_FORMAT_R8G8B8_SNORM:
398
case PIPE_FORMAT_R8G8B8A8_SNORM:
399
case PIPE_FORMAT_R8_USCALED:
400
case PIPE_FORMAT_R8G8_USCALED:
401
case PIPE_FORMAT_R8G8B8_USCALED:
402
case PIPE_FORMAT_R8G8B8A8_USCALED:
403
case PIPE_FORMAT_R8_SSCALED:
404
case PIPE_FORMAT_R8G8_SSCALED:
405
case PIPE_FORMAT_R8G8B8_SSCALED:
406
case PIPE_FORMAT_R8G8B8A8_SSCALED:
407
break;
408
default:
409
return false;
410
}
411
}
412
413
if (usage & PIPE_BIND_INDEX_BUFFER) {
414
switch (format) {
415
case PIPE_FORMAT_R8_UINT:
416
case PIPE_FORMAT_R16_UINT:
417
case PIPE_FORMAT_R32_UINT:
418
break;
419
default:
420
return false;
421
}
422
}
423
424
if (usage & PIPE_BIND_SAMPLER_VIEW)
425
return lima_format_texel_supported(format);
426
427
return true;
428
}
429
430
static const void *
431
lima_screen_get_compiler_options(struct pipe_screen *pscreen,
432
enum pipe_shader_ir ir,
433
enum pipe_shader_type shader)
434
{
435
return lima_program_get_compiler_options(shader);
436
}
437
438
static bool
439
lima_screen_set_plb_max_blk(struct lima_screen *screen)
440
{
441
if (lima_plb_max_blk) {
442
screen->plb_max_blk = lima_plb_max_blk;
443
return true;
444
}
445
446
if (screen->gpu_type == DRM_LIMA_PARAM_GPU_ID_MALI450)
447
screen->plb_max_blk = 4096;
448
else
449
screen->plb_max_blk = 512;
450
451
drmDevicePtr devinfo;
452
453
if (drmGetDevice2(screen->fd, 0, &devinfo))
454
return false;
455
456
if (devinfo->bustype == DRM_BUS_PLATFORM && devinfo->deviceinfo.platform) {
457
char **compatible = devinfo->deviceinfo.platform->compatible;
458
459
if (compatible && *compatible)
460
if (!strcmp("allwinner,sun50i-h5-mali", *compatible))
461
screen->plb_max_blk = 2048;
462
}
463
464
drmFreeDevice(&devinfo);
465
466
return true;
467
}
468
469
static bool
470
lima_screen_query_info(struct lima_screen *screen)
471
{
472
drmVersionPtr version = drmGetVersion(screen->fd);
473
if (!version)
474
return false;
475
476
if (version->version_major > 1 || version->version_minor > 0)
477
screen->has_growable_heap_buffer = true;
478
479
drmFreeVersion(version);
480
481
if (lima_debug & LIMA_DEBUG_NO_GROW_HEAP)
482
screen->has_growable_heap_buffer = false;
483
484
struct drm_lima_get_param param;
485
486
memset(&param, 0, sizeof(param));
487
param.param = DRM_LIMA_PARAM_GPU_ID;
488
if (drmIoctl(screen->fd, DRM_IOCTL_LIMA_GET_PARAM, &param))
489
return false;
490
491
switch (param.value) {
492
case DRM_LIMA_PARAM_GPU_ID_MALI400:
493
case DRM_LIMA_PARAM_GPU_ID_MALI450:
494
screen->gpu_type = param.value;
495
break;
496
default:
497
return false;
498
}
499
500
memset(&param, 0, sizeof(param));
501
param.param = DRM_LIMA_PARAM_NUM_PP;
502
if (drmIoctl(screen->fd, DRM_IOCTL_LIMA_GET_PARAM, &param))
503
return false;
504
505
screen->num_pp = param.value;
506
507
lima_screen_set_plb_max_blk(screen);
508
509
return true;
510
}
511
512
static const uint64_t lima_available_modifiers[] = {
513
DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED,
514
DRM_FORMAT_MOD_LINEAR,
515
};
516
517
static bool lima_is_modifier_external_only(enum pipe_format format)
518
{
519
return util_format_is_yuv(format);
520
}
521
522
static void
523
lima_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
524
enum pipe_format format, int max,
525
uint64_t *modifiers,
526
unsigned int *external_only,
527
int *count)
528
{
529
int num_modifiers = ARRAY_SIZE(lima_available_modifiers);
530
531
if (!modifiers) {
532
*count = num_modifiers;
533
return;
534
}
535
536
*count = MIN2(max, num_modifiers);
537
for (int i = 0; i < *count; i++) {
538
modifiers[i] = lima_available_modifiers[i];
539
if (external_only)
540
external_only[i] = lima_is_modifier_external_only(format);
541
}
542
}
543
544
static bool
545
lima_screen_is_dmabuf_modifier_supported(struct pipe_screen *pscreen,
546
uint64_t modifier,
547
enum pipe_format format,
548
bool *external_only)
549
{
550
for (int i = 0; i < ARRAY_SIZE(lima_available_modifiers); i++) {
551
if (lima_available_modifiers[i] == modifier) {
552
if (external_only)
553
*external_only = lima_is_modifier_external_only(format);
554
555
return true;
556
}
557
}
558
559
return false;
560
}
561
562
static const struct debug_named_value lima_debug_options[] = {
563
{ "gp", LIMA_DEBUG_GP,
564
"print GP shader compiler result of each stage" },
565
{ "pp", LIMA_DEBUG_PP,
566
"print PP shader compiler result of each stage" },
567
{ "dump", LIMA_DEBUG_DUMP,
568
"dump GPU command stream to $PWD/lima.dump" },
569
{ "shaderdb", LIMA_DEBUG_SHADERDB,
570
"print shader information for shaderdb" },
571
{ "nobocache", LIMA_DEBUG_NO_BO_CACHE,
572
"disable BO cache" },
573
{ "bocache", LIMA_DEBUG_BO_CACHE,
574
"print debug info for BO cache" },
575
{ "notiling", LIMA_DEBUG_NO_TILING,
576
"don't use tiled buffers" },
577
{ "nogrowheap", LIMA_DEBUG_NO_GROW_HEAP,
578
"disable growable heap buffer" },
579
{ "singlejob", LIMA_DEBUG_SINGLE_JOB,
580
"disable multi job optimization" },
581
{ "precompile", LIMA_DEBUG_PRECOMPILE,
582
"Precompile shaders for shader-db" },
583
{ "diskcache", LIMA_DEBUG_DISK_CACHE,
584
"print debug info for shader disk cache" },
585
{ NULL }
586
};
587
588
DEBUG_GET_ONCE_FLAGS_OPTION(lima_debug, "LIMA_DEBUG", lima_debug_options, 0)
589
uint32_t lima_debug;
590
591
static void
592
lima_screen_parse_env(void)
593
{
594
lima_debug = debug_get_option_lima_debug();
595
596
lima_ctx_num_plb = debug_get_num_option("LIMA_CTX_NUM_PLB", LIMA_CTX_PLB_DEF_NUM);
597
if (lima_ctx_num_plb > LIMA_CTX_PLB_MAX_NUM ||
598
lima_ctx_num_plb < LIMA_CTX_PLB_MIN_NUM) {
599
fprintf(stderr, "lima: LIMA_CTX_NUM_PLB %d out of range [%d %d], "
600
"reset to default %d\n", lima_ctx_num_plb, LIMA_CTX_PLB_MIN_NUM,
601
LIMA_CTX_PLB_MAX_NUM, LIMA_CTX_PLB_DEF_NUM);
602
lima_ctx_num_plb = LIMA_CTX_PLB_DEF_NUM;
603
}
604
605
lima_plb_max_blk = debug_get_num_option("LIMA_PLB_MAX_BLK", 0);
606
if (lima_plb_max_blk < 0 || lima_plb_max_blk > 65536) {
607
fprintf(stderr, "lima: LIMA_PLB_MAX_BLK %d out of range [%d %d], "
608
"reset to default %d\n", lima_plb_max_blk, 0, 65536, 0);
609
lima_plb_max_blk = 0;
610
}
611
612
lima_ppir_force_spilling = debug_get_num_option("LIMA_PPIR_FORCE_SPILLING", 0);
613
if (lima_ppir_force_spilling < 0) {
614
fprintf(stderr, "lima: LIMA_PPIR_FORCE_SPILLING %d less than 0, "
615
"reset to default 0\n", lima_ppir_force_spilling);
616
lima_ppir_force_spilling = 0;
617
}
618
619
lima_plb_pp_stream_cache_size = debug_get_num_option("LIMA_PLB_PP_STREAM_CACHE_SIZE", 0);
620
if (lima_plb_pp_stream_cache_size < 0) {
621
fprintf(stderr, "lima: LIMA_PLB_PP_STREAM_CACHE_SIZE %d less than 0, "
622
"reset to default 0\n", lima_plb_pp_stream_cache_size);
623
lima_plb_pp_stream_cache_size = 0;
624
}
625
}
626
627
static struct disk_cache *
628
lima_get_disk_shader_cache (struct pipe_screen *pscreen)
629
{
630
struct lima_screen *screen = lima_screen(pscreen);
631
632
return screen->disk_cache;
633
}
634
635
struct pipe_screen *
636
lima_screen_create(int fd, struct renderonly *ro)
637
{
638
uint64_t system_memory;
639
struct lima_screen *screen;
640
641
screen = rzalloc(NULL, struct lima_screen);
642
if (!screen)
643
return NULL;
644
645
screen->fd = fd;
646
screen->ro = ro;
647
648
lima_screen_parse_env();
649
650
/* Limit PP PLB stream cache size to 0.1% of system memory */
651
if (!lima_plb_pp_stream_cache_size &&
652
os_get_total_physical_memory(&system_memory))
653
lima_plb_pp_stream_cache_size = system_memory >> 10;
654
655
/* Set lower limit on PP PLB cache size */
656
lima_plb_pp_stream_cache_size = MAX2(128 * 1024 * lima_ctx_num_plb,
657
lima_plb_pp_stream_cache_size);
658
659
if (!lima_screen_query_info(screen))
660
goto err_out0;
661
662
if (!lima_bo_cache_init(screen))
663
goto err_out0;
664
665
if (!lima_bo_table_init(screen))
666
goto err_out1;
667
668
screen->pp_ra = ppir_regalloc_init(screen);
669
if (!screen->pp_ra)
670
goto err_out2;
671
672
screen->pp_buffer = lima_bo_create(screen, pp_buffer_size, 0);
673
if (!screen->pp_buffer)
674
goto err_out2;
675
screen->pp_buffer->cacheable = false;
676
677
/* fs program for clear buffer?
678
* const0 1 0 0 -1.67773, mov.v0 $0 ^const0.xxxx, stop
679
*/
680
static const uint32_t pp_clear_program[] = {
681
0x00020425, 0x0000000c, 0x01e007cf, 0xb0000000,
682
0x000005f5, 0x00000000, 0x00000000, 0x00000000,
683
};
684
memcpy(lima_bo_map(screen->pp_buffer) + pp_clear_program_offset,
685
pp_clear_program, sizeof(pp_clear_program));
686
687
/* copy texture to framebuffer, used to reload gpu tile buffer
688
* load.v $1 0.xy, texld_2d 0, mov.v0 $0 ^tex_sampler, sync, stop
689
*/
690
static const uint32_t pp_reload_program[] = {
691
0x000005e6, 0xf1003c20, 0x00000000, 0x39001000,
692
0x00000e4e, 0x000007cf, 0x00000000, 0x00000000,
693
};
694
memcpy(lima_bo_map(screen->pp_buffer) + pp_reload_program_offset,
695
pp_reload_program, sizeof(pp_reload_program));
696
697
/* 0/1/2 vertex index for reload/clear draw */
698
static const uint8_t pp_shared_index[] = { 0, 1, 2 };
699
memcpy(lima_bo_map(screen->pp_buffer) + pp_shared_index_offset,
700
pp_shared_index, sizeof(pp_shared_index));
701
702
/* 4096x4096 gl pos used for partial clear */
703
static const float pp_clear_gl_pos[] = {
704
4096, 0, 1, 1,
705
0, 0, 1, 1,
706
0, 4096, 1, 1,
707
};
708
memcpy(lima_bo_map(screen->pp_buffer) + pp_clear_gl_pos_offset,
709
pp_clear_gl_pos, sizeof(pp_clear_gl_pos));
710
711
/* is pp frame render state static? */
712
uint32_t *pp_frame_rsw = lima_bo_map(screen->pp_buffer) + pp_frame_rsw_offset;
713
memset(pp_frame_rsw, 0, 0x40);
714
pp_frame_rsw[8] = 0x0000f008;
715
pp_frame_rsw[9] = screen->pp_buffer->va + pp_clear_program_offset;
716
pp_frame_rsw[13] = 0x00000100;
717
718
screen->base.destroy = lima_screen_destroy;
719
screen->base.get_name = lima_screen_get_name;
720
screen->base.get_vendor = lima_screen_get_vendor;
721
screen->base.get_device_vendor = lima_screen_get_device_vendor;
722
screen->base.get_param = lima_screen_get_param;
723
screen->base.get_paramf = lima_screen_get_paramf;
724
screen->base.get_shader_param = lima_screen_get_shader_param;
725
screen->base.context_create = lima_context_create;
726
screen->base.is_format_supported = lima_screen_is_format_supported;
727
screen->base.get_compiler_options = lima_screen_get_compiler_options;
728
screen->base.query_dmabuf_modifiers = lima_screen_query_dmabuf_modifiers;
729
screen->base.is_dmabuf_modifier_supported = lima_screen_is_dmabuf_modifier_supported;
730
screen->base.get_disk_shader_cache = lima_get_disk_shader_cache;
731
732
lima_resource_screen_init(screen);
733
lima_fence_screen_init(screen);
734
lima_disk_cache_init(screen);
735
736
slab_create_parent(&screen->transfer_pool, sizeof(struct lima_transfer), 16);
737
738
screen->refcnt = 1;
739
740
return &screen->base;
741
742
err_out2:
743
lima_bo_table_fini(screen);
744
err_out1:
745
lima_bo_cache_fini(screen);
746
err_out0:
747
ralloc_free(screen);
748
return NULL;
749
}
750
751