Path: blob/21.2-virgl/src/gallium/drivers/nouveau/nouveau_buffer.c
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1#include "util/u_inlines.h"2#include "util/u_memory.h"3#include "util/u_math.h"4#include "util/u_surface.h"56#include "nouveau_screen.h"7#include "nouveau_context.h"8#include "nouveau_winsys.h"9#include "nouveau_fence.h"10#include "nouveau_buffer.h"11#include "nouveau_mm.h"1213struct nouveau_transfer {14struct pipe_transfer base;1516uint8_t *map;17struct nouveau_bo *bo;18struct nouveau_mm_allocation *mm;19uint32_t offset;20};2122static void *23nouveau_user_ptr_transfer_map(struct pipe_context *pipe,24struct pipe_resource *resource,25unsigned level, unsigned usage,26const struct pipe_box *box,27struct pipe_transfer **ptransfer);2829static void30nouveau_user_ptr_transfer_unmap(struct pipe_context *pipe,31struct pipe_transfer *transfer);3233static inline struct nouveau_transfer *34nouveau_transfer(struct pipe_transfer *transfer)35{36return (struct nouveau_transfer *)transfer;37}3839static inline bool40nouveau_buffer_malloc(struct nv04_resource *buf)41{42if (!buf->data)43buf->data = align_malloc(buf->base.width0, NOUVEAU_MIN_BUFFER_MAP_ALIGN);44return !!buf->data;45}4647static inline bool48nouveau_buffer_allocate(struct nouveau_screen *screen,49struct nv04_resource *buf, unsigned domain)50{51uint32_t size = align(buf->base.width0, 0x100);5253if (domain == NOUVEAU_BO_VRAM) {54buf->mm = nouveau_mm_allocate(screen->mm_VRAM, size,55&buf->bo, &buf->offset);56if (!buf->bo)57return nouveau_buffer_allocate(screen, buf, NOUVEAU_BO_GART);58NOUVEAU_DRV_STAT(screen, buf_obj_current_bytes_vid, buf->base.width0);59} else60if (domain == NOUVEAU_BO_GART) {61buf->mm = nouveau_mm_allocate(screen->mm_GART, size,62&buf->bo, &buf->offset);63if (!buf->bo)64return false;65NOUVEAU_DRV_STAT(screen, buf_obj_current_bytes_sys, buf->base.width0);66} else {67assert(domain == 0);68if (!nouveau_buffer_malloc(buf))69return false;70}71buf->domain = domain;72if (buf->bo)73buf->address = buf->bo->offset + buf->offset;7475util_range_set_empty(&buf->valid_buffer_range);7677return true;78}7980static inline void81release_allocation(struct nouveau_mm_allocation **mm,82struct nouveau_fence *fence)83{84nouveau_fence_work(fence, nouveau_mm_free_work, *mm);85(*mm) = NULL;86}8788inline void89nouveau_buffer_release_gpu_storage(struct nv04_resource *buf)90{91assert(!(buf->status & NOUVEAU_BUFFER_STATUS_USER_PTR));9293if (buf->fence && buf->fence->state < NOUVEAU_FENCE_STATE_FLUSHED) {94nouveau_fence_work(buf->fence, nouveau_fence_unref_bo, buf->bo);95buf->bo = NULL;96} else {97nouveau_bo_ref(NULL, &buf->bo);98}99100if (buf->mm)101release_allocation(&buf->mm, buf->fence);102103if (buf->domain == NOUVEAU_BO_VRAM)104NOUVEAU_DRV_STAT_RES(buf, buf_obj_current_bytes_vid, -(uint64_t)buf->base.width0);105if (buf->domain == NOUVEAU_BO_GART)106NOUVEAU_DRV_STAT_RES(buf, buf_obj_current_bytes_sys, -(uint64_t)buf->base.width0);107108buf->domain = 0;109}110111static inline bool112nouveau_buffer_reallocate(struct nouveau_screen *screen,113struct nv04_resource *buf, unsigned domain)114{115nouveau_buffer_release_gpu_storage(buf);116117nouveau_fence_ref(NULL, &buf->fence);118nouveau_fence_ref(NULL, &buf->fence_wr);119120buf->status &= NOUVEAU_BUFFER_STATUS_REALLOC_MASK;121122return nouveau_buffer_allocate(screen, buf, domain);123}124125void126nouveau_buffer_destroy(struct pipe_screen *pscreen,127struct pipe_resource *presource)128{129struct nv04_resource *res = nv04_resource(presource);130131if (res->status & NOUVEAU_BUFFER_STATUS_USER_PTR) {132FREE(res);133return;134}135136nouveau_buffer_release_gpu_storage(res);137138if (res->data && !(res->status & NOUVEAU_BUFFER_STATUS_USER_MEMORY))139align_free(res->data);140141nouveau_fence_ref(NULL, &res->fence);142nouveau_fence_ref(NULL, &res->fence_wr);143144util_range_destroy(&res->valid_buffer_range);145146FREE(res);147148NOUVEAU_DRV_STAT(nouveau_screen(pscreen), buf_obj_current_count, -1);149}150151/* Set up a staging area for the transfer. This is either done in "regular"152* system memory if the driver supports push_data (nv50+) and the data is153* small enough (and permit_pb == true), or in GART memory.154*/155static uint8_t *156nouveau_transfer_staging(struct nouveau_context *nv,157struct nouveau_transfer *tx, bool permit_pb)158{159const unsigned adj = tx->base.box.x & NOUVEAU_MIN_BUFFER_MAP_ALIGN_MASK;160const unsigned size = align(tx->base.box.width, 4) + adj;161162if (!nv->push_data)163permit_pb = false;164165if ((size <= nv->screen->transfer_pushbuf_threshold) && permit_pb) {166tx->map = align_malloc(size, NOUVEAU_MIN_BUFFER_MAP_ALIGN);167if (tx->map)168tx->map += adj;169} else {170tx->mm =171nouveau_mm_allocate(nv->screen->mm_GART, size, &tx->bo, &tx->offset);172if (tx->bo) {173tx->offset += adj;174if (!nouveau_bo_map(tx->bo, 0, NULL))175tx->map = (uint8_t *)tx->bo->map + tx->offset;176}177}178return tx->map;179}180181/* Copies data from the resource into the transfer's temporary GART182* buffer. Also updates buf->data if present.183*184* Maybe just migrate to GART right away if we actually need to do this. */185static bool186nouveau_transfer_read(struct nouveau_context *nv, struct nouveau_transfer *tx)187{188struct nv04_resource *buf = nv04_resource(tx->base.resource);189const unsigned base = tx->base.box.x;190const unsigned size = tx->base.box.width;191192NOUVEAU_DRV_STAT(nv->screen, buf_read_bytes_staging_vid, size);193194nv->copy_data(nv, tx->bo, tx->offset, NOUVEAU_BO_GART,195buf->bo, buf->offset + base, buf->domain, size);196197if (nouveau_bo_wait(tx->bo, NOUVEAU_BO_RD, nv->client))198return false;199200if (buf->data)201memcpy(buf->data + base, tx->map, size);202203return true;204}205206static void207nouveau_transfer_write(struct nouveau_context *nv, struct nouveau_transfer *tx,208unsigned offset, unsigned size)209{210struct nv04_resource *buf = nv04_resource(tx->base.resource);211uint8_t *data = tx->map + offset;212const unsigned base = tx->base.box.x + offset;213const bool can_cb = !((base | size) & 3);214215if (buf->data)216memcpy(data, buf->data + base, size);217else218buf->status |= NOUVEAU_BUFFER_STATUS_DIRTY;219220if (buf->domain == NOUVEAU_BO_VRAM)221NOUVEAU_DRV_STAT(nv->screen, buf_write_bytes_staging_vid, size);222if (buf->domain == NOUVEAU_BO_GART)223NOUVEAU_DRV_STAT(nv->screen, buf_write_bytes_staging_sys, size);224225if (tx->bo)226nv->copy_data(nv, buf->bo, buf->offset + base, buf->domain,227tx->bo, tx->offset + offset, NOUVEAU_BO_GART, size);228else229if (nv->push_cb && can_cb)230nv->push_cb(nv, buf,231base, size / 4, (const uint32_t *)data);232else233nv->push_data(nv, buf->bo, buf->offset + base, buf->domain, size, data);234235nouveau_fence_ref(nv->screen->fence.current, &buf->fence);236nouveau_fence_ref(nv->screen->fence.current, &buf->fence_wr);237}238239/* Does a CPU wait for the buffer's backing data to become reliably accessible240* for write/read by waiting on the buffer's relevant fences.241*/242static inline bool243nouveau_buffer_sync(struct nouveau_context *nv,244struct nv04_resource *buf, unsigned rw)245{246if (rw == PIPE_MAP_READ) {247if (!buf->fence_wr)248return true;249NOUVEAU_DRV_STAT_RES(buf, buf_non_kernel_fence_sync_count,250!nouveau_fence_signalled(buf->fence_wr));251if (!nouveau_fence_wait(buf->fence_wr, &nv->debug))252return false;253} else {254if (!buf->fence)255return true;256NOUVEAU_DRV_STAT_RES(buf, buf_non_kernel_fence_sync_count,257!nouveau_fence_signalled(buf->fence));258if (!nouveau_fence_wait(buf->fence, &nv->debug))259return false;260261nouveau_fence_ref(NULL, &buf->fence);262}263nouveau_fence_ref(NULL, &buf->fence_wr);264265return true;266}267268static inline bool269nouveau_buffer_busy(struct nv04_resource *buf, unsigned rw)270{271if (rw == PIPE_MAP_READ)272return (buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr));273else274return (buf->fence && !nouveau_fence_signalled(buf->fence));275}276277static inline void278nouveau_buffer_transfer_init(struct nouveau_transfer *tx,279struct pipe_resource *resource,280const struct pipe_box *box,281unsigned usage)282{283tx->base.resource = resource;284tx->base.level = 0;285tx->base.usage = usage;286tx->base.box.x = box->x;287tx->base.box.y = 0;288tx->base.box.z = 0;289tx->base.box.width = box->width;290tx->base.box.height = 1;291tx->base.box.depth = 1;292tx->base.stride = 0;293tx->base.layer_stride = 0;294295tx->bo = NULL;296tx->map = NULL;297}298299static inline void300nouveau_buffer_transfer_del(struct nouveau_context *nv,301struct nouveau_transfer *tx)302{303if (tx->map) {304if (likely(tx->bo)) {305nouveau_fence_work(nv->screen->fence.current,306nouveau_fence_unref_bo, tx->bo);307if (tx->mm)308release_allocation(&tx->mm, nv->screen->fence.current);309} else {310align_free(tx->map -311(tx->base.box.x & NOUVEAU_MIN_BUFFER_MAP_ALIGN_MASK));312}313}314}315316/* Creates a cache in system memory of the buffer data. */317static bool318nouveau_buffer_cache(struct nouveau_context *nv, struct nv04_resource *buf)319{320struct nouveau_transfer tx;321bool ret;322tx.base.resource = &buf->base;323tx.base.box.x = 0;324tx.base.box.width = buf->base.width0;325tx.bo = NULL;326tx.map = NULL;327328if (!buf->data)329if (!nouveau_buffer_malloc(buf))330return false;331if (!(buf->status & NOUVEAU_BUFFER_STATUS_DIRTY))332return true;333nv->stats.buf_cache_count++;334335if (!nouveau_transfer_staging(nv, &tx, false))336return false;337338ret = nouveau_transfer_read(nv, &tx);339if (ret) {340buf->status &= ~NOUVEAU_BUFFER_STATUS_DIRTY;341memcpy(buf->data, tx.map, buf->base.width0);342}343nouveau_buffer_transfer_del(nv, &tx);344return ret;345}346347348#define NOUVEAU_TRANSFER_DISCARD \349(PIPE_MAP_DISCARD_RANGE | PIPE_MAP_DISCARD_WHOLE_RESOURCE)350351/* Checks whether it is possible to completely discard the memory backing this352* resource. This can be useful if we would otherwise have to wait for a read353* operation to complete on this data.354*/355static inline bool356nouveau_buffer_should_discard(struct nv04_resource *buf, unsigned usage)357{358if (!(usage & PIPE_MAP_DISCARD_WHOLE_RESOURCE))359return false;360if (unlikely(buf->base.bind & PIPE_BIND_SHARED))361return false;362if (unlikely(usage & PIPE_MAP_PERSISTENT))363return false;364return buf->mm && nouveau_buffer_busy(buf, PIPE_MAP_WRITE);365}366367/* Returns a pointer to a memory area representing a window into the368* resource's data.369*370* This may or may not be the _actual_ memory area of the resource. However371* when calling nouveau_buffer_transfer_unmap, if it wasn't the actual memory372* area, the contents of the returned map are copied over to the resource.373*374* The usage indicates what the caller plans to do with the map:375*376* WRITE means that the user plans to write to it377*378* READ means that the user plans on reading from it379*380* DISCARD_WHOLE_RESOURCE means that the whole resource is going to be381* potentially overwritten, and even if it isn't, the bits that aren't don't382* need to be maintained.383*384* DISCARD_RANGE means that all the data in the specified range is going to385* be overwritten.386*387* The strategy for determining what kind of memory area to return is complex,388* see comments inside of the function.389*/390void *391nouveau_buffer_transfer_map(struct pipe_context *pipe,392struct pipe_resource *resource,393unsigned level, unsigned usage,394const struct pipe_box *box,395struct pipe_transfer **ptransfer)396{397struct nouveau_context *nv = nouveau_context(pipe);398struct nv04_resource *buf = nv04_resource(resource);399400if (buf->status & NOUVEAU_BUFFER_STATUS_USER_PTR)401return nouveau_user_ptr_transfer_map(pipe, resource, level, usage, box, ptransfer);402403struct nouveau_transfer *tx = MALLOC_STRUCT(nouveau_transfer);404uint8_t *map;405int ret;406407if (!tx)408return NULL;409nouveau_buffer_transfer_init(tx, resource, box, usage);410*ptransfer = &tx->base;411412if (usage & PIPE_MAP_READ)413NOUVEAU_DRV_STAT(nv->screen, buf_transfers_rd, 1);414if (usage & PIPE_MAP_WRITE)415NOUVEAU_DRV_STAT(nv->screen, buf_transfers_wr, 1);416417/* If we are trying to write to an uninitialized range, the user shouldn't418* care what was there before. So we can treat the write as if the target419* range were being discarded. Furthermore, since we know that even if this420* buffer is busy due to GPU activity, because the contents were421* uninitialized, the GPU can't care what was there, and so we can treat422* the write as being unsynchronized.423*/424if ((usage & PIPE_MAP_WRITE) &&425!util_ranges_intersect(&buf->valid_buffer_range, box->x, box->x + box->width))426usage |= PIPE_MAP_DISCARD_RANGE | PIPE_MAP_UNSYNCHRONIZED;427428if (buf->domain == NOUVEAU_BO_VRAM) {429if (usage & NOUVEAU_TRANSFER_DISCARD) {430/* Set up a staging area for the user to write to. It will be copied431* back into VRAM on unmap. */432if (usage & PIPE_MAP_DISCARD_WHOLE_RESOURCE)433buf->status &= NOUVEAU_BUFFER_STATUS_REALLOC_MASK;434nouveau_transfer_staging(nv, tx, true);435} else {436if (buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {437/* The GPU is currently writing to this buffer. Copy its current438* contents to a staging area in the GART. This is necessary since439* not the whole area being mapped is being discarded.440*/441if (buf->data) {442align_free(buf->data);443buf->data = NULL;444}445nouveau_transfer_staging(nv, tx, false);446nouveau_transfer_read(nv, tx);447} else {448/* The buffer is currently idle. Create a staging area for writes,449* and make sure that the cached data is up-to-date. */450if (usage & PIPE_MAP_WRITE)451nouveau_transfer_staging(nv, tx, true);452if (!buf->data)453nouveau_buffer_cache(nv, buf);454}455}456return buf->data ? (buf->data + box->x) : tx->map;457} else458if (unlikely(buf->domain == 0)) {459return buf->data + box->x;460}461462/* At this point, buf->domain == GART */463464if (nouveau_buffer_should_discard(buf, usage)) {465int ref = buf->base.reference.count - 1;466nouveau_buffer_reallocate(nv->screen, buf, buf->domain);467if (ref > 0) /* any references inside context possible ? */468nv->invalidate_resource_storage(nv, &buf->base, ref);469}470471/* Note that nouveau_bo_map ends up doing a nouveau_bo_wait with the472* relevant flags. If buf->mm is set, that means this resource is part of a473* larger slab bo that holds multiple resources. So in that case, don't474* wait on the whole slab and instead use the logic below to return a475* reasonable buffer for that case.476*/477ret = nouveau_bo_map(buf->bo,478buf->mm ? 0 : nouveau_screen_transfer_flags(usage),479nv->client);480if (ret) {481FREE(tx);482return NULL;483}484map = (uint8_t *)buf->bo->map + buf->offset + box->x;485486/* using kernel fences only if !buf->mm */487if ((usage & PIPE_MAP_UNSYNCHRONIZED) || !buf->mm)488return map;489490/* If the GPU is currently reading/writing this buffer, we shouldn't491* interfere with its progress. So instead we either wait for the GPU to492* complete its operation, or set up a staging area to perform our work in.493*/494if (nouveau_buffer_busy(buf, usage & PIPE_MAP_READ_WRITE)) {495if (unlikely(usage & (PIPE_MAP_DISCARD_WHOLE_RESOURCE |496PIPE_MAP_PERSISTENT))) {497/* Discarding was not possible, must sync because498* subsequent transfers might use UNSYNCHRONIZED. */499nouveau_buffer_sync(nv, buf, usage & PIPE_MAP_READ_WRITE);500} else501if (usage & PIPE_MAP_DISCARD_RANGE) {502/* The whole range is being discarded, so it doesn't matter what was503* there before. No need to copy anything over. */504nouveau_transfer_staging(nv, tx, true);505map = tx->map;506} else507if (nouveau_buffer_busy(buf, PIPE_MAP_READ)) {508if (usage & PIPE_MAP_DONTBLOCK)509map = NULL;510else511nouveau_buffer_sync(nv, buf, usage & PIPE_MAP_READ_WRITE);512} else {513/* It is expected that the returned buffer be a representation of the514* data in question, so we must copy it over from the buffer. */515nouveau_transfer_staging(nv, tx, true);516if (tx->map)517memcpy(tx->map, map, box->width);518map = tx->map;519}520}521if (!map)522FREE(tx);523return map;524}525526527528void529nouveau_buffer_transfer_flush_region(struct pipe_context *pipe,530struct pipe_transfer *transfer,531const struct pipe_box *box)532{533struct nouveau_transfer *tx = nouveau_transfer(transfer);534struct nv04_resource *buf = nv04_resource(transfer->resource);535536if (tx->map)537nouveau_transfer_write(nouveau_context(pipe), tx, box->x, box->width);538539util_range_add(&buf->base, &buf->valid_buffer_range,540tx->base.box.x + box->x,541tx->base.box.x + box->x + box->width);542}543544/* Unmap stage of the transfer. If it was a WRITE transfer and the map that545* was returned was not the real resource's data, this needs to transfer the546* data back to the resource.547*548* Also marks vbo dirty based on the buffer's binding549*/550void551nouveau_buffer_transfer_unmap(struct pipe_context *pipe,552struct pipe_transfer *transfer)553{554struct nouveau_context *nv = nouveau_context(pipe);555struct nv04_resource *buf = nv04_resource(transfer->resource);556557if (buf->status & NOUVEAU_BUFFER_STATUS_USER_PTR)558return nouveau_user_ptr_transfer_unmap(pipe, transfer);559560struct nouveau_transfer *tx = nouveau_transfer(transfer);561562if (tx->base.usage & PIPE_MAP_WRITE) {563if (!(tx->base.usage & PIPE_MAP_FLUSH_EXPLICIT)) {564if (tx->map)565nouveau_transfer_write(nv, tx, 0, tx->base.box.width);566567util_range_add(&buf->base, &buf->valid_buffer_range,568tx->base.box.x, tx->base.box.x + tx->base.box.width);569}570571if (likely(buf->domain)) {572const uint8_t bind = buf->base.bind;573/* make sure we invalidate dedicated caches */574if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))575nv->vbo_dirty = true;576}577}578579if (!tx->bo && (tx->base.usage & PIPE_MAP_WRITE))580NOUVEAU_DRV_STAT(nv->screen, buf_write_bytes_direct, tx->base.box.width);581582nouveau_buffer_transfer_del(nv, tx);583FREE(tx);584}585586587void588nouveau_copy_buffer(struct nouveau_context *nv,589struct nv04_resource *dst, unsigned dstx,590struct nv04_resource *src, unsigned srcx, unsigned size)591{592assert(dst->base.target == PIPE_BUFFER && src->base.target == PIPE_BUFFER);593594assert(!(dst->status & NOUVEAU_BUFFER_STATUS_USER_PTR));595assert(!(src->status & NOUVEAU_BUFFER_STATUS_USER_PTR));596597if (likely(dst->domain) && likely(src->domain)) {598nv->copy_data(nv,599dst->bo, dst->offset + dstx, dst->domain,600src->bo, src->offset + srcx, src->domain, size);601602dst->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;603nouveau_fence_ref(nv->screen->fence.current, &dst->fence);604nouveau_fence_ref(nv->screen->fence.current, &dst->fence_wr);605606src->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;607nouveau_fence_ref(nv->screen->fence.current, &src->fence);608} else {609struct pipe_box src_box;610src_box.x = srcx;611src_box.y = 0;612src_box.z = 0;613src_box.width = size;614src_box.height = 1;615src_box.depth = 1;616util_resource_copy_region(&nv->pipe,617&dst->base, 0, dstx, 0, 0,618&src->base, 0, &src_box);619}620621util_range_add(&dst->base, &dst->valid_buffer_range, dstx, dstx + size);622}623624625void *626nouveau_resource_map_offset(struct nouveau_context *nv,627struct nv04_resource *res, uint32_t offset,628uint32_t flags)629{630if (unlikely(res->status & NOUVEAU_BUFFER_STATUS_USER_MEMORY) ||631unlikely(res->status & NOUVEAU_BUFFER_STATUS_USER_PTR))632return res->data + offset;633634if (res->domain == NOUVEAU_BO_VRAM) {635if (!res->data || (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING))636nouveau_buffer_cache(nv, res);637}638if (res->domain != NOUVEAU_BO_GART)639return res->data + offset;640641if (res->mm) {642unsigned rw;643rw = (flags & NOUVEAU_BO_WR) ? PIPE_MAP_WRITE : PIPE_MAP_READ;644nouveau_buffer_sync(nv, res, rw);645if (nouveau_bo_map(res->bo, 0, NULL))646return NULL;647} else {648if (nouveau_bo_map(res->bo, flags, nv->client))649return NULL;650}651return (uint8_t *)res->bo->map + res->offset + offset;652}653654static void *655nouveau_user_ptr_transfer_map(struct pipe_context *pipe,656struct pipe_resource *resource,657unsigned level, unsigned usage,658const struct pipe_box *box,659struct pipe_transfer **ptransfer)660{661struct nouveau_transfer *tx = MALLOC_STRUCT(nouveau_transfer);662if (!tx)663return NULL;664nouveau_buffer_transfer_init(tx, resource, box, usage);665*ptransfer = &tx->base;666return nv04_resource(resource)->data;667}668669static void670nouveau_user_ptr_transfer_unmap(struct pipe_context *pipe,671struct pipe_transfer *transfer)672{673struct nouveau_transfer *tx = nouveau_transfer(transfer);674FREE(tx);675}676677struct pipe_resource *678nouveau_buffer_create(struct pipe_screen *pscreen,679const struct pipe_resource *templ)680{681struct nouveau_screen *screen = nouveau_screen(pscreen);682struct nv04_resource *buffer;683bool ret;684685buffer = CALLOC_STRUCT(nv04_resource);686if (!buffer)687return NULL;688689buffer->base = *templ;690pipe_reference_init(&buffer->base.reference, 1);691buffer->base.screen = pscreen;692693if (buffer->base.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |694PIPE_RESOURCE_FLAG_MAP_COHERENT)) {695buffer->domain = NOUVEAU_BO_GART;696} else if (buffer->base.bind == 0 || (buffer->base.bind &697(screen->vidmem_bindings & screen->sysmem_bindings))) {698switch (buffer->base.usage) {699case PIPE_USAGE_DEFAULT:700case PIPE_USAGE_IMMUTABLE:701buffer->domain = NV_VRAM_DOMAIN(screen);702break;703case PIPE_USAGE_DYNAMIC:704/* For most apps, we'd have to do staging transfers to avoid sync705* with this usage, and GART -> GART copies would be suboptimal.706*/707buffer->domain = NV_VRAM_DOMAIN(screen);708break;709case PIPE_USAGE_STAGING:710case PIPE_USAGE_STREAM:711buffer->domain = NOUVEAU_BO_GART;712break;713default:714assert(0);715break;716}717} else {718if (buffer->base.bind & screen->vidmem_bindings)719buffer->domain = NV_VRAM_DOMAIN(screen);720else721if (buffer->base.bind & screen->sysmem_bindings)722buffer->domain = NOUVEAU_BO_GART;723}724725ret = nouveau_buffer_allocate(screen, buffer, buffer->domain);726727if (ret == false)728goto fail;729730if (buffer->domain == NOUVEAU_BO_VRAM && screen->hint_buf_keep_sysmem_copy)731nouveau_buffer_cache(NULL, buffer);732733NOUVEAU_DRV_STAT(screen, buf_obj_current_count, 1);734735util_range_init(&buffer->valid_buffer_range);736737return &buffer->base;738739fail:740FREE(buffer);741return NULL;742}743744struct pipe_resource *745nouveau_buffer_create_from_user(struct pipe_screen *pscreen,746const struct pipe_resource *templ,747void *user_ptr)748{749struct nv04_resource *buffer;750751buffer = CALLOC_STRUCT(nv04_resource);752if (!buffer)753return NULL;754755buffer->base = *templ;756/* set address and data to the same thing for higher compatibility with757* existing code. It's correct nonetheless as the same pointer is equally758* valid on the CPU and the GPU.759*/760buffer->address = (uintptr_t)user_ptr;761buffer->data = user_ptr;762buffer->status = NOUVEAU_BUFFER_STATUS_USER_PTR;763buffer->base.screen = pscreen;764765pipe_reference_init(&buffer->base.reference, 1);766767return &buffer->base;768}769770struct pipe_resource *771nouveau_user_buffer_create(struct pipe_screen *pscreen, void *ptr,772unsigned bytes, unsigned bind)773{774struct nv04_resource *buffer;775776buffer = CALLOC_STRUCT(nv04_resource);777if (!buffer)778return NULL;779780pipe_reference_init(&buffer->base.reference, 1);781buffer->base.screen = pscreen;782buffer->base.format = PIPE_FORMAT_R8_UNORM;783buffer->base.usage = PIPE_USAGE_IMMUTABLE;784buffer->base.bind = bind;785buffer->base.width0 = bytes;786buffer->base.height0 = 1;787buffer->base.depth0 = 1;788789buffer->data = ptr;790buffer->status = NOUVEAU_BUFFER_STATUS_USER_MEMORY;791792util_range_init(&buffer->valid_buffer_range);793util_range_add(&buffer->base, &buffer->valid_buffer_range, 0, bytes);794795return &buffer->base;796}797798static inline bool799nouveau_buffer_data_fetch(struct nouveau_context *nv, struct nv04_resource *buf,800struct nouveau_bo *bo, unsigned offset, unsigned size)801{802if (!nouveau_buffer_malloc(buf))803return false;804if (nouveau_bo_map(bo, NOUVEAU_BO_RD, nv->client))805return false;806memcpy(buf->data, (uint8_t *)bo->map + offset, size);807return true;808}809810/* Migrate a linear buffer (vertex, index, constants) USER -> GART -> VRAM. */811bool812nouveau_buffer_migrate(struct nouveau_context *nv,813struct nv04_resource *buf, const unsigned new_domain)814{815assert(!(buf->status & NOUVEAU_BUFFER_STATUS_USER_PTR));816817struct nouveau_screen *screen = nv->screen;818struct nouveau_bo *bo;819const unsigned old_domain = buf->domain;820unsigned size = buf->base.width0;821unsigned offset;822int ret;823824assert(new_domain != old_domain);825826if (new_domain == NOUVEAU_BO_GART && old_domain == 0) {827if (!nouveau_buffer_allocate(screen, buf, new_domain))828return false;829ret = nouveau_bo_map(buf->bo, 0, nv->client);830if (ret)831return ret;832memcpy((uint8_t *)buf->bo->map + buf->offset, buf->data, size);833align_free(buf->data);834} else835if (old_domain != 0 && new_domain != 0) {836struct nouveau_mm_allocation *mm = buf->mm;837838if (new_domain == NOUVEAU_BO_VRAM) {839/* keep a system memory copy of our data in case we hit a fallback */840if (!nouveau_buffer_data_fetch(nv, buf, buf->bo, buf->offset, size))841return false;842if (nouveau_mesa_debug)843debug_printf("migrating %u KiB to VRAM\n", size / 1024);844}845846offset = buf->offset;847bo = buf->bo;848buf->bo = NULL;849buf->mm = NULL;850nouveau_buffer_allocate(screen, buf, new_domain);851852nv->copy_data(nv, buf->bo, buf->offset, new_domain,853bo, offset, old_domain, buf->base.width0);854855nouveau_fence_work(screen->fence.current, nouveau_fence_unref_bo, bo);856if (mm)857release_allocation(&mm, screen->fence.current);858} else859if (new_domain == NOUVEAU_BO_VRAM && old_domain == 0) {860struct nouveau_transfer tx;861if (!nouveau_buffer_allocate(screen, buf, NOUVEAU_BO_VRAM))862return false;863tx.base.resource = &buf->base;864tx.base.box.x = 0;865tx.base.box.width = buf->base.width0;866tx.bo = NULL;867tx.map = NULL;868if (!nouveau_transfer_staging(nv, &tx, false))869return false;870nouveau_transfer_write(nv, &tx, 0, tx.base.box.width);871nouveau_buffer_transfer_del(nv, &tx);872} else873return false;874875assert(buf->domain == new_domain);876return true;877}878879/* Migrate data from glVertexAttribPointer(non-VBO) user buffers to GART.880* We'd like to only allocate @size bytes here, but then we'd have to rebase881* the vertex indices ...882*/883bool884nouveau_user_buffer_upload(struct nouveau_context *nv,885struct nv04_resource *buf,886unsigned base, unsigned size)887{888assert(!(buf->status & NOUVEAU_BUFFER_STATUS_USER_PTR));889890struct nouveau_screen *screen = nouveau_screen(buf->base.screen);891int ret;892893assert(buf->status & NOUVEAU_BUFFER_STATUS_USER_MEMORY);894895buf->base.width0 = base + size;896if (!nouveau_buffer_reallocate(screen, buf, NOUVEAU_BO_GART))897return false;898899ret = nouveau_bo_map(buf->bo, 0, nv->client);900if (ret)901return false;902memcpy((uint8_t *)buf->bo->map + buf->offset + base, buf->data + base, size);903904return true;905}906907/* Invalidate underlying buffer storage, reset fences, reallocate to non-busy908* buffer.909*/910void911nouveau_buffer_invalidate(struct pipe_context *pipe,912struct pipe_resource *resource)913{914struct nouveau_context *nv = nouveau_context(pipe);915struct nv04_resource *buf = nv04_resource(resource);916int ref = buf->base.reference.count - 1;917918assert(!(buf->status & NOUVEAU_BUFFER_STATUS_USER_PTR));919920/* Shared buffers shouldn't get reallocated */921if (unlikely(buf->base.bind & PIPE_BIND_SHARED))922return;923924/* If the buffer is sub-allocated and not currently being written, just925* wipe the valid buffer range. Otherwise we have to create fresh926* storage. (We don't keep track of fences for non-sub-allocated BO's.)927*/928if (buf->mm && !nouveau_buffer_busy(buf, PIPE_MAP_WRITE)) {929util_range_set_empty(&buf->valid_buffer_range);930} else {931nouveau_buffer_reallocate(nv->screen, buf, buf->domain);932if (ref > 0) /* any references inside context possible ? */933nv->invalidate_resource_storage(nv, &buf->base, ref);934}935}936937938/* Scratch data allocation. */939940static inline int941nouveau_scratch_bo_alloc(struct nouveau_context *nv, struct nouveau_bo **pbo,942unsigned size)943{944return nouveau_bo_new(nv->screen->device, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,9454096, size, NULL, pbo);946}947948static void949nouveau_scratch_unref_bos(void *d)950{951struct runout *b = d;952int i;953954for (i = 0; i < b->nr; ++i)955nouveau_bo_ref(NULL, &b->bo[i]);956957FREE(b);958}959960void961nouveau_scratch_runout_release(struct nouveau_context *nv)962{963if (!nv->scratch.runout)964return;965966if (!nouveau_fence_work(nv->screen->fence.current, nouveau_scratch_unref_bos,967nv->scratch.runout))968return;969970nv->scratch.end = 0;971nv->scratch.runout = NULL;972}973974/* Allocate an extra bo if we can't fit everything we need simultaneously.975* (Could happen for very large user arrays.)976*/977static inline bool978nouveau_scratch_runout(struct nouveau_context *nv, unsigned size)979{980int ret;981unsigned n;982983if (nv->scratch.runout)984n = nv->scratch.runout->nr;985else986n = 0;987nv->scratch.runout = REALLOC(nv->scratch.runout, n == 0 ? 0 :988(sizeof(*nv->scratch.runout) + (n + 0) * sizeof(void *)),989sizeof(*nv->scratch.runout) + (n + 1) * sizeof(void *));990nv->scratch.runout->nr = n + 1;991nv->scratch.runout->bo[n] = NULL;992993ret = nouveau_scratch_bo_alloc(nv, &nv->scratch.runout->bo[n], size);994if (!ret) {995ret = nouveau_bo_map(nv->scratch.runout->bo[n], 0, NULL);996if (ret)997nouveau_bo_ref(NULL, &nv->scratch.runout->bo[--nv->scratch.runout->nr]);998}999if (!ret) {1000nv->scratch.current = nv->scratch.runout->bo[n];1001nv->scratch.offset = 0;1002nv->scratch.end = size;1003nv->scratch.map = nv->scratch.current->map;1004}1005return !ret;1006}10071008/* Continue to next scratch buffer, if available (no wrapping, large enough).1009* Allocate it if it has not yet been created.1010*/1011static inline bool1012nouveau_scratch_next(struct nouveau_context *nv, unsigned size)1013{1014struct nouveau_bo *bo;1015int ret;1016const unsigned i = (nv->scratch.id + 1) % NOUVEAU_MAX_SCRATCH_BUFS;10171018if ((size > nv->scratch.bo_size) || (i == nv->scratch.wrap))1019return false;1020nv->scratch.id = i;10211022bo = nv->scratch.bo[i];1023if (!bo) {1024ret = nouveau_scratch_bo_alloc(nv, &bo, nv->scratch.bo_size);1025if (ret)1026return false;1027nv->scratch.bo[i] = bo;1028}1029nv->scratch.current = bo;1030nv->scratch.offset = 0;1031nv->scratch.end = nv->scratch.bo_size;10321033ret = nouveau_bo_map(bo, NOUVEAU_BO_WR, nv->client);1034if (!ret)1035nv->scratch.map = bo->map;1036return !ret;1037}10381039static bool1040nouveau_scratch_more(struct nouveau_context *nv, unsigned min_size)1041{1042bool ret;10431044ret = nouveau_scratch_next(nv, min_size);1045if (!ret)1046ret = nouveau_scratch_runout(nv, min_size);1047return ret;1048}104910501051/* Copy data to a scratch buffer and return address & bo the data resides in. */1052uint64_t1053nouveau_scratch_data(struct nouveau_context *nv,1054const void *data, unsigned base, unsigned size,1055struct nouveau_bo **bo)1056{1057unsigned bgn = MAX2(base, nv->scratch.offset);1058unsigned end = bgn + size;10591060if (end >= nv->scratch.end) {1061end = base + size;1062if (!nouveau_scratch_more(nv, end))1063return 0;1064bgn = base;1065}1066nv->scratch.offset = align(end, 4);10671068memcpy(nv->scratch.map + bgn, (const uint8_t *)data + base, size);10691070*bo = nv->scratch.current;1071return (*bo)->offset + (bgn - base);1072}10731074void *1075nouveau_scratch_get(struct nouveau_context *nv,1076unsigned size, uint64_t *gpu_addr, struct nouveau_bo **pbo)1077{1078unsigned bgn = nv->scratch.offset;1079unsigned end = nv->scratch.offset + size;10801081if (end >= nv->scratch.end) {1082end = size;1083if (!nouveau_scratch_more(nv, end))1084return NULL;1085bgn = 0;1086}1087nv->scratch.offset = align(end, 4);10881089*pbo = nv->scratch.current;1090*gpu_addr = nv->scratch.current->offset + bgn;1091return nv->scratch.map + bgn;1092}109310941095