Path: blob/21.2-virgl/src/gallium/drivers/nouveau/nouveau_buffer.h
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#ifndef __NOUVEAU_BUFFER_H__1#define __NOUVEAU_BUFFER_H__23#include "util/u_range.h"4#include "util/u_transfer.h"5#include "util/list.h"67struct pipe_resource;8struct nouveau_context;9struct nouveau_bo;1011/* DIRTY: buffer was (or will be after the next flush) written to by GPU and12* resource->data has not been updated to reflect modified VRAM contents13*14* USER_MEMORY: resource->data is a pointer to client memory and may change15* between GL calls16*17* USER_PTR: bo is backed by user memory mapped into the GPUs VM18*/19#define NOUVEAU_BUFFER_STATUS_GPU_READING (1 << 0)20#define NOUVEAU_BUFFER_STATUS_GPU_WRITING (1 << 1)21#define NOUVEAU_BUFFER_STATUS_DIRTY (1 << 2)22#define NOUVEAU_BUFFER_STATUS_USER_PTR (1 << 6)23#define NOUVEAU_BUFFER_STATUS_USER_MEMORY (1 << 7)2425#define NOUVEAU_BUFFER_STATUS_REALLOC_MASK NOUVEAU_BUFFER_STATUS_USER_MEMORY2627/* Resources, if mapped into the GPU's address space, are guaranteed to28* have constant virtual addresses (nv50+).29*30* The address of a resource will lie within the nouveau_bo referenced,31* and this bo should be added to the memory manager's validation list.32*/33struct nv04_resource {34struct pipe_resource base;3536uint64_t address; /* virtual address (nv50+) */3738uint8_t *data; /* resource's contents, if domain == 0, or cached */39struct nouveau_bo *bo;40uint32_t offset; /* offset into the data/bo */4142uint8_t status;43uint8_t domain;4445uint16_t cb_bindings[6]; /* per-shader per-slot bindings */4647struct nouveau_fence *fence;48struct nouveau_fence *fence_wr;4950struct nouveau_mm_allocation *mm;5152/* buffer range that has been initialized */53struct util_range valid_buffer_range;54};5556void57nouveau_buffer_release_gpu_storage(struct nv04_resource *);5859void60nouveau_copy_buffer(struct nouveau_context *,61struct nv04_resource *dst, unsigned dst_pos,62struct nv04_resource *src, unsigned src_pos, unsigned size);6364bool65nouveau_buffer_migrate(struct nouveau_context *,66struct nv04_resource *, unsigned domain);6768void *69nouveau_resource_map_offset(struct nouveau_context *, struct nv04_resource *,70uint32_t offset, uint32_t flags);7172void73nouveau_buffer_destroy(struct pipe_screen *pscreen,74struct pipe_resource *presource);7576void77nouveau_buffer_transfer_flush_region(struct pipe_context *pipe,78struct pipe_transfer *transfer,79const struct pipe_box *box);8081static inline void82nouveau_resource_unmap(struct nv04_resource *res)83{84/* no-op */85}8687static inline struct nv04_resource *88nv04_resource(struct pipe_resource *resource)89{90return (struct nv04_resource *)resource;91}9293/* is resource mapped into the GPU's address space (i.e. VRAM or GART) ? */94static inline bool95nouveau_resource_mapped_by_gpu(struct pipe_resource *resource)96{97return nv04_resource(resource)->domain != 0;98}99100struct pipe_resource *101nouveau_buffer_create(struct pipe_screen *pscreen,102const struct pipe_resource *templ);103104struct pipe_resource *105nouveau_buffer_create_from_user(struct pipe_screen *pscreen,106const struct pipe_resource *templ,107void *user_ptr);108109struct pipe_resource *110nouveau_user_buffer_create(struct pipe_screen *screen, void *ptr,111unsigned bytes, unsigned usage);112113bool114nouveau_user_buffer_upload(struct nouveau_context *, struct nv04_resource *,115unsigned base, unsigned size);116117void118nouveau_buffer_invalidate(struct pipe_context *pipe,119struct pipe_resource *resource);120121/* Copy data to a scratch buffer and return address & bo the data resides in.122* Returns 0 on failure.123*/124uint64_t125nouveau_scratch_data(struct nouveau_context *,126const void *data, unsigned base, unsigned size,127struct nouveau_bo **);128129void *130nouveau_buffer_transfer_map(struct pipe_context *pipe,131struct pipe_resource *resource,132unsigned level, unsigned usage,133const struct pipe_box *box,134struct pipe_transfer **ptransfer);135136void137nouveau_buffer_transfer_unmap(struct pipe_context *pipe,138struct pipe_transfer *transfer);139140#endif141142143