Path: blob/21.2-virgl/src/gallium/drivers/nouveau/nouveau_screen.h
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#ifndef __NOUVEAU_SCREEN_H__1#define __NOUVEAU_SCREEN_H__23#include "pipe/p_screen.h"4#include "util/disk_cache.h"5#include "util/u_atomic.h"6#include "util/u_memory.h"78#ifndef NDEBUG9# define NOUVEAU_ENABLE_DRIVER_STATISTICS10#endif1112typedef uint32_t u32;13typedef uint16_t u16;1415extern int nouveau_mesa_debug;1617struct nouveau_bo;1819#define NOUVEAU_SHADER_CACHE_FLAGS_IR_TGSI 0 << 020#define NOUVEAU_SHADER_CACHE_FLAGS_IR_NIR 1 << 02122struct nouveau_screen {23struct pipe_screen base;24struct nouveau_drm *drm;25struct nouveau_device *device;26struct nouveau_object *channel;27struct nouveau_client *client;28struct nouveau_pushbuf *pushbuf;2930char chipset_name[8];3132int refcount;3334unsigned transfer_pushbuf_threshold;3536unsigned vidmem_bindings; /* PIPE_BIND_* where VRAM placement is desired */37unsigned sysmem_bindings; /* PIPE_BIND_* where GART placement is desired */38unsigned lowmem_bindings; /* PIPE_BIND_* that require an address < 4 GiB */39/*40* For bindings with (vidmem & sysmem) bits set, PIPE_USAGE_* decides41* placement.42*/4344uint16_t class_3d;4546struct {47struct nouveau_fence *head;48struct nouveau_fence *tail;49struct nouveau_fence *current;50u32 sequence;51u32 sequence_ack;52void (*emit)(struct pipe_screen *, u32 *sequence);53u32 (*update)(struct pipe_screen *);54} fence;5556struct nouveau_mman *mm_VRAM;57struct nouveau_mman *mm_GART;5859int64_t cpu_gpu_time_delta;6061bool hint_buf_keep_sysmem_copy;62bool tegra_sector_layout;6364unsigned vram_domain;6566struct {67unsigned profiles_checked;68unsigned profiles_present;69} firmware_info;7071struct disk_cache *disk_shader_cache;7273bool prefer_nir;74bool force_enable_cl;75bool has_svm;76void *svm_cutout;77size_t svm_cutout_size;7879#ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS80union {81uint64_t v[29];82struct {83uint64_t tex_obj_current_count;84uint64_t tex_obj_current_bytes;85uint64_t buf_obj_current_count;86uint64_t buf_obj_current_bytes_vid;87uint64_t buf_obj_current_bytes_sys;88uint64_t tex_transfers_rd;89uint64_t tex_transfers_wr;90uint64_t tex_copy_count;91uint64_t tex_blit_count;92uint64_t tex_cache_flush_count;93uint64_t buf_transfers_rd;94uint64_t buf_transfers_wr;95uint64_t buf_read_bytes_staging_vid;96uint64_t buf_write_bytes_direct;97uint64_t buf_write_bytes_staging_vid;98uint64_t buf_write_bytes_staging_sys;99uint64_t buf_copy_bytes;100uint64_t buf_non_kernel_fence_sync_count;101uint64_t any_non_kernel_fence_sync_count;102uint64_t query_sync_count;103uint64_t gpu_serialize_count;104uint64_t draw_calls_array;105uint64_t draw_calls_indexed;106uint64_t draw_calls_fallback_count;107uint64_t user_buffer_upload_bytes;108uint64_t constbuf_upload_count;109uint64_t constbuf_upload_bytes;110uint64_t pushbuf_count;111uint64_t resource_validate_count;112} named;113} stats;114#endif115};116117#define NV_VRAM_DOMAIN(screen) ((screen)->vram_domain)118119#ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS120# define NOUVEAU_DRV_STAT(s, n, v) do { \121p_atomic_add(&(s)->stats.named.n, (v)); \122} while(0)123# define NOUVEAU_DRV_STAT_RES(r, n, v) do { \124p_atomic_add(&nouveau_screen((r)->base.screen)->stats.named.n, v); \125} while(0)126# define NOUVEAU_DRV_STAT_IFD(x) x127#else128# define NOUVEAU_DRV_STAT(s, n, v) do { } while(0)129# define NOUVEAU_DRV_STAT_RES(r, n, v) do { } while(0)130# define NOUVEAU_DRV_STAT_IFD(x)131#endif132133static inline struct nouveau_screen *134nouveau_screen(struct pipe_screen *pscreen)135{136return (struct nouveau_screen *)pscreen;137}138139bool nouveau_drm_screen_unref(struct nouveau_screen *screen);140141bool142nouveau_screen_bo_get_handle(struct pipe_screen *pscreen,143struct nouveau_bo *bo,144unsigned stride,145struct winsys_handle *whandle);146struct nouveau_bo *147nouveau_screen_bo_from_handle(struct pipe_screen *pscreen,148struct winsys_handle *whandle,149unsigned *out_stride);150151152int nouveau_screen_init(struct nouveau_screen *, struct nouveau_device *);153void nouveau_screen_fini(struct nouveau_screen *);154155void nouveau_screen_init_vdec(struct nouveau_screen *);156157#endif158159160