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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/nouveau/nouveau_screen.h
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#ifndef __NOUVEAU_SCREEN_H__
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#define __NOUVEAU_SCREEN_H__
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#include "pipe/p_screen.h"
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#include "util/disk_cache.h"
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#include "util/u_atomic.h"
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#include "util/u_memory.h"
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#ifndef NDEBUG
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# define NOUVEAU_ENABLE_DRIVER_STATISTICS
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#endif
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typedef uint32_t u32;
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typedef uint16_t u16;
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extern int nouveau_mesa_debug;
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struct nouveau_bo;
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#define NOUVEAU_SHADER_CACHE_FLAGS_IR_TGSI 0 << 0
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#define NOUVEAU_SHADER_CACHE_FLAGS_IR_NIR 1 << 0
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struct nouveau_screen {
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struct pipe_screen base;
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struct nouveau_drm *drm;
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struct nouveau_device *device;
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struct nouveau_object *channel;
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struct nouveau_client *client;
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struct nouveau_pushbuf *pushbuf;
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char chipset_name[8];
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int refcount;
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unsigned transfer_pushbuf_threshold;
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unsigned vidmem_bindings; /* PIPE_BIND_* where VRAM placement is desired */
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unsigned sysmem_bindings; /* PIPE_BIND_* where GART placement is desired */
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unsigned lowmem_bindings; /* PIPE_BIND_* that require an address < 4 GiB */
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/*
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* For bindings with (vidmem & sysmem) bits set, PIPE_USAGE_* decides
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* placement.
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*/
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uint16_t class_3d;
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struct {
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struct nouveau_fence *head;
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struct nouveau_fence *tail;
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struct nouveau_fence *current;
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u32 sequence;
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u32 sequence_ack;
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void (*emit)(struct pipe_screen *, u32 *sequence);
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u32 (*update)(struct pipe_screen *);
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} fence;
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struct nouveau_mman *mm_VRAM;
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struct nouveau_mman *mm_GART;
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int64_t cpu_gpu_time_delta;
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bool hint_buf_keep_sysmem_copy;
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bool tegra_sector_layout;
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unsigned vram_domain;
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struct {
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unsigned profiles_checked;
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unsigned profiles_present;
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} firmware_info;
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struct disk_cache *disk_shader_cache;
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bool prefer_nir;
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bool force_enable_cl;
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bool has_svm;
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void *svm_cutout;
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size_t svm_cutout_size;
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#ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
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union {
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uint64_t v[29];
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struct {
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uint64_t tex_obj_current_count;
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uint64_t tex_obj_current_bytes;
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uint64_t buf_obj_current_count;
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uint64_t buf_obj_current_bytes_vid;
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uint64_t buf_obj_current_bytes_sys;
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uint64_t tex_transfers_rd;
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uint64_t tex_transfers_wr;
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uint64_t tex_copy_count;
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uint64_t tex_blit_count;
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uint64_t tex_cache_flush_count;
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uint64_t buf_transfers_rd;
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uint64_t buf_transfers_wr;
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uint64_t buf_read_bytes_staging_vid;
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uint64_t buf_write_bytes_direct;
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uint64_t buf_write_bytes_staging_vid;
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uint64_t buf_write_bytes_staging_sys;
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uint64_t buf_copy_bytes;
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uint64_t buf_non_kernel_fence_sync_count;
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uint64_t any_non_kernel_fence_sync_count;
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uint64_t query_sync_count;
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uint64_t gpu_serialize_count;
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uint64_t draw_calls_array;
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uint64_t draw_calls_indexed;
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uint64_t draw_calls_fallback_count;
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uint64_t user_buffer_upload_bytes;
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uint64_t constbuf_upload_count;
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uint64_t constbuf_upload_bytes;
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uint64_t pushbuf_count;
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uint64_t resource_validate_count;
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} named;
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} stats;
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#endif
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};
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#define NV_VRAM_DOMAIN(screen) ((screen)->vram_domain)
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#ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
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# define NOUVEAU_DRV_STAT(s, n, v) do { \
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p_atomic_add(&(s)->stats.named.n, (v)); \
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} while(0)
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# define NOUVEAU_DRV_STAT_RES(r, n, v) do { \
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p_atomic_add(&nouveau_screen((r)->base.screen)->stats.named.n, v); \
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} while(0)
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# define NOUVEAU_DRV_STAT_IFD(x) x
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#else
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# define NOUVEAU_DRV_STAT(s, n, v) do { } while(0)
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# define NOUVEAU_DRV_STAT_RES(r, n, v) do { } while(0)
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# define NOUVEAU_DRV_STAT_IFD(x)
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#endif
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static inline struct nouveau_screen *
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nouveau_screen(struct pipe_screen *pscreen)
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{
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return (struct nouveau_screen *)pscreen;
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}
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bool nouveau_drm_screen_unref(struct nouveau_screen *screen);
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bool
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nouveau_screen_bo_get_handle(struct pipe_screen *pscreen,
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struct nouveau_bo *bo,
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unsigned stride,
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struct winsys_handle *whandle);
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struct nouveau_bo *
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nouveau_screen_bo_from_handle(struct pipe_screen *pscreen,
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struct winsys_handle *whandle,
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unsigned *out_stride);
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int nouveau_screen_init(struct nouveau_screen *, struct nouveau_device *);
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void nouveau_screen_fini(struct nouveau_screen *);
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void nouveau_screen_init_vdec(struct nouveau_screen *);
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#endif
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