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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/nouveau/nv50/nv50_state.c
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/*
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* Copyright 2010 Christoph Bumiller
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "pipe/p_defines.h"
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#include "util/u_framebuffer.h"
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#include "util/u_helpers.h"
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#include "util/u_inlines.h"
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#include "util/u_transfer.h"
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#include "util/format_srgb.h"
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#include "tgsi/tgsi_parse.h"
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#include "compiler/nir/nir.h"
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#include "nv50/nv50_stateobj.h"
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#include "nv50/nv50_context.h"
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#include "nv50/nv50_query_hw.h"
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#include "nv50/nv50_3d.xml.h"
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#include "nv50/g80_texture.xml.h"
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#include "nouveau_gldefs.h"
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/* Caveats:
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* ! pipe_sampler_state.normalized_coords is ignored - rectangle textures will
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* use non-normalized coordinates, everything else won't
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* (The relevant bit is in the TIC entry and not the TSC entry.)
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*
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* ! pipe_sampler_state.seamless_cube_map is ignored - seamless filtering is
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* always activated on NVA0 +
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* (Give me the global bit, otherwise it's not worth the CPU work.)
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*
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* ! pipe_sampler_state.border_color is not swizzled according to the texture
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* swizzle in pipe_sampler_view
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* (This will be ugly with indirect independent texture/sampler access,
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* we'd have to emulate the logic in the shader. GL doesn't have that,
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* D3D doesn't have swizzle, if we knew what we were implementing we'd be
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* good.)
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*
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* ! pipe_rasterizer_state.line_last_pixel is ignored - it is never drawn
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*
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* ! pipe_rasterizer_state.flatshade_first also applies to QUADS
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* (There's a GL query for that, forcing an exception is just ridiculous.)
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*
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* ! pipe_rasterizer_state.sprite_coord_enable is masked with 0xff on NVC0
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* (The hardware only has 8 slots meant for TexCoord and we have to assign
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* in advance to maintain elegant separate shader objects.)
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*/
67
68
static inline uint32_t
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nv50_colormask(unsigned mask)
70
{
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uint32_t ret = 0;
72
73
if (mask & PIPE_MASK_R)
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ret |= 0x0001;
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if (mask & PIPE_MASK_G)
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ret |= 0x0010;
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if (mask & PIPE_MASK_B)
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ret |= 0x0100;
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if (mask & PIPE_MASK_A)
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ret |= 0x1000;
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return ret;
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}
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#define NV50_BLEND_FACTOR_CASE(a, b) \
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case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
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static inline uint32_t
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nv50_blend_fac(unsigned factor)
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{
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switch (factor) {
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NV50_BLEND_FACTOR_CASE(ONE, ONE);
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NV50_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
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NV50_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
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NV50_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
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NV50_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
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NV50_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
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NV50_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
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NV50_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
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NV50_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
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NV50_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
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NV50_BLEND_FACTOR_CASE(ZERO, ZERO);
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NV50_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
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NV50_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
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NV50_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
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NV50_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
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NV50_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
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NV50_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
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NV50_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
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NV50_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
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default:
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return NV50_BLEND_FACTOR_ZERO;
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}
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}
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static void *
117
nv50_blend_state_create(struct pipe_context *pipe,
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const struct pipe_blend_state *cso)
119
{
120
struct nv50_blend_stateobj *so = CALLOC_STRUCT(nv50_blend_stateobj);
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int i;
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bool emit_common_func = cso->rt[0].blend_enable;
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uint32_t ms;
124
125
if (nv50_context(pipe)->screen->tesla->oclass >= NVA3_3D_CLASS) {
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SB_BEGIN_3D(so, BLEND_INDEPENDENT, 1);
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SB_DATA (so, cso->independent_blend_enable);
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}
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so->pipe = *cso;
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SB_BEGIN_3D(so, COLOR_MASK_COMMON, 1);
133
SB_DATA (so, !cso->independent_blend_enable);
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SB_BEGIN_3D(so, BLEND_ENABLE_COMMON, 1);
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SB_DATA (so, !cso->independent_blend_enable);
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if (cso->independent_blend_enable) {
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SB_BEGIN_3D(so, BLEND_ENABLE(0), 8);
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for (i = 0; i < 8; ++i) {
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SB_DATA(so, cso->rt[i].blend_enable);
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if (cso->rt[i].blend_enable)
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emit_common_func = true;
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}
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146
if (nv50_context(pipe)->screen->tesla->oclass >= NVA3_3D_CLASS) {
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emit_common_func = false;
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for (i = 0; i < 8; ++i) {
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if (!cso->rt[i].blend_enable)
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continue;
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SB_BEGIN_3D_(so, NVA3_3D_IBLEND_EQUATION_RGB(i), 6);
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SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
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SB_DATA (so, nv50_blend_fac(cso->rt[i].rgb_src_factor));
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SB_DATA (so, nv50_blend_fac(cso->rt[i].rgb_dst_factor));
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SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
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SB_DATA (so, nv50_blend_fac(cso->rt[i].alpha_src_factor));
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SB_DATA (so, nv50_blend_fac(cso->rt[i].alpha_dst_factor));
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}
160
}
161
} else {
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SB_BEGIN_3D(so, BLEND_ENABLE(0), 1);
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SB_DATA (so, cso->rt[0].blend_enable);
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}
165
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if (emit_common_func) {
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SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
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SB_DATA (so, nvgl_blend_eqn(cso->rt[0].rgb_func));
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SB_DATA (so, nv50_blend_fac(cso->rt[0].rgb_src_factor));
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SB_DATA (so, nv50_blend_fac(cso->rt[0].rgb_dst_factor));
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SB_DATA (so, nvgl_blend_eqn(cso->rt[0].alpha_func));
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SB_DATA (so, nv50_blend_fac(cso->rt[0].alpha_src_factor));
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SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
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SB_DATA (so, nv50_blend_fac(cso->rt[0].alpha_dst_factor));
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}
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if (cso->logicop_enable) {
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SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
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SB_DATA (so, 1);
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SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
181
} else {
182
SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 1);
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SB_DATA (so, 0);
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}
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186
if (cso->independent_blend_enable) {
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SB_BEGIN_3D(so, COLOR_MASK(0), 8);
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for (i = 0; i < 8; ++i)
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SB_DATA(so, nv50_colormask(cso->rt[i].colormask));
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} else {
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SB_BEGIN_3D(so, COLOR_MASK(0), 1);
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SB_DATA (so, nv50_colormask(cso->rt[0].colormask));
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}
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ms = 0;
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if (cso->alpha_to_coverage)
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ms |= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
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if (cso->alpha_to_one)
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ms |= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
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SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
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SB_DATA (so, ms);
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assert(so->size <= ARRAY_SIZE(so->state));
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return so;
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}
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static void
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nv50_blend_state_bind(struct pipe_context *pipe, void *hwcso)
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{
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struct nv50_context *nv50 = nv50_context(pipe);
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nv50->blend = hwcso;
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nv50->dirty_3d |= NV50_NEW_3D_BLEND;
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}
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static void
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nv50_blend_state_delete(struct pipe_context *pipe, void *hwcso)
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{
220
FREE(hwcso);
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}
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/* NOTE: ignoring line_last_pixel */
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static void *
225
nv50_rasterizer_state_create(struct pipe_context *pipe,
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const struct pipe_rasterizer_state *cso)
227
{
228
struct nv50_rasterizer_stateobj *so;
229
uint32_t reg;
230
231
so = CALLOC_STRUCT(nv50_rasterizer_stateobj);
232
if (!so)
233
return NULL;
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so->pipe = *cso;
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#ifndef NV50_SCISSORS_CLIPPING
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for (int i = 0; i < NV50_MAX_VIEWPORTS; i++) {
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SB_BEGIN_3D(so, SCISSOR_ENABLE(i), 1);
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SB_DATA (so, cso->scissor);
240
}
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#endif
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243
SB_BEGIN_3D(so, SHADE_MODEL, 1);
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SB_DATA (so, cso->flatshade ? NV50_3D_SHADE_MODEL_FLAT :
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NV50_3D_SHADE_MODEL_SMOOTH);
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SB_BEGIN_3D(so, PROVOKING_VERTEX_LAST, 1);
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SB_DATA (so, !cso->flatshade_first);
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SB_BEGIN_3D(so, VERTEX_TWO_SIDE_ENABLE, 1);
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SB_DATA (so, cso->light_twoside);
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SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
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SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
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254
SB_BEGIN_3D(so, MULTISAMPLE_ENABLE, 1);
255
SB_DATA (so, cso->multisample);
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257
SB_BEGIN_3D(so, LINE_WIDTH, 1);
258
SB_DATA (so, fui(cso->line_width));
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SB_BEGIN_3D(so, LINE_SMOOTH_ENABLE, 1);
260
SB_DATA (so, cso->line_smooth);
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262
SB_BEGIN_3D(so, LINE_STIPPLE_ENABLE, 1);
263
if (cso->line_stipple_enable) {
264
SB_DATA (so, 1);
265
SB_BEGIN_3D(so, LINE_STIPPLE, 1);
266
SB_DATA (so, (cso->line_stipple_pattern << 8) |
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cso->line_stipple_factor);
268
} else {
269
SB_DATA (so, 0);
270
}
271
272
if (!cso->point_size_per_vertex) {
273
SB_BEGIN_3D(so, POINT_SIZE, 1);
274
SB_DATA (so, fui(cso->point_size));
275
}
276
SB_BEGIN_3D(so, POINT_SPRITE_ENABLE, 1);
277
SB_DATA (so, cso->point_quad_rasterization);
278
SB_BEGIN_3D(so, POINT_SMOOTH_ENABLE, 1);
279
SB_DATA (so, cso->point_smooth);
280
281
SB_BEGIN_3D(so, POLYGON_MODE_FRONT, 3);
282
SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
283
SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
284
SB_DATA (so, cso->poly_smooth);
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286
SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
287
SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
288
SB_DATA (so, cso->front_ccw ? NV50_3D_FRONT_FACE_CCW :
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NV50_3D_FRONT_FACE_CW);
290
switch (cso->cull_face) {
291
case PIPE_FACE_FRONT_AND_BACK:
292
SB_DATA(so, NV50_3D_CULL_FACE_FRONT_AND_BACK);
293
break;
294
case PIPE_FACE_FRONT:
295
SB_DATA(so, NV50_3D_CULL_FACE_FRONT);
296
break;
297
case PIPE_FACE_BACK:
298
default:
299
SB_DATA(so, NV50_3D_CULL_FACE_BACK);
300
break;
301
}
302
303
SB_BEGIN_3D(so, POLYGON_STIPPLE_ENABLE, 1);
304
SB_DATA (so, cso->poly_stipple_enable);
305
SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
306
SB_DATA (so, cso->offset_point);
307
SB_DATA (so, cso->offset_line);
308
SB_DATA (so, cso->offset_tri);
309
310
if (cso->offset_point || cso->offset_line || cso->offset_tri) {
311
SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
312
SB_DATA (so, fui(cso->offset_scale));
313
SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
314
SB_DATA (so, fui(cso->offset_units * 2.0f));
315
SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
316
SB_DATA (so, fui(cso->offset_clamp));
317
}
318
319
if (cso->depth_clip_near) {
320
reg = 0;
321
} else {
322
reg =
323
NV50_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
324
NV50_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
325
NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK1;
326
}
327
#ifndef NV50_SCISSORS_CLIPPING
328
reg |=
329
NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK7 |
330
NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK1;
331
#endif
332
SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
333
SB_DATA (so, reg);
334
335
SB_BEGIN_3D(so, DEPTH_CLIP_NEGATIVE_Z, 1);
336
SB_DATA (so, cso->clip_halfz);
337
338
SB_BEGIN_3D(so, PIXEL_CENTER_INTEGER, 1);
339
SB_DATA (so, !cso->half_pixel_center);
340
341
assert(so->size <= ARRAY_SIZE(so->state));
342
return (void *)so;
343
}
344
345
static void
346
nv50_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
347
{
348
struct nv50_context *nv50 = nv50_context(pipe);
349
350
nv50->rast = hwcso;
351
nv50->dirty_3d |= NV50_NEW_3D_RASTERIZER;
352
}
353
354
static void
355
nv50_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
356
{
357
FREE(hwcso);
358
}
359
360
static void *
361
nv50_zsa_state_create(struct pipe_context *pipe,
362
const struct pipe_depth_stencil_alpha_state *cso)
363
{
364
struct nv50_zsa_stateobj *so = CALLOC_STRUCT(nv50_zsa_stateobj);
365
366
so->pipe = *cso;
367
368
SB_BEGIN_3D(so, DEPTH_WRITE_ENABLE, 1);
369
SB_DATA (so, cso->depth_writemask);
370
SB_BEGIN_3D(so, DEPTH_TEST_ENABLE, 1);
371
if (cso->depth_enabled) {
372
SB_DATA (so, 1);
373
SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
374
SB_DATA (so, nvgl_comparison_op(cso->depth_func));
375
} else {
376
SB_DATA (so, 0);
377
}
378
379
SB_BEGIN_3D(so, DEPTH_BOUNDS_EN, 1);
380
if (cso->depth_bounds_test) {
381
SB_DATA (so, 1);
382
SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
383
SB_DATA (so, fui(cso->depth_bounds_min));
384
SB_DATA (so, fui(cso->depth_bounds_max));
385
} else {
386
SB_DATA (so, 0);
387
}
388
389
if (cso->stencil[0].enabled) {
390
SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
391
SB_DATA (so, 1);
392
SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
393
SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
394
SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
395
SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
396
SB_BEGIN_3D(so, STENCIL_FRONT_MASK, 2);
397
SB_DATA (so, cso->stencil[0].writemask);
398
SB_DATA (so, cso->stencil[0].valuemask);
399
} else {
400
SB_BEGIN_3D(so, STENCIL_ENABLE, 1);
401
SB_DATA (so, 0);
402
}
403
404
if (cso->stencil[1].enabled) {
405
assert(cso->stencil[0].enabled);
406
SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
407
SB_DATA (so, 1);
408
SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
409
SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
410
SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
411
SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
412
SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
413
SB_DATA (so, cso->stencil[1].writemask);
414
SB_DATA (so, cso->stencil[1].valuemask);
415
} else {
416
SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 1);
417
SB_DATA (so, 0);
418
}
419
420
SB_BEGIN_3D(so, ALPHA_TEST_ENABLE, 1);
421
if (cso->alpha_enabled) {
422
SB_DATA (so, 1);
423
SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
424
SB_DATA (so, fui(cso->alpha_ref_value));
425
SB_DATA (so, nvgl_comparison_op(cso->alpha_func));
426
} else {
427
SB_DATA (so, 0);
428
}
429
430
SB_BEGIN_3D(so, CB_ADDR, 1);
431
SB_DATA (so, NV50_CB_AUX_ALPHATEST_OFFSET << (8 - 2) | NV50_CB_AUX);
432
SB_BEGIN_3D(so, CB_DATA(0), 1);
433
SB_DATA (so, fui(cso->alpha_ref_value));
434
435
assert(so->size <= ARRAY_SIZE(so->state));
436
return (void *)so;
437
}
438
439
static void
440
nv50_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
441
{
442
struct nv50_context *nv50 = nv50_context(pipe);
443
444
nv50->zsa = hwcso;
445
nv50->dirty_3d |= NV50_NEW_3D_ZSA;
446
}
447
448
static void
449
nv50_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
450
{
451
FREE(hwcso);
452
}
453
454
/* ====================== SAMPLERS AND TEXTURES ================================
455
*/
456
457
static inline unsigned
458
nv50_tsc_wrap_mode(unsigned wrap)
459
{
460
switch (wrap) {
461
case PIPE_TEX_WRAP_REPEAT:
462
return G80_TSC_WRAP_WRAP;
463
case PIPE_TEX_WRAP_MIRROR_REPEAT:
464
return G80_TSC_WRAP_MIRROR;
465
case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
466
return G80_TSC_WRAP_CLAMP_TO_EDGE;
467
case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
468
return G80_TSC_WRAP_BORDER;
469
case PIPE_TEX_WRAP_CLAMP:
470
return G80_TSC_WRAP_CLAMP_OGL;
471
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
472
return G80_TSC_WRAP_MIRROR_ONCE_CLAMP_TO_EDGE;
473
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
474
return G80_TSC_WRAP_MIRROR_ONCE_BORDER;
475
case PIPE_TEX_WRAP_MIRROR_CLAMP:
476
return G80_TSC_WRAP_MIRROR_ONCE_CLAMP_OGL;
477
default:
478
NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
479
return G80_TSC_WRAP_WRAP;
480
}
481
}
482
483
void *
484
nv50_sampler_state_create(struct pipe_context *pipe,
485
const struct pipe_sampler_state *cso)
486
{
487
struct nv50_tsc_entry *so = MALLOC_STRUCT(nv50_tsc_entry);
488
float f[2];
489
490
so->id = -1;
491
492
so->tsc[0] = (0x00026000 |
493
(nv50_tsc_wrap_mode(cso->wrap_s) << 0) |
494
(nv50_tsc_wrap_mode(cso->wrap_t) << 3) |
495
(nv50_tsc_wrap_mode(cso->wrap_r) << 6));
496
497
switch (cso->mag_img_filter) {
498
case PIPE_TEX_FILTER_LINEAR:
499
so->tsc[1] = G80_TSC_1_MAG_FILTER_LINEAR;
500
break;
501
case PIPE_TEX_FILTER_NEAREST:
502
default:
503
so->tsc[1] = G80_TSC_1_MAG_FILTER_NEAREST;
504
break;
505
}
506
507
switch (cso->min_img_filter) {
508
case PIPE_TEX_FILTER_LINEAR:
509
so->tsc[1] |= G80_TSC_1_MIN_FILTER_LINEAR;
510
break;
511
case PIPE_TEX_FILTER_NEAREST:
512
default:
513
so->tsc[1] |= G80_TSC_1_MIN_FILTER_NEAREST;
514
break;
515
}
516
517
switch (cso->min_mip_filter) {
518
case PIPE_TEX_MIPFILTER_LINEAR:
519
so->tsc[1] |= G80_TSC_1_MIP_FILTER_LINEAR;
520
break;
521
case PIPE_TEX_MIPFILTER_NEAREST:
522
so->tsc[1] |= G80_TSC_1_MIP_FILTER_NEAREST;
523
break;
524
case PIPE_TEX_MIPFILTER_NONE:
525
default:
526
so->tsc[1] |= G80_TSC_1_MIP_FILTER_NONE;
527
break;
528
}
529
530
if (nouveau_screen(pipe->screen)->class_3d >= NVE4_3D_CLASS) {
531
if (cso->seamless_cube_map)
532
so->tsc[1] |= GK104_TSC_1_CUBEMAP_INTERFACE_FILTERING;
533
if (!cso->normalized_coords)
534
so->tsc[1] |= GK104_TSC_1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS;
535
} else {
536
so->seamless_cube_map = cso->seamless_cube_map;
537
}
538
539
if (nouveau_screen(pipe->screen)->class_3d >= GM200_3D_CLASS) {
540
if (cso->reduction_mode == PIPE_TEX_REDUCTION_MIN)
541
so->tsc[1] |= GM204_TSC_1_REDUCTION_MODE_MIN;
542
if (cso->reduction_mode == PIPE_TEX_REDUCTION_MAX)
543
so->tsc[1] |= GM204_TSC_1_REDUCTION_MODE_MAX;
544
}
545
546
if (cso->max_anisotropy >= 16)
547
so->tsc[0] |= (7 << 20);
548
else
549
if (cso->max_anisotropy >= 12)
550
so->tsc[0] |= (6 << 20);
551
else {
552
so->tsc[0] |= (cso->max_anisotropy >> 1) << 20;
553
554
if (cso->max_anisotropy >= 4)
555
so->tsc[1] |= 6 << G80_TSC_1_TRILIN_OPT__SHIFT;
556
else
557
if (cso->max_anisotropy >= 2)
558
so->tsc[1] |= 4 << G80_TSC_1_TRILIN_OPT__SHIFT;
559
}
560
561
if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
562
/* NOTE: must be deactivated for non-shadow textures */
563
so->tsc[0] |= (1 << 9);
564
so->tsc[0] |= (nvgl_comparison_op(cso->compare_func) & 0x7) << 10;
565
}
566
567
f[0] = CLAMP(cso->lod_bias, -16.0f, 15.0f);
568
so->tsc[1] |= ((int)(f[0] * 256.0f) & 0x1fff) << 12;
569
570
f[0] = CLAMP(cso->min_lod, 0.0f, 15.0f);
571
f[1] = CLAMP(cso->max_lod, 0.0f, 15.0f);
572
so->tsc[2] =
573
(((int)(f[1] * 256.0f) & 0xfff) << 12) | ((int)(f[0] * 256.0f) & 0xfff);
574
575
so->tsc[2] |=
576
util_format_linear_float_to_srgb_8unorm(cso->border_color.f[0]) << 24;
577
so->tsc[3] =
578
util_format_linear_float_to_srgb_8unorm(cso->border_color.f[1]) << 12;
579
so->tsc[3] |=
580
util_format_linear_float_to_srgb_8unorm(cso->border_color.f[2]) << 20;
581
582
so->tsc[4] = fui(cso->border_color.f[0]);
583
so->tsc[5] = fui(cso->border_color.f[1]);
584
so->tsc[6] = fui(cso->border_color.f[2]);
585
so->tsc[7] = fui(cso->border_color.f[3]);
586
587
return (void *)so;
588
}
589
590
static void
591
nv50_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
592
{
593
unsigned s, i;
594
595
for (s = 0; s < NV50_MAX_SHADER_STAGES; ++s) {
596
assert(nv50_context(pipe)->num_samplers[s] <= PIPE_MAX_SAMPLERS);
597
for (i = 0; i < nv50_context(pipe)->num_samplers[s]; ++i)
598
if (nv50_context(pipe)->samplers[s][i] == hwcso)
599
nv50_context(pipe)->samplers[s][i] = NULL;
600
}
601
602
nv50_screen_tsc_free(nv50_context(pipe)->screen, nv50_tsc_entry(hwcso));
603
604
FREE(hwcso);
605
}
606
607
static inline void
608
nv50_stage_sampler_states_bind(struct nv50_context *nv50, int s,
609
unsigned nr, void **hwcsos)
610
{
611
unsigned highest_found = 0;
612
unsigned i;
613
614
assert(nr <= PIPE_MAX_SAMPLERS);
615
for (i = 0; i < nr; ++i) {
616
struct nv50_tsc_entry *hwcso = hwcsos ? nv50_tsc_entry(hwcsos[i]) : NULL;
617
struct nv50_tsc_entry *old = nv50->samplers[s][i];
618
619
if (hwcso)
620
highest_found = i;
621
622
nv50->samplers[s][i] = hwcso;
623
if (old)
624
nv50_screen_tsc_unlock(nv50->screen, old);
625
}
626
assert(nv50->num_samplers[s] <= PIPE_MAX_SAMPLERS);
627
if (nr >= nv50->num_samplers[s])
628
nv50->num_samplers[s] = highest_found + 1;
629
}
630
631
static void
632
nv50_bind_sampler_states(struct pipe_context *pipe,
633
enum pipe_shader_type shader, unsigned start,
634
unsigned num_samplers, void **samplers)
635
{
636
unsigned s = nv50_context_shader_stage(shader);
637
638
assert(start == 0);
639
nv50_stage_sampler_states_bind(nv50_context(pipe), s, num_samplers,
640
samplers);
641
642
if (unlikely(s == NV50_SHADER_STAGE_COMPUTE))
643
nv50_context(pipe)->dirty_cp |= NV50_NEW_CP_SAMPLERS;
644
else
645
nv50_context(pipe)->dirty_3d |= NV50_NEW_3D_SAMPLERS;
646
}
647
648
649
650
/* NOTE: only called when not referenced anywhere, won't be bound */
651
static void
652
nv50_sampler_view_destroy(struct pipe_context *pipe,
653
struct pipe_sampler_view *view)
654
{
655
pipe_resource_reference(&view->texture, NULL);
656
657
nv50_screen_tic_free(nv50_context(pipe)->screen, nv50_tic_entry(view));
658
659
FREE(nv50_tic_entry(view));
660
}
661
662
static inline void
663
nv50_stage_set_sampler_views(struct nv50_context *nv50, int s,
664
unsigned nr,
665
struct pipe_sampler_view **views)
666
{
667
unsigned i;
668
669
assert(nr <= PIPE_MAX_SAMPLERS);
670
for (i = 0; i < nr; ++i) {
671
struct pipe_sampler_view *view = views ? views[i] : NULL;
672
struct nv50_tic_entry *old = nv50_tic_entry(nv50->textures[s][i]);
673
if (old)
674
nv50_screen_tic_unlock(nv50->screen, old);
675
676
if (view && view->texture) {
677
struct pipe_resource *res = view->texture;
678
if (res->target == PIPE_BUFFER &&
679
(res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
680
nv50->textures_coherent[s] |= 1 << i;
681
else
682
nv50->textures_coherent[s] &= ~(1 << i);
683
} else {
684
nv50->textures_coherent[s] &= ~(1 << i);
685
}
686
687
pipe_sampler_view_reference(&nv50->textures[s][i], view);
688
}
689
690
assert(nv50->num_textures[s] <= PIPE_MAX_SAMPLERS);
691
for (i = nr; i < nv50->num_textures[s]; ++i) {
692
struct nv50_tic_entry *old = nv50_tic_entry(nv50->textures[s][i]);
693
if (!old)
694
continue;
695
nv50_screen_tic_unlock(nv50->screen, old);
696
697
pipe_sampler_view_reference(&nv50->textures[s][i], NULL);
698
}
699
700
nv50->num_textures[s] = nr;
701
}
702
703
static void
704
nv50_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
705
unsigned start, unsigned nr,
706
unsigned unbind_num_trailing_slots,
707
struct pipe_sampler_view **views)
708
{
709
struct nv50_context *nv50 = nv50_context(pipe);
710
unsigned s = nv50_context_shader_stage(shader);
711
712
assert(start == 0);
713
nv50_stage_set_sampler_views(nv50, s, nr, views);
714
715
if (unlikely(s == NV50_SHADER_STAGE_COMPUTE)) {
716
nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_TEXTURES);
717
718
nv50->dirty_cp |= NV50_NEW_CP_TEXTURES;
719
} else {
720
nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TEXTURES);
721
722
nv50->dirty_3d |= NV50_NEW_3D_TEXTURES;
723
}
724
}
725
726
727
728
/* ============================= SHADERS =======================================
729
*/
730
731
static void *
732
nv50_sp_state_create(struct pipe_context *pipe,
733
const struct pipe_shader_state *cso,
734
enum pipe_shader_type type)
735
{
736
struct nv50_program *prog;
737
738
prog = CALLOC_STRUCT(nv50_program);
739
if (!prog)
740
return NULL;
741
742
prog->type = type;
743
prog->pipe.type = cso->type;
744
745
switch (cso->type) {
746
case PIPE_SHADER_IR_TGSI:
747
prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
748
break;
749
case PIPE_SHADER_IR_NIR:
750
prog->pipe.ir.nir = cso->ir.nir;
751
break;
752
default:
753
assert(!"unsupported IR!");
754
free(prog);
755
return NULL;
756
}
757
758
if (cso->stream_output.num_outputs)
759
prog->pipe.stream_output = cso->stream_output;
760
761
prog->translated = nv50_program_translate(
762
prog, nv50_context(pipe)->screen->base.device->chipset,
763
&nouveau_context(pipe)->debug);
764
765
return (void *)prog;
766
}
767
768
static void
769
nv50_sp_state_delete(struct pipe_context *pipe, void *hwcso)
770
{
771
struct nv50_program *prog = (struct nv50_program *)hwcso;
772
773
nv50_program_destroy(nv50_context(pipe), prog);
774
775
if (prog->pipe.type == PIPE_SHADER_IR_TGSI)
776
FREE((void *)prog->pipe.tokens);
777
else if (prog->pipe.type == PIPE_SHADER_IR_NIR)
778
ralloc_free(prog->pipe.ir.nir);
779
FREE(prog);
780
}
781
782
static void *
783
nv50_vp_state_create(struct pipe_context *pipe,
784
const struct pipe_shader_state *cso)
785
{
786
return nv50_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
787
}
788
789
static void
790
nv50_vp_state_bind(struct pipe_context *pipe, void *hwcso)
791
{
792
struct nv50_context *nv50 = nv50_context(pipe);
793
794
nv50->vertprog = hwcso;
795
nv50->dirty_3d |= NV50_NEW_3D_VERTPROG;
796
}
797
798
static void *
799
nv50_fp_state_create(struct pipe_context *pipe,
800
const struct pipe_shader_state *cso)
801
{
802
return nv50_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
803
}
804
805
static void
806
nv50_fp_state_bind(struct pipe_context *pipe, void *hwcso)
807
{
808
struct nv50_context *nv50 = nv50_context(pipe);
809
810
nv50->fragprog = hwcso;
811
nv50->dirty_3d |= NV50_NEW_3D_FRAGPROG;
812
}
813
814
static void *
815
nv50_gp_state_create(struct pipe_context *pipe,
816
const struct pipe_shader_state *cso)
817
{
818
return nv50_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
819
}
820
821
static void
822
nv50_gp_state_bind(struct pipe_context *pipe, void *hwcso)
823
{
824
struct nv50_context *nv50 = nv50_context(pipe);
825
826
nv50->gmtyprog = hwcso;
827
nv50->dirty_3d |= NV50_NEW_3D_GMTYPROG;
828
}
829
830
static void *
831
nv50_cp_state_create(struct pipe_context *pipe,
832
const struct pipe_compute_state *cso)
833
{
834
struct nv50_program *prog;
835
836
prog = CALLOC_STRUCT(nv50_program);
837
if (!prog)
838
return NULL;
839
prog->type = PIPE_SHADER_COMPUTE;
840
prog->pipe.type = cso->ir_type;
841
842
switch(cso->ir_type) {
843
case PIPE_SHADER_IR_TGSI:
844
prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
845
break;
846
case PIPE_SHADER_IR_NIR:
847
prog->pipe.ir.nir = (nir_shader *)cso->prog;
848
break;
849
default:
850
assert(!"unsupported IR!");
851
free(prog);
852
return NULL;
853
}
854
855
prog->cp.smem_size = cso->req_local_mem;
856
prog->cp.lmem_size = cso->req_private_mem;
857
prog->parm_size = cso->req_input_mem;
858
859
return (void *)prog;
860
}
861
862
static void
863
nv50_cp_state_bind(struct pipe_context *pipe, void *hwcso)
864
{
865
struct nv50_context *nv50 = nv50_context(pipe);
866
867
nv50->compprog = hwcso;
868
nv50->dirty_cp |= NV50_NEW_CP_PROGRAM;
869
}
870
871
static void
872
nv50_set_constant_buffer(struct pipe_context *pipe,
873
enum pipe_shader_type shader, uint index,
874
bool take_ownership,
875
const struct pipe_constant_buffer *cb)
876
{
877
struct nv50_context *nv50 = nv50_context(pipe);
878
struct pipe_resource *res = cb ? cb->buffer : NULL;
879
const unsigned s = nv50_context_shader_stage(shader);
880
const unsigned i = index;
881
882
if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
883
if (nv50->constbuf[s][i].user)
884
nv50->constbuf[s][i].u.buf = NULL;
885
else
886
if (nv50->constbuf[s][i].u.buf)
887
nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_CB(i));
888
889
nv50->dirty_cp |= NV50_NEW_CP_CONSTBUF;
890
} else {
891
if (nv50->constbuf[s][i].user)
892
nv50->constbuf[s][i].u.buf = NULL;
893
else
894
if (nv50->constbuf[s][i].u.buf)
895
nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_CB(s, i));
896
897
nv50->dirty_3d |= NV50_NEW_3D_CONSTBUF;
898
}
899
nv50->constbuf_dirty[s] |= 1 << i;
900
901
if (nv50->constbuf[s][i].u.buf)
902
nv04_resource(nv50->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
903
904
if (take_ownership) {
905
pipe_resource_reference(&nv50->constbuf[s][i].u.buf, NULL);
906
nv50->constbuf[s][i].u.buf = res;
907
} else {
908
pipe_resource_reference(&nv50->constbuf[s][i].u.buf, res);
909
}
910
911
nv50->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
912
if (nv50->constbuf[s][i].user) {
913
nv50->constbuf[s][i].u.data = cb->user_buffer;
914
nv50->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
915
nv50->constbuf_valid[s] |= 1 << i;
916
nv50->constbuf_coherent[s] &= ~(1 << i);
917
} else
918
if (cb) {
919
nv50->constbuf[s][i].offset = cb->buffer_offset;
920
nv50->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
921
nv50->constbuf_valid[s] |= 1 << i;
922
if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
923
nv50->constbuf_coherent[s] |= 1 << i;
924
else
925
nv50->constbuf_coherent[s] &= ~(1 << i);
926
}
927
else {
928
nv50->constbuf_valid[s] &= ~(1 << i);
929
nv50->constbuf_coherent[s] &= ~(1 << i);
930
}
931
}
932
933
/* =============================================================================
934
*/
935
936
static void
937
nv50_set_blend_color(struct pipe_context *pipe,
938
const struct pipe_blend_color *bcol)
939
{
940
struct nv50_context *nv50 = nv50_context(pipe);
941
942
nv50->blend_colour = *bcol;
943
nv50->dirty_3d |= NV50_NEW_3D_BLEND_COLOUR;
944
}
945
946
static void
947
nv50_set_stencil_ref(struct pipe_context *pipe,
948
const struct pipe_stencil_ref sr)
949
{
950
struct nv50_context *nv50 = nv50_context(pipe);
951
952
nv50->stencil_ref = sr;
953
nv50->dirty_3d |= NV50_NEW_3D_STENCIL_REF;
954
}
955
956
static void
957
nv50_set_clip_state(struct pipe_context *pipe,
958
const struct pipe_clip_state *clip)
959
{
960
struct nv50_context *nv50 = nv50_context(pipe);
961
962
memcpy(nv50->clip.ucp, clip->ucp, sizeof(clip->ucp));
963
964
nv50->dirty_3d |= NV50_NEW_3D_CLIP;
965
}
966
967
static void
968
nv50_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
969
{
970
struct nv50_context *nv50 = nv50_context(pipe);
971
972
nv50->sample_mask = sample_mask;
973
nv50->dirty_3d |= NV50_NEW_3D_SAMPLE_MASK;
974
}
975
976
static void
977
nv50_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
978
{
979
struct nv50_context *nv50 = nv50_context(pipe);
980
981
if (nv50->min_samples != min_samples) {
982
nv50->min_samples = min_samples;
983
nv50->dirty_3d |= NV50_NEW_3D_MIN_SAMPLES;
984
}
985
}
986
987
static void
988
nv50_set_framebuffer_state(struct pipe_context *pipe,
989
const struct pipe_framebuffer_state *fb)
990
{
991
struct nv50_context *nv50 = nv50_context(pipe);
992
993
nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_FB);
994
995
util_copy_framebuffer_state(&nv50->framebuffer, fb);
996
997
nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_TEXTURES;
998
}
999
1000
static void
1001
nv50_set_polygon_stipple(struct pipe_context *pipe,
1002
const struct pipe_poly_stipple *stipple)
1003
{
1004
struct nv50_context *nv50 = nv50_context(pipe);
1005
1006
nv50->stipple = *stipple;
1007
nv50->dirty_3d |= NV50_NEW_3D_STIPPLE;
1008
}
1009
1010
static void
1011
nv50_set_scissor_states(struct pipe_context *pipe,
1012
unsigned start_slot,
1013
unsigned num_scissors,
1014
const struct pipe_scissor_state *scissor)
1015
{
1016
struct nv50_context *nv50 = nv50_context(pipe);
1017
int i;
1018
1019
assert(start_slot + num_scissors <= NV50_MAX_VIEWPORTS);
1020
for (i = 0; i < num_scissors; i++) {
1021
if (!memcmp(&nv50->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
1022
continue;
1023
nv50->scissors[start_slot + i] = scissor[i];
1024
nv50->scissors_dirty |= 1 << (start_slot + i);
1025
nv50->dirty_3d |= NV50_NEW_3D_SCISSOR;
1026
}
1027
}
1028
1029
static void
1030
nv50_set_viewport_states(struct pipe_context *pipe,
1031
unsigned start_slot,
1032
unsigned num_viewports,
1033
const struct pipe_viewport_state *vpt)
1034
{
1035
struct nv50_context *nv50 = nv50_context(pipe);
1036
int i;
1037
1038
assert(start_slot + num_viewports <= NV50_MAX_VIEWPORTS);
1039
for (i = 0; i < num_viewports; i++) {
1040
if (!memcmp(&nv50->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
1041
continue;
1042
nv50->viewports[start_slot + i] = vpt[i];
1043
nv50->viewports_dirty |= 1 << (start_slot + i);
1044
nv50->dirty_3d |= NV50_NEW_3D_VIEWPORT;
1045
}
1046
}
1047
1048
static void
1049
nv50_set_window_rectangles(struct pipe_context *pipe,
1050
bool include,
1051
unsigned num_rectangles,
1052
const struct pipe_scissor_state *rectangles)
1053
{
1054
struct nv50_context *nv50 = nv50_context(pipe);
1055
1056
nv50->window_rect.inclusive = include;
1057
nv50->window_rect.rects = MIN2(num_rectangles, NV50_MAX_WINDOW_RECTANGLES);
1058
memcpy(nv50->window_rect.rect, rectangles,
1059
sizeof(struct pipe_scissor_state) * nv50->window_rect.rects);
1060
1061
nv50->dirty_3d |= NV50_NEW_3D_WINDOW_RECTS;
1062
}
1063
1064
static void
1065
nv50_set_vertex_buffers(struct pipe_context *pipe,
1066
unsigned start_slot, unsigned count,
1067
unsigned unbind_num_trailing_slots,
1068
bool take_ownership,
1069
const struct pipe_vertex_buffer *vb)
1070
{
1071
struct nv50_context *nv50 = nv50_context(pipe);
1072
unsigned i;
1073
1074
nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_VERTEX);
1075
nv50->dirty_3d |= NV50_NEW_3D_ARRAYS;
1076
1077
util_set_vertex_buffers_count(nv50->vtxbuf, &nv50->num_vtxbufs, vb,
1078
start_slot, count,
1079
unbind_num_trailing_slots,
1080
take_ownership);
1081
1082
unsigned clear_mask = ~u_bit_consecutive(start_slot + count, unbind_num_trailing_slots);
1083
nv50->vbo_user &= clear_mask;
1084
nv50->vbo_constant &= clear_mask;
1085
nv50->vtxbufs_coherent &= clear_mask;
1086
1087
if (!vb) {
1088
clear_mask = ~u_bit_consecutive(start_slot, count);
1089
nv50->vbo_user &= clear_mask;
1090
nv50->vbo_constant &= clear_mask;
1091
nv50->vtxbufs_coherent &= clear_mask;
1092
return;
1093
}
1094
1095
for (i = 0; i < count; ++i) {
1096
unsigned dst_index = start_slot + i;
1097
1098
if (vb[i].is_user_buffer) {
1099
nv50->vbo_user |= 1 << dst_index;
1100
if (!vb[i].stride)
1101
nv50->vbo_constant |= 1 << dst_index;
1102
else
1103
nv50->vbo_constant &= ~(1 << dst_index);
1104
nv50->vtxbufs_coherent &= ~(1 << dst_index);
1105
} else {
1106
nv50->vbo_user &= ~(1 << dst_index);
1107
nv50->vbo_constant &= ~(1 << dst_index);
1108
1109
if (vb[i].buffer.resource &&
1110
vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1111
nv50->vtxbufs_coherent |= (1 << dst_index);
1112
else
1113
nv50->vtxbufs_coherent &= ~(1 << dst_index);
1114
}
1115
}
1116
}
1117
1118
static void
1119
nv50_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1120
{
1121
struct nv50_context *nv50 = nv50_context(pipe);
1122
1123
nv50->vertex = hwcso;
1124
nv50->dirty_3d |= NV50_NEW_3D_VERTEX;
1125
}
1126
1127
static struct pipe_stream_output_target *
1128
nv50_so_target_create(struct pipe_context *pipe,
1129
struct pipe_resource *res,
1130
unsigned offset, unsigned size)
1131
{
1132
struct nv04_resource *buf = (struct nv04_resource *)res;
1133
struct nv50_so_target *targ = MALLOC_STRUCT(nv50_so_target);
1134
if (!targ)
1135
return NULL;
1136
1137
if (nouveau_context(pipe)->screen->class_3d >= NVA0_3D_CLASS) {
1138
targ->pq = pipe->create_query(pipe,
1139
NVA0_HW_QUERY_STREAM_OUTPUT_BUFFER_OFFSET, 0);
1140
if (!targ->pq) {
1141
FREE(targ);
1142
return NULL;
1143
}
1144
} else {
1145
targ->pq = NULL;
1146
}
1147
targ->clean = true;
1148
1149
targ->pipe.buffer_size = size;
1150
targ->pipe.buffer_offset = offset;
1151
targ->pipe.context = pipe;
1152
targ->pipe.buffer = NULL;
1153
pipe_resource_reference(&targ->pipe.buffer, res);
1154
pipe_reference_init(&targ->pipe.reference, 1);
1155
1156
assert(buf->base.target == PIPE_BUFFER);
1157
util_range_add(&buf->base, &buf->valid_buffer_range, offset, offset + size);
1158
1159
return &targ->pipe;
1160
}
1161
1162
static void
1163
nva0_so_target_save_offset(struct pipe_context *pipe,
1164
struct pipe_stream_output_target *ptarg,
1165
unsigned index, bool serialize)
1166
{
1167
struct nv50_so_target *targ = nv50_so_target(ptarg);
1168
1169
if (serialize) {
1170
struct nouveau_pushbuf *push = nv50_context(pipe)->base.pushbuf;
1171
PUSH_SPACE(push, 2);
1172
BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
1173
PUSH_DATA (push, 0);
1174
}
1175
1176
nv50_query(targ->pq)->index = index;
1177
pipe->end_query(pipe, targ->pq);
1178
}
1179
1180
static void
1181
nv50_so_target_destroy(struct pipe_context *pipe,
1182
struct pipe_stream_output_target *ptarg)
1183
{
1184
struct nv50_so_target *targ = nv50_so_target(ptarg);
1185
if (targ->pq)
1186
pipe->destroy_query(pipe, targ->pq);
1187
pipe_resource_reference(&targ->pipe.buffer, NULL);
1188
FREE(targ);
1189
}
1190
1191
static void
1192
nv50_set_stream_output_targets(struct pipe_context *pipe,
1193
unsigned num_targets,
1194
struct pipe_stream_output_target **targets,
1195
const unsigned *offsets)
1196
{
1197
struct nv50_context *nv50 = nv50_context(pipe);
1198
unsigned i;
1199
bool serialize = true;
1200
const bool can_resume = nv50->screen->base.class_3d >= NVA0_3D_CLASS;
1201
1202
assert(num_targets <= 4);
1203
1204
for (i = 0; i < num_targets; ++i) {
1205
const bool changed = nv50->so_target[i] != targets[i];
1206
const bool append = (offsets[i] == (unsigned)-1);
1207
if (!changed && append)
1208
continue;
1209
nv50->so_targets_dirty |= 1 << i;
1210
1211
if (can_resume && changed && nv50->so_target[i]) {
1212
nva0_so_target_save_offset(pipe, nv50->so_target[i], i, serialize);
1213
serialize = false;
1214
}
1215
1216
if (targets[i] && !append) {
1217
nv50_so_target(targets[i])->clean = true;
1218
nv50->so_used[i] = 0;
1219
}
1220
1221
pipe_so_target_reference(&nv50->so_target[i], targets[i]);
1222
}
1223
for (; i < nv50->num_so_targets; ++i) {
1224
if (can_resume && nv50->so_target[i]) {
1225
nva0_so_target_save_offset(pipe, nv50->so_target[i], i, serialize);
1226
serialize = false;
1227
}
1228
pipe_so_target_reference(&nv50->so_target[i], NULL);
1229
nv50->so_targets_dirty |= 1 << i;
1230
}
1231
nv50->num_so_targets = num_targets;
1232
1233
if (nv50->so_targets_dirty) {
1234
nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_SO);
1235
nv50->dirty_3d |= NV50_NEW_3D_STRMOUT;
1236
}
1237
}
1238
1239
static bool
1240
nv50_bind_images_range(struct nv50_context *nv50,
1241
unsigned start, unsigned nr,
1242
const struct pipe_image_view *pimages)
1243
{
1244
const unsigned end = start + nr;
1245
unsigned mask = 0;
1246
unsigned i;
1247
1248
if (pimages) {
1249
for (i = start; i < end; ++i) {
1250
struct pipe_image_view *img = &nv50->images[i];
1251
const unsigned p = i - start;
1252
1253
if (img->resource == pimages[p].resource &&
1254
img->format == pimages[p].format &&
1255
img->access == pimages[p].access) {
1256
if (img->resource == NULL)
1257
continue;
1258
if (img->resource->target == PIPE_BUFFER &&
1259
img->u.buf.offset == pimages[p].u.buf.offset &&
1260
img->u.buf.size == pimages[p].u.buf.size)
1261
continue;
1262
if (img->resource->target != PIPE_BUFFER &&
1263
img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1264
img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1265
img->u.tex.level == pimages[p].u.tex.level)
1266
continue;
1267
}
1268
1269
mask |= (1 << i);
1270
if (pimages[p].resource)
1271
nv50->images_valid |= (1 << i);
1272
else
1273
nv50->images_valid &= ~(1 << i);
1274
1275
img->format = pimages[p].format;
1276
img->access = pimages[p].access;
1277
if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1278
img->u.buf = pimages[p].u.buf;
1279
else
1280
img->u.tex = pimages[p].u.tex;
1281
1282
pipe_resource_reference(
1283
&img->resource, pimages[p].resource);
1284
}
1285
if (!mask)
1286
return false;
1287
} else {
1288
mask = ((1 << nr) - 1) << start;
1289
if (!(nv50->images_valid & mask))
1290
return false;
1291
for (i = start; i < end; ++i) {
1292
pipe_resource_reference(&nv50->images[i].resource, NULL);
1293
}
1294
nv50->images_valid &= ~mask;
1295
}
1296
nv50->images_dirty |= mask;
1297
1298
nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_SUF);
1299
1300
return true;
1301
}
1302
1303
static void
1304
nv50_set_shader_images(struct pipe_context *pipe,
1305
enum pipe_shader_type shader,
1306
unsigned start, unsigned nr,
1307
unsigned unbind_num_trailing_slots,
1308
const struct pipe_image_view *images)
1309
{
1310
const unsigned s = nv50_context_shader_stage(shader);
1311
1312
if (s != NV50_SHADER_STAGE_COMPUTE)
1313
return;
1314
1315
nv50_bind_images_range(nv50_context(pipe), start + nr,
1316
unbind_num_trailing_slots, NULL);
1317
1318
if (!nv50_bind_images_range(nv50_context(pipe), start, nr, images))
1319
return;
1320
1321
nv50_context(pipe)->dirty_cp |= NV50_NEW_CP_SURFACES;
1322
}
1323
1324
static void
1325
nv50_set_compute_resources(struct pipe_context *pipe,
1326
unsigned start, unsigned nr,
1327
struct pipe_surface **resources)
1328
{
1329
/* TODO: bind surfaces */
1330
}
1331
1332
static bool
1333
nv50_bind_buffers_range(struct nv50_context *nv50,
1334
unsigned start, unsigned nr,
1335
const struct pipe_shader_buffer *pbuffers)
1336
{
1337
const unsigned end = start + nr;
1338
unsigned mask = 0;
1339
unsigned i;
1340
1341
if (pbuffers) {
1342
for (i = start; i < end; ++i) {
1343
struct pipe_shader_buffer *buf = &nv50->buffers[i];
1344
const unsigned p = i - start;
1345
if (buf->buffer == pbuffers[p].buffer &&
1346
buf->buffer_offset == pbuffers[p].buffer_offset &&
1347
buf->buffer_size == pbuffers[p].buffer_size)
1348
continue;
1349
1350
mask |= (1 << i);
1351
if (pbuffers[p].buffer)
1352
nv50->buffers_valid |= (1 << i);
1353
else
1354
nv50->buffers_valid &= ~(1 << i);
1355
buf->buffer_offset = pbuffers[p].buffer_offset;
1356
buf->buffer_size = pbuffers[p].buffer_size;
1357
pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1358
}
1359
if (!mask)
1360
return false;
1361
} else {
1362
mask = ((1 << nr) - 1) << start;
1363
if (!(nv50->buffers_valid & mask))
1364
return false;
1365
for (i = start; i < end; ++i)
1366
pipe_resource_reference(&nv50->buffers[i].buffer, NULL);
1367
nv50->buffers_valid &= ~mask;
1368
}
1369
nv50->buffers_dirty |= mask;
1370
1371
nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_BUF);
1372
1373
return true;
1374
}
1375
1376
static void
1377
nv50_set_shader_buffers(struct pipe_context *pipe,
1378
enum pipe_shader_type shader,
1379
unsigned start, unsigned nr,
1380
const struct pipe_shader_buffer *buffers,
1381
unsigned writable_bitmask)
1382
{
1383
const unsigned s = nv50_context_shader_stage(shader);
1384
1385
if (s != NV50_SHADER_STAGE_COMPUTE)
1386
return;
1387
1388
if (!nv50_bind_buffers_range(nv50_context(pipe), start, nr, buffers))
1389
return;
1390
1391
nv50_context(pipe)->dirty_cp |= NV50_NEW_CP_BUFFERS;
1392
}
1393
1394
static inline void
1395
nv50_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1396
{
1397
struct nv04_resource *buf = nv04_resource(res);
1398
if (buf) {
1399
uint64_t limit = (buf->address + buf->base.width0) - 1;
1400
if (limit < (1ULL << 32)) {
1401
*phandle = (uint32_t)buf->address;
1402
} else {
1403
NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1404
"resource not contained within 32-bit address space !\n");
1405
*phandle = 0;
1406
}
1407
} else {
1408
*phandle = 0;
1409
}
1410
}
1411
1412
static void
1413
nv50_set_global_bindings(struct pipe_context *pipe,
1414
unsigned start, unsigned nr,
1415
struct pipe_resource **resources,
1416
uint32_t **handles)
1417
{
1418
struct nv50_context *nv50 = nv50_context(pipe);
1419
struct pipe_resource **ptr;
1420
unsigned i;
1421
const unsigned end = start + nr;
1422
1423
if (nv50->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1424
const unsigned old_size = nv50->global_residents.size;
1425
if (util_dynarray_resize(&nv50->global_residents, struct pipe_resource *, end)) {
1426
memset((uint8_t *)nv50->global_residents.data + old_size, 0,
1427
nv50->global_residents.size - old_size);
1428
} else {
1429
NOUVEAU_ERR("Could not resize global residents array\n");
1430
return;
1431
}
1432
}
1433
1434
if (resources) {
1435
ptr = util_dynarray_element(
1436
&nv50->global_residents, struct pipe_resource *, start);
1437
for (i = 0; i < nr; ++i) {
1438
pipe_resource_reference(&ptr[i], resources[i]);
1439
nv50_set_global_handle(handles[i], resources[i]);
1440
}
1441
} else {
1442
ptr = util_dynarray_element(
1443
&nv50->global_residents, struct pipe_resource *, start);
1444
for (i = 0; i < nr; ++i)
1445
pipe_resource_reference(&ptr[i], NULL);
1446
}
1447
1448
nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_GLOBAL);
1449
1450
nv50->dirty_cp |= NV50_NEW_CP_GLOBALS;
1451
}
1452
1453
void
1454
nv50_init_state_functions(struct nv50_context *nv50)
1455
{
1456
struct pipe_context *pipe = &nv50->base.pipe;
1457
1458
pipe->create_blend_state = nv50_blend_state_create;
1459
pipe->bind_blend_state = nv50_blend_state_bind;
1460
pipe->delete_blend_state = nv50_blend_state_delete;
1461
1462
pipe->create_rasterizer_state = nv50_rasterizer_state_create;
1463
pipe->bind_rasterizer_state = nv50_rasterizer_state_bind;
1464
pipe->delete_rasterizer_state = nv50_rasterizer_state_delete;
1465
1466
pipe->create_depth_stencil_alpha_state = nv50_zsa_state_create;
1467
pipe->bind_depth_stencil_alpha_state = nv50_zsa_state_bind;
1468
pipe->delete_depth_stencil_alpha_state = nv50_zsa_state_delete;
1469
1470
pipe->create_sampler_state = nv50_sampler_state_create;
1471
pipe->delete_sampler_state = nv50_sampler_state_delete;
1472
pipe->bind_sampler_states = nv50_bind_sampler_states;
1473
1474
pipe->create_sampler_view = nv50_create_sampler_view;
1475
pipe->sampler_view_destroy = nv50_sampler_view_destroy;
1476
pipe->set_sampler_views = nv50_set_sampler_views;
1477
1478
pipe->create_vs_state = nv50_vp_state_create;
1479
pipe->create_fs_state = nv50_fp_state_create;
1480
pipe->create_gs_state = nv50_gp_state_create;
1481
pipe->create_compute_state = nv50_cp_state_create;
1482
pipe->bind_vs_state = nv50_vp_state_bind;
1483
pipe->bind_fs_state = nv50_fp_state_bind;
1484
pipe->bind_gs_state = nv50_gp_state_bind;
1485
pipe->bind_compute_state = nv50_cp_state_bind;
1486
pipe->delete_vs_state = nv50_sp_state_delete;
1487
pipe->delete_fs_state = nv50_sp_state_delete;
1488
pipe->delete_gs_state = nv50_sp_state_delete;
1489
pipe->delete_compute_state = nv50_sp_state_delete;
1490
1491
pipe->set_blend_color = nv50_set_blend_color;
1492
pipe->set_stencil_ref = nv50_set_stencil_ref;
1493
pipe->set_clip_state = nv50_set_clip_state;
1494
pipe->set_sample_mask = nv50_set_sample_mask;
1495
pipe->set_min_samples = nv50_set_min_samples;
1496
pipe->set_constant_buffer = nv50_set_constant_buffer;
1497
pipe->set_framebuffer_state = nv50_set_framebuffer_state;
1498
pipe->set_polygon_stipple = nv50_set_polygon_stipple;
1499
pipe->set_scissor_states = nv50_set_scissor_states;
1500
pipe->set_viewport_states = nv50_set_viewport_states;
1501
pipe->set_window_rectangles = nv50_set_window_rectangles;
1502
1503
pipe->create_vertex_elements_state = nv50_vertex_state_create;
1504
pipe->delete_vertex_elements_state = nv50_vertex_state_delete;
1505
pipe->bind_vertex_elements_state = nv50_vertex_state_bind;
1506
1507
pipe->set_vertex_buffers = nv50_set_vertex_buffers;
1508
1509
pipe->create_stream_output_target = nv50_so_target_create;
1510
pipe->stream_output_target_destroy = nv50_so_target_destroy;
1511
pipe->set_stream_output_targets = nv50_set_stream_output_targets;
1512
1513
pipe->set_global_binding = nv50_set_global_bindings;
1514
pipe->set_compute_resources = nv50_set_compute_resources;
1515
pipe->set_shader_images = nv50_set_shader_images;
1516
pipe->set_shader_buffers = nv50_set_shader_buffers;
1517
1518
nv50->sample_mask = ~0;
1519
nv50->min_samples = 1;
1520
}
1521
1522