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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/nouveau/nv50/nv98_video_ppp.c
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/*
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* Copyright 2011-2013 Maarten Lankhorst, Ilia Mirkin
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "nv50/nv98_video.h"
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static void
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nv98_decoder_setup_ppp(struct nouveau_vp3_decoder *dec, struct nouveau_vp3_video_buffer *target, uint32_t low700) {
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struct nouveau_pushbuf *push = dec->pushbuf[2];
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uint32_t stride_in = mb(dec->base.width);
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uint32_t stride_out = mb(target->resources[0]->width0);
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uint32_t dec_h = mb(dec->base.height);
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uint32_t dec_w = mb(dec->base.width);
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uint64_t in_addr;
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uint32_t y2, cbcr, cbcr2, i;
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struct nouveau_pushbuf_refn bo_refs[] = {
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{ NULL, NOUVEAU_BO_WR | NOUVEAU_BO_VRAM },
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{ NULL, NOUVEAU_BO_WR | NOUVEAU_BO_VRAM },
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{ dec->ref_bo, NOUVEAU_BO_RD | NOUVEAU_BO_VRAM },
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#if NOUVEAU_VP3_DEBUG_FENCE
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{ dec->fence_bo, NOUVEAU_BO_WR | NOUVEAU_BO_GART },
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#endif
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};
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unsigned num_refs = ARRAY_SIZE(bo_refs);
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for (i = 0; i < 2; ++i) {
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struct nv50_miptree *mt = (struct nv50_miptree *)target->resources[i];
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bo_refs[i].bo = mt->base.bo;
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}
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nouveau_pushbuf_refn(push, bo_refs, num_refs);
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nouveau_vp3_ycbcr_offsets(dec, &y2, &cbcr, &cbcr2);
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BEGIN_NV04(push, SUBC_PPP(0x700), 10);
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in_addr = nouveau_vp3_video_addr(dec, target) >> 8;
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PUSH_DATA (push, (stride_out << 24) | (stride_out << 16) | low700); // 700
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PUSH_DATA (push, (stride_in << 24) | (stride_in << 16) | (dec_h << 8) | dec_w); // 704
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assert(dec_w == stride_in);
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/* Input: */
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PUSH_DATA (push, in_addr); // 708
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PUSH_DATA (push, in_addr + y2); // 70c
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PUSH_DATA (push, in_addr + cbcr); // 710
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PUSH_DATA (push, in_addr + cbcr2); // 714
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for (i = 0; i < 2; ++i) {
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struct nv50_miptree *mt = (struct nv50_miptree *)target->resources[i];
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PUSH_DATA (push, mt->base.address >> 8);
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PUSH_DATA (push, (mt->base.address + mt->total_size/2) >> 8);
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mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
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}
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}
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static uint32_t
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nv98_decoder_vc1_ppp(struct nouveau_vp3_decoder *dec, struct pipe_vc1_picture_desc *desc, struct nouveau_vp3_video_buffer *target) {
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struct nouveau_pushbuf *push = dec->pushbuf[2];
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nv98_decoder_setup_ppp(dec, target, 0x1412);
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assert(!desc->deblockEnable);
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assert(!(dec->base.width & 0xf));
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assert(!(dec->base.height & 0xf));
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BEGIN_NV04(push, SUBC_PPP(0x400), 1);
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PUSH_DATA (push, desc->pquant << 11);
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// 728 = wtf?
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return 0x10;
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}
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void
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nv98_decoder_ppp(struct nouveau_vp3_decoder *dec, union pipe_desc desc, struct nouveau_vp3_video_buffer *target, unsigned comm_seq) {
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enum pipe_video_format codec = u_reduce_video_profile(dec->base.profile);
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struct nouveau_pushbuf *push = dec->pushbuf[2];
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unsigned ppp_caps = 0x10;
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nouveau_pushbuf_space(push, 32, 4, 0);
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switch (codec) {
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case PIPE_VIDEO_FORMAT_MPEG12: {
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unsigned mpeg2 = dec->base.profile != PIPE_VIDEO_PROFILE_MPEG1;
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nv98_decoder_setup_ppp(dec, target, 0x1410 | mpeg2);
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break;
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}
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case PIPE_VIDEO_FORMAT_MPEG4: nv98_decoder_setup_ppp(dec, target, 0x1414); break;
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case PIPE_VIDEO_FORMAT_VC1: ppp_caps = nv98_decoder_vc1_ppp(dec, desc.vc1, target); break;
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case PIPE_VIDEO_FORMAT_MPEG4_AVC: nv98_decoder_setup_ppp(dec, target, 0x1413); break;
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default: assert(0);
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}
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BEGIN_NV04(push, SUBC_PPP(0x734), 2);
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PUSH_DATA (push, comm_seq);
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PUSH_DATA (push, ppp_caps);
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#if NOUVEAU_VP3_DEBUG_FENCE
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BEGIN_NV04(push, SUBC_PPP(0x240), 3);
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PUSH_DATAh(push, (dec->fence_bo->offset + 0x20));
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PUSH_DATA (push, (dec->fence_bo->offset + 0x20));
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PUSH_DATA (push, dec->fence_seq);
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BEGIN_NV04(push, SUBC_PPP(0x300), 1);
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PUSH_DATA (push, 1);
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PUSH_KICK (push);
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{
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unsigned spin = 0;
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do {
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usleep(100);
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if ((spin++ & 0xff) == 0xff)
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debug_printf("p%u: %u\n", dec->fence_seq, dec->fence_map[8]);
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} while (dec->fence_seq > dec->fence_map[8]);
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}
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#else
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BEGIN_NV04(push, SUBC_PPP(0x300), 1);
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PUSH_DATA (push, 0);
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PUSH_KICK (push);
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#endif
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}
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